* Re: [RFC PATCH 7/9] drm/i915/gt: Allow the creation of multi-mode CCS masks
[not found] <20240723112046.123938-8-andi.shyti@linux.intel.com>
@ 2024-07-23 21:42 ` kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2024-07-23 21:42 UTC (permalink / raw)
To: Andi Shyti; +Cc: llvm, oe-kbuild-all
Hi Andi,
[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.10 next-20240723]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Andi-Shyti/drm-i915-gt-Refactor-uabi-engine-class-instance-list-creation/20240723-192341
base: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link: https://lore.kernel.org/r/20240723112046.123938-8-andi.shyti%40linux.intel.com
patch subject: [RFC PATCH 7/9] drm/i915/gt: Allow the creation of multi-mode CCS masks
config: i386-randconfig-001-20240724 (https://download.01.org/0day-ci/archive/20240724/202407240533.cEF8jOoJ-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240724/202407240533.cEF8jOoJ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202407240533.cEF8jOoJ-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c:62:6: warning: variable 'mode_val' set but not used [-Wunused-but-set-variable]
62 | u32 mode_val = 0;
| ^
1 warning generated.
vim +/mode_val +62 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
58
59 void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode)
60 {
61 unsigned long cslices_mask = gt->ccs.cslice_mask;
> 62 u32 mode_val = 0;
63 int ccs_id;
64 int cslice;
65 u32 m = mode;
66
67 lockdep_assert_held(>->ccs.mutex);
68
69 if (!IS_DG2(gt->i915))
70 return;
71
72 /*
73 * The mode has two bit dedicated for each engine
74 * that will be used for the CCS balancing algorithm:
75 *
76 * BIT | CCS slice
77 * ------------------
78 * 0 | CCS slice
79 * 1 | 0
80 * ------------------
81 * 2 | CCS slice
82 * 3 | 1
83 * ------------------
84 * 4 | CCS slice
85 * 5 | 2
86 * ------------------
87 * 6 | CCS slice
88 * 7 | 3
89 * ------------------
90 *
91 * When a CCS slice is not available, then we will write 0x7,
92 * oterwise we will write the user engine id which load will
93 * be forwarded to that slice.
94 *
95 * The possible configurations are:
96 *
97 * 1 engine (ccs0):
98 * slice 0, 1, 2, 3: ccs0
99 *
100 * 2 engines (ccs0, ccs1):
101 * slice 0, 2: ccs0
102 * slice 1, 3: ccs1
103 *
104 * 4 engines (ccs0, ccs1, ccs2, ccs3):
105 * slice 0: ccs0
106 * slice 1: ccs1
107 * slice 2: ccs2
108 * slice 3: ccs3
109 */
110 ccs_id = __ffs(cslices_mask);
111
112 for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
113 if (!(cslices_mask & BIT(cslice))) {
114 /*
115 * If not available, mark the slice as unavailable
116 * and no task will be dispatched here.
117 */
118 mode_val |= XEHP_CCS_MODE_CSLICE(cslice,
119 XEHP_CCS_MODE_CSLICE_MASK);
120 continue;
121 }
122
123 mode_val |= XEHP_CCS_MODE_CSLICE(cslice, ccs_id);
124
125 if (!m) {
126 m = mode;
127 ccs_id = __ffs(cslices_mask);
128 continue;
129 }
130
131 m--;
132 ccs_id = find_next_bit(&cslices_mask, I915_MAX_CCS, ccs_id + 1);
133 }
134
135 gt->ccs.mode_reg_val = mode;
136 }
137
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] only message in thread