Re: [PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization

Re: [PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization

[kernel test robot]

Hi Kobayashi,Daisuke,

kernel test robot noticed the following build errors:

[auto build test ERROR on cxl/next]
[also build test ERROR on linus/master cxl/pending v6.11-rc6 next-20240903]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Kobayashi-Daisuke/cxl-core-regs-Add-rcd_pcie_cap-initialization/20240903-110023
base:   https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git next
patch link:    https://lore.kernel.org/r/20240903025915.270521-2-kobayashi.da-06%40fujitsu.com
patch subject: [PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization
config: x86_64-randconfig-001-20240903 (https://download.01.org/0day-ci/archive/20240904/202409040010.afyGcWUe-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240904/202409040010.afyGcWUe-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202409040010.afyGcWUe-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/cxl/pci.c:510:25: error: use of undeclared identifier '__free_put_cxl_port'; did you mean '__free_put_cxl_root'?
     510 |                 struct cxl_port *port __free(put_cxl_port) =
         |                                       ^
   include/linux/cleanup.h:64:33: note: expanded from macro '__free'
      64 | #define __free(_name)   __cleanup(__free_##_name)
         |                                   ^
   <scratch space>:28:1: note: expanded from here
      28 | __free_put_cxl_port
         | ^
   drivers/cxl/cxl.h:752:1: note: '__free_put_cxl_root' declared here
     752 | DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))
         | ^
   include/linux/cleanup.h:62:21: note: expanded from macro 'DEFINE_FREE'
      62 |         static inline void __free_##_name(void *p) { _type _T = *(_type *)p; _free; }
         |                            ^
   <scratch space>:64:1: note: expanded from here
      64 | __free_put_cxl_root
         | ^
   1 error generated.


vim +510 drivers/cxl/pci.c

   495	
   496	static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
   497				      struct cxl_register_map *map)
   498	{
   499		int rc;
   500	
   501		rc = cxl_find_regblock(pdev, type, map);
   502	
   503		/*
   504		 * If the Register Locator DVSEC does not exist, check if it
   505		 * is an RCH and try to extract the Component Registers from
   506		 * an RCRB.
   507		 */
   508		if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
   509			struct cxl_dport *dport;
 > 510			struct cxl_port *port __free(put_cxl_port) =
   511				cxl_pci_find_port(pdev, &dport);
   512			if (!port)
   513				return -EPROBE_DEFER;
   514	
   515			rc = cxl_rcrb_get_comp_regs(pdev, map, dport);
   516			if (rc)
   517				return rc;
   518	
   519			rc = cxl_dport_map_rcd_linkcap(pdev, dport);
   520			if (rc)
   521				return rc;
   522	
   523		} else if (rc) {
   524			return rc;
   525		}
   526	
   527		return cxl_setup_regs(map);
   528	}
   529	

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