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* Re: [PATCH 2/2] soc cache: L3 cache lockdown support for HiSilicon SoC
       [not found] <20250107132907.3521574-3-wangyushan12@huawei.com>
@ 2025-01-08 14:37 ` kernel test robot
  0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2025-01-08 14:37 UTC (permalink / raw)
  To: Yushan Wang, xuwei5, yangyicong, Jonathan.Cameron, wangjie125,
	linux-kernel
  Cc: llvm, oe-kbuild-all, prime.zeng, fanghao11, wangyushan12,
	linuxarm

Hi Yushan,

kernel test robot noticed the following build warnings:

[auto build test WARNING on linus/master]
[also build test WARNING on v6.13-rc6 next-20250108]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Yushan-Wang/soc-cache-Add-framework-driver-for-HiSilicon-SoC-cache/20250107-213022
base:   linus/master
patch link:    https://lore.kernel.org/r/20250107132907.3521574-3-wangyushan12%40huawei.com
patch subject: [PATCH 2/2] soc cache: L3 cache lockdown support for HiSilicon SoC
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20250108/202501082259.J9fBJZTQ-lkp@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250108/202501082259.J9fBJZTQ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501082259.J9fBJZTQ-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/soc/hisilicon/hisi_soc_l3c.c:146: warning: Function parameter or struct member 'regset' not described in 'hisi_soc_l3c_free_lock_reg_set'
>> drivers/soc/hisilicon/hisi_soc_l3c.c:146: warning: Excess function parameter 'addr' description in 'hisi_soc_l3c_free_lock_reg_set'


vim +146 drivers/soc/hisilicon/hisi_soc_l3c.c

   136	
   137	/**
   138	 * hisi_soc_l3c_free_lock_reg_set - Free an allocated register set by locked
   139	 *				    address.
   140	 *
   141	 * @soc_l3c:	The L3C instance on which the register set is allocated.
   142	 * @addr:	The locked address.
   143	 */
   144	static void hisi_soc_l3c_free_lock_reg_set(struct hisi_soc_l3c *soc_l3c,
   145						   int regset)
 > 146	{
   147		if (regset < 0)
   148			return;
   149	
   150		xa_erase(&soc_l3c->lock_sets, regset);
   151	}
   152	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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     [not found] <20250107132907.3521574-3-wangyushan12@huawei.com>
2025-01-08 14:37 ` [PATCH 2/2] soc cache: L3 cache lockdown support for HiSilicon SoC kernel test robot

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