drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c:347:8: error: call to __compiletime_assert_586 declared with 'error' attribute: FIELD_PREP: value too large for the field

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c:347:8: error: call to __compiletime_assert_586 declared with 'error' attribute: FIELD_PREP: value too large for the field

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   b0cb56cbbdb4754918c28d6d7c294d56e28a3dd5
commit: 9f1e1e14f59de8e5a62226840abecbcdbd50221a drm/rockchip: Add MIPI DSI2 glue driver for RK3588
date:   3 months ago
config: s390-randconfig-002-20250325 (https://download.01.org/0day-ci/archive/20250325/202503250754.qfYSEP7S-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250325/202503250754.qfYSEP7S-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503250754.qfYSEP7S-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c:347:8: error: call to __compiletime_assert_586 declared with 'error' attribute: FIELD_PREP: value too large for the field
                        PHY_SYS_RATIO(tmp));
                        ^
   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c:90:27: note: expanded from macro 'PHY_SYS_RATIO'
   #define PHY_SYS_RATIO(x)                FIELD_PREP(GENMASK(16, 0), x)
                                           ^
   include/linux/bitfield.h:115:3: note: expanded from macro 'FIELD_PREP'
                   __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");    \
                   ^
   include/linux/bitfield.h:68:3: note: expanded from macro '__BF_FIELD_CHECK'
                   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?           \
                   ^
   note: (skipping 2 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:530:2: note: expanded from macro '_compiletime_assert'
           __compiletime_assert(condition, msg, prefix, suffix)
           ^
   include/linux/compiler_types.h:523:4: note: expanded from macro '__compiletime_assert'
                           prefix ## suffix();                             \
                           ^
   <scratch space>:36:1: note: expanded from here
   __compiletime_assert_586
   ^
   1 error generated.


vim +/error +347 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

0d6d86253fef1e Heiko Stuebner 2024-12-10  319  
0d6d86253fef1e Heiko Stuebner 2024-12-10  320  static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)
0d6d86253fef1e Heiko Stuebner 2024-12-10  321  {
0d6d86253fef1e Heiko Stuebner 2024-12-10  322  	struct drm_display_mode *mode = &dsi2->mode;
0d6d86253fef1e Heiko Stuebner 2024-12-10  323  	u64 sys_clk = clk_get_rate(dsi2->sys_clk);
0d6d86253fef1e Heiko Stuebner 2024-12-10  324  	u64 pixel_clk, ipi_clk, phy_hsclk;
0d6d86253fef1e Heiko Stuebner 2024-12-10  325  	u64 tmp;
0d6d86253fef1e Heiko Stuebner 2024-12-10  326  
0d6d86253fef1e Heiko Stuebner 2024-12-10  327  	/*
0d6d86253fef1e Heiko Stuebner 2024-12-10  328  	 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed
0d6d86253fef1e Heiko Stuebner 2024-12-10  329  	 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio
0d6d86253fef1e Heiko Stuebner 2024-12-10  330  	 * high speed symbol rate.
0d6d86253fef1e Heiko Stuebner 2024-12-10  331  	 */
0d6d86253fef1e Heiko Stuebner 2024-12-10  332  	phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_mbps * USEC_PER_SEC, 16);
0d6d86253fef1e Heiko Stuebner 2024-12-10  333  
0d6d86253fef1e Heiko Stuebner 2024-12-10  334  	/* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */
0d6d86253fef1e Heiko Stuebner 2024-12-10  335  	pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
0d6d86253fef1e Heiko Stuebner 2024-12-10  336  	ipi_clk = pixel_clk / 4;
0d6d86253fef1e Heiko Stuebner 2024-12-10  337  
0d6d86253fef1e Heiko Stuebner 2024-12-10  338  	tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk);
0d6d86253fef1e Heiko Stuebner 2024-12-10  339  	regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG,
0d6d86253fef1e Heiko Stuebner 2024-12-10  340  		     PHY_IPI_RATIO(tmp));
0d6d86253fef1e Heiko Stuebner 2024-12-10  341  
0d6d86253fef1e Heiko Stuebner 2024-12-10  342  	/*
0d6d86253fef1e Heiko Stuebner 2024-12-10  343  	 * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq
0d6d86253fef1e Heiko Stuebner 2024-12-10  344  	 */
0d6d86253fef1e Heiko Stuebner 2024-12-10  345  	tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, sys_clk);
0d6d86253fef1e Heiko Stuebner 2024-12-10  346  	regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG,
0d6d86253fef1e Heiko Stuebner 2024-12-10 @347  		     PHY_SYS_RATIO(tmp));
0d6d86253fef1e Heiko Stuebner 2024-12-10  348  }
0d6d86253fef1e Heiko Stuebner 2024-12-10  349  

:::::: The code at line 347 was first introduced by commit
:::::: 0d6d86253fef1e6b1e38a54db14bcbea9d0d9ca4 drm/bridge/synopsys: Add MIPI DSI2 host controller bridge

:::::: TO: Heiko Stuebner <heiko.stuebner@cherry.de>
:::::: CC: Heiko Stuebner <heiko@sntech.de>

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki