[devsec-tsm:devsec-phase2 13/24] include/linux/pci-tsm.h:190:13: error: no member named 'ide_cap' in 'struct pci_dev'; did you mean 'devcap'?

[devsec-tsm:devsec-phase2 13/24] include/linux/pci-tsm.h:190:13: error: no member named 'ide_cap' in 'struct pci_dev'; did you mean 'devcap'?

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm devsec-phase2
head:   fca18645f5a7726a7d2723322a520ecff3e72b45
commit: a2be27064cb1e7ccb165e331527d1123a4df0fc9 [13/24] PCI, device core: Add private memory access for DEVICE_TRUST_TCB
config: loongarch-allnoconfig (https://download.01.org/0day-ci/archive/20260706/202607061540.myoxX79B-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260706/202607061540.myoxX79B-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202607061540.myoxX79B-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from drivers/pci/pci-driver.c:22:
>> include/linux/pci-tsm.h:190:13: error: no member named 'ide_cap' in 'struct pci_dev'; did you mean 'devcap'?
     190 |                 if (pdev->ide_cap || (pdev->devcap & PCI_EXP_DEVCAP_TEE))
         |                           ^~~~~~~
         |                           devcap
   include/linux/pci.h:377:7: note: 'devcap' declared here
     377 |         u32             devcap;         /* PCIe Device Capabilities */
         |                         ^
   1 error generated.


vim +190 include/linux/pci-tsm.h

f224c20c3d76138 Dan Williams 2026-03-02  166  
3225f52cde56f46 Dan Williams 2025-10-31  167  /* physical function0 and capable of 'connect' */
3225f52cde56f46 Dan Williams 2025-10-31  168  static inline bool is_pci_tsm_pf0(struct pci_dev *pdev)
3225f52cde56f46 Dan Williams 2025-10-31  169  {
3225f52cde56f46 Dan Williams 2025-10-31  170  	if (!pdev)
3225f52cde56f46 Dan Williams 2025-10-31  171  		return false;
3225f52cde56f46 Dan Williams 2025-10-31  172  
3225f52cde56f46 Dan Williams 2025-10-31  173  	if (!pci_is_pcie(pdev))
3225f52cde56f46 Dan Williams 2025-10-31  174  		return false;
3225f52cde56f46 Dan Williams 2025-10-31  175  
3225f52cde56f46 Dan Williams 2025-10-31  176  	if (pdev->is_virtfn)
3225f52cde56f46 Dan Williams 2025-10-31  177  		return false;
3225f52cde56f46 Dan Williams 2025-10-31  178  
3225f52cde56f46 Dan Williams 2025-10-31  179  	/*
3225f52cde56f46 Dan Williams 2025-10-31  180  	 * Allow for a Device Security Manager (DSM) associated with function0
3225f52cde56f46 Dan Williams 2025-10-31  181  	 * of an Endpoint to coordinate TDISP requests for other functions
3225f52cde56f46 Dan Williams 2025-10-31  182  	 * (physical or virtual) of the device, or allow for an Upstream Port
3225f52cde56f46 Dan Williams 2025-10-31  183  	 * DSM to accept TDISP requests for the Endpoints downstream of the
3225f52cde56f46 Dan Williams 2025-10-31  184  	 * switch.
3225f52cde56f46 Dan Williams 2025-10-31  185  	 */
3225f52cde56f46 Dan Williams 2025-10-31  186  	switch (pci_pcie_type(pdev)) {
3225f52cde56f46 Dan Williams 2025-10-31  187  	case PCI_EXP_TYPE_ENDPOINT:
3225f52cde56f46 Dan Williams 2025-10-31  188  	case PCI_EXP_TYPE_UPSTREAM:
3225f52cde56f46 Dan Williams 2025-10-31  189  	case PCI_EXP_TYPE_RC_END:
3225f52cde56f46 Dan Williams 2025-10-31 @190  		if (pdev->ide_cap || (pdev->devcap & PCI_EXP_DEVCAP_TEE))
3225f52cde56f46 Dan Williams 2025-10-31  191  			break;
3225f52cde56f46 Dan Williams 2025-10-31  192  		fallthrough;
3225f52cde56f46 Dan Williams 2025-10-31  193  	default:
3225f52cde56f46 Dan Williams 2025-10-31  194  		return false;
3225f52cde56f46 Dan Williams 2025-10-31  195  	}
3225f52cde56f46 Dan Williams 2025-10-31  196  
3225f52cde56f46 Dan Williams 2025-10-31  197  	return PCI_FUNC(pdev->devfn) == 0;
3225f52cde56f46 Dan Williams 2025-10-31  198  }
3225f52cde56f46 Dan Williams 2025-10-31  199  

:::::: The code at line 190 was first introduced by commit
:::::: 3225f52cde56f46789a4972d3c54df8a4d75f022 PCI/TSM: Establish Secure Sessions and Link Encryption

:::::: TO: Dan Williams <dan.j.williams@intel.com>
:::::: CC: Dan Williams <dan.j.williams@intel.com>

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki