* Re: [PATCH v7 1/6] riscv: vector: refactor vector context operations
[not found] <20261111184359.1239821-2-tchiu@tenstorrent.com>
@ 2026-11-13 18:15 ` kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2026-11-13 18:15 UTC (permalink / raw)
To: Andy Chiu, Anup Patel, Atish Patra, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, kvm, kvm-riscv, linux-riscv
Cc: llvm, oe-kbuild-all, andybnac, Andy Chiu, dfustini, greentime.hu,
Aurelien Jarno, Yong-Xuan Wang, daichengrong, Troy Mitchell
Hi Andy,
kernel test robot noticed the following build errors:
[auto build test ERROR on d1a8d411533d6be16ac79796c02a9bfc7d7958f1]
url: https://github.com/intel-lab-lkp/linux/commits/Andy-Chiu/riscv-vector-refactor-vector-context-operations/20261111-124323
base: d1a8d411533d6be16ac79796c02a9bfc7d7958f1
patch link: https://lore.kernel.org/r/20261111184359.1239821-2-tchiu%40tenstorrent.com
patch subject: [PATCH v7 1/6] riscv: vector: refactor vector context operations
config: riscv-randconfig-1001-20261113 (https://download.01.org/0day-ci/archive/20261114/202611140219.tkhKWAca-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261114/202611140219.tkhKWAca-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202611140219.tkhKWAca-lkp@intel.com/
All errors (new ones prefixed by >>):
>> arch/riscv/kvm/vcpu.c:828:3: error: call to undeclared function 'kvm_riscv_vector_restore'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
828 | kvm_riscv_vector_restore(gcntx);
| ^
arch/riscv/kvm/vcpu.c:828:3: note: did you mean '__kvm_riscv_vector_restore'?
arch/riscv/include/asm/kvm_vcpu_vector.h:62:29: note: '__kvm_riscv_vector_restore' declared here
62 | static __always_inline void __kvm_riscv_vector_restore(struct kvm_cpu_context *context)
| ^
1 error generated.
vim +/kvm_riscv_vector_restore +828 arch/riscv/kvm/vcpu.c
798
799 /*
800 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
801 * the vCPU is running.
802 *
803 * This must be noinstr as instrumentation may make use of RCU, and this is not
804 * safe during the EQS.
805 */
806 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu,
807 struct kvm_cpu_trap *trap)
808 {
809 void *nsh;
810 struct kvm_cpu_context *gcntx = &vcpu->arch.guest_context;
811 struct kvm_cpu_context *hcntx = &vcpu->arch.host_context;
812
813 /*
814 * We save trap CSRs (such as SEPC, SCAUSE, STVAL, HTVAL, and
815 * HTINST) here because we do local_irq_enable() after this
816 * function in kvm_arch_vcpu_ioctl_run() which can result in
817 * an interrupt immediately after local_irq_enable() and can
818 * potentially change trap CSRs.
819 */
820
821 kvm_riscv_vcpu_swap_in_guest_state(vcpu);
822 guest_state_enter_irqoff();
823
824 /* sstatus.VS != SR_VS_OFF is guaranteed when NEED_RESTORE is set */
825 if (current->thread.riscv_v_flags & RISCV_V_VCPU_NEED_RESTORE) {
826 current->thread.riscv_v_flags &= ~RISCV_V_VCPU_NEED_RESTORE;
827 current->thread.riscv_v_flags |= RISCV_V_VCPU_CTX;
> 828 kvm_riscv_vector_restore(gcntx);
829 gcntx->sstatus = (gcntx->sstatus & ~SR_VS) | SR_VS_CLEAN;
830 }
831
832 if (kvm_riscv_nacl_sync_sret_available()) {
833 nsh = nacl_shmem();
834
835 if (kvm_riscv_nacl_autoswap_csr_available()) {
836 hcntx->hstatus =
837 nacl_csr_read(nsh, CSR_HSTATUS);
838 nacl_scratch_write_long(nsh,
839 SBI_NACL_SHMEM_AUTOSWAP_OFFSET +
840 SBI_NACL_SHMEM_AUTOSWAP_HSTATUS,
841 gcntx->hstatus);
842 nacl_scratch_write_long(nsh,
843 SBI_NACL_SHMEM_AUTOSWAP_OFFSET,
844 SBI_NACL_SHMEM_AUTOSWAP_FLAG_HSTATUS);
845 } else if (kvm_riscv_nacl_sync_csr_available()) {
846 hcntx->hstatus = nacl_csr_swap(nsh,
847 CSR_HSTATUS, gcntx->hstatus);
848 } else {
849 hcntx->hstatus = csr_swap(CSR_HSTATUS, gcntx->hstatus);
850 }
851
852 nacl_scratch_write_longs(nsh,
853 SBI_NACL_SHMEM_SRET_OFFSET +
854 SBI_NACL_SHMEM_SRET_X(1),
855 &gcntx->ra,
856 SBI_NACL_SHMEM_SRET_X_LAST);
857
858 __kvm_riscv_nacl_switch_to(&vcpu->arch, SBI_EXT_NACL,
859 SBI_EXT_NACL_SYNC_SRET);
860
861 if (kvm_riscv_nacl_autoswap_csr_available()) {
862 nacl_scratch_write_long(nsh,
863 SBI_NACL_SHMEM_AUTOSWAP_OFFSET,
864 0);
865 gcntx->hstatus = nacl_scratch_read_long(nsh,
866 SBI_NACL_SHMEM_AUTOSWAP_OFFSET +
867 SBI_NACL_SHMEM_AUTOSWAP_HSTATUS);
868 } else {
869 gcntx->hstatus = csr_swap(CSR_HSTATUS, hcntx->hstatus);
870 }
871
872 trap->htval = nacl_csr_read(nsh, CSR_HTVAL);
873 trap->htinst = nacl_csr_read(nsh, CSR_HTINST);
874 } else {
875 hcntx->hstatus = csr_swap(CSR_HSTATUS, gcntx->hstatus);
876
877 __kvm_riscv_switch_to(&vcpu->arch);
878
879 gcntx->hstatus = csr_swap(CSR_HSTATUS, hcntx->hstatus);
880
881 trap->htval = csr_read(CSR_HTVAL);
882 trap->htinst = csr_read(CSR_HTINST);
883 }
884
885 trap->sepc = gcntx->sepc;
886 trap->scause = csr_read(CSR_SCAUSE);
887 trap->stval = csr_read(CSR_STVAL);
888
889 vcpu->arch.last_exit_cpu = vcpu->cpu;
890 guest_state_exit_irqoff();
891 kvm_riscv_vcpu_swap_in_host_state(vcpu);
892 }
893
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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