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From: Cyril Hrubis <chrubis@suse.cz>
To: Piotr Kubaj <piotr.kubaj@intel.com>
Cc: daniel.niestepski@intel.com, tomasz.ossowski@intel.com,
	helena.anna.dubel@intel.com, rafael.j.wysocki@intel.com,
	ltp@lists.linux.it
Subject: Re: [LTP] [PATCH v13] high_freq_hwp_cap_cppc.c: new test
Date: Tue, 9 Jun 2026 12:26:18 +0200	[thread overview]
Message-ID: <aifqSgdF-_F5nz8-@yuki.lan> (raw)
In-Reply-To: <20260514093559.125070-2-piotr.kubaj@intel.com>

Hi!
> +#include "tst_test.h"
> +#include "tst_safe_prw.h"
> +
> +#define MSR_HWP_CAPABILITIES	0x771
> +#define HIGHEST_PERF_MASK	0xFF
> +
> +static int nproc;
> +static int fd = -1;
> +static int *mismatch;
> +
> +static void setup(void)
> +{
> +	if (access("/dev/cpu/0/msr", F_OK) == -1)
> +		tst_brk(TCONF | TERRNO, "msr driver not loaded");
> +
> +	if (access("/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf", F_OK) == -1)
> +		tst_brk(TCONF | TERRNO, "CPPC sysfs not available");
> +
> +	nproc = tst_ncpus_conf();
> +	mismatch = SAFE_MALLOC(nproc * sizeof(int));
> +}
> +
> +static void cleanup(void)
> +{
> +	if (fd != -1)
> +		SAFE_CLOSE(fd);
> +
> +	free(mismatch);
> +}
> +
> +static void run(void)
> +{
> +	bool status = true;
> +	char path[PATH_MAX];
> +
> +	memset(mismatch, 0, nproc * sizeof(*mismatch));
> +
> +	for (int i = 0; i < nproc; i++) {
> +		int online = 1;
> +		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
> +
> +		if (i) {
> +			snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/online", i);
> +			SAFE_FILE_SCANF(path, "%d", &online);
> +		}
> +
> +		if (!online) {
> +			tst_res(TINFO, "CPU%d offline, skipping", i);
> +			continue;
> +		}
> +
> +		snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
> +		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);
> +		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
> +
> +		snprintf(path, sizeof(path), "/dev/cpu/%d/msr", i);
> +		fd = SAFE_OPEN(path, O_RDONLY);
> +
> +		SAFE_PREAD(1, fd, &msr_highest_perf, sizeof(msr_highest_perf), MSR_HWP_CAPABILITIES);

If I run the test on AMD Ryzen I get EIO here. I suppose that we need to
limit this test to a family of CPUs that match the MSR format we expect.

-- 
Cyril Hrubis
chrubis@suse.cz

-- 
Mailing list info: https://lists.linux.it/listinfo/ltp

      parent reply	other threads:[~2026-06-09 10:26 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-14  9:35 [LTP] [PATCH v13] high_freq_hwp_cap_cppc.c: new test Piotr Kubaj
2026-05-14 11:58 ` [LTP] " linuxtestproject.agent
2026-06-02  9:06 ` [LTP] [PATCH v13] " Kubaj, Piotr
2026-06-09 10:26 ` Cyril Hrubis [this message]

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