[PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[Jesse Huang]

From: Jesse Huang <jesse@icplus.com.tw>

Change Logs:
   - Fix TX Pause bug (reset_tx, intr_handler)

Signed-off-by: Jesse Huang <jesse@icplus.com.tw>

---

 sundance.c |   53 ++++++++++++++++++++++++++++++-----------------------
 1 files changed, 30 insertions(+), 23 deletions(-)

ba5de849a1160e56f83456ea059ea600029dfb43
diff --git a/sundance.c b/sundance.c
index ac17377..0ef8f19 100755
--- a/sundance.c
+++ b/sundance.c
@@ -21,8 +21,8 @@
 */
 
 #define DRV_NAME	"sundance"
-#define DRV_VERSION	"1.1"
-#define DRV_RELDATE	"27-Jun-2006"
+#define DRV_VERSION	"1.2"
+#define DRV_RELDATE	"03-Aug-2006"
 
 
 /* The user-configurable values.
@@ -262,8 +262,6 @@ enum alta_offsets {
 	ASICCtrl = 0x30,
 	EEData = 0x34,
 	EECtrl = 0x36,
-	TxStartThresh = 0x3c,
-	RxEarlyThresh = 0x3e,
 	FlashAddr = 0x40,
 	FlashData = 0x44,
 	TxStatus = 0x46,
@@ -1084,6 +1082,8 @@ reset_tx (struct net_device *dev)
 	}
 	/* free all tx skbuff */
 	for (i = 0; i < TX_RING_SIZE; i++) {
+		np->tx_ring[i].next_desc = 0;
+		
 		skb = np->tx_skbuff[i];
 		if (skb) {
 			pci_unmap_single(np->pci_dev, 
@@ -1099,6 +1099,10 @@ reset_tx (struct net_device *dev)
 	}
 	np->cur_tx = np->dirty_tx = 0;
 	np->cur_task = 0;
+	
+	np->last_tx=0;
+	iowrite8(127, ioaddr + TxDMAPollPeriod);	
+	
 	iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
 	return 0;
 }
@@ -1156,29 +1160,29 @@ static irqreturn_t intr_handler(int irq,
 						np->stats.tx_fifo_errors++;
 					if (tx_status & 0x02)
 						np->stats.tx_window_errors++;
-					/*
-					** This reset has been verified on
-					** DFE-580TX boards ! phdm@macqel.be.
-					*/
-					if (tx_status & 0x10) {	/* TxUnderrun */
-						unsigned short txthreshold;
-
-						txthreshold = ioread16 (ioaddr + TxStartThresh);
-						/* Restart Tx FIFO and transmitter */
-						sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
-						iowrite16 (txthreshold, ioaddr + TxStartThresh);
-						/* No need to reset the Tx pointer here */
+
+					/* FIFO ERROR need to be reset tx */
+					if (tx_status & 0x10) {	/* Reset the Tx. */
+						spin_lock(&np->lock);
+						reset_tx(dev);
+						spin_unlock(&np->lock);
+					}
+					if (tx_status & 0x1e) {
+					/* need to make sure tx enabled */
+						int i = 10;
+						do {
+							iowrite16 (ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
+							if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
+								break;
+							mdelay(1);
+						} while (--i);
 					}
-					/* Restart the Tx. */
-					iowrite16 (TxEnable, ioaddr + MACCtrl1);
 				}
-				/* Yup, this is a documentation bug.  It cost me *hours*. */
+				
 				iowrite16 (0, ioaddr + TxStatus);
-				if (tx_cnt < 0) {
-					iowrite32(5000, ioaddr + DownCounter);
-					break;
-				}
 				tx_status = ioread16 (ioaddr + TxStatus);
+				if (tx_cnt < 0)
+					break;
 			}
 			hw_frame_id = (tx_status >> 8) & 0xff;
 		} else 	{
@@ -1244,6 +1248,9 @@ static irqreturn_t intr_handler(int irq,
 	if (netif_msg_intr(np))
 		printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
 			   dev->name, ioread16(ioaddr + IntrStatus));
+			   
+	iowrite32(5000, ioaddr + DownCounter); 
+				   
 	return IRQ_RETVAL(handled);
 }
 
-- 
1.3.GIT

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[Philippe De Muyter]

On Thu, Sep 14, 2006 at 12:58:30AM +0000, Jesse Huang wrote:
[...]
> @@ -262,8 +262,6 @@ enum alta_offsets {
>  	ASICCtrl = 0x30,
>  	EEData = 0x34,
>  	EECtrl = 0x36,
> -	TxStartThresh = 0x3c,
> -	RxEarlyThresh = 0x3e,

Why ?

>  	FlashAddr = 0x40,
>  	FlashData = 0x44,
>  	TxStatus = 0x46,
[...]
> @@ -1156,29 +1160,29 @@ static irqreturn_t intr_handler(int irq,
>  						np->stats.tx_fifo_errors++;
>  					if (tx_status & 0x02)
>  						np->stats.tx_window_errors++;
> -					/*
> -					** This reset has been verified on
> -					** DFE-580TX boards ! phdm@macqel.be.
> -					*/
> -					if (tx_status & 0x10) {	/* TxUnderrun */
> -						unsigned short txthreshold;
> -
> -						txthreshold = ioread16 (ioaddr + TxStartThresh);
> -						/* Restart Tx FIFO and transmitter */
> -						sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
> -						iowrite16 (txthreshold, ioaddr + TxStartThresh);
> -						/* No need to reset the Tx pointer here */
> +
> +					/* FIFO ERROR need to be reset tx */
> +					if (tx_status & 0x10) {	/* Reset the Tx. */
> +						spin_lock(&np->lock);
> +						reset_tx(dev);
> +						spin_unlock(&np->lock);
> +					}

Just as the comments say, on DFE-580TX 4 port boards, where it is easy to
reproduce TxUnderrun problems, just resetting on the chip the Tx FIFO and
transmitter is enough.
There is no need to call reset_tx, which discards all pending messages and
frees all the skb's.  It is also not necessary to reload the Tx pointer.

Is it different with newer versions of the chip ?

Philippe

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[Jesse Huang]

Dear Philippe:

(1) We are not allow to support register TxStartThresh and, RxEarlyThresh,
so
we remove it.

(2) Your consideration is right. But reset_tx is workaround for customer's
embedded system, I don't have this
enviroment now. I can't sure it will work fine if I removed this.

Thanks you very mutch.

Best Regards,
Jesse Huang.

----- Original Message ----- 
From: "Philippe De Muyter" <phdm@macqel.be>
To: "Jesse Huang" <jesse@icplus.com.tw>
Cc: <netdev@vger.kernel.org>
Sent: Friday, September 15, 2006 7:44 PM
Subject: Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)


On Thu, Sep 14, 2006 at 12:58:30AM +0000, Jesse Huang wrote:
[...]
> @@ -262,8 +262,6 @@ enum alta_offsets {
>  ASICCtrl = 0x30,
>  EEData = 0x34,
>  EECtrl = 0x36,
> - TxStartThresh = 0x3c,
> - RxEarlyThresh = 0x3e,

Why ?

>  FlashAddr = 0x40,
>  FlashData = 0x44,
>  TxStatus = 0x46,
[...]
> @@ -1156,29 +1160,29 @@ static irqreturn_t intr_handler(int irq,
>  np->stats.tx_fifo_errors++;
>  if (tx_status & 0x02)
>  np->stats.tx_window_errors++;
> - /*
> - ** This reset has been verified on
> - ** DFE-580TX boards ! phdm@macqel.be.
> - */
> - if (tx_status & 0x10) { /* TxUnderrun */
> - unsigned short txthreshold;
> -
> - txthreshold = ioread16 (ioaddr + TxStartThresh);
> - /* Restart Tx FIFO and transmitter */
> - sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
> - iowrite16 (txthreshold, ioaddr + TxStartThresh);
> - /* No need to reset the Tx pointer here */
> +
> + /* FIFO ERROR need to be reset tx */
> + if (tx_status & 0x10) { /* Reset the Tx. */
> + spin_lock(&np->lock);
> + reset_tx(dev);
> + spin_unlock(&np->lock);
> + }

Just as the comments say, on DFE-580TX 4 port boards, where it is easy to
reproduce TxUnderrun problems, just resetting on the chip the Tx FIFO and
transmitter is enough.
There is no need to call reset_tx, which discards all pending messages and
frees all the skb's.  It is also not necessary to reload the Tx pointer.

Is it different with newer versions of the chip ?

Philippe

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[Philippe De Muyter]

On Mon, Sep 18, 2006 at 11:41:09AM +0800, Jesse Huang wrote:
> Dear Philippe:
> 
> (1) We are not allow to support register TxStartThresh and, RxEarlyThresh,
> so
> we remove it.

Could you develop ?
- What do you mean by `We are not allow'
- Is it specific to the IP100A chip ?

Those register are documented in the Sundance Technology ST201 Data Sheet
and when modified with fine-tuned values, they can have a real positive
effect on the overall throughput on a loaded system.

> 
> (2) Your consideration is right. But reset_tx is workaround for customer's
> embedded system, I don't have this
> enviroment now. I can't sure it will work fine if I removed this.

On DFE-580TX boards, the reset_tx way did not work.  The ports remained
blocked until a power-cycle.  I do not know if the TxUnderrun problem ever
happened with earlier (one port) boards, so I doubt that the reset_tx way
ever worked.  Is was even commented as not being tested.  On DFE-580TX
boards, the current way has been verified by me and others to work, so
please do not break it.

Best regards

Philippe

> 
> Thanks you very mutch.
> 
> Best Regards,
> Jesse Huang.
> 
> ----- Original Message ----- 
> From: "Philippe De Muyter" <phdm@macqel.be>
> To: "Jesse Huang" <jesse@icplus.com.tw>
> Cc: <netdev@vger.kernel.org>
> Sent: Friday, September 15, 2006 7:44 PM
> Subject: Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)
> 
> 
> On Thu, Sep 14, 2006 at 12:58:30AM +0000, Jesse Huang wrote:
> [...]
> > @@ -262,8 +262,6 @@ enum alta_offsets {
> >  ASICCtrl = 0x30,
> >  EEData = 0x34,
> >  EECtrl = 0x36,
> > - TxStartThresh = 0x3c,
> > - RxEarlyThresh = 0x3e,
> 
> Why ?
> 
> >  FlashAddr = 0x40,
> >  FlashData = 0x44,
> >  TxStatus = 0x46,
> [...]
> > @@ -1156,29 +1160,29 @@ static irqreturn_t intr_handler(int irq,
> >  np->stats.tx_fifo_errors++;
> >  if (tx_status & 0x02)
> >  np->stats.tx_window_errors++;
> > - /*
> > - ** This reset has been verified on
> > - ** DFE-580TX boards ! phdm@macqel.be.
> > - */
> > - if (tx_status & 0x10) { /* TxUnderrun */
> > - unsigned short txthreshold;
> > -
> > - txthreshold = ioread16 (ioaddr + TxStartThresh);
> > - /* Restart Tx FIFO and transmitter */
> > - sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
> > - iowrite16 (txthreshold, ioaddr + TxStartThresh);
> > - /* No need to reset the Tx pointer here */
> > +
> > + /* FIFO ERROR need to be reset tx */
> > + if (tx_status & 0x10) { /* Reset the Tx. */
> > + spin_lock(&np->lock);
> > + reset_tx(dev);
> > + spin_unlock(&np->lock);
> > + }
> 
> Just as the comments say, on DFE-580TX 4 port boards, where it is easy to
> reproduce TxUnderrun problems, just resetting on the chip the Tx FIFO and
> transmitter is enough.
> There is no need to call reset_tx, which discards all pending messages and
> frees all the skb's.  It is also not necessary to reload the Tx pointer.
> 
> Is it different with newer versions of the chip ?
> 
> Philippe
> 

-- 

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[Jesse Huang]

Dear Philippe:
(1)Because this is a patent issue, we are not allow to use it again, even it
is in Data Sheet.

(2)Ok, sorry for this, I will add it back.

Should I resent those 4 patches? Or generate this as a new patch?

Thanks very much!

Best Regards,
Jesse Huang.

----- Original Message ----- 
From: "Philippe De Muyter" <phdm@macqel.be>
To: "Jesse Huang" <jesse@icplus.com.tw>
Cc: <netdev@vger.kernel.org>
Sent: Monday, September 18, 2006 5:41 PM
Subject: Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)


On Mon, Sep 18, 2006 at 11:41:09AM +0800, Jesse Huang wrote:
> Dear Philippe:
>
> (1) We are not allow to support register TxStartThresh and, RxEarlyThresh,
> so
> we remove it.

Could you develop ?
- What do you mean by `We are not allow'
- Is it specific to the IP100A chip ?

Those register are documented in the Sundance Technology ST201 Data Sheet
and when modified with fine-tuned values, they can have a real positive
effect on the overall throughput on a loaded system.

>
> (2) Your consideration is right. But reset_tx is workaround for customer's
> embedded system, I don't have this
> enviroment now. I can't sure it will work fine if I removed this.

On DFE-580TX boards, the reset_tx way did not work.  The ports remained
blocked until a power-cycle.  I do not know if the TxUnderrun problem ever
happened with earlier (one port) boards, so I doubt that the reset_tx way
ever worked.  Is was even commented as not being tested.  On DFE-580TX
boards, the current way has been verified by me and others to work, so
please do not break it.

Best regards

Philippe

>
> Thanks you very mutch.
>
> Best Regards,
> Jesse Huang.
>
> ----- Original Message ----- 
> From: "Philippe De Muyter" <phdm@macqel.be>
> To: "Jesse Huang" <jesse@icplus.com.tw>
> Cc: <netdev@vger.kernel.org>
> Sent: Friday, September 15, 2006 7:44 PM
> Subject: Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)
>
>
> On Thu, Sep 14, 2006 at 12:58:30AM +0000, Jesse Huang wrote:
> [...]
> > @@ -262,8 +262,6 @@ enum alta_offsets {
> >  ASICCtrl = 0x30,
> >  EEData = 0x34,
> >  EECtrl = 0x36,
> > - TxStartThresh = 0x3c,
> > - RxEarlyThresh = 0x3e,
>
> Why ?
>
> >  FlashAddr = 0x40,
> >  FlashData = 0x44,
> >  TxStatus = 0x46,
> [...]
> > @@ -1156,29 +1160,29 @@ static irqreturn_t intr_handler(int irq,
> >  np->stats.tx_fifo_errors++;
> >  if (tx_status & 0x02)
> >  np->stats.tx_window_errors++;
> > - /*
> > - ** This reset has been verified on
> > - ** DFE-580TX boards ! phdm@macqel.be.
> > - */
> > - if (tx_status & 0x10) { /* TxUnderrun */
> > - unsigned short txthreshold;
> > -
> > - txthreshold = ioread16 (ioaddr + TxStartThresh);
> > - /* Restart Tx FIFO and transmitter */
> > - sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
> > - iowrite16 (txthreshold, ioaddr + TxStartThresh);
> > - /* No need to reset the Tx pointer here */
> > +
> > + /* FIFO ERROR need to be reset tx */
> > + if (tx_status & 0x10) { /* Reset the Tx. */
> > + spin_lock(&np->lock);
> > + reset_tx(dev);
> > + spin_unlock(&np->lock);
> > + }
>
> Just as the comments say, on DFE-580TX 4 port boards, where it is easy to
> reproduce TxUnderrun problems, just resetting on the chip the Tx FIFO and
> transmitter is enough.
> There is no need to call reset_tx, which discards all pending messages and
> frees all the skb's.  It is also not necessary to reload the Tx pointer.
>
> Is it different with newer versions of the chip ?
>
> Philippe
>

--

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[Philippe De Muyter]

Hi Jesse,

On Mon, Sep 18, 2006 at 07:11:29PM +0800, Jesse Huang wrote:
> Dear Philippe:
> (1)Because this is a patent issue, we are not allow to use it again, even it
> is in Data Sheet.

I surmise this is only a concern for icplus as a hardware company.

The sundance driver in Linux is meant to work also with the previous versions
of the chip (Sundance, Kendin, D-Link).  If you wish you can make it clear
that those registers have disappeared or have no effect in the icplus 100A
version.

> 
> (2)Ok, sorry for this, I will add it back.

Thanks

> 
> Should I resent those 4 patches? Or generate this as a new patch?

I do not know about the other patches, but for this one of course you should

Philippe

> 
> Thanks very much!
> 
> Best Regards,
> Jesse Huang.
> 
> ----- Original Message ----- 
> From: "Philippe De Muyter" <phdm@macqel.be>
> To: "Jesse Huang" <jesse@icplus.com.tw>
> Cc: <netdev@vger.kernel.org>
> Sent: Monday, September 18, 2006 5:41 PM
> Subject: Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)
> 
> 
> On Mon, Sep 18, 2006 at 11:41:09AM +0800, Jesse Huang wrote:
> > Dear Philippe:
> >
> > (1) We are not allow to support register TxStartThresh and, RxEarlyThresh,
> > so
> > we remove it.
> 
> Could you develop ?
> - What do you mean by `We are not allow'
> - Is it specific to the IP100A chip ?
> 
> Those register are documented in the Sundance Technology ST201 Data Sheet
> and when modified with fine-tuned values, they can have a real positive
> effect on the overall throughput on a loaded system.
> 
> >
> > (2) Your consideration is right. But reset_tx is workaround for customer's
> > embedded system, I don't have this
> > enviroment now. I can't sure it will work fine if I removed this.
> 
> On DFE-580TX boards, the reset_tx way did not work.  The ports remained
> blocked until a power-cycle.  I do not know if the TxUnderrun problem ever
> happened with earlier (one port) boards, so I doubt that the reset_tx way
> ever worked.  Is was even commented as not being tested.  On DFE-580TX
> boards, the current way has been verified by me and others to work, so
> please do not break it.
> 
> Best regards
> 
> Philippe
> 
> >
> > Thanks you very mutch.
> >
> > Best Regards,
> > Jesse Huang.
> >
> > ----- Original Message ----- 
> > From: "Philippe De Muyter" <phdm@macqel.be>
> > To: "Jesse Huang" <jesse@icplus.com.tw>
> > Cc: <netdev@vger.kernel.org>
> > Sent: Friday, September 15, 2006 7:44 PM
> > Subject: Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)
> >
> >
> > On Thu, Sep 14, 2006 at 12:58:30AM +0000, Jesse Huang wrote:
> > [...]
> > > @@ -262,8 +262,6 @@ enum alta_offsets {
> > >  ASICCtrl = 0x30,
> > >  EEData = 0x34,
> > >  EECtrl = 0x36,
> > > - TxStartThresh = 0x3c,
> > > - RxEarlyThresh = 0x3e,
> >
> > Why ?
> >
> > >  FlashAddr = 0x40,
> > >  FlashData = 0x44,
> > >  TxStatus = 0x46,
> > [...]
> > > @@ -1156,29 +1160,29 @@ static irqreturn_t intr_handler(int irq,
> > >  np->stats.tx_fifo_errors++;
> > >  if (tx_status & 0x02)
> > >  np->stats.tx_window_errors++;
> > > - /*
> > > - ** This reset has been verified on
> > > - ** DFE-580TX boards ! phdm@macqel.be.
> > > - */
> > > - if (tx_status & 0x10) { /* TxUnderrun */
> > > - unsigned short txthreshold;
> > > -
> > > - txthreshold = ioread16 (ioaddr + TxStartThresh);
> > > - /* Restart Tx FIFO and transmitter */
> > > - sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
> > > - iowrite16 (txthreshold, ioaddr + TxStartThresh);
> > > - /* No need to reset the Tx pointer here */
> > > +
> > > + /* FIFO ERROR need to be reset tx */
> > > + if (tx_status & 0x10) { /* Reset the Tx. */
> > > + spin_lock(&np->lock);
> > > + reset_tx(dev);
> > > + spin_unlock(&np->lock);
> > > + }
> >
> > Just as the comments say, on DFE-580TX 4 port boards, where it is easy to
> > reproduce TxUnderrun problems, just resetting on the chip the Tx FIFO and
> > transmitter is enough.
> > There is no need to call reset_tx, which discards all pending messages and
> > frees all the skb's.  It is also not necessary to reload the Tx pointer.
> >
> > Is it different with newer versions of the chip ?
> >
> > Philippe
> >
> 
> --
> 

-- 

Re: [PATCH 1/4] IP100A: Fix TX Pause bug (reset_tx, intr_handler)

[Francois Romieu]

Philippe De Muyter <phdm@macqel.be> :
[...]
> On Mon, Sep 18, 2006 at 07:11:29PM +0800, Jesse Huang wrote:
> > Dear Philippe:
> > (1)Because this is a patent issue, we are not allow to use it again, even it
> > is in Data Sheet.
> 
> I surmise this is only a concern for icplus as a hardware company.

I'd rather avoid that any Linux user of the old sundance driver with
a new ip100a chipset instantly has some problem with the said patent.

Who would be responsible for it ? :o(

-- 
Ueimor