Re: [PATCH 3/3] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata

[Fidelio LAWSON <lawson.fidelio@gmail.com>]

On 4/4/26 16:45, Andrew Lunn wrote:
> On Fri, Apr 03, 2026 at 11:43:24AM +0200, Fidelio LAWSON wrote:
>> On 3/26/26 13:18, Andrew Lunn wrote:
>>>> +	mutex_lock(&dev->alu_mutex);
>>>> +
>>>> +	ret = ksz_write8(dev, regs[REG_IND_CTRL_0], 0xA0);
>>>> +
>>>> +	if (!ret)
>>>> +		ret = ksz_write8(dev, 0x6F, indir_reg);
>>>> +
>>>> +	if (!ret)
>>>> +		ret = ksz_write8(dev, regs[REG_IND_BYTE], indir_val);
>>>> +
>>>> +	mutex_unlock(&dev->alu_mutex);
>>>
>>> What address space are these registers in? Normally workarounds for a
>>> PHY would be in the PHY driver. But that assumes the registers are
>>> accessible from the PHY driver.
>>>
>>> 	   Andrew
>>
>> Hi Andrew,
>> These registers belong to the KSZ87xx switch address space, accessed through
>> the switch’s indirect access mechanism. In particular, the offsets used here
>> correspond to entries within the TABLE_LINK_MD_V indirect table of the
>> KSZ8-family switches.
> 
> So this errata is for ksz87xx only?
> 
> For this PHY, do all PHY register reads and writes go through
> 
> https://elixir.bootlin.com/linux/v6.19.11/source/drivers/net/dsa/microchip/ksz8.c#L957
> ksz8_r_phy()
> 
> and
> 
> https://elixir.bootlin.com/linux/v6.19.11/source/drivers/net/dsa/microchip/ksz8.c#L1221
> ksz8_w_phy()?
> 
> We already have some "interesting" things going on in these
> functions. PHY_REG_LINK_MD and PHY_REG_PHY_CTRL are not standard C22
> PHY registers. They take the values 0x1d and 0x1f. The 802.3 standard
> defines 0x10-0x1f as vendor specific, so this is O.K.
> 
> So you could define 2 bits in say register 0x1c to indicate the errata
> mode. You can have a PHY tunable which does reads/writes to these two
> bits, and ksz8_w_phy/ksz8_r_phy which translates them to indirect
> register accesses?
> 
> It is not even really violating the layering.
> 
> 	 Andrew

Hi Andrew,

Thanks a lot for the feedback, it was very helpful.

Yes, the erratum affects KSZ87xx devices only, and all accesses to the 
embedded PHYs indeed go through ksz8_r_phy() / ksz8_w_phy(), as you 
pointed out.
I followed your suggestion and reworked the implementation accordingly: 
the errata selection is now modeled as a vendor‑specific Clause 22 PHY 
register (0x1c), handled entirely in ksz8_r_phy() / ksz8_w_phy(), which 
translate reads and writes into the appropriate indirect TABLE_LINK_MD_V 
accesses. This keeps the PHY‑facing API clean without breaking the layering.
I’ve dropped the DT approach and adjusted the implementation based on 
the review comments. I’m sending a v2 with these changes shortly.

Thanks again for the guidance.
Best regards,
Fidelio