* [PATCH net-next 0/3] Automatic PHY interrupts
@ 2018-03-17 19:32 Andrew Lunn
2018-03-17 19:32 ` [PATCH net-next 1/3] net: dsa: mv88e6xxx: Add missing g1 IRQ numbers Andrew Lunn
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Andrew Lunn @ 2018-03-17 19:32 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Andrew Lunn
Now that the mv88e6xxx driver either installs in interrupt handler, or
polls for interrupts, it is possible to always handle PHY interrupts,
rather than have phylib perform the polling. This speeds up detection
of link changes and reduces the load on the MDIO bus, which is
beneficial for PTP.
Andrew Lunn (3):
net: dsa: mv88e6xxx: Add missing g1 IRQ numbers
net: dsa: mv88e6xxx: Add number of internal PHYs
net: dsa: mv88e6xxx: Add MDIO interrupts for internal PHYs
drivers/net/dsa/mv88e6xxx/chip.c | 40 +++++++++++++++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/chip.h | 1 +
drivers/net/dsa/mv88e6xxx/global2.c | 32 +++++++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/global2.h | 16 +++++++++++++++
4 files changed, 89 insertions(+)
--
2.16.2
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH net-next 1/3] net: dsa: mv88e6xxx: Add missing g1 IRQ numbers 2018-03-17 19:32 [PATCH net-next 0/3] Automatic PHY interrupts Andrew Lunn @ 2018-03-17 19:32 ` Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 2/3] net: dsa: mv88e6xxx: Add number of internal PHYs Andrew Lunn ` (2 subsequent siblings) 3 siblings, 0 replies; 5+ messages in thread From: Andrew Lunn @ 2018-03-17 19:32 UTC (permalink / raw) To: David Miller; +Cc: netdev, Andrew Lunn With the recent change to polling for interrupts, it is important that the number of global 1 interrupts is listed. Without it, the driver requests an interrupt domain for zero interrupts, which returns EINVAL, and the probe fails. Add two missing entries. Signed-off-by: Andrew Lunn <andrew@lunn.ch> --- drivers/net/dsa/mv88e6xxx/chip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index bd3ee84770c7..003ce048f3c4 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3420,6 +3420,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .global2_addr = 0x1c, .age_time_coeff = 3750, .atu_move_port_mask = 0x1f, + .g1_irqs = 9, .g2_irqs = 10, .pvt = true, .multi_chip = true, @@ -3728,6 +3729,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .global2_addr = 0x1c, .age_time_coeff = 3750, .atu_move_port_mask = 0x1f, + .g1_irqs = 9, .g2_irqs = 10, .pvt = true, .multi_chip = true, -- 2.16.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH net-next 2/3] net: dsa: mv88e6xxx: Add number of internal PHYs 2018-03-17 19:32 [PATCH net-next 0/3] Automatic PHY interrupts Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 1/3] net: dsa: mv88e6xxx: Add missing g1 IRQ numbers Andrew Lunn @ 2018-03-17 19:32 ` Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 3/3] net: dsa: mv88e6xxx: Add MDIO interrupts for " Andrew Lunn 2018-03-18 20:53 ` [PATCH net-next 0/3] Automatic PHY interrupts David Miller 3 siblings, 0 replies; 5+ messages in thread From: Andrew Lunn @ 2018-03-17 19:32 UTC (permalink / raw) To: David Miller; +Cc: netdev, Andrew Lunn Add to the info structure the number of internal PHYs, if they generate interrupts. Some of the older generations of switches have internal PHYs, but no interrupt registers. In this case, set the count to zero. Signed-off-by: Andrew Lunn <andrew@lunn.ch> --- drivers/net/dsa/mv88e6xxx/chip.c | 28 ++++++++++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 1 + 2 files changed, 29 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 003ce048f3c4..04226fa708e4 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3317,6 +3317,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6085", .num_databases = 4096, .num_ports = 10, + .num_internal_phys = 5, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3337,6 +3338,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6095/88E6095F", .num_databases = 256, .num_ports = 11, + .num_internal_phys = 0, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3355,6 +3357,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6097/88E6097F", .num_databases = 4096, .num_ports = 11, + .num_internal_phys = 8, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3375,6 +3378,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6123", .num_databases = 4096, .num_ports = 3, + .num_internal_phys = 5, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3395,6 +3399,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6131", .num_databases = 256, .num_ports = 8, + .num_internal_phys = 0, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3413,6 +3418,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6341", .num_databases = 4096, .num_ports = 6, + .num_internal_phys = 5, .num_gpio = 11, .max_vid = 4095, .port_base_addr = 0x10, @@ -3434,6 +3440,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6161", .num_databases = 4096, .num_ports = 6, + .num_internal_phys = 5, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3454,6 +3461,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6165", .num_databases = 4096, .num_ports = 6, + .num_internal_phys = 0, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3474,6 +3482,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6171", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3494,6 +3503,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6172", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .num_gpio = 15, .max_vid = 4095, .port_base_addr = 0x10, @@ -3515,6 +3525,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6175", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3535,6 +3546,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6176", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .num_gpio = 15, .max_vid = 4095, .port_base_addr = 0x10, @@ -3556,6 +3568,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6185", .num_databases = 256, .num_ports = 10, + .num_internal_phys = 0, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3574,6 +3587,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6190", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 11, .num_gpio = 16, .max_vid = 8191, .port_base_addr = 0x0, @@ -3595,6 +3609,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6190X", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 11, .num_gpio = 16, .max_vid = 8191, .port_base_addr = 0x0, @@ -3616,6 +3631,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6191", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 11, .max_vid = 8191, .port_base_addr = 0x0, .global1_addr = 0x1b, @@ -3637,6 +3653,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6240", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .num_gpio = 15, .max_vid = 4095, .port_base_addr = 0x10, @@ -3659,6 +3676,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6290", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 11, .num_gpio = 16, .max_vid = 8191, .port_base_addr = 0x0, @@ -3681,6 +3699,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6320", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .num_gpio = 15, .max_vid = 4095, .port_base_addr = 0x10, @@ -3688,6 +3707,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .global2_addr = 0x1c, .age_time_coeff = 15000, .g1_irqs = 8, + .g2_irqs = 10, .atu_move_port_mask = 0xf, .pvt = true, .multi_chip = true, @@ -3702,6 +3722,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6321", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .num_gpio = 15, .max_vid = 4095, .port_base_addr = 0x10, @@ -3709,6 +3730,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .global2_addr = 0x1c, .age_time_coeff = 15000, .g1_irqs = 8, + .g2_irqs = 10, .atu_move_port_mask = 0xf, .multi_chip = true, .tag_protocol = DSA_TAG_PROTO_EDSA, @@ -3721,6 +3743,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .family = MV88E6XXX_FAMILY_6341, .name = "Marvell 88E6341", .num_databases = 4096, + .num_internal_phys = 5, .num_ports = 6, .num_gpio = 11, .max_vid = 4095, @@ -3744,6 +3767,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6350", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3764,6 +3788,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6351", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .max_vid = 4095, .port_base_addr = 0x10, .global1_addr = 0x1b, @@ -3784,6 +3809,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6352", .num_databases = 4096, .num_ports = 7, + .num_internal_phys = 5, .num_gpio = 15, .max_vid = 4095, .port_base_addr = 0x10, @@ -3805,6 +3831,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6390", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 11, .num_gpio = 16, .max_vid = 8191, .port_base_addr = 0x0, @@ -3826,6 +3853,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .name = "Marvell 88E6390X", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 11, .num_gpio = 16, .max_vid = 8191, .port_base_addr = 0x0, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 26b9a618cdee..bad211014e91 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -110,6 +110,7 @@ struct mv88e6xxx_info { const char *name; unsigned int num_databases; unsigned int num_ports; + unsigned int num_internal_phys; unsigned int num_gpio; unsigned int max_vid; unsigned int port_base_addr; -- 2.16.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH net-next 3/3] net: dsa: mv88e6xxx: Add MDIO interrupts for internal PHYs 2018-03-17 19:32 [PATCH net-next 0/3] Automatic PHY interrupts Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 1/3] net: dsa: mv88e6xxx: Add missing g1 IRQ numbers Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 2/3] net: dsa: mv88e6xxx: Add number of internal PHYs Andrew Lunn @ 2018-03-17 19:32 ` Andrew Lunn 2018-03-18 20:53 ` [PATCH net-next 0/3] Automatic PHY interrupts David Miller 3 siblings, 0 replies; 5+ messages in thread From: Andrew Lunn @ 2018-03-17 19:32 UTC (permalink / raw) To: David Miller; +Cc: netdev, Andrew Lunn When registering an MDIO bus, it is possible to pass an array of interrupts, one per address on the bus. phylib will then associate the interrupt to the PHY device, if no other interrupt is provided. Some of the global2 interrupts are PHY interrupts. Place them into the MDIO bus structure. Signed-off-by: Andrew Lunn <andrew@lunn.ch> --- drivers/net/dsa/mv88e6xxx/chip.c | 10 ++++++++++ drivers/net/dsa/mv88e6xxx/global2.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/global2.h | 16 ++++++++++++++++ 3 files changed, 58 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 04226fa708e4..08a8aba216f3 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2291,12 +2291,19 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, bus->write = mv88e6xxx_mdio_write; bus->parent = chip->dev; + if (!external) { + err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); + if (err) + return err; + } + if (np) err = of_mdiobus_register(bus, np); else err = mdiobus_register(bus); if (err) { dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); + mv88e6xxx_g2_irq_mdio_free(chip, bus); return err; } @@ -2323,6 +2330,9 @@ static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) list_for_each_entry(mdio_bus, &chip->mdios, list) { bus = mdio_bus->bus; + if (!mdio_bus->external) + mv88e6xxx_g2_irq_mdio_free(chip, bus); + mdiobus_unregister(bus); } } diff --git a/drivers/net/dsa/mv88e6xxx/global2.c b/drivers/net/dsa/mv88e6xxx/global2.c index 5f370f1fc7c4..6c620974fef3 100644 --- a/drivers/net/dsa/mv88e6xxx/global2.c +++ b/drivers/net/dsa/mv88e6xxx/global2.c @@ -1107,6 +1107,38 @@ int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) return err; } +int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, + struct mii_bus *bus) +{ + int phy, irq, err, err_phy; + + for (phy = 0; phy < chip->info->num_internal_phys; phy++) { + irq = irq_find_mapping(chip->g2_irq.domain, phy); + if (irq < 0) { + err = irq; + goto out; + } + bus->irq[chip->info->port_base_addr + phy] = irq; + } + return 0; +out: + err_phy = phy; + + for (phy = 0; phy < err_phy; phy++) + irq_dispose_mapping(bus->irq[phy]); + + return err; +} + +void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, + struct mii_bus *bus) +{ + int phy; + + for (phy = 0; phy < chip->info->num_internal_phys; phy++) + irq_dispose_mapping(bus->irq[phy]); +} + int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) { u16 reg; diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h index aa3f0a736966..520ec70d32e8 100644 --- a/drivers/net/dsa/mv88e6xxx/global2.h +++ b/drivers/net/dsa/mv88e6xxx/global2.h @@ -317,6 +317,11 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip); int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); +int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, + struct mii_bus *bus); +void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, + struct mii_bus *bus); + int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); @@ -450,6 +455,17 @@ static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) { } +static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, + struct mii_bus *bus) +{ + return 0; +} + +static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, + struct mii_bus *bus) +{ +} + static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) { return -EOPNOTSUPP; -- 2.16.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH net-next 0/3] Automatic PHY interrupts 2018-03-17 19:32 [PATCH net-next 0/3] Automatic PHY interrupts Andrew Lunn ` (2 preceding siblings ...) 2018-03-17 19:32 ` [PATCH net-next 3/3] net: dsa: mv88e6xxx: Add MDIO interrupts for " Andrew Lunn @ 2018-03-18 20:53 ` David Miller 3 siblings, 0 replies; 5+ messages in thread From: David Miller @ 2018-03-18 20:53 UTC (permalink / raw) To: andrew; +Cc: netdev From: Andrew Lunn <andrew@lunn.ch> Date: Sat, 17 Mar 2018 20:32:02 +0100 > Now that the mv88e6xxx driver either installs in interrupt handler, or > polls for interrupts, it is possible to always handle PHY interrupts, > rather than have phylib perform the polling. This speeds up detection > of link changes and reduces the load on the MDIO bus, which is > beneficial for PTP. Series applied, thanks Andrew. ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-03-18 20:53 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-03-17 19:32 [PATCH net-next 0/3] Automatic PHY interrupts Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 1/3] net: dsa: mv88e6xxx: Add missing g1 IRQ numbers Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 2/3] net: dsa: mv88e6xxx: Add number of internal PHYs Andrew Lunn 2018-03-17 19:32 ` [PATCH net-next 3/3] net: dsa: mv88e6xxx: Add MDIO interrupts for " Andrew Lunn 2018-03-18 20:53 ` [PATCH net-next 0/3] Automatic PHY interrupts David Miller
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