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From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: Vladimir Oltean <olteanv@gmail.com>,
	Jakub Kicinski <kuba@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	Andrew Lunn <andrew@lunn.ch>,
	Vivien Didelot <vivien.didelot@gmail.com>,
	Russell King <linux@armlinux.org.uk>
Subject: Re: [PATCH net-next 12/13] net: dsa: sja1105: expose the SGMII PCS as an mdio_device
Date: Tue, 25 May 2021 11:50:08 +0000	[thread overview]
Message-ID: <20210525115007.ntp52e4vutybb7lq@skbuf> (raw)
In-Reply-To: <5c287794-1f47-ad79-0a60-2eeec8469a5f@gmail.com>

On Mon, May 24, 2021 at 07:35:29PM -0700, Florian Fainelli wrote:
> 
> 
> On 5/24/2021 4:22 PM, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > 
> > The SJA1110 has up to 4 PCSes for SGMII/2500base-x, and they have a
> > different access procedure compared to the SJA1105. Since both have a
> > register layout reminiscent of clause 45, the chosen abstraction to hide
> > this difference away was to implement an internal MDIO bus for the PCS,
> > and to use a high-level set of procedures called sja1105_pcs_read and
> > sja1105_pcs_write.
> > 
> > Since we touch all PCS accessors again, now it is a good time to check
> > for error codes from the hardware access as well. We can't propagate the
> > errors very far due to phylink returning void for mac_config and
> > mac_link_up, but at least we print them to the console.
> > 
> > The SGMII PCS of the SJA1110 is not functional at this point, it needs a
> > different initialization sequence compared to SJA1105. That will be done
> > by the next patch.
> > 
> > Cc: Russell King <linux@armlinux.org.uk>
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> 
> [snip]
> 
> > +
> > +int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg)
> > +{
> > +	struct sja1105_mdio_private *mdio_priv = bus->priv;
> > +	struct sja1105_private *priv = mdio_priv->priv;
> > +	const struct sja1105_regs *regs = priv->info->regs;
> > +	int offset, bank;
> > +	u64 addr;
> > +	u32 tmp;
> > +	u16 mmd;
> > +	int rc;
> > +
> > +	if (!(reg & MII_ADDR_C45))
> > +		return -EINVAL;
> > +
> > +	/* This addressing scheme reserves register 0xff for the bank address
> > +	 * register, so that can never be addressed.
> > +	 */
> > +	if (WARN_ON(offset == 0xff))
> > +		return -ENODEV;
> 
> offset is not initialized here, did you mean to do this after it gets
> initialized? And likewise in sja1110_pcs_mdio_write()?

Yikes, you're right, I fiddled around too much with this and I left it
broken, it seems.

  reply	other threads:[~2021-05-25 11:50 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-24 23:22 [PATCH net-next 00/13] Add NXP SJA1110 support to the sja1105 DSA driver Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 01/13] net: dsa: sja1105: be compatible with "ethernet-ports" OF node name Vladimir Oltean
2021-05-25  2:13   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 02/13] net: dsa: sja1105: allow SGMII PCS configuration to be per port Vladimir Oltean
2021-05-25  2:16   ` Florian Fainelli
2021-05-26 12:39     ` Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 03/13] net: dsa: sja1105: the 0x1F0000 SGMII "base address" is actually MDIO_MMD_VEND2 Vladimir Oltean
2021-05-25  2:19   ` Florian Fainelli
2021-05-25  9:12     ` Vladimir Oltean
2021-05-25  2:40   ` Andrew Lunn
2021-05-24 23:22 ` [PATCH net-next 04/13] net: dsa: sja1105: cache the phy-mode port property Vladimir Oltean
2021-05-25  2:19   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 05/13] net: dsa: sja1105: add a PHY interface type compatibility matrix Vladimir Oltean
2021-05-25  2:23   ` Florian Fainelli
2021-05-26 12:37     ` Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 06/13] net: dsa: sja1105: add a translation table for port speeds Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 07/13] net: dsa: sja1105: always keep RGMII ports in the MAC role Vladimir Oltean
2021-05-25  2:24   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 08/13] net: dsa: sja1105: some table entries are always present when read dynamically Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 09/13] dt-bindings: net: dsa: sja1105: add compatible strings for SJA1110 Vladimir Oltean
2021-05-25  2:24   ` Florian Fainelli
2021-05-25 11:57     ` Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 10/13] net: dsa: sja1105: add support for the SJA1110 switch family Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 11/13] net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX Vladimir Oltean
2021-05-25  2:18   ` Andrew Lunn
2021-05-25 11:54     ` Vladimir Oltean
2021-05-25 13:16       ` Andrew Lunn
2021-05-25 13:21         ` Vladimir Oltean
2021-05-25 13:43           ` Andrew Lunn
2021-05-26 11:52             ` Vladimir Oltean
2021-05-25  2:27   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 12/13] net: dsa: sja1105: expose the SGMII PCS as an mdio_device Vladimir Oltean
2021-05-25  2:33   ` Andrew Lunn
2021-05-25  2:35   ` Florian Fainelli
2021-05-25 11:50     ` Vladimir Oltean [this message]
2021-05-24 23:22 ` [PATCH net-next 13/13] net: dsa: sja1105: add support for the SJA1110 SGMII/2500base-x PCS Vladimir Oltean
2021-05-25  2:39   ` Florian Fainelli
2021-05-25 11:47     ` Vladimir Oltean
2021-05-25  2:03 ` [PATCH net-next 00/13] Add NXP SJA1110 support to the sja1105 DSA driver Andrew Lunn
2021-05-26 12:51   ` Vladimir Oltean

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