* [PATCH 6.6 v2 2/4] riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1 [not found] <20240912025539.1928223-1-wangyuli@uniontech.com> @ 2024-09-12 2:55 ` WangYuli 2024-09-12 2:55 ` [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 WangYuli 2024-09-12 2:55 ` [PATCH 6.6 v2 4/4] riscv: dts: starfive: Add JH7110 PWM-DAC support WangYuli 2 siblings, 0 replies; 7+ messages in thread From: WangYuli @ 2024-09-12 2:55 UTC (permalink / raw) To: stable, gregkh, sashal, william.qiu, emil.renner.berthing, conor.dooley, wangyuli, xingyu.wu, walker.chen, robh, hal.feng Cc: kernel, robh+dt, krzysztof.kozlowski+dt, conor+dt, paul.walmsley, palmer, aou, devicetree, linux-riscv, linux-kernel, richardcochran, netdev From: Xingyu Wu <xingyu.wu@starfivetech.com> [ Upstream commit 4e1abae5688aae9dd8345dbd4ea92a4b9adf340d ] These pins are actually I2STX1 clock input, not I2STX0, so their names should be changed. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: WangYuli <wangyuli@uniontech.com> --- arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h index fb0139b56723..256de17f5261 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h +++ b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h @@ -240,8 +240,8 @@ #define GPI_SYS_MCLK_EXT 30 #define GPI_SYS_I2SRX_BCLK 31 #define GPI_SYS_I2SRX_LRCK 32 -#define GPI_SYS_I2STX0_BCLK 33 -#define GPI_SYS_I2STX0_LRCK 34 +#define GPI_SYS_I2STX1_BCLK 33 +#define GPI_SYS_I2STX1_LRCK 34 #define GPI_SYS_TDM_CLK 35 #define GPI_SYS_TDM_RXD 36 #define GPI_SYS_TDM_SYNC 37 -- 2.43.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 [not found] <20240912025539.1928223-1-wangyuli@uniontech.com> 2024-09-12 2:55 ` [PATCH 6.6 v2 2/4] riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1 WangYuli @ 2024-09-12 2:55 ` WangYuli 2024-09-12 10:23 ` Hal Feng 2024-09-12 2:55 ` [PATCH 6.6 v2 4/4] riscv: dts: starfive: Add JH7110 PWM-DAC support WangYuli 2 siblings, 1 reply; 7+ messages in thread From: WangYuli @ 2024-09-12 2:55 UTC (permalink / raw) To: stable, gregkh, sashal, william.qiu, emil.renner.berthing, conor.dooley, wangyuli, xingyu.wu, walker.chen, robh, hal.feng Cc: kernel, robh+dt, krzysztof.kozlowski+dt, conor+dt, paul.walmsley, palmer, aou, devicetree, linux-riscv, linux-kernel, richardcochran, netdev From: Xingyu Wu <xingyu.wu@starfivetech.com> [ Upstream commit 92cfc35838b2a4006abb9e3bafc291b56f135d01 ] Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: WangYuli <wangyuli@uniontech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 58 +++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 +++++++++++++++++++ 2 files changed, 123 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 4874e3bb42ab..caa59b9b2f19 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -202,6 +202,24 @@ &i2c6 { status = "okay"; }; +&i2srx { + pinctrl-names = "default"; + pinctrl-0 = <&i2srx_pins>; + status = "okay"; +}; + +&i2stx0 { + pinctrl-names = "default"; + pinctrl-0 = <&mclk_ext_pins>; + status = "okay"; +}; + +&i2stx1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2stx1_pins>; + status = "okay"; +}; + &mmc0 { max-frequency = <100000000>; assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; @@ -340,6 +358,46 @@ GPOEN_SYS_I2C6_DATA, }; }; + i2srx_pins: i2srx-0 { + clk-sd-pins { + pinmux = <GPIOMUX(38, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_BCLK)>, + <GPIOMUX(63, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_LRCK)>, + <GPIOMUX(38, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2STX1_BCLK)>, + <GPIOMUX(63, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2STX1_LRCK)>, + <GPIOMUX(61, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_SDIN0)>; + input-enable; + }; + }; + + i2stx1_pins: i2stx1-0 { + sd-pins { + pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + input-disable; + }; + }; + + mclk_ext_pins: mclk-ext-0 { + mclk-ext-pins { + pinmux = <GPIOMUX(4, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_MCLK_EXT)>; + input-enable; + }; + }; + mmc0_pins: mmc0-0 { rst-pins { pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index e85464c328d0..621b68c02ea8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -512,6 +512,30 @@ tdm: tdm@10090000 { status = "disabled"; }; + i2srx: i2s@100e0000 { + compatible = "starfive,jh7110-i2srx"; + reg = <0x0 0x100e0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2SRX_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>, + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>, + <&i2srx_bclk_ext>, + <&i2srx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>, + <&syscrg JH7110_SYSRST_I2SRX_BCLK>; + dmas = <0>, <&dma 24>; + dma-names = "tx", "rx"; + starfive,syscon = <&sys_syscon 0x18 0x2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + usb0: usb@10100000 { compatible = "starfive,jh7110-usb"; ranges = <0x0 0x0 0x10100000 0x100000>; @@ -736,6 +760,47 @@ spi6: spi@120a0000 { status = "disabled"; }; + i2stx0: i2s@120b0000 { + compatible = "starfive,jh7110-i2stx0"; + reg = <0x0 0x120b0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX0_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner","mclk_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>, + <&syscrg JH7110_SYSRST_I2STX0_BCLK>; + dmas = <&dma 47>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2stx1: i2s@120c0000 { + compatible = "starfive,jh7110-i2stx1"; + reg = <0x0 0x120c0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX1_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2STX1_BCLK>, + <&syscrg JH7110_SYSCLK_I2STX1_LRCK>, + <&i2stx_bclk_ext>, + <&i2stx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX1_APB>, + <&syscrg JH7110_SYSRST_I2STX1_BCLK>; + dmas = <&dma 48>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>; -- 2.43.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 2024-09-12 2:55 ` [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 WangYuli @ 2024-09-12 10:23 ` Hal Feng 2024-09-12 10:40 ` Conor Dooley 0 siblings, 1 reply; 7+ messages in thread From: Hal Feng @ 2024-09-12 10:23 UTC (permalink / raw) To: WangYuli, stable@vger.kernel.org, gregkh@linuxfoundation.org, sashal@kernel.org, William Qiu, emil.renner.berthing@canonical.com, conor.dooley@microchip.com, Xingyu Wu, Walker Chen, robh@kernel.org Cc: kernel@esmil.dk, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, richardcochran@gmail.com, netdev@vger.kernel.org > On 12.09.24 10:55, WangYuli wrote: > > From: Xingyu Wu <xingyu.wu@starfivetech.com> > > [ Upstream commit 92cfc35838b2a4006abb9e3bafc291b56f135d01 ] > > Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the StarFive JH7110 > SoC. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Reviewed-by: Walker Chen <walker.chen@starfivetech.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: WangYuli <wangyuli@uniontech.com> > --- > .../jh7110-starfive-visionfive-2.dtsi | 58 +++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 +++++++++++++++++++ > 2 files changed, 123 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 4874e3bb42ab..caa59b9b2f19 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -202,6 +202,24 @@ &i2c6 { > status = "okay"; > }; > > +&i2srx { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2srx_pins>; > + status = "okay"; > +}; > + > +&i2stx0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mclk_ext_pins>; > + status = "okay"; > +}; > + > +&i2stx1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2stx1_pins>; > + status = "okay"; > +}; > + > &mmc0 { > max-frequency = <100000000>; > assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; @@ - > 340,6 +358,46 @@ GPOEN_SYS_I2C6_DATA, > }; > }; > > + i2srx_pins: i2srx-0 { > + clk-sd-pins { > + pinmux = <GPIOMUX(38, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_SYS_I2SRX_BCLK)>, > + <GPIOMUX(63, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_SYS_I2SRX_LRCK)>, > + <GPIOMUX(38, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_SYS_I2STX1_BCLK)>, > + <GPIOMUX(63, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_SYS_I2STX1_LRCK)>, > + <GPIOMUX(61, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_SYS_I2SRX_SDIN0)>; > + input-enable; > + }; > + }; > + > + i2stx1_pins: i2stx1-0 { > + sd-pins { > + pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0, > + GPOEN_ENABLE, > + GPI_NONE)>; > + bias-disable; > + input-disable; > + }; > + }; > + > + mclk_ext_pins: mclk-ext-0 { > + mclk-ext-pins { > + pinmux = <GPIOMUX(4, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_SYS_MCLK_EXT)>; > + input-enable; > + }; > + }; > + > mmc0_pins: mmc0-0 { > rst-pins { > pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, The above changes had been reverted in commit e0503d47e93d in the mainline. Is it appropriate to merge this patch into the stable branch? https://lore.kernel.org/all/20240415125033.86909-1-hannah.peuckmann@canonical.com/ Best regards, Hal > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi > b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index e85464c328d0..621b68c02ea8 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -512,6 +512,30 @@ tdm: tdm@10090000 { > status = "disabled"; > }; > > + i2srx: i2s@100e0000 { > + compatible = "starfive,jh7110-i2srx"; > + reg = <0x0 0x100e0000 0x0 0x1000>; > + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>, > + <&syscrg JH7110_SYSCLK_I2SRX_APB>, > + <&syscrg JH7110_SYSCLK_MCLK>, > + <&syscrg JH7110_SYSCLK_MCLK_INNER>, > + <&mclk_ext>, > + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>, > + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>, > + <&i2srx_bclk_ext>, > + <&i2srx_lrck_ext>; > + clock-names = "i2sclk", "apb", "mclk", > + "mclk_inner", "mclk_ext", "bclk", > + "lrck", "bclk_ext", "lrck_ext"; > + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>, > + <&syscrg JH7110_SYSRST_I2SRX_BCLK>; > + dmas = <0>, <&dma 24>; > + dma-names = "tx", "rx"; > + starfive,syscon = <&sys_syscon 0x18 0x2>; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > usb0: usb@10100000 { > compatible = "starfive,jh7110-usb"; > ranges = <0x0 0x0 0x10100000 0x100000>; @@ - > 736,6 +760,47 @@ spi6: spi@120a0000 { > status = "disabled"; > }; > > + i2stx0: i2s@120b0000 { > + compatible = "starfive,jh7110-i2stx0"; > + reg = <0x0 0x120b0000 0x0 0x1000>; > + clocks = <&syscrg > JH7110_SYSCLK_I2STX0_BCLK_MST>, > + <&syscrg JH7110_SYSCLK_I2STX0_APB>, > + <&syscrg JH7110_SYSCLK_MCLK>, > + <&syscrg JH7110_SYSCLK_MCLK_INNER>, > + <&mclk_ext>; > + clock-names = "i2sclk", "apb", "mclk", > + "mclk_inner","mclk_ext"; > + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>, > + <&syscrg JH7110_SYSRST_I2STX0_BCLK>; > + dmas = <&dma 47>; > + dma-names = "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > + i2stx1: i2s@120c0000 { > + compatible = "starfive,jh7110-i2stx1"; > + reg = <0x0 0x120c0000 0x0 0x1000>; > + clocks = <&syscrg > JH7110_SYSCLK_I2STX1_BCLK_MST>, > + <&syscrg JH7110_SYSCLK_I2STX1_APB>, > + <&syscrg JH7110_SYSCLK_MCLK>, > + <&syscrg JH7110_SYSCLK_MCLK_INNER>, > + <&mclk_ext>, > + <&syscrg JH7110_SYSCLK_I2STX1_BCLK>, > + <&syscrg JH7110_SYSCLK_I2STX1_LRCK>, > + <&i2stx_bclk_ext>, > + <&i2stx_lrck_ext>; > + clock-names = "i2sclk", "apb", "mclk", > + "mclk_inner", "mclk_ext", "bclk", > + "lrck", "bclk_ext", "lrck_ext"; > + resets = <&syscrg JH7110_SYSRST_I2STX1_APB>, > + <&syscrg JH7110_SYSRST_I2STX1_BCLK>; > + dmas = <&dma 48>; > + dma-names = "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > sfctemp: temperature-sensor@120e0000 { > compatible = "starfive,jh7110-temp"; > reg = <0x0 0x120e0000 0x0 0x10000>; > -- > 2.43.4 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 2024-09-12 10:23 ` Hal Feng @ 2024-09-12 10:40 ` Conor Dooley 2024-09-12 11:19 ` WangYuli 0 siblings, 1 reply; 7+ messages in thread From: Conor Dooley @ 2024-09-12 10:40 UTC (permalink / raw) To: Hal Feng Cc: WangYuli, stable@vger.kernel.org, gregkh@linuxfoundation.org, sashal@kernel.org, William Qiu, emil.renner.berthing@canonical.com, Xingyu Wu, Walker Chen, robh@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, richardcochran@gmail.com, netdev@vger.kernel.org [-- Attachment #1: Type: text/plain, Size: 1919 bytes --] On Thu, Sep 12, 2024 at 10:23:09AM +0000, Hal Feng wrote: > > On 12.09.24 10:55, WangYuli wrote: > > + i2srx_pins: i2srx-0 { > > + clk-sd-pins { > > + pinmux = <GPIOMUX(38, GPOUT_LOW, > > + GPOEN_DISABLE, > > + GPI_SYS_I2SRX_BCLK)>, > > + <GPIOMUX(63, GPOUT_LOW, > > + GPOEN_DISABLE, > > + GPI_SYS_I2SRX_LRCK)>, > > + <GPIOMUX(38, GPOUT_LOW, > > + GPOEN_DISABLE, > > + GPI_SYS_I2STX1_BCLK)>, > > + <GPIOMUX(63, GPOUT_LOW, > > + GPOEN_DISABLE, > > + GPI_SYS_I2STX1_LRCK)>, > > + <GPIOMUX(61, GPOUT_LOW, > > + GPOEN_DISABLE, > > + GPI_SYS_I2SRX_SDIN0)>; > > + input-enable; > > + }; > > + }; > > + > > + i2stx1_pins: i2stx1-0 { > > + sd-pins { > > + pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0, > > + GPOEN_ENABLE, > > + GPI_NONE)>; > > + bias-disable; > > + input-disable; > > + }; > > + }; > > + > > + mclk_ext_pins: mclk-ext-0 { > > + mclk-ext-pins { > > + pinmux = <GPIOMUX(4, GPOUT_LOW, > > + GPOEN_DISABLE, > > + GPI_SYS_MCLK_EXT)>; > > + input-enable; > > + }; > > + }; > > + > > mmc0_pins: mmc0-0 { > > rst-pins { > > pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, > > The above changes had been reverted in commit e0503d47e93d in the mainline. > Is it appropriate to merge this patch into the stable branch? > > https://lore.kernel.org/all/20240415125033.86909-1-hannah.peuckmann@canonical.com/ Hah, I had gone looking this morning because I had a hunch that there was some missing fix this series didn't, but couldn't remember what it was. I completely forgot that some of this was non-present overlay related stuff that had had to be reverted. So yes, if it had to be reverted in mainline, it shouldn't get backported. Thanks for spotting that Hal. Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 2024-09-12 10:40 ` Conor Dooley @ 2024-09-12 11:19 ` WangYuli 2024-09-12 18:48 ` Conor Dooley 0 siblings, 1 reply; 7+ messages in thread From: WangYuli @ 2024-09-12 11:19 UTC (permalink / raw) To: Conor Dooley, Hal Feng Cc: stable@vger.kernel.org, gregkh@linuxfoundation.org, sashal@kernel.org, William Qiu, emil.renner.berthing@canonical.com, Xingyu Wu, Walker Chen, robh@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, richardcochran@gmail.com, netdev@vger.kernel.org [-- Attachment #1.1.1: Type: text/plain, Size: 2120 bytes --] On 2024/9/12 18:40, Conor Dooley wrote: > On Thu, Sep 12, 2024 at 10:23:09AM +0000, Hal Feng wrote: >>> On 12.09.24 10:55, WangYuli wrote: >>> + i2srx_pins: i2srx-0 { >>> + clk-sd-pins { >>> + pinmux = <GPIOMUX(38, GPOUT_LOW, >>> + GPOEN_DISABLE, >>> + GPI_SYS_I2SRX_BCLK)>, >>> + <GPIOMUX(63, GPOUT_LOW, >>> + GPOEN_DISABLE, >>> + GPI_SYS_I2SRX_LRCK)>, >>> + <GPIOMUX(38, GPOUT_LOW, >>> + GPOEN_DISABLE, >>> + GPI_SYS_I2STX1_BCLK)>, >>> + <GPIOMUX(63, GPOUT_LOW, >>> + GPOEN_DISABLE, >>> + GPI_SYS_I2STX1_LRCK)>, >>> + <GPIOMUX(61, GPOUT_LOW, >>> + GPOEN_DISABLE, >>> + GPI_SYS_I2SRX_SDIN0)>; >>> + input-enable; >>> + }; >>> + }; >>> + >>> + i2stx1_pins: i2stx1-0 { >>> + sd-pins { >>> + pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0, >>> + GPOEN_ENABLE, >>> + GPI_NONE)>; >>> + bias-disable; >>> + input-disable; >>> + }; >>> + }; >>> + >>> + mclk_ext_pins: mclk-ext-0 { >>> + mclk-ext-pins { >>> + pinmux = <GPIOMUX(4, GPOUT_LOW, >>> + GPOEN_DISABLE, >>> + GPI_SYS_MCLK_EXT)>; >>> + input-enable; >>> + }; >>> + }; >>> + >>> mmc0_pins: mmc0-0 { >>> rst-pins { >>> pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, >> The above changes had been reverted in commit e0503d47e93d in the mainline. >> Is it appropriate to merge this patch into the stable branch? >> >> https://lore.kernel.org/all/20240415125033.86909-1-hannah.peuckmann@canonical.com/ > Hah, I had gone looking this morning because I had a hunch that there > was some missing fix this series didn't, but couldn't remember what it > was. I completely forgot that some of this was non-present overlay > related stuff that had had to be reverted. > > So yes, if it had to be reverted in mainline, it shouldn't get > backported. Thanks for spotting that Hal. > > Cheers, > Conor. Got it. Thanks for pointing that out, and sorry for bothering you all... And thank you for your patience... Thanks, -- WangYuli [-- Attachment #1.1.2: OpenPGP public key --] [-- Type: application/pgp-keys, Size: 645 bytes --] [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 236 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 2024-09-12 11:19 ` WangYuli @ 2024-09-12 18:48 ` Conor Dooley 0 siblings, 0 replies; 7+ messages in thread From: Conor Dooley @ 2024-09-12 18:48 UTC (permalink / raw) To: WangYuli Cc: Conor Dooley, Hal Feng, stable@vger.kernel.org, gregkh@linuxfoundation.org, sashal@kernel.org, William Qiu, emil.renner.berthing@canonical.com, Xingyu Wu, Walker Chen, robh@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, richardcochran@gmail.com, netdev@vger.kernel.org [-- Attachment #1: Type: text/plain, Size: 2417 bytes --] On Thu, Sep 12, 2024 at 07:19:05PM +0800, WangYuli wrote: > On 2024/9/12 18:40, Conor Dooley wrote: > > > On Thu, Sep 12, 2024 at 10:23:09AM +0000, Hal Feng wrote: > > > > On 12.09.24 10:55, WangYuli wrote: > > > > + i2srx_pins: i2srx-0 { > > > > + clk-sd-pins { > > > > + pinmux = <GPIOMUX(38, GPOUT_LOW, > > > > + GPOEN_DISABLE, > > > > + GPI_SYS_I2SRX_BCLK)>, > > > > + <GPIOMUX(63, GPOUT_LOW, > > > > + GPOEN_DISABLE, > > > > + GPI_SYS_I2SRX_LRCK)>, > > > > + <GPIOMUX(38, GPOUT_LOW, > > > > + GPOEN_DISABLE, > > > > + GPI_SYS_I2STX1_BCLK)>, > > > > + <GPIOMUX(63, GPOUT_LOW, > > > > + GPOEN_DISABLE, > > > > + GPI_SYS_I2STX1_LRCK)>, > > > > + <GPIOMUX(61, GPOUT_LOW, > > > > + GPOEN_DISABLE, > > > > + GPI_SYS_I2SRX_SDIN0)>; > > > > + input-enable; > > > > + }; > > > > + }; > > > > + > > > > + i2stx1_pins: i2stx1-0 { > > > > + sd-pins { > > > > + pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0, > > > > + GPOEN_ENABLE, > > > > + GPI_NONE)>; > > > > + bias-disable; > > > > + input-disable; > > > > + }; > > > > + }; > > > > + > > > > + mclk_ext_pins: mclk-ext-0 { > > > > + mclk-ext-pins { > > > > + pinmux = <GPIOMUX(4, GPOUT_LOW, > > > > + GPOEN_DISABLE, > > > > + GPI_SYS_MCLK_EXT)>; > > > > + input-enable; > > > > + }; > > > > + }; > > > > + > > > > mmc0_pins: mmc0-0 { > > > > rst-pins { > > > > pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, > > > The above changes had been reverted in commit e0503d47e93d in the mainline. > > > Is it appropriate to merge this patch into the stable branch? > > > > > > https://lore.kernel.org/all/20240415125033.86909-1-hannah.peuckmann@canonical.com/ > > Hah, I had gone looking this morning because I had a hunch that there > > was some missing fix this series didn't, but couldn't remember what it > > was. I completely forgot that some of this was non-present overlay > > related stuff that had had to be reverted. > > > > So yes, if it had to be reverted in mainline, it shouldn't get > > backported. Thanks for spotting that Hal. > > > Got it. Thanks for pointing that out, and sorry for bothering you all... Patch 1 still seems like it could be backported though, even if these pwmdac patches are not suitble? [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 6.6 v2 4/4] riscv: dts: starfive: Add JH7110 PWM-DAC support [not found] <20240912025539.1928223-1-wangyuli@uniontech.com> 2024-09-12 2:55 ` [PATCH 6.6 v2 2/4] riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1 WangYuli 2024-09-12 2:55 ` [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 WangYuli @ 2024-09-12 2:55 ` WangYuli 2 siblings, 0 replies; 7+ messages in thread From: WangYuli @ 2024-09-12 2:55 UTC (permalink / raw) To: stable, gregkh, sashal, william.qiu, emil.renner.berthing, conor.dooley, wangyuli, xingyu.wu, walker.chen, robh, hal.feng Cc: kernel, robh+dt, krzysztof.kozlowski+dt, conor+dt, paul.walmsley, palmer, aou, devicetree, linux-riscv, linux-kernel, richardcochran, netdev From: Hal Feng <hal.feng@starfivetech.com> [ Upstream commit be326bee09374a2ebd18cb5af8fcd6f1e7825260 ] Add PWM-DAC support for StarFive JH7110 SoC. Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: WangYuli <wangyuli@uniontech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 49 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++ 2 files changed, 62 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index caa59b9b2f19..0e077f2f02d1 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -40,6 +40,33 @@ gpio-restart { gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; priority = <224>; }; + + pwmdac_codec: pwmdac-codec { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sound-pwmdac { + compatible = "simple-audio-card"; + simple-audio-card,name = "StarFive-PWMDAC-Sound-Card"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "left_j"; + bitclock-master = <&sndcpu0>; + frame-master = <&sndcpu0>; + + sndcpu0: cpu { + sound-dai = <&pwmdac>; + }; + + codec { + sound-dai = <&pwmdac_codec>; + }; + }; + }; }; &dvp_clk { @@ -253,6 +280,12 @@ &mmc1 { status = "okay"; }; +&pwmdac { + pinctrl-names = "default"; + pinctrl-0 = <&pwmdac_pins>; + status = "okay"; +}; + &qspi { #address-cells = <1>; #size-cells = <0>; @@ -463,6 +496,22 @@ GPOEN_SYS_SDIO1_DATA3, }; }; + pwmdac_pins: pwmdac-0 { + pwmdac-pins { + pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, + GPOEN_ENABLE, + GPI_NONE)>, + <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + drive-strength = <2>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 621b68c02ea8..9f31dec57c0d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -536,6 +536,19 @@ i2srx: i2s@100e0000 { status = "disabled"; }; + pwmdac: pwmdac@100b0000 { + compatible = "starfive,jh7110-pwmdac"; + reg = <0x0 0x100b0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>, + <&syscrg JH7110_SYSCLK_PWMDAC_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>; + dmas = <&dma 22>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + usb0: usb@10100000 { compatible = "starfive,jh7110-usb"; ranges = <0x0 0x0 0x10100000 0x100000>; -- 2.43.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
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[not found] <20240912025539.1928223-1-wangyuli@uniontech.com>
2024-09-12 2:55 ` [PATCH 6.6 v2 2/4] riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1 WangYuli
2024-09-12 2:55 ` [PATCH 6.6 v2 3/4] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 WangYuli
2024-09-12 10:23 ` Hal Feng
2024-09-12 10:40 ` Conor Dooley
2024-09-12 11:19 ` WangYuli
2024-09-12 18:48 ` Conor Dooley
2024-09-12 2:55 ` [PATCH 6.6 v2 4/4] riscv: dts: starfive: Add JH7110 PWM-DAC support WangYuli
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