* [PATCH 00/26] clk: mediatek: Add MT8196 clock support
@ 2025-03-07 3:26 Guangjie Song
2025-03-07 3:26 ` [PATCH 01/26] clk: mediatek: Add defines for vote Guangjie Song
` (25 more replies)
0 siblings, 26 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
This series is based on linux-next, tag: next-20250306.
Changes:
- Update clock driver for MT8196
- Add MT8196 clock support
Guangjie Song (26):
clk: mediatek: Add defines for vote
clk: mediatek: Support voting for pll
clk: mediatek: Support voting for mux
clk: mediatek: Support voting for gate
clk: mediatek: Add gate ops without disable
dt-bindings: clock: mediatek: Add new MT8196 clock
clk: mediatek: Add MT8196 apmixedsys clock support
clk: mediatek: Add MT8196 apmixedsys_gp2 clock support
clk: mediatek: Add MT8196 topckgen clock support
clk: mediatek: Add MT8196 topckgen2 clock support
clk: mediatek: Add MT8196 vlpckgen clock support
clk: mediatek: Add MT8196 peripheral clock support
clk: mediatek: Add MT8196 adsp clock support
clk: mediatek: Add MT8196 i2c clock support
clk: mediatek: Add MT8196 mcu clock support
clk: mediatek: Add MT8196 mdpsys clock support
clk: mediatek: Add MT8196 mfg clock support
clk: mediatek: Add MT8196 disp0 clock support
clk: mediatek: Add MT8196 disp1 clock support
clk: mediatek: Add MT8196 disp-ao clock support
clk: mediatek: Add MT8196 ovl0 clock support
clk: mediatek: Add MT8196 ovl1 clock support
clk: mediatek: Add MT8196 pextpsys clock support
clk: mediatek: Add MT8196 ufssys clock support
clk: mediatek: Add MT8196 vdecsys clock support
clk: mediatek: Add MT8196 vencsys clock support
.../bindings/clock/mediatek,mt8196-clock.yaml | 66 +
.../clock/mediatek,mt8196-sys-clock.yaml | 63 +
drivers/clk/mediatek/Kconfig | 78 +
drivers/clk/mediatek/Makefile | 14 +
drivers/clk/mediatek/clk-gate.c | 236 ++-
drivers/clk/mediatek/clk-gate.h | 6 +
drivers/clk/mediatek/clk-mt8196-adsp.c | 291 ++++
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 146 ++
.../clk/mediatek/clk-mt8196-apmixedsys_gp2.c | 154 ++
drivers/clk/mediatek/clk-mt8196-disp0.c | 247 +++
drivers/clk/mediatek/clk-mt8196-disp1.c | 260 +++
.../clk/mediatek/clk-mt8196-imp_iic_wrap.c | 211 +++
drivers/clk/mediatek/clk-mt8196-mcu.c | 167 ++
drivers/clk/mediatek/clk-mt8196-mdpsys.c | 357 ++++
drivers/clk/mediatek/clk-mt8196-mfg.c | 143 ++
drivers/clk/mediatek/clk-mt8196-ovl0.c | 256 +++
drivers/clk/mediatek/clk-mt8196-ovl1.c | 255 +++
drivers/clk/mediatek/clk-mt8196-peri_ao.c | 218 +++
drivers/clk/mediatek/clk-mt8196-pextp.c | 162 ++
drivers/clk/mediatek/clk-mt8196-topckgen.c | 1373 +++++++++++++++
drivers/clk/mediatek/clk-mt8196-topckgen2.c | 701 ++++++++
drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 107 ++
drivers/clk/mediatek/clk-mt8196-vdec.c | 449 +++++
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c | 100 ++
drivers/clk/mediatek/clk-mt8196-venc.c | 413 +++++
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 777 +++++++++
drivers/clk/mediatek/clk-mtk.h | 10 +
drivers/clk/mediatek/clk-mux.c | 198 ++-
drivers/clk/mediatek/clk-mux.h | 79 +
drivers/clk/mediatek/clk-pll.c | 51 +-
drivers/clk/mediatek/clk-pll.h | 5 +
include/dt-bindings/clock/mt8196-clk.h | 1503 +++++++++++++++++
32 files changed, 9086 insertions(+), 10 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
create mode 100644 drivers/clk/mediatek/clk-mt8196-adsp.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys_gp2.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-disp0.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-disp1.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-mcu.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-mdpsys.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-mfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl0.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl1.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-peri_ao.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen2.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-venc.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-vlpckgen.c
create mode 100644 include/dt-bindings/clock/mt8196-clk.h
--
2.45.2
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 01/26] clk: mediatek: Add defines for vote
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
@ 2025-03-07 3:26 ` Guangjie Song
2025-03-07 3:26 ` [PATCH 02/26] clk: mediatek: Support voting for pll Guangjie Song
` (24 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Clock supports voting mechanism. If any xPU votes clock on, the clock keep
on.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/clk-mtk.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c17fe1c2d732..ba3917aabd83 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -20,6 +20,16 @@
#define MHZ (1000 * 1000)
+#define MTK_WAIT_VOTE_PREPARE_CNT 200000
+#define MTK_WAIT_VOTE_PREPARE_US 1
+#define MTK_WAIT_VOTE_DONE_CNT 5000000
+#define MTK_WAIT_VOTE_DONE_US 1
+#define MTK_WAIT_FENC_DONE_CNT 5000000
+#define MTK_WAIT_FENC_DONE_US 1
+
+#define CLK_USE_VOTE BIT(30)
+#define CLK_FENC_ENABLE BIT(31)
+
struct platform_device;
/*
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 02/26] clk: mediatek: Support voting for pll
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
2025-03-07 3:26 ` [PATCH 01/26] clk: mediatek: Add defines for vote Guangjie Song
@ 2025-03-07 3:26 ` Guangjie Song
2025-03-07 3:26 ` [PATCH 03/26] clk: mediatek: Support voting for mux Guangjie Song
` (23 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add data fields and ops to support voting for pll.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/clk-pll.c | 51 +++++++++++++++++++++++++++++++++-
drivers/clk/mediatek/clk-pll.h | 5 ++++
2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index ce453e1718e5..fdaa4ee74608 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -13,6 +13,7 @@
#include <linux/of_address.h>
#include <linux/slab.h>
+#include "clk-mtk.h"
#include "clk-pll.h"
#define MHZ (1000 * 1000)
@@ -37,6 +38,13 @@ int mtk_pll_is_prepared(struct clk_hw *hw)
return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
}
+static int mtk_pll_fenc_is_prepared(struct clk_hw *hw)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+
+ return (((readl(pll->fenc_addr) & pll->fenc_mask) != 0) || (pll->onoff_cnt != 0));
+}
+
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
u32 pcw, int postdiv)
{
@@ -274,6 +282,30 @@ void mtk_pll_unprepare(struct clk_hw *hw)
writel(r, pll->pwr_addr);
}
+static int mtk_pll_fenc_prepare(struct clk_hw *hw)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+
+ if (pll->onoff_cnt == 1) {
+ pr_err("%s: %s is already prepared\n", __func__, clk_hw_get_name(hw));
+ return -EPERM;
+ }
+
+ pll->onoff_cnt = 1;
+
+ return 0;
+}
+
+static void mtk_pll_fenc_unprepare(struct clk_hw *hw)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+
+ if (pll->onoff_cnt == 0)
+ pr_err("%s: %s is not prepared\n", __func__, clk_hw_get_name(hw));
+ else
+ pll->onoff_cnt = 0;
+}
+
const struct clk_ops mtk_pll_ops = {
.is_prepared = mtk_pll_is_prepared,
.prepare = mtk_pll_prepare,
@@ -283,6 +315,15 @@ const struct clk_ops mtk_pll_ops = {
.set_rate = mtk_pll_set_rate,
};
+static const struct clk_ops mtk_pll_fenc_ops = {
+ .is_prepared = mtk_pll_fenc_is_prepared,
+ .prepare = mtk_pll_fenc_prepare,
+ .unprepare = mtk_pll_fenc_unprepare,
+ .recalc_rate = mtk_pll_recalc_rate,
+ .round_rate = mtk_pll_round_rate,
+ .set_rate = mtk_pll_set_rate,
+};
+
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
const struct mtk_pll_data *data,
void __iomem *base,
@@ -313,6 +354,11 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
init.name = data->name;
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
+ if (data->flags & CLK_FENC_ENABLE) {
+ pll->fenc_addr = base + data->fenc_sta_ofs;
+ pll->fenc_mask = BIT(data->fenc_sta_bit);
+ }
+
init.ops = pll_ops;
if (data->parent_name)
init.parent_names = &data->parent_name;
@@ -338,7 +384,10 @@ struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
if (!pll)
return ERR_PTR(-ENOMEM);
- hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
+ if (data->flags & CLK_FENC_ENABLE)
+ hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_fenc_ops);
+ else
+ hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
if (IS_ERR(hw))
kfree(pll);
diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index 285c8db958b3..3a1e48006e34 100644
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -29,6 +29,7 @@ struct mtk_pll_data {
u32 reg;
u32 pwr_reg;
u32 en_mask;
+ u32 fenc_sta_ofs;
u32 pd_reg;
u32 tuner_reg;
u32 tuner_en_reg;
@@ -49,6 +50,7 @@ struct mtk_pll_data {
u32 en_reg;
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
u8 pcw_chg_bit;
+ u8 fenc_sta_bit;
};
/*
@@ -69,6 +71,9 @@ struct mtk_clk_pll {
void __iomem *pcw_chg_addr;
void __iomem *en_addr;
const struct mtk_pll_data *data;
+ void __iomem *fenc_addr;
+ u32 fenc_mask;
+ u32 onoff_cnt;
};
int mtk_clk_register_plls(struct device_node *node,
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 03/26] clk: mediatek: Support voting for mux
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
2025-03-07 3:26 ` [PATCH 01/26] clk: mediatek: Add defines for vote Guangjie Song
2025-03-07 3:26 ` [PATCH 02/26] clk: mediatek: Support voting for pll Guangjie Song
@ 2025-03-07 3:26 ` Guangjie Song
2025-03-10 14:12 ` AngeloGioacchino Del Regno
2025-03-07 3:27 ` [PATCH 04/26] clk: mediatek: Support voting for gate Guangjie Song
` (22 subsequent siblings)
25 siblings, 1 reply; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add data fields, defines and ops to support voting for mux.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/clk-mux.c | 198 ++++++++++++++++++++++++++++++++-
drivers/clk/mediatek/clk-mux.h | 79 +++++++++++++
2 files changed, 275 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
index 60990296450b..8a2c89cb3cd5 100644
--- a/drivers/clk/mediatek/clk-mux.c
+++ b/drivers/clk/mediatek/clk-mux.c
@@ -15,11 +15,13 @@
#include <linux/spinlock.h>
#include <linux/slab.h>
+#include "clk-mtk.h"
#include "clk-mux.h"
struct mtk_clk_mux {
struct clk_hw hw;
struct regmap *regmap;
+ struct regmap *vote_regmap;
const struct mtk_mux *data;
spinlock_t *lock;
bool reparent;
@@ -30,6 +32,46 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
return container_of(hw, struct mtk_clk_mux, hw);
}
+static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ unsigned long flags = 0;
+ u32 val = 0;
+ int i = 0;
+ int ret = 0;
+
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+
+ regmap_write(mux->regmap, mux->data->clr_ofs, BIT(mux->data->gate_shift));
+
+ while (1) {
+ regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
+
+ if ((val & BIT(mux->data->fenc_shift)) != 0)
+ break;
+
+ if (i < MTK_WAIT_FENC_DONE_CNT) {
+ udelay(MTK_WAIT_FENC_DONE_US);
+ } else {
+ pr_err("%s wait fenc done timeout\n", clk_hw_get_name(hw));
+ ret = -EBUSY;
+ break;
+ }
+
+ i++;
+ }
+
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+
+ return ret;
+}
+
static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
@@ -70,6 +112,16 @@ static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
BIT(mux->data->gate_shift));
}
+static int mtk_clk_mux_fenc_is_enabled(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 val = 0;
+
+ regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
+
+ return (val & BIT(mux->data->fenc_shift)) != 0;
+}
+
static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
@@ -80,6 +132,106 @@ static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
return (val & BIT(mux->data->gate_shift)) == 0;
}
+static int mtk_clk_vote_mux_is_enabled(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 val = 0;
+
+ regmap_read(mux->vote_regmap, mux->data->vote_set_ofs, &val);
+
+ return (val & BIT(mux->data->gate_shift)) != 0;
+}
+
+static int mtk_clk_vote_mux_is_done(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 val = 0;
+
+ regmap_read(mux->vote_regmap, mux->data->vote_sta_ofs, &val);
+
+ return (val & BIT(mux->data->gate_shift)) != 0;
+}
+
+static int mtk_clk_mux_vote_fenc_enable(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 val = 0, val2 = 0;
+ bool is_done = false;
+ int i = 0;
+
+ regmap_write(mux->vote_regmap, mux->data->vote_set_ofs, BIT(mux->data->gate_shift));
+
+ while (!mtk_clk_vote_mux_is_enabled(hw)) {
+ if (i < MTK_WAIT_VOTE_PREPARE_CNT) {
+ udelay(MTK_WAIT_VOTE_PREPARE_US);
+ } else {
+ pr_err("%s mux prepare timeout(%x)\n", clk_hw_get_name(hw), val);
+ return -EBUSY;
+ }
+
+ i++;
+ }
+
+ i = 0;
+
+ while (1) {
+ if (!is_done)
+ regmap_read(mux->vote_regmap, mux->data->vote_sta_ofs, &val);
+
+ if (((val & BIT(mux->data->gate_shift)) != 0))
+ is_done = true;
+
+ if (is_done) {
+ regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val2);
+ if ((val2 & BIT(mux->data->fenc_shift)) != 0)
+ break;
+ }
+
+ if (i < MTK_WAIT_VOTE_DONE_CNT) {
+ udelay(MTK_WAIT_VOTE_DONE_US);
+ } else {
+ pr_err("%s mux enable timeout(%x %x)\n", clk_hw_get_name(hw), val, val2);
+ return -EBUSY;
+ }
+
+ i++;
+ }
+
+ return 0;
+}
+
+static void mtk_clk_mux_vote_disable(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ int i = 0;
+
+ regmap_write(mux->vote_regmap, mux->data->vote_clr_ofs, BIT(mux->data->gate_shift));
+
+ while (mtk_clk_vote_mux_is_enabled(hw)) {
+ if (i < MTK_WAIT_VOTE_PREPARE_CNT) {
+ udelay(MTK_WAIT_VOTE_PREPARE_US);
+ } else {
+ pr_err("%s mux unprepare timeout\n", clk_hw_get_name(hw));
+ return;
+ }
+
+ i++;
+ }
+
+ i = 0;
+
+ while (!mtk_clk_vote_mux_is_done(hw)) {
+ if (i < MTK_WAIT_VOTE_DONE_CNT) {
+ udelay(MTK_WAIT_VOTE_DONE_US);
+ } else {
+ pr_err("%s mux disable timeout\n", clk_hw_get_name(hw));
+ return;
+ }
+
+ i++;
+ }
+}
+
static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
@@ -151,6 +303,12 @@ static int mtk_clk_mux_determine_rate(struct clk_hw *hw,
return clk_mux_determine_rate_flags(hw, req, mux->data->flags);
}
+static void mtk_clk_mux_vote_fenc_disable_unused(struct clk_hw *hw)
+{
+ mtk_clk_mux_vote_fenc_enable(hw);
+ mtk_clk_mux_vote_disable(hw);
+}
+
const struct clk_ops mtk_mux_clr_set_upd_ops = {
.get_parent = mtk_clk_mux_get_parent,
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
@@ -168,9 +326,31 @@ const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
};
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
+const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops = {
+ .enable = mtk_clk_mux_fenc_enable_setclr,
+ .disable = mtk_clk_mux_disable_setclr,
+ .is_enabled = mtk_clk_mux_fenc_is_enabled,
+ .get_parent = mtk_clk_mux_get_parent,
+ .set_parent = mtk_clk_mux_set_parent_setclr_lock,
+ .determine_rate = mtk_clk_mux_determine_rate,
+};
+EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops);
+
+const struct clk_ops mtk_mux_vote_fenc_ops = {
+ .enable = mtk_clk_mux_vote_fenc_enable,
+ .disable = mtk_clk_mux_vote_disable,
+ .is_enabled = mtk_clk_mux_fenc_is_enabled,
+ .get_parent = mtk_clk_mux_get_parent,
+ .set_parent = mtk_clk_mux_set_parent_setclr_lock,
+ .determine_rate = mtk_clk_mux_determine_rate,
+ .disable_unused = mtk_clk_mux_vote_fenc_disable_unused,
+};
+EXPORT_SYMBOL_GPL(mtk_mux_vote_fenc_ops);
+
static struct clk_hw *mtk_clk_register_mux(struct device *dev,
const struct mtk_mux *mux,
struct regmap *regmap,
+ struct regmap *vote_regmap,
spinlock_t *lock)
{
struct mtk_clk_mux *clk_mux;
@@ -185,9 +365,17 @@ static struct clk_hw *mtk_clk_register_mux(struct device *dev,
init.flags = mux->flags;
init.parent_names = mux->parent_names;
init.num_parents = mux->num_parents;
- init.ops = mux->ops;
+ if (mux->flags & CLK_USE_VOTE) {
+ if (vote_regmap)
+ init.ops = mux->ops;
+ else
+ init.ops = mux->dma_ops;
+ } else {
+ init.ops = mux->ops;
+ }
clk_mux->regmap = regmap;
+ clk_mux->vote_regmap = vote_regmap;
clk_mux->data = mux;
clk_mux->lock = lock;
clk_mux->hw.init = &init;
@@ -220,6 +408,7 @@ int mtk_clk_register_muxes(struct device *dev,
struct clk_hw_onecell_data *clk_data)
{
struct regmap *regmap;
+ struct regmap *vote_regmap = NULL;
struct clk_hw *hw;
int i;
@@ -238,8 +427,13 @@ int mtk_clk_register_muxes(struct device *dev,
continue;
}
- hw = mtk_clk_register_mux(dev, mux, regmap, lock);
+ if (mux->vote_comp) {
+ vote_regmap = syscon_regmap_lookup_by_phandle(node, mux->vote_comp);
+ if (IS_ERR(vote_regmap))
+ vote_regmap = NULL;
+ }
+ hw = mtk_clk_register_mux(dev, mux, regmap, vote_regmap, lock);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", mux->name,
hw);
diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
index 943ad1d7ce4b..c202ad42be16 100644
--- a/drivers/clk/mediatek/clk-mux.h
+++ b/drivers/clk/mediatek/clk-mux.h
@@ -21,6 +21,7 @@ struct mtk_mux {
int id;
const char *name;
const char * const *parent_names;
+ const char *vote_comp;
const u8 *parent_index;
unsigned int flags;
@@ -28,13 +29,19 @@ struct mtk_mux {
u32 set_ofs;
u32 clr_ofs;
u32 upd_ofs;
+ u32 vote_set_ofs;
+ u32 vote_clr_ofs;
+ u32 vote_sta_ofs;
+ u32 fenc_sta_mon_ofs;
u8 mux_shift;
u8 mux_width;
u8 gate_shift;
s8 upd_shift;
+ u8 fenc_shift;
const struct clk_ops *ops;
+ const struct clk_ops *dma_ops;
signed char num_parents;
};
@@ -77,6 +84,8 @@ struct mtk_mux {
extern const struct clk_ops mtk_mux_clr_set_upd_ops;
extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
+extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops;
+extern const struct clk_ops mtk_mux_vote_fenc_ops;
#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
@@ -118,6 +127,76 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
mtk_mux_clr_set_upd_ops)
+#define MUX_MULT_VOTE_FENC_FLAGS(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _vote_comp,\
+ _vote_sta_ofs, _vote_set_ofs, _vote_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd, \
+ _fenc_sta_mon_ofs, _fenc, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .mux_ofs = _mux_ofs, \
+ .set_ofs = _mux_set_ofs, \
+ .clr_ofs = _mux_clr_ofs, \
+ .vote_comp = _vote_comp, \
+ .vote_sta_ofs = _vote_sta_ofs, \
+ .vote_set_ofs = _vote_set_ofs, \
+ .vote_clr_ofs = _vote_clr_ofs, \
+ .upd_ofs = _upd_ofs, \
+ .fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \
+ .mux_shift = _shift, \
+ .mux_width = _width, \
+ .gate_shift = _gate, \
+ .upd_shift = _upd, \
+ .fenc_shift = _fenc, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_USE_VOTE | (_flags), \
+ .ops = &mtk_mux_vote_fenc_ops, \
+ .dma_ops = &mtk_mux_gate_fenc_clr_set_upd_ops, \
+ }
+
+#define MUX_MULT_VOTE_FENC(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _vote_comp,\
+ _vote_sta_ofs, _vote_set_ofs, _vote_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd, \
+ _fenc_sta_mon_ofs, _fenc) \
+ MUX_MULT_VOTE_FENC_FLAGS(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _vote_comp,\
+ _vote_sta_ofs, _vote_set_ofs, _vote_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd, \
+ _fenc_sta_mon_ofs, _fenc, 0)
+
+#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd, \
+ _fenc_sta_mon_ofs, _fenc, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .mux_ofs = _mux_ofs, \
+ .set_ofs = _mux_set_ofs, \
+ .clr_ofs = _mux_clr_ofs, \
+ .upd_ofs = _upd_ofs, \
+ .fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \
+ .mux_shift = _shift, \
+ .mux_width = _width, \
+ .gate_shift = _gate, \
+ .upd_shift = _upd, \
+ .fenc_shift = _fenc, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = _flags, \
+ .ops = &mtk_mux_gate_fenc_clr_set_upd_ops, \
+ }
+
+#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd, \
+ _fenc_sta_mon_ofs, _fenc) \
+ MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd, \
+ _fenc_sta_mon_ofs, _fenc, 0)
+
int mtk_clk_register_muxes(struct device *dev,
const struct mtk_mux *muxes,
int num, struct device_node *node,
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 04/26] clk: mediatek: Support voting for gate
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (2 preceding siblings ...)
2025-03-07 3:26 ` [PATCH 03/26] clk: mediatek: Support voting for mux Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 05/26] clk: mediatek: Add gate ops without disable Guangjie Song
` (21 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add data fields and ops to support voting for gate.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/clk-gate.c | 230 +++++++++++++++++++++++++++++++-
drivers/clk/mediatek/clk-gate.h | 5 +
2 files changed, 228 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 67d9e741c5e7..be6cf4a6d246 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -12,14 +12,19 @@
#include <linux/slab.h>
#include <linux/types.h>
+#include "clk-mtk.h"
#include "clk-gate.h"
struct mtk_clk_gate {
struct clk_hw hw;
struct regmap *regmap;
+ struct regmap *vote_regmap;
int set_ofs;
int clr_ofs;
int sta_ofs;
+ int vote_set_ofs;
+ int vote_clr_ofs;
+ int vote_sta_ofs;
u8 bit;
};
@@ -100,6 +105,143 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
mtk_cg_clr_bit(hw);
}
+static int mtk_cg_vote_is_set(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 val = 0;
+
+ regmap_read(cg->vote_regmap, cg->vote_set_ofs, &val);
+
+ val &= BIT(cg->bit);
+
+ return val != 0;
+}
+
+static int mtk_cg_vote_is_done(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 val = 0;
+
+ regmap_read(cg->vote_regmap, cg->vote_sta_ofs, &val);
+
+ val &= BIT(cg->bit);
+
+ return val != 0;
+}
+
+static int __cg_vote_enable(struct clk_hw *hw, bool inv)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 val = 0, val2 = 0;
+ bool is_done = false;
+ int i = 0;
+
+ regmap_write(cg->vote_regmap, cg->vote_set_ofs, BIT(cg->bit));
+
+ while (!mtk_cg_vote_is_set(hw)) {
+ if (i < MTK_WAIT_VOTE_PREPARE_CNT) {
+ udelay(MTK_WAIT_VOTE_PREPARE_US);
+ } else {
+ pr_err("%s cg prepare timeout\n", clk_hw_get_name(hw));
+ return -EBUSY;
+ }
+
+ i++;
+ }
+
+ i = 0;
+
+ while (1) {
+ if (!is_done)
+ regmap_read(cg->vote_regmap, cg->vote_sta_ofs, &val);
+
+ if ((val & BIT(cg->bit)) != 0)
+ is_done = true;
+
+ if (is_done) {
+ regmap_read(cg->regmap, cg->sta_ofs, &val2);
+ if ((inv && (val2 & BIT(cg->bit)) != 0) ||
+ (!inv && (val2 & BIT(cg->bit)) == 0))
+ break;
+ }
+
+ if (i < MTK_WAIT_VOTE_DONE_CNT) {
+ udelay(MTK_WAIT_VOTE_DONE_US);
+ } else {
+ pr_err("%s cg enable timeout(%x %x)\n", clk_hw_get_name(hw), val, val2);
+
+ if (inv)
+ regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
+ else
+ regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
+
+ return -EBUSY;
+ }
+
+ i++;
+ }
+
+ return 0;
+}
+
+static int mtk_cg_vote_enable(struct clk_hw *hw)
+{
+ return __cg_vote_enable(hw, false);
+}
+
+static int mtk_cg_vote_enable_inv(struct clk_hw *hw)
+{
+ return __cg_vote_enable(hw, true);
+}
+
+static void mtk_cg_vote_disable(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 val;
+ int i = 0;
+
+ /* dummy read to clr idle signal of hw voter bus */
+ regmap_read(cg->vote_regmap, cg->vote_clr_ofs, &val);
+
+ regmap_write(cg->vote_regmap, cg->vote_clr_ofs, BIT(cg->bit));
+
+ while (mtk_cg_vote_is_set(hw)) {
+ if (i < MTK_WAIT_VOTE_PREPARE_CNT) {
+ udelay(MTK_WAIT_VOTE_PREPARE_US);
+ } else {
+ pr_err("%s cg unprepare timeout\n", clk_hw_get_name(hw));
+ return;
+ }
+
+ i++;
+ }
+
+ i = 0;
+
+ while (!mtk_cg_vote_is_done(hw)) {
+ if (i < MTK_WAIT_VOTE_DONE_CNT) {
+ udelay(MTK_WAIT_VOTE_DONE_US);
+ } else {
+ pr_err("%s cg disable timeout\n", clk_hw_get_name(hw));
+ return;
+ }
+
+ i++;
+ }
+}
+
+static void mtk_cg_vote_disable_unused(struct clk_hw *hw)
+{
+ mtk_cg_vote_enable(hw);
+ mtk_cg_vote_disable(hw);
+}
+
+static void mtk_cg_vote_disable_unused_inv(struct clk_hw *hw)
+{
+ mtk_cg_vote_enable_inv(hw);
+ mtk_cg_vote_disable(hw);
+}
+
static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
{
mtk_cg_clr_bit_no_setclr(hw);
@@ -138,6 +280,22 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
+const struct clk_ops mtk_clk_gate_ops_vote = {
+ .is_enabled = mtk_cg_bit_is_cleared,
+ .enable = mtk_cg_vote_enable,
+ .disable = mtk_cg_vote_disable,
+ .disable_unused = mtk_cg_vote_disable_unused,
+};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_vote);
+
+const struct clk_ops mtk_clk_gate_ops_vote_inv = {
+ .is_enabled = mtk_cg_bit_is_set,
+ .enable = mtk_cg_vote_enable_inv,
+ .disable = mtk_cg_vote_disable,
+ .disable_unused = mtk_cg_vote_disable_unused_inv,
+};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_vote_inv);
+
const struct clk_ops mtk_clk_gate_ops_no_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable_no_setclr,
@@ -190,6 +348,53 @@ static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name
return &cg->hw;
}
+static struct clk_hw *mtk_clk_register_gate_vote(struct device *dev,
+ const struct mtk_gate *gate,
+ struct regmap *regmap,
+ struct regmap *vote_regmap)
+{
+ struct mtk_clk_gate *cg;
+ int ret;
+ struct clk_init_data init = {};
+
+ cg = kzalloc(sizeof(*cg), GFP_KERNEL);
+ if (!cg)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = gate->name;
+ init.flags = gate->flags | CLK_SET_RATE_PARENT;
+ init.parent_names = gate->parent_name ? &gate->parent_name : NULL;
+ init.num_parents = gate->parent_name ? 1 : 0;
+ if (vote_regmap)
+ init.ops = gate->ops;
+ else
+ init.ops = gate->dma_ops;
+
+ cg->regmap = regmap;
+ cg->vote_regmap = vote_regmap;
+ if (gate->regs) {
+ cg->set_ofs = gate->regs->set_ofs;
+ cg->clr_ofs = gate->regs->clr_ofs;
+ cg->sta_ofs = gate->regs->sta_ofs;
+ }
+ if (gate->vote_regs) {
+ cg->vote_set_ofs = gate->vote_regs->set_ofs;
+ cg->vote_clr_ofs = gate->vote_regs->clr_ofs;
+ cg->vote_sta_ofs = gate->vote_regs->sta_ofs;
+ }
+ cg->bit = gate->shift;
+
+ cg->hw.init = &init;
+
+ ret = clk_hw_register(dev, &cg->hw);
+ if (ret) {
+ kfree(cg);
+ return ERR_PTR(ret);
+ }
+
+ return &cg->hw;
+}
+
static void mtk_clk_unregister_gate(struct clk_hw *hw)
{
struct mtk_clk_gate *cg;
@@ -209,6 +414,7 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
int i;
struct clk_hw *hw;
struct regmap *regmap;
+ struct regmap *vote_regmap = NULL;
if (!clk_data)
return -ENOMEM;
@@ -228,13 +434,23 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
continue;
}
- hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
- regmap,
- gate->regs->set_ofs,
- gate->regs->clr_ofs,
- gate->regs->sta_ofs,
- gate->shift, gate->ops,
- gate->flags);
+ if (gate->flags & CLK_USE_VOTE) {
+ if (gate->vote_comp) {
+ vote_regmap = syscon_regmap_lookup_by_phandle(node, gate->vote_comp);
+ if (IS_ERR(vote_regmap))
+ vote_regmap = NULL;
+ }
+
+ hw = mtk_clk_register_gate_vote(dev, gate, regmap, vote_regmap);
+ } else {
+ hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
+ regmap,
+ gate->regs->set_ofs,
+ gate->regs->clr_ofs,
+ gate->regs->sta_ofs,
+ gate->shift, gate->ops,
+ gate->flags);
+ }
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", gate->name,
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 1a46b4c56fc5..7d93fc84ad51 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -19,6 +19,8 @@ extern const struct clk_ops mtk_clk_gate_ops_setclr;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
+extern const struct clk_ops mtk_clk_gate_ops_vote;
+extern const struct clk_ops mtk_clk_gate_ops_vote_inv;
struct mtk_gate_regs {
u32 sta_ofs;
@@ -30,9 +32,12 @@ struct mtk_gate {
int id;
const char *name;
const char *parent_name;
+ const char *vote_comp;
const struct mtk_gate_regs *regs;
+ const struct mtk_gate_regs *vote_regs;
int shift;
const struct clk_ops *ops;
+ const struct clk_ops *dma_ops;
unsigned long flags;
};
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 05/26] clk: mediatek: Add gate ops without disable
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (3 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 04/26] clk: mediatek: Support voting for gate Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock Guangjie Song
` (20 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add gate ops without .disable and the ops is used for gate which is not
allowed to disable but cannot affect its parent clock to disable.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/clk-gate.c | 6 ++++++
drivers/clk/mediatek/clk-gate.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index be6cf4a6d246..a36136c61252 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -273,6 +273,12 @@ const struct clk_ops mtk_clk_gate_ops_setclr = {
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
+const struct clk_ops mtk_clk_gate_ops_setclr_enable = {
+ .is_enabled = mtk_cg_bit_is_cleared,
+ .enable = mtk_cg_enable,
+};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_enable);
+
const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv,
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 7d93fc84ad51..d992e3edd457 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -16,6 +16,7 @@ struct device;
struct device_node;
extern const struct clk_ops mtk_clk_gate_ops_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_setclr_enable;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (4 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 05/26] clk: mediatek: Add gate ops without disable Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 4:16 ` Rob Herring (Arm)
` (2 more replies)
2025-03-07 3:27 ` [PATCH 07/26] clk: mediatek: Add MT8196 apmixedsys clock support Guangjie Song
` (19 subsequent siblings)
25 siblings, 3 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add the new binding documentation for system clock and functional clock
on Mediatek MT8196.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
.../bindings/clock/mediatek,mt8196-clock.yaml | 66 +
.../clock/mediatek,mt8196-sys-clock.yaml | 63 +
include/dt-bindings/clock/mt8196-clk.h | 1503 +++++++++++++++++
3 files changed, 1632 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
create mode 100644 include/dt-bindings/clock/mt8196-clk.h
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
new file mode 100644
index 000000000000..014c6c4840f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Functional Clock Controller for MT8196
+
+maintainers:
+ - Guangjie Song <guangjie.song@mediatek.com>
+
+description:
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The devices provide clock gate control in different IP blocks.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8196-audiosys
+ - mediatek,mt8196-dispsys0
+ - mediatek,mt8196-dispsys1
+ - mediatek,mt8196-disp_vdisp_ao_config
+ - mediatek,mt8196-imp_iic_wrap_c
+ - mediatek,mt8196-imp_iic_wrap_e
+ - mediatek,mt8196-imp_iic_wrap_n
+ - mediatek,mt8196-imp_iic_wrap_w
+ - mediatek,mt8196-mdpsys
+ - mediatek,mt8196-mdpsys1
+ - mediatek,mt8196-ovlsys0
+ - mediatek,mt8196-ovlsys1
+ - mediatek,mt8196-pericfg_ao
+ - mediatek,mt8196-pextp0cfg_ao
+ - mediatek,mt8196-pextp1cfg_ao
+ - mediatek,mt8196-ufscfg_ao
+ - mediatek,mt8196-vdecsys
+ - mediatek,mt8196-vdecsys_soc
+ - mediatek,mt8196-vencsys
+ - mediatek,mt8196-vencsys_c1
+ - mediatek,mt8196-vencsys_c2
+
+ reg:
+ description: Address range of the subsys.
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@16300000 {
+ compatible = "mediatek,mt8196-imp_iic_wrap_c";
+ reg = <0x16300000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
new file mode 100644
index 000000000000..0909b9f1ee52
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Clock Controller for MT8196
+
+maintainers:
+ - Guangjie Song <guangjie.song@mediatek.com>
+
+description:
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The apmixedsys, vlp_cksys, armpll, ccipll, mfgpll and ptppll provides most of PLLs
+ which generated from SoC 26m.
+ The cksys, cksys_gp2 and vlp_cksys provides dividers and muxes which provide the
+ clock source to other IP blocks.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8196-armpll_ll_pll_ctrl
+ - mediatek,mt8196-armpll_bl_pll_ctrl
+ - mediatek,mt8196-armpll_b_pll_ctrl
+ - mediatek,mt8196-apmixedsys
+ - mediatek,mt8196-apmixedsys_gp2
+ - mediatek,mt8196-ccipll_pll_ctrl
+ - mediatek,mt8196-cksys
+ - mediatek,mt8196-cksys_gp2
+ - mediatek,mt8196-mfgpll_pll_ctrl
+ - mediatek,mt8196-mfgpll_sc0_pll_ctrl
+ - mediatek,mt8196-mfgpll_sc1_pll_ctrl
+ - mediatek,mt8196-ptppll_pll_ctrl
+ - mediatek,mt8196-vlp_cksys
+ - const: syscon
+
+ reg:
+ description: Address range of the subsys.
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@10000800 {
+ compatible = "mediatek,mt8196-apmixedsys", "syscon";
+ reg = <0 0x10000800 0 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/mt8196-clk.h b/include/dt-bindings/clock/mt8196-clk.h
new file mode 100644
index 000000000000..9bd33c46f7de
--- /dev/null
+++ b/include/dt-bindings/clock/mt8196-clk.h
@@ -0,0 +1,1503 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8196_H
+#define _DT_BINDINGS_CLK_MT8196_H
+
+/* CKSYS */
+#define CLK_CK_AXI_SEL 0
+#define CLK_CK_MEM_SUB_SEL 1
+#define CLK_CK_IO_NOC_SEL 2
+#define CLK_CK_P_AXI_SEL 3
+#define CLK_CK_PEXTP0_AXI_SEL 4
+#define CLK_CK_PEXTP1_USB_AXI_SEL 5
+#define CLK_CK_P_FMEM_SUB_SEL 6
+#define CLK_CK_PEXPT0_MEM_SUB_SEL 7
+#define CLK_CK_PEXTP1_USB_MEM_SUB_SEL 8
+#define CLK_CK_P_NOC_SEL 9
+#define CLK_CK_EMI_N_SEL 10
+#define CLK_CK_EMI_S_SEL 11
+#define CLK_CK_AP2CONN_HOST_SEL 12
+#define CLK_CK_ATB_SEL 13
+#define CLK_CK_CIRQ_SEL 14
+#define CLK_CK_PBUS_156M_SEL 15
+#define CLK_CK_EFUSE_SEL 16
+#define CLK_CK_MCL3GIC_SEL 17
+#define CLK_CK_MCINFRA_SEL 18
+#define CLK_CK_DSP_SEL 19
+#define CLK_CK_MFG_REF_SEL 20
+#define CLK_CK_MFG_EB_SEL 21
+#define CLK_CK_UART_SEL 22
+#define CLK_CK_SPI0_BCLK_SEL 23
+#define CLK_CK_SPI1_BCLK_SEL 24
+#define CLK_CK_SPI2_BCLK_SEL 25
+#define CLK_CK_SPI3_BCLK_SEL 26
+#define CLK_CK_SPI4_BCLK_SEL 27
+#define CLK_CK_SPI5_BCLK_SEL 28
+#define CLK_CK_SPI6_BCLK_SEL 29
+#define CLK_CK_SPI7_BCLK_SEL 30
+#define CLK_CK_MSDC30_1_SEL 31
+#define CLK_CK_MSDC30_2_SEL 32
+#define CLK_CK_DISP_PWM_SEL 33
+#define CLK_CK_USB_TOP_1P_SEL 34
+#define CLK_CK_USB_XHCI_1P_SEL 35
+#define CLK_CK_USB_FMCNT_P1_SEL 36
+#define CLK_CK_I2C_P_SEL 37
+#define CLK_CK_I2C_EAST_SEL 38
+#define CLK_CK_I2C_WEST_SEL 39
+#define CLK_CK_I2C_NORTH_SEL 40
+#define CLK_CK_AES_UFSFDE_SEL 41
+#define CLK_CK_SEL 42
+#define CLK_CK_AUD_1_SEL 43
+#define CLK_CK_AUD_2_SEL 44
+#define CLK_CK_ADSP_SEL 45
+#define CLK_CK_ADSP_UARTHUB_BCLK_SEL 46
+#define CLK_CK_DPMAIF_MAIN_SEL 47
+#define CLK_CK_PWM_SEL 48
+#define CLK_CK_MCUPM_SEL 49
+#define CLK_CK_IPSEAST_SEL 50
+#define CLK_CK_TL_SEL 51
+#define CLK_CK_TL_P1_SEL 52
+#define CLK_CK_TL_P2_SEL 53
+#define CLK_CK_EMI_INTERFACE_546_SEL 54
+#define CLK_CK_SDF_SEL 55
+#define CLK_CK_UARTHUB_BCLK_SEL 56
+#define CLK_CK_DPSW_CMP_26M_SEL 57
+#define CLK_CK_SMAPCK_SEL 58
+#define CLK_CK_SSR_PKA_SEL 59
+#define CLK_CK_SSR_DMA_SEL 60
+#define CLK_CK_SSR_KDF_SEL 61
+#define CLK_CK_SSR_RNG_SEL 62
+#define CLK_CK_SPU0_SEL 63
+#define CLK_CK_SPU1_SEL 64
+#define CLK_CK_DXCC_SEL 65
+#define CLK_CK_APLL_I2SIN0_MCK_SEL 66
+#define CLK_CK_APLL_I2SIN1_MCK_SEL 67
+#define CLK_CK_APLL_I2SIN2_MCK_SEL 68
+#define CLK_CK_APLL_I2SIN3_MCK_SEL 69
+#define CLK_CK_APLL_I2SIN4_MCK_SEL 70
+#define CLK_CK_APLL_I2SIN6_MCK_SEL 71
+#define CLK_CK_APLL_I2SOUT0_MCK_SEL 72
+#define CLK_CK_APLL_I2SOUT1_MCK_SEL 73
+#define CLK_CK_APLL_I2SOUT2_MCK_SEL 74
+#define CLK_CK_APLL_I2SOUT3_MCK_SEL 75
+#define CLK_CK_APLL_I2SOUT4_MCK_SEL 76
+#define CLK_CK_APLL_I2SOUT6_MCK_SEL 77
+#define CLK_CK_APLL_FMI2S_MCK_SEL 78
+#define CLK_CK_APLL_TDMOUT_MCK_SEL 79
+#define CLK_CK_APLL12_CK_DIV_I2SIN0 80
+#define CLK_CK_APLL12_CK_DIV_I2SIN1 81
+#define CLK_CK_APLL12_CK_DIV_I2SIN2 82
+#define CLK_CK_APLL12_CK_DIV_I2SIN3 83
+#define CLK_CK_APLL12_CK_DIV_I2SIN4 84
+#define CLK_CK_APLL12_CK_DIV_I2SIN6 85
+#define CLK_CK_APLL12_CK_DIV_I2SOUT0 86
+#define CLK_CK_APLL12_CK_DIV_I2SOUT1 87
+#define CLK_CK_APLL12_CK_DIV_I2SOUT2 88
+#define CLK_CK_APLL12_CK_DIV_I2SOUT3 89
+#define CLK_CK_APLL12_CK_DIV_I2SOUT4 90
+#define CLK_CK_APLL12_CK_DIV_I2SOUT6 91
+#define CLK_CK_APLL12_CK_DIV_FMI2S 92
+#define CLK_CK_APLL12_CK_DIV_TDMOUT_M 93
+#define CLK_CK_APLL12_CK_DIV_TDMOUT_B 94
+#define CLK_CK_MAINPLL_D3 95
+#define CLK_CK_MAINPLL_D4 96
+#define CLK_CK_MAINPLL_D4_D2 97
+#define CLK_CK_MAINPLL_D4_D4 98
+#define CLK_CK_MAINPLL_D4_D8 99
+#define CLK_CK_MAINPLL_D5 100
+#define CLK_CK_MAINPLL_D5_D2 101
+#define CLK_CK_MAINPLL_D5_D4 102
+#define CLK_CK_MAINPLL_D5_D8 103
+#define CLK_CK_MAINPLL_D6 104
+#define CLK_CK_MAINPLL_D6_D2 105
+#define CLK_CK_MAINPLL_D7 106
+#define CLK_CK_MAINPLL_D7_D2 107
+#define CLK_CK_MAINPLL_D7_D4 108
+#define CLK_CK_MAINPLL_D7_D8 109
+#define CLK_CK_MAINPLL_D9 110
+#define CLK_CK_UNIVPLL_D4 111
+#define CLK_CK_UNIVPLL_D4_D2 112
+#define CLK_CK_UNIVPLL_D4_D4 113
+#define CLK_CK_UNIVPLL_D4_D8 114
+#define CLK_CK_UNIVPLL_D5 115
+#define CLK_CK_UNIVPLL_D5_D2 116
+#define CLK_CK_UNIVPLL_D5_D4 117
+#define CLK_CK_UNIVPLL_D6 118
+#define CLK_CK_UNIVPLL_D6_D2 119
+#define CLK_CK_UNIVPLL_D6_D4 120
+#define CLK_CK_UNIVPLL_D6_D8 121
+#define CLK_CK_UNIVPLL_D6_D16 122
+#define CLK_CK_UNIVPLL_192M 123
+#define CLK_CK_UNIVPLL_192M_D4 124
+#define CLK_CK_UNIVPLL_192M_D8 125
+#define CLK_CK_UNIVPLL_192M_D16 126
+#define CLK_CK_UNIVPLL_192M_D32 127
+#define CLK_CK_UNIVPLL_192M_D10 128
+#define CLK_CK_APLL1 129
+#define CLK_CK_APLL1_D4 130
+#define CLK_CK_APLL1_D8 131
+#define CLK_CK_APLL2 132
+#define CLK_CK_APLL2_D4 133
+#define CLK_CK_APLL2_D8 134
+#define CLK_CK_ADSPPLL 135
+#define CLK_CK_EMIPLL1 136
+#define CLK_CK_TVDPLL1_D2 137
+#define CLK_CK_MSDCPLL_D2 138
+#define CLK_CK_CLKRTC 139
+#define CLK_CK_TCK_26M_MX9 140
+#define CLK_CK_F26M 141
+#define CLK_CK_F26M_CK_D2 142
+#define CLK_CK_OSC 143
+#define CLK_CK_OSC_D2 144
+#define CLK_CK_OSC_D3 145
+#define CLK_CK_OSC_D4 146
+#define CLK_CK_OSC_D5 147
+#define CLK_CK_OSC_D7 148
+#define CLK_CK_OSC_D8 149
+#define CLK_CK_OSC_D10 150
+#define CLK_CK_OSC_D14 151
+#define CLK_CK_OSC_D20 152
+#define CLK_CK_OSC_D32 153
+#define CLK_CK_OSC_D40 154
+#define CLK_CK_OSC3 155
+#define CLK_CK_P_AXI 156
+#define CLK_CK_PEXTP0_AXI 157
+#define CLK_CK_PEXTP1_USB_AXI 158
+#define CLK_CK_PEXPT0_MEM_SUB 159
+#define CLK_CK_PEXTP1_USB_MEM_SUB 160
+#define CLK_CK_UART 161
+#define CLK_CK_SPI0_BCLK 162
+#define CLK_CK_SPI1_BCLK 163
+#define CLK_CK_SPI2_BCLK 164
+#define CLK_CK_SPI3_BCLK 165
+#define CLK_CK_SPI4_BCLK 166
+#define CLK_CK_SPI5_BCLK 167
+#define CLK_CK_SPI6_BCLK 168
+#define CLK_CK_SPI7_BCLK 169
+#define CLK_CK_MSDC30_1 170
+#define CLK_CK_MSDC30_2 171
+#define CLK_CK_I2C_PERI 172
+#define CLK_CK_I2C_EAST 173
+#define CLK_CK_I2C_WEST 174
+#define CLK_CK_I2C_NORTH 175
+#define CLK_CK_AES_UFSFDE 176
+#define CLK_CK_UFS 177
+#define CLK_CK_AUD_1 178
+#define CLK_CK_AUD_2 179
+#define CLK_CK_DPMAIF_MAIN 180
+#define CLK_CK_PWM 181
+#define CLK_CK_TL 182
+#define CLK_CK_TL_P1 183
+#define CLK_CK_TL_P2 184
+#define CLK_CK_SSR_RNG 185
+#define CLK_CK_SPU0 186
+#define CLK_CK_DXCC 187
+#define CLK_CK_SFLASH_SEL 188
+#define CLK_CK_SFLASH 189
+#define CLK_CK_NR_CLK 190
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_MAINPLL 0
+#define CLK_APMIXED_UNIVPLL 1
+#define CLK_APMIXED_MSDCPLL 2
+#define CLK_APMIXED_ADSPPLL 3
+#define CLK_APMIXED_EMIPLL 4
+#define CLK_APMIXED_EMIPLL2 5
+#define CLK_APMIXED_NR_CLK 6
+
+/* CKSYS_GP2 */
+#define CLK_CK2_SENINF0_SEL 0
+#define CLK_CK2_SENINF1_SEL 1
+#define CLK_CK2_SENINF2_SEL 2
+#define CLK_CK2_SENINF3_SEL 3
+#define CLK_CK2_SENINF4_SEL 4
+#define CLK_CK2_SENINF5_SEL 5
+#define CLK_CK2_IMG1_SEL 6
+#define CLK_CK2_IPE_SEL 7
+#define CLK_CK2_CAM_SEL 8
+#define CLK_CK2_CAMTM_SEL 9
+#define CLK_CK2_DPE_SEL 10
+#define CLK_CK2_VDEC_SEL 11
+#define CLK_CK2_CCUSYS_SEL 12
+#define CLK_CK2_CCUTM_SEL 13
+#define CLK_CK2_VENC_SEL 14
+#define CLK_CK2_DP1_SEL 15
+#define CLK_CK2_DP0_SEL 16
+#define CLK_CK2_DISP_SEL 17
+#define CLK_CK2_MDP_SEL 18
+#define CLK_CK2_MMINFRA_SEL 19
+#define CLK_CK2_MMINFRA_SNOC_SEL 20
+#define CLK_CK2_MMUP_SEL 21
+#define CLK_CK2_MMINFRA_AO_SEL 22
+#define CLK_CK2_MAINPLL2_D2 23
+#define CLK_CK2_MAINPLL2_D3 24
+#define CLK_CK2_MAINPLL2_D4 25
+#define CLK_CK2_MAINPLL2_D4_D2 26
+#define CLK_CK2_MAINPLL2_D4_D4 27
+#define CLK_CK2_MAINPLL2_D5 28
+#define CLK_CK2_MAINPLL2_D5_D2 29
+#define CLK_CK2_MAINPLL2_D6 30
+#define CLK_CK2_MAINPLL2_D6_D2 31
+#define CLK_CK2_MAINPLL2_D7 32
+#define CLK_CK2_MAINPLL2_D7_D2 33
+#define CLK_CK2_MAINPLL2_D9 34
+#define CLK_CK2_UNIVPLL2_D3 35
+#define CLK_CK2_UNIVPLL2_D4 36
+#define CLK_CK2_UNIVPLL2_D4_D2 37
+#define CLK_CK2_UNIVPLL2_D5 38
+#define CLK_CK2_UNIVPLL2_D5_D2 39
+#define CLK_CK2_UNIVPLL2_D6 40
+#define CLK_CK2_UNIVPLL2_D6_D2 41
+#define CLK_CK2_UNIVPLL2_D6_D4 42
+#define CLK_CK2_UNIVPLL2_D7 43
+#define CLK_CK2_IMGPLL_D2 44
+#define CLK_CK2_IMGPLL_D4 45
+#define CLK_CK2_IMGPLL_D5 46
+#define CLK_CK2_IMGPLL_D5_D2 47
+#define CLK_CK2_MMPLL2_D3 48
+#define CLK_CK2_MMPLL2_D4 49
+#define CLK_CK2_MMPLL2_D4_D2 50
+#define CLK_CK2_MMPLL2_D5 51
+#define CLK_CK2_MMPLL2_D5_D2 52
+#define CLK_CK2_MMPLL2_D6 53
+#define CLK_CK2_MMPLL2_D6_D2 54
+#define CLK_CK2_MMPLL2_D7 55
+#define CLK_CK2_MMPLL2_D9 56
+#define CLK_CK2_TVDPLL1_D4 57
+#define CLK_CK2_TVDPLL1_D8 58
+#define CLK_CK2_TVDPLL1_D16 59
+#define CLK_CK2_TVDPLL2_D2 60
+#define CLK_CK2_TVDPLL2_D4 61
+#define CLK_CK2_TVDPLL2_D8 62
+#define CLK_CK2_TVDPLL2_D16 63
+#define CLK_CK2_CCUSYS 64
+#define CLK_CK2_VENC 65
+#define CLK_CK2_MMINFRA 66
+#define CLK_CK2_IMG1 67
+#define CLK_CK2_IPE 68
+#define CLK_CK2_CAM 69
+#define CLK_CK2_CAMTM 70
+#define CLK_CK2_DPE 71
+#define CLK_CK2_VDEC 72
+#define CLK_CK2_DP1 73
+#define CLK_CK2_DP0 74
+#define CLK_CK2_MDP 75
+#define CLK_CK2_DISP 76
+#define CLK_CK2_AVS_IMG 77
+#define CLK_CK2_AVS_VDEC 78
+#define CLK_CK2_DVO_SEL 79
+#define CLK_CK2_DVO_FAVT_SEL 80
+#define CLK_CK2_TVDPLL3_D2 81
+#define CLK_CK2_TVDPLL3_D4 82
+#define CLK_CK2_TVDPLL3_D8 83
+#define CLK_CK2_TVDPLL3_D16 84
+#define CLK_CK2_NR_CLK 85
+
+/* APMIXEDSYS_GP2 */
+#define CLK_APMIXED2_MAINPLL2 0
+#define CLK_APMIXED2_UNIVPLL2 1
+#define CLK_APMIXED2_MMPLL2 2
+#define CLK_APMIXED2_IMGPLL 3
+#define CLK_APMIXED2_TVDPLL1 4
+#define CLK_APMIXED2_TVDPLL2 5
+#define CLK_APMIXED2_TVDPLL3 6
+#define CLK_APMIXED2_NR_CLK 7
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_I2C5 0
+#define CLK_IMPE_I2C5_I2C 1
+#define CLK_IMPE_NR_CLK 2
+
+/* IMP_IIC_WRAP_W */
+#define CLK_IMPW_I2C0 0
+#define CLK_IMPW_I2C0_I2C 1
+#define CLK_IMPW_I2C3 2
+#define CLK_IMPW_I2C3_I2C 3
+#define CLK_IMPW_I2C6 4
+#define CLK_IMPW_I2C6_I2C 5
+#define CLK_IMPW_I2C10 6
+#define CLK_IMPW_I2C10_I2C 7
+#define CLK_IMPW_NR_CLK 8
+
+/* IMP_IIC_WRAP_N */
+#define CLK_IMPN_I2C1 0
+#define CLK_IMPN_I2C1_I2C 1
+#define CLK_IMPN_I2C2 2
+#define CLK_IMPN_I2C2_I2C 3
+#define CLK_IMPN_I2C4 4
+#define CLK_IMPN_I2C4_I2C 5
+#define CLK_IMPN_I2C7 6
+#define CLK_IMPN_I2C7_I2C 7
+#define CLK_IMPN_I2C8 8
+#define CLK_IMPN_I2C8_I2C 9
+#define CLK_IMPN_I2C9 10
+#define CLK_IMPN_I2C9_I2C 11
+#define CLK_IMPN_NR_CLK 12
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMPC_I2C11 0
+#define CLK_IMPC_I2C11_I2C 1
+#define CLK_IMPC_I2C12 2
+#define CLK_IMPC_I2C12_I2C 3
+#define CLK_IMPC_I2C13 4
+#define CLK_IMPC_I2C13_I2C 5
+#define CLK_IMPC_I2C14 6
+#define CLK_IMPC_I2C14_I2C 7
+#define CLK_IMPC_NR_CLK 8
+
+/* PERICFG_AO */
+#define CLK_PERAO_UART0_BCLK 0
+#define CLK_PERAO_UART0_BCLK_UART 1
+#define CLK_PERAO_UART1_BCLK 2
+#define CLK_PERAO_UART1_BCLK_UART 3
+#define CLK_PERAO_UART2_BCLK 4
+#define CLK_PERAO_UART2_BCLK_UART 5
+#define CLK_PERAO_UART3_BCLK 6
+#define CLK_PERAO_UART3_BCLK_UART 7
+#define CLK_PERAO_UART4_BCLK 8
+#define CLK_PERAO_UART4_BCLK_UART 9
+#define CLK_PERAO_UART5_BCLK 10
+#define CLK_PERAO_UART5_BCLK_UART 11
+#define CLK_PERAO_PWM_X16W_HCLK 12
+#define CLK_PERAO_PWM_X16W_HCLK_PWM 13
+#define CLK_PERAO_PWM_X16W_BCLK 14
+#define CLK_PERAO_PWM_X16W_BCLK_PWM 15
+#define CLK_PERAO_PWM_PWM_BCLK0 16
+#define CLK_PERAO_PWM_PWM_BCLK0_PWM 17
+#define CLK_PERAO_PWM_PWM_BCLK1 18
+#define CLK_PERAO_PWM_PWM_BCLK1_PWM 19
+#define CLK_PERAO_PWM_PWM_BCLK2 20
+#define CLK_PERAO_PWM_PWM_BCLK2_PWM 21
+#define CLK_PERAO_PWM_PWM_BCLK3 22
+#define CLK_PERAO_PWM_PWM_BCLK3_PWM 23
+#define CLK_PERAO_SPI0_BCLK 24
+#define CLK_PERAO_SPI0_BCLK_SPI 25
+#define CLK_PERAO_SPI1_BCLK 26
+#define CLK_PERAO_SPI1_BCLK_SPI 27
+#define CLK_PERAO_SPI2_BCLK 28
+#define CLK_PERAO_SPI2_BCLK_SPI 29
+#define CLK_PERAO_SPI3_BCLK 30
+#define CLK_PERAO_SPI3_BCLK_SPI 31
+#define CLK_PERAO_SPI4_BCLK 32
+#define CLK_PERAO_SPI4_BCLK_SPI 33
+#define CLK_PERAO_SPI5_BCLK 34
+#define CLK_PERAO_SPI5_BCLK_SPI 35
+#define CLK_PERAO_SPI6_BCLK 36
+#define CLK_PERAO_SPI6_BCLK_SPI 37
+#define CLK_PERAO_SPI7_BCLK 38
+#define CLK_PERAO_SPI7_BCLK_SPI 39
+#define CLK_PERAO_AP_DMA_X32W_BCLK 40
+#define CLK_PERAO_AP_DMA_X32W_BCLK_UART 41
+#define CLK_PERAO_AP_DMA_X32W_BCLK_I2C 42
+#define CLK_PERAO_MSDC1_MSDC_SRC 43
+#define CLK_PERAO_MSDC1_MSDC_SRC_MSDC1 44
+#define CLK_PERAO_MSDC1_HCLK 45
+#define CLK_PERAO_MSDC1_HCLK_MSDC1 46
+#define CLK_PERAO_MSDC1_AXI 47
+#define CLK_PERAO_MSDC1_AXI_MSDC1 48
+#define CLK_PERAO_MSDC1_HCLK_WRAP 49
+#define CLK_PERAO_MSDC1_HCLK_WRAP_MSDC1 50
+#define CLK_PERAO_MSDC2_MSDC_SRC 51
+#define CLK_PERAO_MSDC2_MSDC_SRC_MSDC2 52
+#define CLK_PERAO_MSDC2_HCLK 53
+#define CLK_PERAO_MSDC2_HCLK_MSDC2 54
+#define CLK_PERAO_MSDC2_AXI 55
+#define CLK_PERAO_MSDC2_AXI_MSDC2 56
+#define CLK_PERAO_MSDC2_HCLK_WRAP 57
+#define CLK_PERAO_MSDC2_HCLK_WRAP_MSDC2 58
+#define CLK_PERAO_FLASHIF_FLASH 59
+#define CLK_PERAO_FLASHIF_FLASH_FLASHIF 60
+#define CLK_PERAO_FLASHIF_27M 61
+#define CLK_PERAO_FLASHIF_27M_FLASHIF 62
+#define CLK_PERAO_FLASHIF_DRAM 63
+#define CLK_PERAO_FLASHIF_DRAM_FLASHIF 64
+#define CLK_PERAO_FLASHIF_AXI 65
+#define CLK_PERAO_FLASHIF_AXI_FLASHIF 66
+#define CLK_PERAO_FLASHIF_BCLK 67
+#define CLK_PERAO_FLASHIF_BCLK_FLASHIF 68
+#define CLK_PERAO_NR_CLK 69
+
+/* UFSCFG_AO */
+#define CLK_UFSAO_UNIPRO_TX_SYM 0
+#define CLK_UFSAO_UNIPRO_TX_SYM_UFS 1
+#define CLK_UFSAO_UNIPRO_RX_SYM0 2
+#define CLK_UFSAO_UNIPRO_RX_SYM0_UFS 3
+#define CLK_UFSAO_UNIPRO_RX_SYM1 4
+#define CLK_UFSAO_UNIPRO_RX_SYM1_UFS 5
+#define CLK_UFSAO_UNIPRO_SYS 6
+#define CLK_UFSAO_UNIPRO_SYS_UFS 7
+#define CLK_UFSAO_UNIPRO_SAP 8
+#define CLK_UFSAO_UNIPRO_SAP_UFS 9
+#define CLK_UFSAO_PHY_SAP 10
+#define CLK_UFSAO_PHY_SAP_UFS 11
+#define CLK_UFSAO_UFSHCI_UFS 12
+#define CLK_UFSAO_UFSHCI_UFS_UFS 13
+#define CLK_UFSAO_UFSHCI_AES 14
+#define CLK_UFSAO_UFSHCI_AES_UFS 15
+#define CLK_UFSAO_NR_CLK 16
+
+/* PEXTP0CFG_AO */
+#define CLK_PEXT_PEXTP_MAC_P0_TL 0
+#define CLK_PEXT_PEXTP_MAC_P0_TL_PCIE 1
+#define CLK_PEXT_PEXTP_MAC_P0_REF 2
+#define CLK_PEXT_PEXTP_MAC_P0_REF_PCIE 3
+#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS 4
+#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS_PCIE 5
+#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF 6
+#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF_PCIE 7
+#define CLK_PEXT_PEXTP_MAC_P0_AXI_250 8
+#define CLK_PEXT_PEXTP_MAC_P0_AXI_250_PCIE 9
+#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB 10
+#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB_PCIE 11
+#define CLK_PEXT_PEXTP_MAC_P0_PL_P 12
+#define CLK_PEXT_PEXTP_MAC_P0_PL_P_PCIE 13
+#define CLK_PEXT_PEXTP_VLP_AO_P0_LP 14
+#define CLK_PEXT_PEXTP_VLP_AO_P0_LP_PCIE 15
+#define CLK_PEXT_NR_CLK 16
+
+/* PEXTP1CFG_AO */
+#define CLK_PEXT1_PEXTP_MAC_P1_TL 0
+#define CLK_PEXT1_PEXTP_MAC_P1_TL_PCIE 1
+#define CLK_PEXT1_PEXTP_MAC_P1_REF 2
+#define CLK_PEXT1_PEXTP_MAC_P1_REF_PCIE 3
+#define CLK_PEXT1_PEXTP_MAC_P2_TL 4
+#define CLK_PEXT1_PEXTP_MAC_P2_TL_PCIE 5
+#define CLK_PEXT1_PEXTP_MAC_P2_REF 6
+#define CLK_PEXT1_PEXTP_MAC_P2_REF_PCIE 7
+#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS 8
+#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS_PCIE 9
+#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF 10
+#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF_PCIE 11
+#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS 12
+#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS_PCIE 13
+#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF 14
+#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF_PCIE 15
+#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250 16
+#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250_PCIE 17
+#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB 18
+#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB_PCIE 19
+#define CLK_PEXT1_PEXTP_MAC_P1_PL_P 20
+#define CLK_PEXT1_PEXTP_MAC_P1_PL_P_PCIE 21
+#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250 22
+#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250_PCIE 23
+#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB 24
+#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB_PCIE 25
+#define CLK_PEXT1_PEXTP_MAC_P2_PL_P 26
+#define CLK_PEXT1_PEXTP_MAC_P2_PL_P_PCIE 27
+#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP 28
+#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP_PCIE 29
+#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP 30
+#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP_PCIE 31
+#define CLK_PEXT1_NR_CLK 32
+
+/* VLP_CKSYS */
+#define CLK_VLP_CK_VLP_APLL1 0
+#define CLK_VLP_CK_VLP_APLL2 1
+#define CLK_VLP_CK_SCP_SEL 2
+#define CLK_VLP_CK_SCP_SPI_SEL 3
+#define CLK_VLP_CK_SCP_IIC_SEL 4
+#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 5
+#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 6
+#define CLK_VLP_CK_SPMI_M_TIA_32K_SEL 7
+#define CLK_VLP_CK_APXGPT_26M_BCLK_SEL 8
+#define CLK_VLP_CK_DPSW_SEL 9
+#define CLK_VLP_CK_DPSW_CENTRAL_SEL 10
+#define CLK_VLP_CK_SPMI_M_MST_SEL 11
+#define CLK_VLP_CK_DVFSRC_SEL 12
+#define CLK_VLP_CK_PWM_VLP_SEL 13
+#define CLK_VLP_CK_AXI_VLP_SEL 14
+#define CLK_VLP_CK_SYSTIMER_26M_SEL 15
+#define CLK_VLP_CK_SSPM_SEL 16
+#define CLK_VLP_CK_SRCK_SEL 17
+#define CLK_VLP_CK_CAMTG0_SEL 18
+#define CLK_VLP_CK_CAMTG1_SEL 19
+#define CLK_VLP_CK_CAMTG2_SEL 20
+#define CLK_VLP_CK_CAMTG3_SEL 21
+#define CLK_VLP_CK_CAMTG4_SEL 22
+#define CLK_VLP_CK_CAMTG5_SEL 23
+#define CLK_VLP_CK_CAMTG6_SEL 24
+#define CLK_VLP_CK_CAMTG7_SEL 25
+#define CLK_VLP_CK_SSPM_26M_SEL 26
+#define CLK_VLP_CK_ULPOSC_SSPM_SEL 27
+#define CLK_VLP_CK_VLP_PBUS_26M_SEL 28
+#define CLK_VLP_CK_DEBUG_ERR_FLAG_SEL 29
+#define CLK_VLP_CK_DPMSRDMA_SEL 30
+#define CLK_VLP_CK_VLP_PBUS_156M_SEL 31
+#define CLK_VLP_CK_SPM_SEL 32
+#define CLK_VLP_CK_MMINFRA_VLP_SEL 33
+#define CLK_VLP_CK_USB_TOP_SEL 34
+#define CLK_VLP_CK_USB_XHCI_SEL 35
+#define CLK_VLP_CK_NOC_VLP_SEL 36
+#define CLK_VLP_CK_AUDIO_H_SEL 37
+#define CLK_VLP_CK_AUD_ENGEN1_SEL 38
+#define CLK_VLP_CK_AUD_ENGEN2_SEL 39
+#define CLK_VLP_CK_AUD_INTBUS_SEL 40
+#define CLK_VLP_CK_SPVLP_26M_SEL 41
+#define CLK_VLP_CK_SPU0_VLP_SEL 42
+#define CLK_VLP_CK_SPU1_VLP_SEL 43
+#define CLK_VLP_CK_OSC3 44
+#define CLK_VLP_CK_CLKSQ 45
+#define CLK_VLP_CK_AUDIO_H 46
+#define CLK_VLP_CK_AUD_ENGEN1 47
+#define CLK_VLP_CK_AUD_ENGEN2 48
+#define CLK_VLP_CK_INFRA_26M 49
+#define CLK_VLP_CK_AUD_CLKSQ 50
+#define CLK_VLP_CK_NR_CLK 51
+
+/* AFE */
+#define CLK_AFE_PCM1 0
+#define CLK_AFE_PCM1_AFE 1
+#define CLK_AFE_PCM0 2
+#define CLK_AFE_PCM0_AFE 3
+#define CLK_AFE_CM2 4
+#define CLK_AFE_CM2_AFE 5
+#define CLK_AFE_CM1 6
+#define CLK_AFE_CM1_AFE 7
+#define CLK_AFE_CM0 8
+#define CLK_AFE_CM0_AFE 9
+#define CLK_AFE_STF 10
+#define CLK_AFE_STF_AFE 11
+#define CLK_AFE_HW_GAIN23 12
+#define CLK_AFE_HW_GAIN23_AFE 13
+#define CLK_AFE_HW_GAIN01 14
+#define CLK_AFE_HW_GAIN01_AFE 15
+#define CLK_AFE_FM_I2S 16
+#define CLK_AFE_FM_I2S_AFE 17
+#define CLK_AFE_MTKAIFV4 18
+#define CLK_AFE_MTKAIFV4_AFE 19
+#define CLK_AFE_UL2_ADC_HIRES_TML 20
+#define CLK_AFE_UL2_ADC_HIRES_TML_AFE 21
+#define CLK_AFE_UL2_ADC_HIRES 22
+#define CLK_AFE_UL2_ADC_HIRES_AFE 23
+#define CLK_AFE_UL2_TML 24
+#define CLK_AFE_UL2_TML_AFE 25
+#define CLK_AFE_UL2_ADC 26
+#define CLK_AFE_UL2_ADC_AFE 27
+#define CLK_AFE_UL1_ADC_HIRES_TML 28
+#define CLK_AFE_UL1_ADC_HIRES_TML_AFE 29
+#define CLK_AFE_UL1_ADC_HIRES 30
+#define CLK_AFE_UL1_ADC_HIRES_AFE 31
+#define CLK_AFE_UL1_TML 32
+#define CLK_AFE_UL1_TML_AFE 33
+#define CLK_AFE_UL1_ADC 34
+#define CLK_AFE_UL1_ADC_AFE 35
+#define CLK_AFE_UL0_ADC_HIRES_TML 36
+#define CLK_AFE_UL0_ADC_HIRES_TML_AFE 37
+#define CLK_AFE_UL0_ADC_HIRES 38
+#define CLK_AFE_UL0_ADC_HIRES_AFE 39
+#define CLK_AFE_UL0_TML 40
+#define CLK_AFE_UL0_TML_AFE 41
+#define CLK_AFE_UL0_ADC 42
+#define CLK_AFE_UL0_ADC_AFE 43
+#define CLK_AFE_ETDM_IN6 44
+#define CLK_AFE_ETDM_IN6_AFE 45
+#define CLK_AFE_ETDM_IN5 46
+#define CLK_AFE_ETDM_IN5_AFE 47
+#define CLK_AFE_ETDM_IN4 48
+#define CLK_AFE_ETDM_IN4_AFE 49
+#define CLK_AFE_ETDM_IN3 50
+#define CLK_AFE_ETDM_IN3_AFE 51
+#define CLK_AFE_ETDM_IN2 52
+#define CLK_AFE_ETDM_IN2_AFE 53
+#define CLK_AFE_ETDM_IN1 54
+#define CLK_AFE_ETDM_IN1_AFE 55
+#define CLK_AFE_ETDM_IN0 56
+#define CLK_AFE_ETDM_IN0_AFE 57
+#define CLK_AFE_ETDM_OUT6 58
+#define CLK_AFE_ETDM_OUT6_AFE 59
+#define CLK_AFE_ETDM_OUT5 60
+#define CLK_AFE_ETDM_OUT5_AFE 61
+#define CLK_AFE_ETDM_OUT4 62
+#define CLK_AFE_ETDM_OUT4_AFE 63
+#define CLK_AFE_ETDM_OUT3 64
+#define CLK_AFE_ETDM_OUT3_AFE 65
+#define CLK_AFE_ETDM_OUT2 66
+#define CLK_AFE_ETDM_OUT2_AFE 67
+#define CLK_AFE_ETDM_OUT1 68
+#define CLK_AFE_ETDM_OUT1_AFE 69
+#define CLK_AFE_ETDM_OUT0 70
+#define CLK_AFE_ETDM_OUT0_AFE 71
+#define CLK_AFE_TDM_OUT 72
+#define CLK_AFE_TDM_OUT_AFE 73
+#define CLK_AFE_GENERAL15_ASRC 74
+#define CLK_AFE_GENERAL15_ASRC_AFE 75
+#define CLK_AFE_GENERAL14_ASRC 76
+#define CLK_AFE_GENERAL14_ASRC_AFE 77
+#define CLK_AFE_GENERAL13_ASRC 78
+#define CLK_AFE_GENERAL13_ASRC_AFE 79
+#define CLK_AFE_GENERAL12_ASRC 80
+#define CLK_AFE_GENERAL12_ASRC_AFE 81
+#define CLK_AFE_GENERAL11_ASRC 82
+#define CLK_AFE_GENERAL11_ASRC_AFE 83
+#define CLK_AFE_GENERAL10_ASRC 84
+#define CLK_AFE_GENERAL10_ASRC_AFE 85
+#define CLK_AFE_GENERAL9_ASRC 86
+#define CLK_AFE_GENERAL9_ASRC_AFE 87
+#define CLK_AFE_GENERAL8_ASRC 88
+#define CLK_AFE_GENERAL8_ASRC_AFE 89
+#define CLK_AFE_GENERAL7_ASRC 90
+#define CLK_AFE_GENERAL7_ASRC_AFE 91
+#define CLK_AFE_GENERAL6_ASRC 92
+#define CLK_AFE_GENERAL6_ASRC_AFE 93
+#define CLK_AFE_GENERAL5_ASRC 94
+#define CLK_AFE_GENERAL5_ASRC_AFE 95
+#define CLK_AFE_GENERAL4_ASRC 96
+#define CLK_AFE_GENERAL4_ASRC_AFE 97
+#define CLK_AFE_GENERAL3_ASRC 98
+#define CLK_AFE_GENERAL3_ASRC_AFE 99
+#define CLK_AFE_GENERAL2_ASRC 100
+#define CLK_AFE_GENERAL2_ASRC_AFE 101
+#define CLK_AFE_GENERAL1_ASRC 102
+#define CLK_AFE_GENERAL1_ASRC_AFE 103
+#define CLK_AFE_GENERAL0_ASRC 104
+#define CLK_AFE_GENERAL0_ASRC_AFE 105
+#define CLK_AFE_CONNSYS_I2S_ASRC 106
+#define CLK_AFE_CONNSYS_I2S_ASRC_AFE 107
+#define CLK_AFE_AUDIO_HOPPING 108
+#define CLK_AFE_AUDIO_HOPPING_AFE 109
+#define CLK_AFE_AUDIO_F26M 110
+#define CLK_AFE_AUDIO_F26M_AFE 111
+#define CLK_AFE_APLL1 112
+#define CLK_AFE_APLL1_AFE 113
+#define CLK_AFE_APLL2 114
+#define CLK_AFE_APLL2_AFE 115
+#define CLK_AFE_H208M 116
+#define CLK_AFE_H208M_AFE 117
+#define CLK_AFE_APLL_TUNER2 118
+#define CLK_AFE_APLL_TUNER2_AFE 119
+#define CLK_AFE_APLL_TUNER1 120
+#define CLK_AFE_APLL_TUNER1_AFE 121
+#define CLK_AFE_NR_CLK 122
+
+/* DISPSYS_CONFIG */
+#define CLK_MM_CONFIG 0
+#define CLK_MM_CONFIG_DISP 1
+#define CLK_MM_DISP_MUTEX0 2
+#define CLK_MM_DISP_MUTEX0_DISP 3
+#define CLK_MM_DISP_AAL0 4
+#define CLK_MM_DISP_AAL0_PQ 5
+#define CLK_MM_DISP_AAL1 6
+#define CLK_MM_DISP_AAL1_PQ 7
+#define CLK_MM_DISP_C3D0 8
+#define CLK_MM_DISP_C3D0_PQ 9
+#define CLK_MM_DISP_C3D1 10
+#define CLK_MM_DISP_C3D1_PQ 11
+#define CLK_MM_DISP_C3D2 12
+#define CLK_MM_DISP_C3D2_PQ 13
+#define CLK_MM_DISP_C3D3 14
+#define CLK_MM_DISP_C3D3_PQ 15
+#define CLK_MM_DISP_CCORR0 16
+#define CLK_MM_DISP_CCORR0_PQ 17
+#define CLK_MM_DISP_CCORR1 18
+#define CLK_MM_DISP_CCORR1_PQ 19
+#define CLK_MM_DISP_CCORR2 20
+#define CLK_MM_DISP_CCORR2_PQ 21
+#define CLK_MM_DISP_CCORR3 22
+#define CLK_MM_DISP_CCORR3_PQ 23
+#define CLK_MM_DISP_CHIST0 24
+#define CLK_MM_DISP_CHIST0_PQ 25
+#define CLK_MM_DISP_CHIST1 26
+#define CLK_MM_DISP_CHIST1_PQ 27
+#define CLK_MM_DISP_COLOR0 28
+#define CLK_MM_DISP_COLOR0_PQ 29
+#define CLK_MM_DISP_COLOR1 30
+#define CLK_MM_DISP_COLOR1_PQ 31
+#define CLK_MM_DISP_DITHER0 32
+#define CLK_MM_DISP_DITHER0_PQ 33
+#define CLK_MM_DISP_DITHER1 34
+#define CLK_MM_DISP_DITHER1_PQ 35
+#define CLK_MM_DISP_DLI_ASYNC0 36
+#define CLK_MM_DISP_DLI_ASYNC0_DISP 37
+#define CLK_MM_DISP_DLI_ASYNC1 38
+#define CLK_MM_DISP_DLI_ASYNC1_DISP 39
+#define CLK_MM_DISP_DLI_ASYNC2 40
+#define CLK_MM_DISP_DLI_ASYNC2_DISP 41
+#define CLK_MM_DISP_DLI_ASYNC3 42
+#define CLK_MM_DISP_DLI_ASYNC3_DISP 43
+#define CLK_MM_DISP_DLI_ASYNC4 44
+#define CLK_MM_DISP_DLI_ASYNC4_DISP 45
+#define CLK_MM_DISP_DLI_ASYNC5 46
+#define CLK_MM_DISP_DLI_ASYNC5_DISP 47
+#define CLK_MM_DISP_DLI_ASYNC6 48
+#define CLK_MM_DISP_DLI_ASYNC6_DISP 49
+#define CLK_MM_DISP_DLI_ASYNC7 50
+#define CLK_MM_DISP_DLI_ASYNC7_DISP 51
+#define CLK_MM_DISP_DLI_ASYNC8 52
+#define CLK_MM_DISP_DLI_ASYNC8_DISP 53
+#define CLK_MM_DISP_DLI_ASYNC9 54
+#define CLK_MM_DISP_DLI_ASYNC9_DISP 55
+#define CLK_MM_DISP_DLI_ASYNC10 56
+#define CLK_MM_DISP_DLI_ASYNC10_DISP 57
+#define CLK_MM_DISP_DLI_ASYNC11 58
+#define CLK_MM_DISP_DLI_ASYNC11_DISP 59
+#define CLK_MM_DISP_DLI_ASYNC12 60
+#define CLK_MM_DISP_DLI_ASYNC12_DISP 61
+#define CLK_MM_DISP_DLI_ASYNC13 62
+#define CLK_MM_DISP_DLI_ASYNC13_DISP 63
+#define CLK_MM_DISP_DLI_ASYNC14 64
+#define CLK_MM_DISP_DLI_ASYNC14_DISP 65
+#define CLK_MM_DISP_DLI_ASYNC15 66
+#define CLK_MM_DISP_DLI_ASYNC15_DISP 67
+#define CLK_MM_DISP_DLO_ASYNC0 68
+#define CLK_MM_DISP_DLO_ASYNC0_DISP 69
+#define CLK_MM_DISP_DLO_ASYNC1 70
+#define CLK_MM_DISP_DLO_ASYNC1_DISP 71
+#define CLK_MM_DISP_DLO_ASYNC2 72
+#define CLK_MM_DISP_DLO_ASYNC2_DISP 73
+#define CLK_MM_DISP_DLO_ASYNC3 74
+#define CLK_MM_DISP_DLO_ASYNC3_DISP 75
+#define CLK_MM_DISP_DLO_ASYNC4 76
+#define CLK_MM_DISP_DLO_ASYNC4_DISP 77
+#define CLK_MM_DISP_DLO_ASYNC5 78
+#define CLK_MM_DISP_DLO_ASYNC5_DISP 79
+#define CLK_MM_DISP_DLO_ASYNC6 80
+#define CLK_MM_DISP_DLO_ASYNC6_DISP 81
+#define CLK_MM_DISP_DLO_ASYNC7 82
+#define CLK_MM_DISP_DLO_ASYNC7_DISP 83
+#define CLK_MM_DISP_DLO_ASYNC8 84
+#define CLK_MM_DISP_DLO_ASYNC8_DISP 85
+#define CLK_MM_DISP_GAMMA0 86
+#define CLK_MM_DISP_GAMMA0_PQ 87
+#define CLK_MM_DISP_GAMMA1 88
+#define CLK_MM_DISP_GAMMA1_PQ 89
+#define CLK_MM_MDP_AAL0 90
+#define CLK_MM_MDP_AAL0_PQ 91
+#define CLK_MM_MDP_AAL1 92
+#define CLK_MM_MDP_AAL1_PQ 93
+#define CLK_MM_MDP_RDMA0 94
+#define CLK_MM_MDP_RDMA0_DISP 95
+#define CLK_MM_DISP_POSTMASK0 96
+#define CLK_MM_DISP_POSTMASK0_DISP 97
+#define CLK_MM_DISP_POSTMASK1 98
+#define CLK_MM_DISP_POSTMASK1_DISP 99
+#define CLK_MM_MDP_RSZ0 100
+#define CLK_MM_MDP_RSZ0_DISP 101
+#define CLK_MM_MDP_RSZ1 102
+#define CLK_MM_MDP_RSZ1_DISP 103
+#define CLK_MM_DISP_SPR0 104
+#define CLK_MM_DISP_SPR0_DISP 105
+#define CLK_MM_DISP_TDSHP0 106
+#define CLK_MM_DISP_TDSHP0_PQ 107
+#define CLK_MM_DISP_TDSHP1 108
+#define CLK_MM_DISP_TDSHP1_PQ 109
+#define CLK_MM_DISP_WDMA0 110
+#define CLK_MM_DISP_WDMA0_DISP 111
+#define CLK_MM_DISP_Y2R0 112
+#define CLK_MM_DISP_Y2R0_DISP 113
+#define CLK_MM_SMI_SUB_COMM0 114
+#define CLK_MM_SMI_SUB_COMM0_SMI 115
+#define CLK_MM_DISP_FAKE_ENG0 116
+#define CLK_MM_DISP_FAKE_ENG0_DISP 117
+#define CLK_MM_NR_CLK 118
+
+/* DISPSYS1_CONFIG */
+#define CLK_MM1_DISPSYS1_CONFIG 0
+#define CLK_MM1_DISPSYS1_CONFIG_DISP 1
+#define CLK_MM1_DISPSYS1_S_CONFIG 2
+#define CLK_MM1_DISPSYS1_S_CONFIG_DISP 3
+#define CLK_MM1_DISP_MUTEX0 4
+#define CLK_MM1_DISP_MUTEX0_DISP 5
+#define CLK_MM1_DISP_DLI_ASYNC20 6
+#define CLK_MM1_DISP_DLI_ASYNC20_DISP 7
+#define CLK_MM1_DISP_DLI_ASYNC21 8
+#define CLK_MM1_DISP_DLI_ASYNC21_DISP 9
+#define CLK_MM1_DISP_DLI_ASYNC22 10
+#define CLK_MM1_DISP_DLI_ASYNC22_DISP 11
+#define CLK_MM1_DISP_DLI_ASYNC23 12
+#define CLK_MM1_DISP_DLI_ASYNC23_DISP 13
+#define CLK_MM1_DISP_DLI_ASYNC24 14
+#define CLK_MM1_DISP_DLI_ASYNC24_DISP 15
+#define CLK_MM1_DISP_DLI_ASYNC25 16
+#define CLK_MM1_DISP_DLI_ASYNC25_DISP 17
+#define CLK_MM1_DISP_DLI_ASYNC26 18
+#define CLK_MM1_DISP_DLI_ASYNC26_DISP 19
+#define CLK_MM1_DISP_DLI_ASYNC27 20
+#define CLK_MM1_DISP_DLI_ASYNC27_DISP 21
+#define CLK_MM1_DISP_DLI_ASYNC28 22
+#define CLK_MM1_DISP_DLI_ASYNC28_DISP 23
+#define CLK_MM1_DISP_RELAY0 24
+#define CLK_MM1_DISP_RELAY0_DISP 25
+#define CLK_MM1_DISP_RELAY1 26
+#define CLK_MM1_DISP_RELAY1_DISP 27
+#define CLK_MM1_DISP_RELAY2 28
+#define CLK_MM1_DISP_RELAY2_DISP 29
+#define CLK_MM1_DISP_RELAY3 30
+#define CLK_MM1_DISP_RELAY3_DISP 31
+#define CLK_MM1_DISP_DP_INTF0 32
+#define CLK_MM1_DISP_DP_INTF0_DISP 33
+#define CLK_MM1_DISP_DP_INTF1 34
+#define CLK_MM1_DISP_DP_INTF1_DISP 35
+#define CLK_MM1_DISP_DSC_WRAP0 36
+#define CLK_MM1_DISP_DSC_WRAP0_DISP 37
+#define CLK_MM1_DISP_DSC_WRAP1 38
+#define CLK_MM1_DISP_DSC_WRAP1_DISP 39
+#define CLK_MM1_DISP_DSC_WRAP2 40
+#define CLK_MM1_DISP_DSC_WRAP2_DISP 41
+#define CLK_MM1_DISP_DSC_WRAP3 42
+#define CLK_MM1_DISP_DSC_WRAP3_DISP 43
+#define CLK_MM1_DISP_DSI0 44
+#define CLK_MM1_DISP_DSI0_DISP 45
+#define CLK_MM1_DISP_DSI1 46
+#define CLK_MM1_DISP_DSI1_DISP 47
+#define CLK_MM1_DISP_DSI2 48
+#define CLK_MM1_DISP_DSI2_DISP 49
+#define CLK_MM1_DISP_DVO0 50
+#define CLK_MM1_DISP_DVO0_DISP 51
+#define CLK_MM1_DISP_GDMA0 52
+#define CLK_MM1_DISP_GDMA0_DISP 53
+#define CLK_MM1_DISP_MERGE0 54
+#define CLK_MM1_DISP_MERGE0_DISP 55
+#define CLK_MM1_DISP_MERGE1 56
+#define CLK_MM1_DISP_MERGE1_DISP 57
+#define CLK_MM1_DISP_MERGE2 58
+#define CLK_MM1_DISP_MERGE2_DISP 59
+#define CLK_MM1_DISP_ODDMR0 60
+#define CLK_MM1_DISP_ODDMR0_PQ 61
+#define CLK_MM1_DISP_POSTALIGN0 62
+#define CLK_MM1_DISP_POSTALIGN0_PQ 63
+#define CLK_MM1_DISP_DITHER2 64
+#define CLK_MM1_DISP_DITHER2_PQ 65
+#define CLK_MM1_DISP_R2Y0 66
+#define CLK_MM1_DISP_R2Y0_DISP 67
+#define CLK_MM1_DISP_SPLITTER0 68
+#define CLK_MM1_DISP_SPLITTER0_DISP 69
+#define CLK_MM1_DISP_SPLITTER1 70
+#define CLK_MM1_DISP_SPLITTER1_DISP 71
+#define CLK_MM1_DISP_SPLITTER2 72
+#define CLK_MM1_DISP_SPLITTER2_DISP 73
+#define CLK_MM1_DISP_SPLITTER3 74
+#define CLK_MM1_DISP_SPLITTER3_DISP 75
+#define CLK_MM1_DISP_VDCM0 76
+#define CLK_MM1_DISP_VDCM0_DISP 77
+#define CLK_MM1_DISP_WDMA1 78
+#define CLK_MM1_DISP_WDMA1_DISP 79
+#define CLK_MM1_DISP_WDMA2 80
+#define CLK_MM1_DISP_WDMA2_DISP 81
+#define CLK_MM1_DISP_WDMA3 82
+#define CLK_MM1_DISP_WDMA3_DISP 83
+#define CLK_MM1_DISP_WDMA4 84
+#define CLK_MM1_DISP_WDMA4_DISP 85
+#define CLK_MM1_MDP_RDMA1 86
+#define CLK_MM1_MDP_RDMA1_DISP 87
+#define CLK_MM1_SMI_LARB0 88
+#define CLK_MM1_SMI_LARB0_SMI 89
+#define CLK_MM1_MOD1 90
+#define CLK_MM1_MOD1_DISP 91
+#define CLK_MM1_MOD2 92
+#define CLK_MM1_MOD2_DISP 93
+#define CLK_MM1_MOD3 94
+#define CLK_MM1_MOD3_DISP 95
+#define CLK_MM1_MOD4 96
+#define CLK_MM1_MOD4_DISP 97
+#define CLK_MM1_MOD5 98
+#define CLK_MM1_MOD5_DISP 99
+#define CLK_MM1_MOD6 100
+#define CLK_MM1_MOD6_DISP 101
+#define CLK_MM1_CK_CG0 102
+#define CLK_MM1_CK_CG0_DISP 103
+#define CLK_MM1_CK_CG1 104
+#define CLK_MM1_CK_CG1_DISP 105
+#define CLK_MM1_CK_CG2 106
+#define CLK_MM1_CK_CG2_DISP 107
+#define CLK_MM1_CK_CG3 108
+#define CLK_MM1_CK_CG3_DISP 109
+#define CLK_MM1_CK_CG4 110
+#define CLK_MM1_CK_CG4_DISP 111
+#define CLK_MM1_CK_CG5 112
+#define CLK_MM1_CK_CG5_DISP 113
+#define CLK_MM1_CK_CG6 114
+#define CLK_MM1_CK_CG6_DISP 115
+#define CLK_MM1_CK_CG7 116
+#define CLK_MM1_CK_CG7_DISP 117
+#define CLK_MM1_F26M 118
+#define CLK_MM1_F26M_DISP 119
+#define CLK_MM1_NR_CLK 120
+
+/* OVLSYS_CONFIG */
+#define CLK_OVLSYS_CONFIG 0
+#define CLK_OVLSYS_CONFIG_DISP 1
+#define CLK_OVL_FAKE_ENG0 2
+#define CLK_OVL_FAKE_ENG0_DISP 3
+#define CLK_OVL_FAKE_ENG1 4
+#define CLK_OVL_FAKE_ENG1_DISP 5
+#define CLK_OVL_MUTEX0 6
+#define CLK_OVL_MUTEX0_DISP 7
+#define CLK_OVL_EXDMA0 8
+#define CLK_OVL_EXDMA0_DISP 9
+#define CLK_OVL_EXDMA1 10
+#define CLK_OVL_EXDMA1_DISP 11
+#define CLK_OVL_EXDMA2 12
+#define CLK_OVL_EXDMA2_DISP 13
+#define CLK_OVL_EXDMA3 14
+#define CLK_OVL_EXDMA3_DISP 15
+#define CLK_OVL_EXDMA4 16
+#define CLK_OVL_EXDMA4_DISP 17
+#define CLK_OVL_EXDMA5 18
+#define CLK_OVL_EXDMA5_DISP 19
+#define CLK_OVL_EXDMA6 20
+#define CLK_OVL_EXDMA6_DISP 21
+#define CLK_OVL_EXDMA7 22
+#define CLK_OVL_EXDMA7_DISP 23
+#define CLK_OVL_EXDMA8 24
+#define CLK_OVL_EXDMA8_DISP 25
+#define CLK_OVL_EXDMA9 26
+#define CLK_OVL_EXDMA9_DISP 27
+#define CLK_OVL_BLENDER0 28
+#define CLK_OVL_BLENDER0_DISP 29
+#define CLK_OVL_BLENDER1 30
+#define CLK_OVL_BLENDER1_DISP 31
+#define CLK_OVL_BLENDER2 32
+#define CLK_OVL_BLENDER2_DISP 33
+#define CLK_OVL_BLENDER3 34
+#define CLK_OVL_BLENDER3_DISP 35
+#define CLK_OVL_BLENDER4 36
+#define CLK_OVL_BLENDER4_DISP 37
+#define CLK_OVL_BLENDER5 38
+#define CLK_OVL_BLENDER5_DISP 39
+#define CLK_OVL_BLENDER6 40
+#define CLK_OVL_BLENDER6_DISP 41
+#define CLK_OVL_BLENDER7 42
+#define CLK_OVL_BLENDER7_DISP 43
+#define CLK_OVL_BLENDER8 44
+#define CLK_OVL_BLENDER8_DISP 45
+#define CLK_OVL_BLENDER9 46
+#define CLK_OVL_BLENDER9_DISP 47
+#define CLK_OVL_OUTPROC0 48
+#define CLK_OVL_OUTPROC0_DISP 49
+#define CLK_OVL_OUTPROC1 50
+#define CLK_OVL_OUTPROC1_DISP 51
+#define CLK_OVL_OUTPROC2 52
+#define CLK_OVL_OUTPROC2_DISP 53
+#define CLK_OVL_OUTPROC3 54
+#define CLK_OVL_OUTPROC3_DISP 55
+#define CLK_OVL_OUTPROC4 56
+#define CLK_OVL_OUTPROC4_DISP 57
+#define CLK_OVL_OUTPROC5 58
+#define CLK_OVL_OUTPROC5_DISP 59
+#define CLK_OVL_MDP_RSZ0 60
+#define CLK_OVL_MDP_RSZ0_DISP 61
+#define CLK_OVL_MDP_RSZ1 62
+#define CLK_OVL_MDP_RSZ1_DISP 63
+#define CLK_OVL_DISP_WDMA0 64
+#define CLK_OVL_DISP_WDMA0_DISP 65
+#define CLK_OVL_DISP_WDMA1 66
+#define CLK_OVL_DISP_WDMA1_DISP 67
+#define CLK_OVL_UFBC_WDMA0 68
+#define CLK_OVL_UFBC_WDMA0_DISP 69
+#define CLK_OVL_MDP_RDMA0 70
+#define CLK_OVL_MDP_RDMA0_DISP 71
+#define CLK_OVL_MDP_RDMA1 72
+#define CLK_OVL_MDP_RDMA1_DISP 73
+#define CLK_OVL_BWM0 74
+#define CLK_OVL_BWM0_DISP 75
+#define CLK_OVL_DLI0 76
+#define CLK_OVL_DLI0_DISP 77
+#define CLK_OVL_DLI1 78
+#define CLK_OVL_DLI1_DISP 79
+#define CLK_OVL_DLI2 80
+#define CLK_OVL_DLI2_DISP 81
+#define CLK_OVL_DLI3 82
+#define CLK_OVL_DLI3_DISP 83
+#define CLK_OVL_DLI4 84
+#define CLK_OVL_DLI4_DISP 85
+#define CLK_OVL_DLI5 86
+#define CLK_OVL_DLI5_DISP 87
+#define CLK_OVL_DLI6 88
+#define CLK_OVL_DLI6_DISP 89
+#define CLK_OVL_DLI7 90
+#define CLK_OVL_DLI7_DISP 91
+#define CLK_OVL_DLI8 92
+#define CLK_OVL_DLI8_DISP 93
+#define CLK_OVL_DLO0 94
+#define CLK_OVL_DLO0_DISP 95
+#define CLK_OVL_DLO1 96
+#define CLK_OVL_DLO1_DISP 97
+#define CLK_OVL_DLO2 98
+#define CLK_OVL_DLO2_DISP 99
+#define CLK_OVL_DLO3 100
+#define CLK_OVL_DLO3_DISP 101
+#define CLK_OVL_DLO4 102
+#define CLK_OVL_DLO4_DISP 103
+#define CLK_OVL_DLO5 104
+#define CLK_OVL_DLO5_DISP 105
+#define CLK_OVL_DLO6 106
+#define CLK_OVL_DLO6_DISP 107
+#define CLK_OVL_DLO7 108
+#define CLK_OVL_DLO7_DISP 109
+#define CLK_OVL_DLO8 110
+#define CLK_OVL_DLO8_DISP 111
+#define CLK_OVL_DLO9 112
+#define CLK_OVL_DLO9_DISP 113
+#define CLK_OVL_DLO10 114
+#define CLK_OVL_DLO10_DISP 115
+#define CLK_OVL_DLO11 116
+#define CLK_OVL_DLO11_DISP 117
+#define CLK_OVL_DLO12 118
+#define CLK_OVL_DLO12_DISP 119
+#define CLK_OVLSYS_RELAY0 120
+#define CLK_OVLSYS_RELAY0_DISP 121
+#define CLK_OVL_INLINEROT0 122
+#define CLK_OVL_INLINEROT0_DISP 123
+#define CLK_OVL_SMI 124
+#define CLK_OVL_SMI_SMI 125
+#define CLK_OVL_NR_CLK 126
+
+/* OVLSYS1_CONFIG */
+#define CLK_OVL1_OVLSYS_CONFIG 0
+#define CLK_OVL1_OVLSYS_CONFIG_DISP 1
+#define CLK_OVL1_OVL_FAKE_ENG0 2
+#define CLK_OVL1_OVL_FAKE_ENG0_DISP 3
+#define CLK_OVL1_OVL_FAKE_ENG1 4
+#define CLK_OVL1_OVL_FAKE_ENG1_DISP 5
+#define CLK_OVL1_OVL_MUTEX0 6
+#define CLK_OVL1_OVL_MUTEX0_DISP 7
+#define CLK_OVL1_OVL_EXDMA0 8
+#define CLK_OVL1_OVL_EXDMA0_DISP 9
+#define CLK_OVL1_OVL_EXDMA1 10
+#define CLK_OVL1_OVL_EXDMA1_DISP 11
+#define CLK_OVL1_OVL_EXDMA2 12
+#define CLK_OVL1_OVL_EXDMA2_DISP 13
+#define CLK_OVL1_OVL_EXDMA3 14
+#define CLK_OVL1_OVL_EXDMA3_DISP 15
+#define CLK_OVL1_OVL_EXDMA4 16
+#define CLK_OVL1_OVL_EXDMA4_DISP 17
+#define CLK_OVL1_OVL_EXDMA5 18
+#define CLK_OVL1_OVL_EXDMA5_DISP 19
+#define CLK_OVL1_OVL_EXDMA6 20
+#define CLK_OVL1_OVL_EXDMA6_DISP 21
+#define CLK_OVL1_OVL_EXDMA7 22
+#define CLK_OVL1_OVL_EXDMA7_DISP 23
+#define CLK_OVL1_OVL_EXDMA8 24
+#define CLK_OVL1_OVL_EXDMA8_DISP 25
+#define CLK_OVL1_OVL_EXDMA9 26
+#define CLK_OVL1_OVL_EXDMA9_DISP 27
+#define CLK_OVL1_OVL_BLENDER0 28
+#define CLK_OVL1_OVL_BLENDER0_DISP 29
+#define CLK_OVL1_OVL_BLENDER1 30
+#define CLK_OVL1_OVL_BLENDER1_DISP 31
+#define CLK_OVL1_OVL_BLENDER2 32
+#define CLK_OVL1_OVL_BLENDER2_DISP 33
+#define CLK_OVL1_OVL_BLENDER3 34
+#define CLK_OVL1_OVL_BLENDER3_DISP 35
+#define CLK_OVL1_OVL_BLENDER4 36
+#define CLK_OVL1_OVL_BLENDER4_DISP 37
+#define CLK_OVL1_OVL_BLENDER5 38
+#define CLK_OVL1_OVL_BLENDER5_DISP 39
+#define CLK_OVL1_OVL_BLENDER6 40
+#define CLK_OVL1_OVL_BLENDER6_DISP 41
+#define CLK_OVL1_OVL_BLENDER7 42
+#define CLK_OVL1_OVL_BLENDER7_DISP 43
+#define CLK_OVL1_OVL_BLENDER8 44
+#define CLK_OVL1_OVL_BLENDER8_DISP 45
+#define CLK_OVL1_OVL_BLENDER9 46
+#define CLK_OVL1_OVL_BLENDER9_DISP 47
+#define CLK_OVL1_OVL_OUTPROC0 48
+#define CLK_OVL1_OVL_OUTPROC0_DISP 49
+#define CLK_OVL1_OVL_OUTPROC1 50
+#define CLK_OVL1_OVL_OUTPROC1_DISP 51
+#define CLK_OVL1_OVL_OUTPROC2 52
+#define CLK_OVL1_OVL_OUTPROC2_DISP 53
+#define CLK_OVL1_OVL_OUTPROC3 54
+#define CLK_OVL1_OVL_OUTPROC3_DISP 55
+#define CLK_OVL1_OVL_OUTPROC4 56
+#define CLK_OVL1_OVL_OUTPROC4_DISP 57
+#define CLK_OVL1_OVL_OUTPROC5 58
+#define CLK_OVL1_OVL_OUTPROC5_DISP 59
+#define CLK_OVL1_OVL_MDP_RSZ0 60
+#define CLK_OVL1_OVL_MDP_RSZ0_DISP 61
+#define CLK_OVL1_OVL_MDP_RSZ1 62
+#define CLK_OVL1_OVL_MDP_RSZ1_DISP 63
+#define CLK_OVL1_OVL_DISP_WDMA0 64
+#define CLK_OVL1_OVL_DISP_WDMA0_DISP 65
+#define CLK_OVL1_OVL_DISP_WDMA1 66
+#define CLK_OVL1_OVL_DISP_WDMA1_DISP 67
+#define CLK_OVL1_OVL_UFBC_WDMA0 68
+#define CLK_OVL1_OVL_UFBC_WDMA0_DISP 69
+#define CLK_OVL1_OVL_MDP_RDMA0 70
+#define CLK_OVL1_OVL_MDP_RDMA0_DISP 71
+#define CLK_OVL1_OVL_MDP_RDMA1 72
+#define CLK_OVL1_OVL_MDP_RDMA1_DISP 73
+#define CLK_OVL1_OVL_BWM0 74
+#define CLK_OVL1_OVL_BWM0_DISP 75
+#define CLK_OVL1_DLI0 76
+#define CLK_OVL1_DLI0_DISP 77
+#define CLK_OVL1_DLI1 78
+#define CLK_OVL1_DLI1_DISP 79
+#define CLK_OVL1_DLI2 80
+#define CLK_OVL1_DLI2_DISP 81
+#define CLK_OVL1_DLI3 82
+#define CLK_OVL1_DLI3_DISP 83
+#define CLK_OVL1_DLI4 84
+#define CLK_OVL1_DLI4_DISP 85
+#define CLK_OVL1_DLI5 86
+#define CLK_OVL1_DLI5_DISP 87
+#define CLK_OVL1_DLI6 88
+#define CLK_OVL1_DLI6_DISP 89
+#define CLK_OVL1_DLI7 90
+#define CLK_OVL1_DLI7_DISP 91
+#define CLK_OVL1_DLI8 92
+#define CLK_OVL1_DLI8_DISP 93
+#define CLK_OVL1_DLO0 94
+#define CLK_OVL1_DLO0_DISP 95
+#define CLK_OVL1_DLO1 96
+#define CLK_OVL1_DLO1_DISP 97
+#define CLK_OVL1_DLO2 98
+#define CLK_OVL1_DLO2_DISP 99
+#define CLK_OVL1_DLO3 100
+#define CLK_OVL1_DLO3_DISP 101
+#define CLK_OVL1_DLO4 102
+#define CLK_OVL1_DLO4_DISP 103
+#define CLK_OVL1_DLO5 104
+#define CLK_OVL1_DLO5_DISP 105
+#define CLK_OVL1_DLO6 106
+#define CLK_OVL1_DLO6_DISP 107
+#define CLK_OVL1_DLO7 108
+#define CLK_OVL1_DLO7_DISP 109
+#define CLK_OVL1_DLO8 110
+#define CLK_OVL1_DLO8_DISP 111
+#define CLK_OVL1_DLO9 112
+#define CLK_OVL1_DLO9_DISP 113
+#define CLK_OVL1_DLO10 114
+#define CLK_OVL1_DLO10_DISP 115
+#define CLK_OVL1_DLO11 116
+#define CLK_OVL1_DLO11_DISP 117
+#define CLK_OVL1_DLO12 118
+#define CLK_OVL1_DLO12_DISP 119
+#define CLK_OVL1_OVLSYS_RELAY0 120
+#define CLK_OVL1_OVLSYS_RELAY0_DISP 121
+#define CLK_OVL1_OVL_INLINEROT0 122
+#define CLK_OVL1_OVL_INLINEROT0_DISP 123
+#define CLK_OVL1_SMI 124
+#define CLK_OVL1_SMI_SMI 125
+#define CLK_OVL1_NR_CLK 126
+
+/* VDEC_SOC_GCON_BASE */
+#define CLK_VDE1_LARB1_CKEN 0
+#define CLK_VDE1_LARB1_CKEN_VDEC 1
+#define CLK_VDE1_LARB1_CKEN_SMI 2
+#define CLK_VDE1_LAT_CKEN 3
+#define CLK_VDE1_LAT_CKEN_VDEC 4
+#define CLK_VDE1_LAT_ACTIVE 5
+#define CLK_VDE1_LAT_ACTIVE_VDEC 6
+#define CLK_VDE1_LAT_CKEN_ENG 7
+#define CLK_VDE1_LAT_CKEN_ENG_VDEC 8
+#define CLK_VDE1_VDEC_CKEN 9
+#define CLK_VDE1_VDEC_CKEN_VDEC 10
+#define CLK_VDE1_VDEC_ACTIVE 11
+#define CLK_VDE1_VDEC_ACTIVE_VDEC 12
+#define CLK_VDE1_VDEC_CKEN_ENG 13
+#define CLK_VDE1_VDEC_CKEN_ENG_VDEC 14
+#define CLK_VDE1_VDEC_SOC_APTV_EN 15
+#define CLK_VDE1_VDEC_SOC_APTV_EN_VDEC 16
+#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN 17
+#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN_VDEC 18
+#define CLK_VDE1_VDEC_SOC_IPS_EN 19
+#define CLK_VDE1_VDEC_SOC_IPS_EN_VDEC 20
+#define CLK_VDE1_NR_CLK 21
+
+/* VDEC_GCON_BASE */
+#define CLK_VDE2_LARB1_CKEN 0
+#define CLK_VDE2_LARB1_CKEN_VDEC 1
+#define CLK_VDE2_LARB1_CKEN_SMI 2
+#define CLK_VDE2_LAT_CKEN 3
+#define CLK_VDE2_LAT_CKEN_VDEC 4
+#define CLK_VDE2_LAT_ACTIVE 5
+#define CLK_VDE2_LAT_ACTIVE_VDEC 6
+#define CLK_VDE2_LAT_CKEN_ENG 7
+#define CLK_VDE2_LAT_CKEN_ENG_VDEC 8
+#define CLK_VDE2_VDEC_CKEN 9
+#define CLK_VDE2_VDEC_CKEN_VDEC 10
+#define CLK_VDE2_VDEC_ACTIVE 11
+#define CLK_VDE2_VDEC_ACTIVE_VDEC 12
+#define CLK_VDE2_VDEC_CKEN_ENG 13
+#define CLK_VDE2_VDEC_CKEN_ENG_VDEC 14
+#define CLK_VDE2_NR_CLK 15
+
+/* VENC_GCON */
+#define CLK_VEN1_CKE0_LARB 0
+#define CLK_VEN1_CKE0_LARB_VENC 1
+#define CLK_VEN1_CKE0_LARB_JPGENC 2
+#define CLK_VEN1_CKE0_LARB_JPGDEC 3
+#define CLK_VEN1_CKE0_LARB_SMI 4
+#define CLK_VEN1_CKE1_VENC 5
+#define CLK_VEN1_CKE1_VENC_VENC 6
+#define CLK_VEN1_CKE1_VENC_SMI 7
+#define CLK_VEN1_CKE2_JPGENC 8
+#define CLK_VEN1_CKE2_JPGENC_JPGENC 9
+#define CLK_VEN1_CKE3_JPGDEC 10
+#define CLK_VEN1_CKE3_JPGDEC_JPGDEC 11
+#define CLK_VEN1_CKE4_JPGDEC_C1 12
+#define CLK_VEN1_CKE4_JPGDEC_C1_JPGDEC 13
+#define CLK_VEN1_CKE5_GALS 14
+#define CLK_VEN1_CKE5_GALS_VENC 15
+#define CLK_VEN1_CKE5_GALS_JPGENC 16
+#define CLK_VEN1_CKE5_GALS_JPGDEC 17
+#define CLK_VEN1_CKE29_VENC_ADAB_CTRL 18
+#define CLK_VEN1_CKE29_VENC_ADAB_CTRL_VENC 19
+#define CLK_VEN1_CKE29_VENC_XPC_CTRL 20
+#define CLK_VEN1_CKE29_VENC_XPC_CTRL_VENC 21
+#define CLK_VEN1_CKE29_VENC_XPC_CTRL_JPGENC 22
+#define CLK_VEN1_CKE29_VENC_XPC_CTRL_JPGDEC 23
+#define CLK_VEN1_CKE6_GALS_SRAM 24
+#define CLK_VEN1_CKE6_GALS_SRAM_VENC 25
+#define CLK_VEN1_RES_FLAT 26
+#define CLK_VEN1_RES_FLAT_VENC 27
+#define CLK_VEN1_RES_FLAT_JPGENC 28
+#define CLK_VEN1_RES_FLAT_JPGDEC 29
+#define CLK_VEN1_NR_CLK 30
+
+/* VENC_GCON_CORE1 */
+#define CLK_VEN2_CKE0_LARB 0
+#define CLK_VEN2_CKE0_LARB_VENC 1
+#define CLK_VEN2_CKE0_LARB_JPGENC 2
+#define CLK_VEN2_CKE0_LARB_JPGDEC 3
+#define CLK_VEN2_CKE0_LARB_SMI 4
+#define CLK_VEN2_CKE1_VENC 5
+#define CLK_VEN2_CKE1_VENC_VENC 6
+#define CLK_VEN2_CKE1_VENC_SMI 7
+#define CLK_VEN2_CKE2_JPGENC 8
+#define CLK_VEN2_CKE2_JPGENC_JPGENC 9
+#define CLK_VEN2_CKE3_JPGDEC 10
+#define CLK_VEN2_CKE3_JPGDEC_JPGDEC 11
+#define CLK_VEN2_CKE5_GALS 12
+#define CLK_VEN2_CKE5_GALS_VENC 13
+#define CLK_VEN2_CKE5_GALS_JPGENC 14
+#define CLK_VEN2_CKE5_GALS_JPGDEC 15
+#define CLK_VEN2_CKE29_VENC_XPC_CTRL 16
+#define CLK_VEN2_CKE29_VENC_XPC_CTRL_VENC 17
+#define CLK_VEN2_CKE29_VENC_XPC_CTRL_JPGENC 18
+#define CLK_VEN2_CKE29_VENC_XPC_CTRL_JPGDEC 19
+#define CLK_VEN2_CKE6_GALS_SRAM 20
+#define CLK_VEN2_CKE6_GALS_SRAM_VENC 21
+#define CLK_VEN2_RES_FLAT 22
+#define CLK_VEN2_RES_FLAT_VENC 23
+#define CLK_VEN2_RES_FLAT_JPGENC 24
+#define CLK_VEN2_RES_FLAT_JPGDEC 25
+#define CLK_VEN2_NR_CLK 26
+
+/* VENC_GCON_CORE2 */
+#define CLK_VEN_C2_CKE0_LARB 0
+#define CLK_VEN_C2_CKE0_LARB_VENC 1
+#define CLK_VEN_C2_CKE0_LARB_SMI 2
+#define CLK_VEN_C2_CKE1_VENC 3
+#define CLK_VEN_C2_CKE1_VENC_VENC 4
+#define CLK_VEN_C2_CKE1_VENC_SMI 5
+#define CLK_VEN_C2_CKE5_GALS 6
+#define CLK_VEN_C2_CKE5_GALS_VENC 7
+#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL 8
+#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL_VENC 9
+#define CLK_VEN_C2_CKE6_GALS_SRAM 10
+#define CLK_VEN_C2_CKE6_GALS_SRAM_VENC 11
+#define CLK_VEN_C2_RES_FLAT 12
+#define CLK_VEN_C2_RES_FLAT_VENC 13
+#define CLK_VEN_C2_NR_CLK 14
+
+/* MDPSYS_CONFIG */
+#define CLK_MDP_MDP_MUTEX0 0
+#define CLK_MDP_MDP_MUTEX0_MML 1
+#define CLK_MDP_SMI0 2
+#define CLK_MDP_SMI0_MML 3
+#define CLK_MDP_SMI0_SMI 4
+#define CLK_MDP_APB_BUS 5
+#define CLK_MDP_APB_BUS_MML 6
+#define CLK_MDP_MDP_RDMA0 7
+#define CLK_MDP_MDP_RDMA0_MML 8
+#define CLK_MDP_MDP_RDMA1 9
+#define CLK_MDP_MDP_RDMA1_MML 10
+#define CLK_MDP_MDP_RDMA2 11
+#define CLK_MDP_MDP_RDMA2_MML 12
+#define CLK_MDP_MDP_BIRSZ0 13
+#define CLK_MDP_MDP_BIRSZ0_MML 14
+#define CLK_MDP_MDP_HDR0 15
+#define CLK_MDP_MDP_HDR0_MML 16
+#define CLK_MDP_MDP_AAL0 17
+#define CLK_MDP_MDP_AAL0_MML 18
+#define CLK_MDP_MDP_RSZ0 19
+#define CLK_MDP_MDP_RSZ0_MML 20
+#define CLK_MDP_MDP_RSZ2 21
+#define CLK_MDP_MDP_RSZ2_MML 22
+#define CLK_MDP_MDP_TDSHP0 23
+#define CLK_MDP_MDP_TDSHP0_MML 24
+#define CLK_MDP_MDP_COLOR0 25
+#define CLK_MDP_MDP_COLOR0_MML 26
+#define CLK_MDP_MDP_WROT0 27
+#define CLK_MDP_MDP_WROT0_MML 28
+#define CLK_MDP_MDP_WROT1 29
+#define CLK_MDP_MDP_WROT1_MML 30
+#define CLK_MDP_MDP_WROT2 31
+#define CLK_MDP_MDP_WROT2_MML 32
+#define CLK_MDP_MDP_FAKE_ENG0 33
+#define CLK_MDP_MDP_FAKE_ENG0_MML 34
+#define CLK_MDP_APB_DB 35
+#define CLK_MDP_APB_DB_MML 36
+#define CLK_MDP_MDP_DLI_ASYNC0 37
+#define CLK_MDP_MDP_DLI_ASYNC0_MML 38
+#define CLK_MDP_MDP_DLI_ASYNC1 39
+#define CLK_MDP_MDP_DLI_ASYNC1_MML 40
+#define CLK_MDP_MDP_DLO_ASYNC0 41
+#define CLK_MDP_MDP_DLO_ASYNC0_MML 42
+#define CLK_MDP_MDP_DLO_ASYNC1 43
+#define CLK_MDP_MDP_DLO_ASYNC1_MML 44
+#define CLK_MDP_MDP_DLI_ASYNC2 45
+#define CLK_MDP_MDP_DLI_ASYNC2_MML 46
+#define CLK_MDP_MDP_DLO_ASYNC2 47
+#define CLK_MDP_MDP_DLO_ASYNC2_MML 48
+#define CLK_MDP_MDP_DLO_ASYNC3 49
+#define CLK_MDP_MDP_DLO_ASYNC3_MML 50
+#define CLK_MDP_IMG_DL_ASYNC0 51
+#define CLK_MDP_IMG_DL_ASYNC0_MML 52
+#define CLK_MDP_MDP_RROT0 53
+#define CLK_MDP_MDP_RROT0_MML 54
+#define CLK_MDP_MDP_MERGE0 55
+#define CLK_MDP_MDP_MERGE0_MML 56
+#define CLK_MDP_MDP_C3D0 57
+#define CLK_MDP_MDP_C3D0_MML 58
+#define CLK_MDP_MDP_FG0 59
+#define CLK_MDP_MDP_FG0_MML 60
+#define CLK_MDP_MDP_CLA2 61
+#define CLK_MDP_MDP_CLA2_MML 62
+#define CLK_MDP_MDP_DLO_ASYNC4 63
+#define CLK_MDP_MDP_DLO_ASYNC4_MML 64
+#define CLK_MDP_VPP_RSZ0 65
+#define CLK_MDP_VPP_RSZ0_MML 66
+#define CLK_MDP_VPP_RSZ1 67
+#define CLK_MDP_VPP_RSZ1_MML 68
+#define CLK_MDP_MDP_DLO_ASYNC5 69
+#define CLK_MDP_MDP_DLO_ASYNC5_MML 70
+#define CLK_MDP_IMG0 71
+#define CLK_MDP_IMG0_MML 72
+#define CLK_MDP_F26M 73
+#define CLK_MDP_F26M_MML 74
+#define CLK_MDP_IMG_DL_RELAY0 75
+#define CLK_MDP_IMG_DL_RELAY0_MML 76
+#define CLK_MDP_IMG_DL_RELAY1 77
+#define CLK_MDP_IMG_DL_RELAY1_MML 78
+#define CLK_MDP_NR_CLK 79
+
+/* MDPSYS1_CONFIG */
+#define CLK_MDP1_MDP_MUTEX0 0
+#define CLK_MDP1_MDP_MUTEX0_MML 1
+#define CLK_MDP1_SMI0 2
+#define CLK_MDP1_SMI0_SMI 3
+#define CLK_MDP1_APB_BUS 4
+#define CLK_MDP1_APB_BUS_MML 5
+#define CLK_MDP1_MDP_RDMA0 6
+#define CLK_MDP1_MDP_RDMA0_MML 7
+#define CLK_MDP1_MDP_RDMA1 8
+#define CLK_MDP1_MDP_RDMA1_MML 9
+#define CLK_MDP1_MDP_RDMA2 10
+#define CLK_MDP1_MDP_RDMA2_MML 11
+#define CLK_MDP1_MDP_BIRSZ0 12
+#define CLK_MDP1_MDP_BIRSZ0_MML 13
+#define CLK_MDP1_MDP_HDR0 14
+#define CLK_MDP1_MDP_HDR0_MML 15
+#define CLK_MDP1_MDP_AAL0 16
+#define CLK_MDP1_MDP_AAL0_MML 17
+#define CLK_MDP1_MDP_RSZ0 18
+#define CLK_MDP1_MDP_RSZ0_MML 19
+#define CLK_MDP1_MDP_RSZ2 20
+#define CLK_MDP1_MDP_RSZ2_MML 21
+#define CLK_MDP1_MDP_TDSHP0 22
+#define CLK_MDP1_MDP_TDSHP0_MML 23
+#define CLK_MDP1_MDP_COLOR0 24
+#define CLK_MDP1_MDP_COLOR0_MML 25
+#define CLK_MDP1_MDP_WROT0 26
+#define CLK_MDP1_MDP_WROT0_MML 27
+#define CLK_MDP1_MDP_WROT1 28
+#define CLK_MDP1_MDP_WROT1_MML 29
+#define CLK_MDP1_MDP_WROT2 30
+#define CLK_MDP1_MDP_WROT2_MML 31
+#define CLK_MDP1_MDP_FAKE_ENG0 32
+#define CLK_MDP1_MDP_FAKE_ENG0_MML 33
+#define CLK_MDP1_APB_DB 34
+#define CLK_MDP1_APB_DB_MML 35
+#define CLK_MDP1_MDP_DLI_ASYNC0 36
+#define CLK_MDP1_MDP_DLI_ASYNC0_MML 37
+#define CLK_MDP1_MDP_DLI_ASYNC1 38
+#define CLK_MDP1_MDP_DLI_ASYNC1_MML 39
+#define CLK_MDP1_MDP_DLO_ASYNC0 40
+#define CLK_MDP1_MDP_DLO_ASYNC0_MML 41
+#define CLK_MDP1_MDP_DLO_ASYNC1 42
+#define CLK_MDP1_MDP_DLO_ASYNC1_MML 43
+#define CLK_MDP1_MDP_DLI_ASYNC2 44
+#define CLK_MDP1_MDP_DLI_ASYNC2_MML 45
+#define CLK_MDP1_MDP_DLO_ASYNC2 46
+#define CLK_MDP1_MDP_DLO_ASYNC2_MML 47
+#define CLK_MDP1_MDP_DLO_ASYNC3 48
+#define CLK_MDP1_MDP_DLO_ASYNC3_MML 49
+#define CLK_MDP1_IMG_DL_ASYNC0 50
+#define CLK_MDP1_IMG_DL_ASYNC0_MML 51
+#define CLK_MDP1_MDP_RROT0 52
+#define CLK_MDP1_MDP_RROT0_MML 53
+#define CLK_MDP1_MDP_MERGE0 54
+#define CLK_MDP1_MDP_MERGE0_MML 55
+#define CLK_MDP1_MDP_C3D0 56
+#define CLK_MDP1_MDP_C3D0_MML 57
+#define CLK_MDP1_MDP_FG0 58
+#define CLK_MDP1_MDP_FG0_MML 59
+#define CLK_MDP1_MDP_CLA2 60
+#define CLK_MDP1_MDP_CLA2_MML 61
+#define CLK_MDP1_MDP_DLO_ASYNC4 62
+#define CLK_MDP1_MDP_DLO_ASYNC4_MML 63
+#define CLK_MDP1_VPP_RSZ0 64
+#define CLK_MDP1_VPP_RSZ0_MML 65
+#define CLK_MDP1_VPP_RSZ1 66
+#define CLK_MDP1_VPP_RSZ1_MML 67
+#define CLK_MDP1_MDP_DLO_ASYNC5 68
+#define CLK_MDP1_MDP_DLO_ASYNC5_MML 69
+#define CLK_MDP1_IMG0 70
+#define CLK_MDP1_IMG0_MML 71
+#define CLK_MDP1_F26M 72
+#define CLK_MDP1_F26M_MML 73
+#define CLK_MDP1_IMG_DL_RELAY0 74
+#define CLK_MDP1_IMG_DL_RELAY0_MML 75
+#define CLK_MDP1_IMG_DL_RELAY1 76
+#define CLK_MDP1_IMG_DL_RELAY1_MML 77
+#define CLK_MDP1_NR_CLK 78
+
+/* DISP_VDISP_AO_CONFIG */
+#define CLK_MM_V_DISP_VDISP_AO_CONFIG 0
+#define CLK_MM_V_DISP_VDISP_AO_CONFIG_DISP 1
+#define CLK_MM_V_DISP_DPC 2
+#define CLK_MM_V_DISP_DPC_DISP 3
+#define CLK_MM_V_SMI_SUB_SOMM0 4
+#define CLK_MM_V_SMI_SUB_SOMM0_SMI 5
+#define CLK_MM_V_NR_CLK 6
+
+/* MFGPLL_PLL_CTRL */
+#define CLK_MFG_AO_MFGPLL 0
+#define CLK_MFG_AO_NR_CLK 1
+
+/* MFGPLL_SC0_PLL_CTRL */
+#define CLK_MFGSC0_AO_MFGPLL_SC0 0
+#define CLK_MFGSC0_AO_NR_CLK 1
+
+/* MFGPLL_SC1_PLL_CTRL */
+#define CLK_MFGSC1_AO_MFGPLL_SC1 0
+#define CLK_MFGSC1_AO_NR_CLK 1
+
+/* CCIPLL_PLL_CTRL */
+#define CLK_CCIPLL 0
+#define CLK_CCI_NR_CLK 1
+
+/* ARMPLL_LL_PLL_CTRL */
+#define CLK_CPLL_ARMPLL_LL 0
+#define CLK_CPU_LL_NR_CLK 1
+
+/* ARMPLL_BL_PLL_CTRL */
+#define CLK_CPBL_ARMPLL_BL 0
+#define CLK_CPU_BL_NR_CLK 1
+
+/* ARMPLL_B_PLL_CTRL */
+#define CLK_CPB_ARMPLL_B 0
+#define CLK_CPU_B_NR_CLK 1
+
+/* PTPPLL_PLL_CTRL */
+#define CLK_PTPPLL 0
+#define CLK_PTP_NR_CLK 1
+
+#endif /* _DT_BINDINGS_CLK_MT8196_H */
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 07/26] clk: mediatek: Add MT8196 apmixedsys clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (5 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-11 17:05 ` Jeff Johnson
2025-03-07 3:27 ` [PATCH 08/26] clk: mediatek: Add MT8196 apmixedsys_gp2 " Guangjie Song
` (18 subsequent siblings)
25 siblings, 1 reply; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 apmixedsys clock controller which provides pll generated from
SoC 26m.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 8 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 146 +++++++++++++++++++
3 files changed, 155 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 5f8e6d68fa14..1e0c6f177ecd 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1002,6 +1002,14 @@ config COMMON_CLK_MT8195_VENCSYS
help
This driver supports MediaTek MT8195 vencsys clocks.
+config COMMON_CLK_MT8196
+ tristate "Clock driver for MediaTek MT8196"
+ depends on ARM64 || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8196 basic clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6efec95406bd..6144fdce3f9a 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -150,6 +150,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
+obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
new file mode 100644
index 000000000000..3aa62eec07f7
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+/* PLL REG */
+#define MAINPLL_CON0 0x250
+#define MAINPLL_CON1 0x254
+#define MAINPLL_CON2 0x258
+#define MAINPLL_CON3 0x25c
+#define UNIVPLL_CON0 0x264
+#define UNIVPLL_CON1 0x268
+#define UNIVPLL_CON2 0x26c
+#define UNIVPLL_CON3 0x270
+#define MSDCPLL_CON0 0x278
+#define MSDCPLL_CON1 0x27c
+#define MSDCPLL_CON2 0x280
+#define MSDCPLL_CON3 0x284
+#define ADSPPLL_CON0 0x28c
+#define ADSPPLL_CON1 0x290
+#define ADSPPLL_CON2 0x294
+#define ADSPPLL_CON3 0x298
+#define EMIPLL_CON0 0x2a0
+#define EMIPLL_CON1 0x2a4
+#define EMIPLL_CON2 0x2a8
+#define EMIPLL_CON3 0x2ac
+#define EMIPLL2_CON0 0x2b4
+#define EMIPLL2_CON1 0x2b8
+#define EMIPLL2_CON2 0x2bc
+#define EMIPLL2_CON3 0x2c0
+
+#define MT8196_PLL_FMAX (3800UL * MHZ)
+#define MT8196_PLL_FMIN (1500UL * MHZ)
+#define MT8196_INTEGER_BITS 8
+
+#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit, \
+ _flags, _pd_reg, _pd_shift, \
+ _pcw_reg, _pcw_shift, _pcwbits) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .fenc_sta_ofs = _fenc_sta_ofs, \
+ .fenc_sta_bit = _fenc_sta_bit, \
+ .flags = (_flags) | CLK_FENC_ENABLE, \
+ .fmax = MT8196_PLL_FMAX, \
+ .fmin = MT8196_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8196_INTEGER_BITS, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL_FENC(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0,
+ 0x003c, 7, PLL_AO,
+ MAINPLL_CON1, 24,
+ MAINPLL_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0,
+ 0x003c, 6, 0,
+ UNIVPLL_CON1, 24,
+ UNIVPLL_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0,
+ 0x003c, 5, 0,
+ MSDCPLL_CON1, 24,
+ MSDCPLL_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED_ADSPPLL, "adsppll", ADSPPLL_CON0,
+ 0x003c, 4, 0,
+ ADSPPLL_CON1, 24,
+ ADSPPLL_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED_EMIPLL, "emipll", EMIPLL_CON0,
+ 0x003c, 3, PLL_AO,
+ EMIPLL_CON1, 24,
+ EMIPLL_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED_EMIPLL2, "emipll2", EMIPLL2_CON0,
+ 0x003c, 2, PLL_AO,
+ EMIPLL2_CON1, 24,
+ EMIPLL2_CON1, 0, 22),
+};
+
+static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int num_plls = ARRAY_SIZE(apmixed_plls);
+ int r;
+
+ clk_data = mtk_alloc_clk_data(num_plls);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_plls(node, apmixed_plls, num_plls, clk_data);
+ if (r) {
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+ mtk_clk_unregister_plls(apmixed_plls, num_plls, clk_data);
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ return 0;
+}
+
+static void clk_mt8196_apmixed_remove(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_plls(apmixed_plls, ARRAY_SIZE(apmixed_plls), clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8196_apmixed[] = {
+ { .compatible = "mediatek,mt8196-apmixedsys", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_apmixed_drv = {
+ .probe = clk_mt8196_apmixed_probe,
+ .remove = clk_mt8196_apmixed_remove,
+ .driver = {
+ .name = "clk-mt8196-apmixed",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8196_apmixed,
+ },
+};
+
+module_platform_driver(clk_mt8196_apmixed_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 08/26] clk: mediatek: Add MT8196 apmixedsys_gp2 clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (6 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 07/26] clk: mediatek: Add MT8196 apmixedsys clock support Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 09/26] clk: mediatek: Add MT8196 topckgen " Guangjie Song
` (17 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 apmixedsys_gp2 clock controller which provides pll generated
from SoC 26m
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
.../clk/mediatek/clk-mt8196-apmixedsys_gp2.c | 154 ++++++++++++++++++
2 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys_gp2.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6144fdce3f9a..247bad396cfb 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -150,7 +150,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
-obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o
+obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys_gp2.c b/drivers/clk/mediatek/clk-mt8196-apmixedsys_gp2.c
new file mode 100644
index 000000000000..dc895d103bfe
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys_gp2.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+/* PLL REG */
+#define MAINPLL2_CON0 0x250
+#define MAINPLL2_CON1 0x254
+#define MAINPLL2_CON2 0x258
+#define MAINPLL2_CON3 0x25c
+#define UNIVPLL2_CON0 0x264
+#define UNIVPLL2_CON1 0x268
+#define UNIVPLL2_CON2 0x26c
+#define UNIVPLL2_CON3 0x270
+#define MMPLL2_CON0 0x278
+#define MMPLL2_CON1 0x27c
+#define MMPLL2_CON2 0x280
+#define MMPLL2_CON3 0x284
+#define IMGPLL_CON0 0x28c
+#define IMGPLL_CON1 0x290
+#define IMGPLL_CON2 0x294
+#define IMGPLL_CON3 0x298
+#define TVDPLL1_CON0 0x2a0
+#define TVDPLL1_CON1 0x2a4
+#define TVDPLL1_CON2 0x2a8
+#define TVDPLL1_CON3 0x2ac
+#define TVDPLL2_CON0 0x2b4
+#define TVDPLL2_CON1 0x2b8
+#define TVDPLL2_CON2 0x2bc
+#define TVDPLL2_CON3 0x2c0
+#define TVDPLL3_CON0 0x2c8
+#define TVDPLL3_CON1 0x2cc
+#define TVDPLL3_CON2 0x2d0
+#define TVDPLL3_CON3 0x2d4
+
+#define MT8196_PLL_FMAX (3800UL * MHZ)
+#define MT8196_PLL_FMIN (1500UL * MHZ)
+#define MT8196_INTEGER_BITS 8
+
+#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
+ _flags, _pd_reg, _pd_shift, \
+ _pcw_reg, _pcw_shift, _pcwbits) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .fenc_sta_ofs = _fenc_sta_ofs, \
+ .fenc_sta_bit = _fenc_sta_bit, \
+ .flags = (_flags) | CLK_FENC_ENABLE, \
+ .fmax = MT8196_PLL_FMAX, \
+ .fmin = MT8196_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8196_INTEGER_BITS, \
+ }
+
+static const struct mtk_pll_data apmixed2_plls[] = {
+ PLL_FENC(CLK_APMIXED2_MAINPLL2, "mainpll2", MAINPLL2_CON0,
+ 0x03c, 6, 0,
+ MAINPLL2_CON1, 24,
+ MAINPLL2_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED2_UNIVPLL2, "univpll2", UNIVPLL2_CON0,
+ 0x03c, 5, 0,
+ UNIVPLL2_CON1, 24,
+ UNIVPLL2_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED2_MMPLL2, "mmpll2", MMPLL2_CON0,
+ 0x03c, 4, 0,
+ MMPLL2_CON1, 24,
+ MMPLL2_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED2_IMGPLL, "imgpll", IMGPLL_CON0,
+ 0x03c, 3, 0,
+ IMGPLL_CON1, 24,
+ IMGPLL_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED2_TVDPLL1, "tvdpll1", TVDPLL1_CON0,
+ 0x03c, 2, 0,
+ TVDPLL1_CON1, 24,
+ TVDPLL1_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED2_TVDPLL2, "tvdpll2", TVDPLL2_CON0,
+ 0x03c, 1, 0,
+ TVDPLL2_CON1, 24,
+ TVDPLL2_CON1, 0, 22),
+ PLL_FENC(CLK_APMIXED2_TVDPLL3, "tvdpll3", TVDPLL3_CON0,
+ 0x03c, 0, 0,
+ TVDPLL3_CON1, 24,
+ TVDPLL3_CON1, 0, 22),
+};
+
+static int clk_mt8196_apmixed2_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int num_plls = ARRAY_SIZE(apmixed2_plls);
+ int r;
+
+ clk_data = mtk_alloc_clk_data(num_plls);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_plls(node, apmixed2_plls, num_plls, clk_data);
+ if (r) {
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+ mtk_clk_unregister_plls(apmixed2_plls, num_plls, clk_data);
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ return 0;
+}
+
+static void clk_mt8196_apmixed2_remove(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_plls(apmixed2_plls, ARRAY_SIZE(apmixed2_plls), clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8196_apmixed2[] = {
+ { .compatible = "mediatek,mt8196-apmixedsys_gp2", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_apmixed2_drv = {
+ .probe = clk_mt8196_apmixed2_probe,
+ .remove = clk_mt8196_apmixed2_remove,
+ .driver = {
+ .name = "clk-mt8196-apmixed2",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8196_apmixed2,
+ },
+};
+
+module_platform_driver(clk_mt8196_apmixed2_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 09/26] clk: mediatek: Add MT8196 topckgen clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (7 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 08/26] clk: mediatek: Add MT8196 apmixedsys_gp2 " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-04-16 9:04 ` Chen-Yu Tsai
2025-03-07 3:27 ` [PATCH 10/26] clk: mediatek: Add MT8196 topckgen2 " Guangjie Song
` (16 subsequent siblings)
25 siblings, 1 reply; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 topckgen clock controller which provides muxes and dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8196-topckgen.c | 1373 ++++++++++++++++++++
2 files changed, 1375 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 247bad396cfb..cd6f42a6fd10 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -150,7 +150,8 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
-obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o
+obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o \
+ clk-mt8196-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-topckgen.c b/drivers/clk/mediatek/clk-mt8196-topckgen.c
new file mode 100644
index 000000000000..41c5431561fe
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-topckgen.c
@@ -0,0 +1,1373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+
+/* MUX SEL REG */
+#define CLK_CFG_UPDATE 0x0004
+#define CLK_CFG_UPDATE1 0x0008
+#define CLK_CFG_UPDATE2 0x000c
+#define CLK_CFG_0 0x0010
+#define CLK_CFG_0_SET 0x0014
+#define CLK_CFG_0_CLR 0x0018
+#define CLK_CFG_1 0x0020
+#define CLK_CFG_1_SET 0x0024
+#define CLK_CFG_1_CLR 0x0028
+#define CLK_CFG_2 0x0030
+#define CLK_CFG_2_SET 0x0034
+#define CLK_CFG_2_CLR 0x0038
+#define CLK_CFG_3 0x0040
+#define CLK_CFG_3_SET 0x0044
+#define CLK_CFG_3_CLR 0x0048
+#define CLK_CFG_4 0x0050
+#define CLK_CFG_4_SET 0x0054
+#define CLK_CFG_4_CLR 0x0058
+#define CLK_CFG_5 0x0060
+#define CLK_CFG_5_SET 0x0064
+#define CLK_CFG_5_CLR 0x0068
+#define CLK_CFG_6 0x0070
+#define CLK_CFG_6_SET 0x0074
+#define CLK_CFG_6_CLR 0x0078
+#define CLK_CFG_7 0x0080
+#define CLK_CFG_7_SET 0x0084
+#define CLK_CFG_7_CLR 0x0088
+#define CLK_CFG_8 0x0090
+#define CLK_CFG_8_SET 0x0094
+#define CLK_CFG_8_CLR 0x0098
+#define CLK_CFG_9 0x00a0
+#define CLK_CFG_9_SET 0x00a4
+#define CLK_CFG_9_CLR 0x00a8
+#define CLK_CFG_10 0x00b0
+#define CLK_CFG_10_SET 0x00b4
+#define CLK_CFG_10_CLR 0x00b8
+#define CLK_CFG_11 0x00c0
+#define CLK_CFG_11_SET 0x00c4
+#define CLK_CFG_11_CLR 0x00c8
+#define CLK_CFG_12 0x00d0
+#define CLK_CFG_12_SET 0x00d4
+#define CLK_CFG_12_CLR 0x00d8
+#define CLK_CFG_13 0x00e0
+#define CLK_CFG_13_SET 0x00e4
+#define CLK_CFG_13_CLR 0x00e8
+#define CLK_CFG_14 0x00f0
+#define CLK_CFG_14_SET 0x00f4
+#define CLK_CFG_14_CLR 0x00f8
+#define CLK_CFG_15 0x0100
+#define CLK_CFG_15_SET 0x0104
+#define CLK_CFG_15_CLR 0x0108
+#define CLK_CFG_16 0x0110
+#define CLK_CFG_16_SET 0x0114
+#define CLK_CFG_16_CLR 0x0118
+#define CLK_CFG_17 0x0120
+#define CLK_CFG_17_SET 0x0124
+#define CLK_CFG_17_CLR 0x0128
+#define CLK_CFG_18 0x0130
+#define CLK_CFG_18_SET 0x0134
+#define CLK_CFG_18_CLR 0x0138
+#define CLK_CFG_19 0x0140
+#define CLK_CFG_19_SET 0x0144
+#define CLK_CFG_19_CLR 0x0148
+#define CLK_AUDDIV_0 0x020c
+#define CLK_FENC_STATUS_MON_0 0x0270
+#define CLK_FENC_STATUS_MON_1 0x0274
+#define CLK_FENC_STATUS_MON_2 0x0278
+
+/* MUX SHIFT */
+#define TOP_MUX_AXI_SHIFT 0
+#define TOP_MUX_MEM_SUB_SHIFT 1
+#define TOP_MUX_IO_NOC_SHIFT 2
+#define TOP_MUX_PERI_AXI_SHIFT 3
+#define TOP_MUX_UFS_PEXTP0_AXI_SHIFT 4
+#define TOP_MUX_PEXTP1_USB_AXI_SHIFT 5
+#define TOP_MUX_PERI_FMEM_SUB_SHIFT 6
+#define TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT 7
+#define TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT 8
+#define TOP_MUX_PERI_NOC_SHIFT 9
+#define TOP_MUX_EMI_N_SHIFT 10
+#define TOP_MUX_EMI_S_SHIFT 11
+#define TOP_MUX_AP2CONN_HOST_SHIFT 14
+#define TOP_MUX_ATB_SHIFT 15
+#define TOP_MUX_CIRQ_SHIFT 16
+#define TOP_MUX_PBUS_156M_SHIFT 17
+#define TOP_MUX_EFUSE_SHIFT 20
+#define TOP_MUX_MCU_L3GIC_SHIFT 21
+#define TOP_MUX_MCU_INFRA_SHIFT 22
+#define TOP_MUX_DSP_SHIFT 23
+#define TOP_MUX_MFG_REF_SHIFT 24
+#define TOP_MUX_MFG_EB_SHIFT 26
+#define TOP_MUX_UART_SHIFT 27
+#define TOP_MUX_SPI0_BCLK_SHIFT 28
+#define TOP_MUX_SPI1_BCLK_SHIFT 29
+#define TOP_MUX_SPI2_BCLK_SHIFT 30
+#define TOP_MUX_SPI3_BCLK_SHIFT 0
+#define TOP_MUX_SPI4_BCLK_SHIFT 1
+#define TOP_MUX_SPI5_BCLK_SHIFT 2
+#define TOP_MUX_SPI6_BCLK_SHIFT 3
+#define TOP_MUX_SPI7_BCLK_SHIFT 4
+#define TOP_MUX_MSDC30_1_SHIFT 7
+#define TOP_MUX_MSDC30_2_SHIFT 8
+#define TOP_MUX_DISP_PWM_SHIFT 9
+#define TOP_MUX_USB_TOP_1P_SHIFT 10
+#define TOP_MUX_SSUSB_XHCI_1P_SHIFT 11
+#define TOP_MUX_SSUSB_FMCNT_P1_SHIFT 12
+#define TOP_MUX_I2C_PERI_SHIFT 13
+#define TOP_MUX_I2C_EAST_SHIFT 14
+#define TOP_MUX_I2C_WEST_SHIFT 15
+#define TOP_MUX_I2C_NORTH_SHIFT 16
+#define TOP_MUX_AES_UFSFDE_SHIFT 17
+#define TOP_MUX_UFS_SHIFT 18
+#define TOP_MUX_AUD_1_SHIFT 21
+#define TOP_MUX_AUD_2_SHIFT 22
+#define TOP_MUX_ADSP_SHIFT 23
+#define TOP_MUX_ADSP_UARTHUB_BCLK_SHIFT 24
+#define TOP_MUX_DPMAIF_MAIN_SHIFT 25
+#define TOP_MUX_PWM_SHIFT 26
+#define TOP_MUX_MCUPM_SHIFT 27
+#define TOP_MUX_SFLASH_SHIFT 28
+#define TOP_MUX_IPSEAST_SHIFT 29
+#define TOP_MUX_TL_SHIFT 0
+#define TOP_MUX_TL_P1_SHIFT 1
+#define TOP_MUX_TL_P2_SHIFT 2
+#define TOP_MUX_EMI_INTERFACE_546_SHIFT 3
+#define TOP_MUX_SDF_SHIFT 4
+#define TOP_MUX_UARTHUB_BCLK_SHIFT 5
+#define TOP_MUX_DPSW_CMP_26M_SHIFT 6
+#define TOP_MUX_SMAPCK_SHIFT 7
+#define TOP_MUX_SSR_PKA_SHIFT 8
+#define TOP_MUX_SSR_DMA_SHIFT 9
+#define TOP_MUX_SSR_KDF_SHIFT 10
+#define TOP_MUX_SSR_RNG_SHIFT 11
+#define TOP_MUX_SPU0_SHIFT 12
+#define TOP_MUX_SPU1_SHIFT 13
+#define TOP_MUX_DXCC_SHIFT 14
+
+/* CKSTA REG */
+#define CKSTA_REG 0x01c8
+#define CKSTA_REG1 0x01cc
+#define CKSTA_REG2 0x01d0
+
+/* DIVIDER REG */
+#define CLK_AUDDIV_2 0x0214
+#define CLK_AUDDIV_3 0x0220
+#define CLK_AUDDIV_4 0x0224
+#define CLK_AUDDIV_5 0x0228
+
+/* HW Voter REG */
+#define VOTE_CG_0_SET 0x0000
+#define VOTE_CG_0_CLR 0x0004
+#define VOTE_CG_0_DONE 0x2c00
+#define VOTE_CG_1_SET 0x0008
+#define VOTE_CG_1_CLR 0x000c
+#define VOTE_CG_1_DONE 0x2c04
+#define VOTE_CG_2_SET 0x0010
+#define VOTE_CG_2_CLR 0x0014
+#define VOTE_CG_2_DONE 0x2c08
+#define VOTE_CG_3_SET 0x0018
+#define VOTE_CG_3_CLR 0x001c
+#define VOTE_CG_3_DONE 0x2c0c
+#define VOTE_CG_4_SET 0x0020
+#define VOTE_CG_4_CLR 0x0024
+#define VOTE_CG_4_DONE 0x2c10
+#define VOTE_CG_5_SET 0x0028
+#define VOTE_CG_5_CLR 0x002c
+#define VOTE_CG_5_DONE 0x2c14
+#define VOTE_CG_6_SET 0x0030
+#define VOTE_CG_6_CLR 0x0034
+#define VOTE_CG_6_DONE 0x2c18
+#define VOTE_CG_7_SET 0x0038
+#define VOTE_CG_7_CLR 0x003c
+#define VOTE_CG_7_DONE 0x2c1c
+#define VOTE_CG_8_SET 0x0040
+#define VOTE_CG_8_CLR 0x0044
+#define VOTE_CG_8_DONE 0x2c20
+
+static DEFINE_SPINLOCK(mt8196_clk_ck_lock);
+
+static const struct mtk_fixed_factor ck_divs[] = {
+ FACTOR(CLK_CK_MAINPLL_D3, "ck_mainpll_d3", "mainpll", 1, 3),
+ FACTOR(CLK_CK_MAINPLL_D4, "ck_mainpll_d4", "mainpll", 1, 4),
+ FACTOR(CLK_CK_MAINPLL_D4_D2, "ck_mainpll_d4_d2", "mainpll", 1, 8),
+ FACTOR(CLK_CK_MAINPLL_D4_D4, "ck_mainpll_d4_d4", "mainpll", 1, 16),
+ FACTOR(CLK_CK_MAINPLL_D4_D8, "ck_mainpll_d4_d8", "mainpll", 1, 32),
+ FACTOR(CLK_CK_MAINPLL_D5, "ck_mainpll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_CK_MAINPLL_D5_D2, "ck_mainpll_d5_d2", "mainpll", 1, 10),
+ FACTOR(CLK_CK_MAINPLL_D5_D4, "ck_mainpll_d5_d4", "mainpll", 1, 20),
+ FACTOR(CLK_CK_MAINPLL_D5_D8, "ck_mainpll_d5_d8", "mainpll", 1, 40),
+ FACTOR(CLK_CK_MAINPLL_D6, "ck_mainpll_d6", "mainpll", 1, 6),
+ FACTOR(CLK_CK_MAINPLL_D6_D2, "ck_mainpll_d6_d2", "mainpll", 1, 12),
+ FACTOR(CLK_CK_MAINPLL_D7, "ck_mainpll_d7", "mainpll", 1, 7),
+ FACTOR(CLK_CK_MAINPLL_D7_D2, "ck_mainpll_d7_d2", "mainpll", 1, 14),
+ FACTOR(CLK_CK_MAINPLL_D7_D4, "ck_mainpll_d7_d4", "mainpll", 1, 28),
+ FACTOR(CLK_CK_MAINPLL_D7_D8, "ck_mainpll_d7_d8", "mainpll", 1, 56),
+ FACTOR(CLK_CK_MAINPLL_D9, "ck_mainpll_d9", "mainpll", 1, 9),
+ FACTOR(CLK_CK_UNIVPLL_D4, "ck_univpll_d4", "univpll", 1, 4),
+ FACTOR(CLK_CK_UNIVPLL_D4_D2, "ck_univpll_d4_d2", "univpll", 1, 8),
+ FACTOR(CLK_CK_UNIVPLL_D4_D4, "ck_univpll_d4_d4", "univpll", 1, 16),
+ FACTOR(CLK_CK_UNIVPLL_D4_D8, "ck_univpll_d4_d8", "univpll", 1, 32),
+ FACTOR(CLK_CK_UNIVPLL_D5, "ck_univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_CK_UNIVPLL_D5_D2, "ck_univpll_d5_d2", "univpll", 1, 10),
+ FACTOR(CLK_CK_UNIVPLL_D5_D4, "ck_univpll_d5_d4", "univpll", 1, 20),
+ FACTOR(CLK_CK_UNIVPLL_D6, "ck_univpll_d6", "univpll", 1, 6),
+ FACTOR(CLK_CK_UNIVPLL_D6_D2, "ck_univpll_d6_d2", "univpll", 1, 12),
+ FACTOR(CLK_CK_UNIVPLL_D6_D4, "ck_univpll_d6_d4", "univpll", 1, 24),
+ FACTOR(CLK_CK_UNIVPLL_D6_D8, "ck_univpll_d6_d8", "univpll", 1, 48),
+ FACTOR(CLK_CK_UNIVPLL_D6_D16, "ck_univpll_d6_d16", "univpll", 1, 96),
+ FACTOR(CLK_CK_UNIVPLL_192M, "ck_univpll_192m", "univpll", 1, 13),
+ FACTOR(CLK_CK_UNIVPLL_192M_D4, "ck_univpll_192m_d4", "univpll", 1, 52),
+ FACTOR(CLK_CK_UNIVPLL_192M_D8, "ck_univpll_192m_d8", "univpll", 1, 104),
+ FACTOR(CLK_CK_UNIVPLL_192M_D16, "ck_univpll_192m_d16", "univpll", 1, 208),
+ FACTOR(CLK_CK_UNIVPLL_192M_D32, "ck_univpll_192m_d32", "univpll", 1, 416),
+ FACTOR(CLK_CK_UNIVPLL_192M_D10, "ck_univpll_192m_d10", "univpll", 1, 130),
+ FACTOR(CLK_CK_APLL1, "ck_apll1_ck", "vlp_apll1", 1, 1),
+ FACTOR(CLK_CK_APLL1_D4, "ck_apll1_d4", "vlp_apll1", 1, 4),
+ FACTOR(CLK_CK_APLL1_D8, "ck_apll1_d8", "vlp_apll1", 1, 8),
+ FACTOR(CLK_CK_APLL2, "ck_apll2_ck", "vlp_apll2", 1, 1),
+ FACTOR(CLK_CK_APLL2_D4, "ck_apll2_d4", "vlp_apll2", 1, 4),
+ FACTOR(CLK_CK_APLL2_D8, "ck_apll2_d8", "vlp_apll2", 1, 8),
+ FACTOR(CLK_CK_ADSPPLL, "ck_adsppll_ck", "adsppll", 1, 1),
+ FACTOR(CLK_CK_EMIPLL1, "ck_emipll1_ck", "emipll", 1, 1),
+ FACTOR(CLK_CK_TVDPLL1_D2, "ck_tvdpll1_d2", "tvdpll1", 1, 2),
+ FACTOR(CLK_CK_MSDCPLL_D2, "ck_msdcpll_d2", "msdcpll", 1, 2),
+ FACTOR(CLK_CK_CLKRTC, "ck_clkrtc", "clk32k", 1, 1),
+ FACTOR(CLK_CK_TCK_26M_MX9, "ck_tck_26m_mx9_ck", "clk26m", 1, 1),
+ FACTOR(CLK_CK_F26M, "ck_f26m_ck", "clk26m", 1, 1),
+ FACTOR(CLK_CK_F26M_CK_D2, "ck_f26m_d2", "clk13m", 1, 1),
+ FACTOR(CLK_CK_OSC, "ck_osc", "ulposc", 1, 1),
+ FACTOR(CLK_CK_OSC_D2, "ck_osc_d2", "ulposc", 1, 2),
+ FACTOR(CLK_CK_OSC_D3, "ck_osc_d3", "ulposc", 1, 3),
+ FACTOR(CLK_CK_OSC_D4, "ck_osc_d4", "ulposc", 1, 4),
+ FACTOR(CLK_CK_OSC_D5, "ck_osc_d5", "ulposc", 1, 5),
+ FACTOR(CLK_CK_OSC_D7, "ck_osc_d7", "ulposc", 1, 7),
+ FACTOR(CLK_CK_OSC_D8, "ck_osc_d8", "ulposc", 1, 8),
+ FACTOR(CLK_CK_OSC_D10, "ck_osc_d10", "ulposc", 1, 10),
+ FACTOR(CLK_CK_OSC_D14, "ck_osc_d14", "ulposc", 1, 14),
+ FACTOR(CLK_CK_OSC_D20, "ck_osc_d20", "ulposc", 1, 20),
+ FACTOR(CLK_CK_OSC_D32, "ck_osc_d32", "ulposc", 1, 32),
+ FACTOR(CLK_CK_OSC_D40, "ck_osc_d40", "ulposc", 1, 40),
+ FACTOR(CLK_CK_OSC3, "ck_osc3", "ulposc3", 1, 1),
+ FACTOR(CLK_CK_P_AXI, "ck_p_axi_ck", "ck_p_axi_sel", 1, 1),
+ FACTOR(CLK_CK_PEXTP0_AXI, "ck_pextp0_axi_ck", "ck_pextp0_axi_sel", 1, 1),
+ FACTOR(CLK_CK_PEXTP1_USB_AXI, "ck_pextp1_usb_axi_ck", "ck_pextp1_usb_axi_sel", 1, 1),
+ FACTOR(CLK_CK_PEXPT0_MEM_SUB, "ck_pexpt0_mem_sub_ck", "ck_pexpt0_mem_sub_sel", 1, 1),
+ FACTOR(CLK_CK_PEXTP1_USB_MEM_SUB, "ck_pextp1_usb_mem_sub_ck", "ck_pextp1_usb_mem_sub_sel", 1, 1),
+ FACTOR(CLK_CK_UART, "ck_uart_ck", "ck_uart_sel", 1, 1),
+ FACTOR(CLK_CK_SPI0_BCLK, "ck_spi0_b_ck", "ck_spi0_b_sel", 1, 1),
+ FACTOR(CLK_CK_SPI1_BCLK, "ck_spi1_b_ck", "ck_spi1_b_sel", 1, 1),
+ FACTOR(CLK_CK_SPI2_BCLK, "ck_spi2_b_ck", "ck_spi2_b_sel", 1, 1),
+ FACTOR(CLK_CK_SPI3_BCLK, "ck_spi3_b_ck", "ck_spi3_b_sel", 1, 1),
+ FACTOR(CLK_CK_SPI4_BCLK, "ck_spi4_b_ck", "ck_spi4_b_sel", 1, 1),
+ FACTOR(CLK_CK_SPI5_BCLK, "ck_spi5_b_ck", "ck_spi5_b_sel", 1, 1),
+ FACTOR(CLK_CK_SPI6_BCLK, "ck_spi6_b_ck", "ck_spi6_b_sel", 1, 1),
+ FACTOR(CLK_CK_SPI7_BCLK, "ck_spi7_b_ck", "ck_spi7_b_sel", 1, 1),
+ FACTOR(CLK_CK_MSDC30_1, "ck_msdc30_1_ck", "ck_msdc30_1_sel", 1, 1),
+ FACTOR(CLK_CK_MSDC30_2, "ck_msdc30_2_ck", "ck_msdc30_2_sel", 1, 1),
+ FACTOR(CLK_CK_I2C_PERI, "ck_i2c_p_ck", "ck_i2c_p_sel", 1, 1),
+ FACTOR(CLK_CK_I2C_EAST, "ck_i2c_east_ck", "ck_i2c_east_sel", 1, 1),
+ FACTOR(CLK_CK_I2C_WEST, "ck_i2c_west_ck", "ck_i2c_west_sel", 1, 1),
+ FACTOR(CLK_CK_I2C_NORTH, "ck_i2c_north_ck", "ck_i2c_north_sel", 1, 1),
+ FACTOR(CLK_CK_AES_UFSFDE, "ck_aes_ufsfde_ck", "ck_aes_ufsfde_sel", 1, 1),
+ FACTOR(CLK_CK_UFS, "ck_ck", "ck_sel", 1, 1),
+ FACTOR(CLK_CK_AUD_1, "ck_aud_1_ck", "ck_aud_1_sel", 1, 1),
+ FACTOR(CLK_CK_AUD_2, "ck_aud_2_ck", "ck_aud_2_sel", 1, 1),
+ FACTOR(CLK_CK_DPMAIF_MAIN, "ck_dpmaif_main_ck", "ck_dpmaif_main_sel", 1, 1),
+ FACTOR(CLK_CK_PWM, "ck_pwm_ck", "ck_pwm_sel", 1, 1),
+ FACTOR(CLK_CK_TL, "ck_tl_ck", "ck_tl_sel", 1, 1),
+ FACTOR(CLK_CK_TL_P1, "ck_tl_p1_ck", "ck_tl_p1_sel", 1, 1),
+ FACTOR(CLK_CK_TL_P2, "ck_tl_p2_ck", "ck_tl_p2_sel", 1, 1),
+ FACTOR(CLK_CK_SSR_RNG, "ck_ssr_rng_ck", "ck_ssr_rng_sel", 1, 1),
+ FACTOR(CLK_CK_SFLASH, "ck_sflash_ck", "ck_sflash_sel", 1, 1),
+};
+
+static const char * const ck_axi_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_osc_d8",
+ "ck_osc_d4",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const ck_mem_sub_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_osc_d4",
+ "ck_univpll_d4_d4",
+ "ck_osc_d3",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5",
+ "ck_univpll_d5",
+ "ck_mainpll_d4",
+ "ck_mainpll_d3"
+};
+
+static const char * const ck_io_noc_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_osc_d8",
+ "ck_osc_d4",
+ "ck_mainpll_d6_d2",
+ "ck_mainpll_d9"
+};
+
+static const char * const ck_p_axi_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d8",
+ "ck_mainpll_d5_d8",
+ "ck_osc_d8",
+ "ck_mainpll_d7_d4",
+ "ck_mainpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const ck_pextp0_axi_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d8",
+ "ck_mainpll_d5_d8",
+ "ck_osc_d8",
+ "ck_mainpll_d7_d4",
+ "ck_mainpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const ck_pextp1_usb_axi_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d8",
+ "ck_mainpll_d5_d8",
+ "ck_osc_d8",
+ "ck_mainpll_d7_d4",
+ "ck_mainpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const ck_p_fmem_sub_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d8",
+ "ck_mainpll_d5_d4",
+ "ck_osc_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5",
+ "ck_univpll_d5",
+ "ck_mainpll_d4"
+};
+
+static const char * const ck_pexpt0_mem_sub_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d8",
+ "ck_mainpll_d5_d4",
+ "ck_osc_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5",
+ "ck_univpll_d5",
+ "ck_mainpll_d4"
+};
+
+static const char * const ck_pextp1_usb_mem_sub_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d8",
+ "ck_mainpll_d5_d4",
+ "ck_osc_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5",
+ "ck_univpll_d5",
+ "ck_mainpll_d4"
+};
+
+static const char * const ck_p_noc_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d8",
+ "ck_mainpll_d5_d4",
+ "ck_osc_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5",
+ "ck_univpll_d5",
+ "ck_mainpll_d4",
+ "ck_mainpll_d3"
+};
+
+static const char * const ck_emi_n_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_mainpll_d5_d8",
+ "ck_mainpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_emipll1_ck"
+};
+
+static const char * const ck_emi_s_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_mainpll_d5_d8",
+ "ck_mainpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_emipll1_ck"
+};
+
+static const char * const ck_ap2conn_host_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d4"
+};
+
+static const char * const ck_atb_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6"
+};
+
+static const char * const ck_cirq_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d7_d4"
+};
+
+static const char * const ck_pbus_156m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d2",
+ "ck_osc_d2",
+ "ck_mainpll_d7"
+};
+
+static const char * const ck_efuse_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const ck_mcl3gic_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d8",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const ck_mcinfra_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d9",
+ "ck_mainpll_d6"
+};
+
+static const char * const ck_dsp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d5",
+ "ck_osc_d4",
+ "ck_osc_d3",
+ "ck_univpll_d6_d2",
+ "ck_osc_d2",
+ "ck_univpll_d5",
+ "ck_osc"
+};
+
+static const char * const ck_mfg_ref_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const ck_mfg_eb_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d6_d2",
+ "ck_mainpll_d5_d2"
+};
+
+static const char * const ck_uart_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d8",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi0_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi1_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi2_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi3_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi4_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi5_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi6_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_spi7_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d4_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_192m",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_msdc30_1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_d6_d2",
+ "ck_msdcpll_d2"
+};
+
+static const char * const ck_msdc30_2_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_d6_d2",
+ "ck_msdcpll_d2"
+};
+
+static const char * const ck_disp_pwm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d32",
+ "ck_osc_d8",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d5_d4",
+ "ck_osc_d4",
+ "ck_mainpll_d4_d4"
+};
+
+static const char * const ck_usb_1p_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d5_d4"
+};
+
+static const char * const ck_usb_xhci_1p_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d5_d4"
+};
+
+static const char * const ck_usb_fmcnt_p1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d4"
+};
+
+static const char * const ck_i2c_p_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d8",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d5_d2"
+};
+
+static const char * const ck_i2c_east_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d8",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d5_d2"
+};
+
+static const char * const ck_i2c_west_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d8",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d5_d2"
+};
+
+static const char * const ck_i2c_north_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d8",
+ "ck_univpll_d5_d4",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d5_d2"
+};
+
+static const char * const ck_aes_ufsfde_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d6_d2",
+ "ck_mainpll_d4_d2",
+ "ck_univpll_d6",
+ "ck_mainpll_d4"
+};
+
+static const char * const ck_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_univpll_d6_d2",
+ "ck_mainpll_d4_d2",
+ "ck_univpll_d6",
+ "ck_mainpll_d5",
+ "ck_univpll_d5"
+};
+
+static const char * const ck_aud_1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_apll1_ck"
+};
+
+static const char * const ck_aud_2_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_apll2_ck"
+};
+
+static const char * const ck_adsp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_adsppll_ck"
+};
+
+static const char * const ck_adsp_uarthub_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_dpmaif_main_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d4_d4",
+ "ck_univpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_univpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck_univpll_d6",
+ "ck_mainpll_d5",
+ "ck_univpll_d5"
+};
+
+static const char * const ck_pwm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d4",
+ "ck_univpll_d4_d8"
+};
+
+static const char * const ck_mcupm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d6_d2",
+ "ck_univpll_d6_d2",
+ "ck_mainpll_d5_d2"
+};
+
+static const char * const ck_ipseast_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5",
+ "ck_mainpll_d4",
+ "ck_mainpll_d3"
+};
+
+static const char * const ck_tl_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d4",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d5_d2"
+};
+
+static const char * const ck_tl_p1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d4",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d5_d2"
+};
+
+static const char * const ck_tl_p2_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d4",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d5_d2"
+};
+
+static const char * const ck_md_emi_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4"
+};
+
+static const char * const ck_sdf_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck_mainpll_d4",
+ "ck_univpll_d4"
+};
+
+static const char * const ck_uarthub_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_d6_d4",
+ "ck_univpll_d6_d2"
+};
+
+static const char * const ck_dpsw_cmp_26m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const ck_smapck_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d8"
+};
+
+static const char * const ck_ssr_pka_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d7",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5"
+};
+
+static const char * const ck_ssr_dma_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d7",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5"
+};
+
+static const char * const ck_ssr_kdf_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d7"
+};
+
+static const char * const ck_ssr_rng_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2"
+};
+
+static const char * const ck_spu0_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d7",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5"
+};
+
+static const char * const ck_spu1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d7",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5"
+};
+
+static const char * const ck_dxcc_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d4_d8",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2"
+};
+
+static const char * const ck_apll_i2sin0_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sin1_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sin2_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sin3_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sin4_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sin6_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sout0_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sout1_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sout2_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sout3_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sout4_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_i2sout6_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_fmi2s_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_apll_tdmout_m_parents[] = {
+ "ck_aud_1_sel",
+ "ck_aud_2_sel"
+};
+
+static const char * const ck_sflash_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d8",
+ "ck_univpll_d6_d8"
+};
+
+static const struct mtk_mux ck_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD(CLK_CK_AXI_SEL, "ck_axi_sel",
+ ck_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR, 0, 3,
+ CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_MEM_SUB_SEL, "ck_mem_sub_sel",
+ ck_mem_sub_parents, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR, 8, 4,
+ CLK_CFG_UPDATE, TOP_MUX_MEM_SUB_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_IO_NOC_SEL, "ck_io_noc_sel",
+ ck_io_noc_parents, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR, 16, 3,
+ CLK_CFG_UPDATE, TOP_MUX_IO_NOC_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_P_AXI_SEL, "ck_p_axi_sel",
+ ck_p_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
+ CLK_CFG_0_CLR, 24, 3,
+ CLK_CFG_UPDATE, TOP_MUX_PERI_AXI_SHIFT),
+ /* CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_CK_PEXTP0_AXI_SEL, "ck_pextp0_axi_sel",
+ ck_pextp0_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR, 0, 3,
+ CLK_CFG_UPDATE, TOP_MUX_UFS_PEXTP0_AXI_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_PEXTP1_USB_AXI_SEL, "ck_pextp1_usb_axi_sel",
+ ck_pextp1_usb_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR, 8, 3,
+ CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_AXI_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_P_FMEM_SUB_SEL, "ck_p_fmem_sub_sel",
+ ck_p_fmem_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR, 16, 4,
+ CLK_CFG_UPDATE, TOP_MUX_PERI_FMEM_SUB_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_PEXPT0_MEM_SUB_SEL, "ck_pexpt0_mem_sub_sel",
+ ck_pexpt0_mem_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
+ CLK_CFG_1_CLR, 24, 4,
+ CLK_CFG_UPDATE, TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT),
+ /* CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_CK_PEXTP1_USB_MEM_SUB_SEL, "ck_pextp1_usb_mem_sub_sel",
+ ck_pextp1_usb_mem_sub_parents, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR, 0, 4,
+ CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_P_NOC_SEL, "ck_p_noc_sel",
+ ck_p_noc_parents, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR, 8, 4,
+ CLK_CFG_UPDATE, TOP_MUX_PERI_NOC_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_EMI_N_SEL, "ck_emi_n_sel",
+ ck_emi_n_parents, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR, 16, 3,
+ CLK_CFG_UPDATE, TOP_MUX_EMI_N_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_EMI_S_SEL, "ck_emi_s_sel",
+ ck_emi_s_parents, CLK_CFG_2, CLK_CFG_2_SET,
+ CLK_CFG_2_CLR, 24, 3,
+ CLK_CFG_UPDATE, TOP_MUX_EMI_S_SHIFT),
+ /* CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_CK_AP2CONN_HOST_SEL, "ck_ap2conn_host_sel",
+ ck_ap2conn_host_parents, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR, 16, 1,
+ CLK_CFG_UPDATE, TOP_MUX_AP2CONN_HOST_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_ATB_SEL, "ck_atb_sel",
+ ck_atb_parents, CLK_CFG_3, CLK_CFG_3_SET,
+ CLK_CFG_3_CLR, 24, 2,
+ CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT),
+ /* CLK_CFG_4 */
+ MUX_CLR_SET_UPD(CLK_CK_CIRQ_SEL, "ck_cirq_sel",
+ ck_cirq_parents, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR, 0, 2,
+ CLK_CFG_UPDATE, TOP_MUX_CIRQ_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_PBUS_156M_SEL, "ck_pbus_156m_sel",
+ ck_pbus_156m_parents, CLK_CFG_4, CLK_CFG_4_SET,
+ CLK_CFG_4_CLR, 8, 2,
+ CLK_CFG_UPDATE, TOP_MUX_PBUS_156M_SHIFT),
+ /* CLK_CFG_5 */
+ MUX_CLR_SET_UPD(CLK_CK_EFUSE_SEL, "ck_efuse_sel",
+ ck_efuse_parents, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR, 0, 1,
+ CLK_CFG_UPDATE, TOP_MUX_EFUSE_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_MCL3GIC_SEL, "ck_mcl3gic_sel",
+ ck_mcl3gic_parents, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR, 8, 2,
+ CLK_CFG_UPDATE, TOP_MUX_MCU_L3GIC_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_MCINFRA_SEL, "ck_mcinfra_sel",
+ ck_mcinfra_parents, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR, 16, 3,
+ CLK_CFG_UPDATE, TOP_MUX_MCU_INFRA_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_DSP_SEL, "ck_dsp_sel",
+ ck_dsp_parents, CLK_CFG_5, CLK_CFG_5_SET,
+ CLK_CFG_5_CLR, 24, 3,
+ CLK_CFG_UPDATE, TOP_MUX_DSP_SHIFT),
+ /* CLK_CFG_6 */
+ MUX_GATE_FENC_CLR_SET_UPD_FLAGS(CLK_CK_MFG_REF_SEL, "ck_mfg_ref_sel", ck_mfg_ref_parents,
+ CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR,
+ 0, 1, 7, CLK_CFG_UPDATE, TOP_MUX_MFG_REF_SHIFT,
+ CLK_FENC_STATUS_MON_0, 7, CLK_IGNORE_UNUSED),
+ MUX_CLR_SET_UPD(CLK_CK_MFG_EB_SEL, "ck_mfg_eb_sel",
+ ck_mfg_eb_parents, CLK_CFG_6, CLK_CFG_6_SET,
+ CLK_CFG_6_CLR, 16, 2,
+ CLK_CFG_UPDATE, TOP_MUX_MFG_EB_SHIFT),
+ MUX_MULT_VOTE_FENC(CLK_CK_UART_SEL, "ck_uart_sel", ck_uart_parents,
+ CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, "vote-regmap",
+ VOTE_CG_3_DONE, VOTE_CG_3_SET, VOTE_CG_3_CLR,
+ 24, 2, 31, CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT,
+ CLK_FENC_STATUS_MON_0, 4),
+ /* CLK_CFG_7 */
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI0_BCLK_SEL, "ck_spi0_b_sel", ck_spi0_b_parents,
+ CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
+ VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
+ 0, 3, 7, CLK_CFG_UPDATE, TOP_MUX_SPI0_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_0, 3),
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI1_BCLK_SEL, "ck_spi1_b_sel", ck_spi1_b_parents,
+ CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
+ VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
+ 8, 3, 15, CLK_CFG_UPDATE, TOP_MUX_SPI1_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_0, 2),
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI2_BCLK_SEL, "ck_spi2_b_sel", ck_spi2_b_parents,
+ CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
+ VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
+ 16, 3, 23, CLK_CFG_UPDATE, TOP_MUX_SPI2_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_0, 1),
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI3_BCLK_SEL, "ck_spi3_b_sel", ck_spi3_b_parents,
+ CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
+ VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
+ 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI3_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_0, 0),
+ /* CLK_CFG_8 */
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI4_BCLK_SEL, "ck_spi4_b_sel", ck_spi4_b_parents,
+ CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
+ VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
+ 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_SPI4_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_1, 31),
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI5_BCLK_SEL, "ck_spi5_b_sel", ck_spi5_b_parents,
+ CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
+ VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
+ 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_SPI5_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_1, 30),
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI6_BCLK_SEL, "ck_spi6_b_sel", ck_spi6_b_parents,
+ CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
+ VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
+ 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_SPI6_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_1, 29),
+ MUX_MULT_VOTE_FENC(CLK_CK_SPI7_BCLK_SEL, "ck_spi7_b_sel", ck_spi7_b_parents,
+ CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
+ VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
+ 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI7_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_1, 28),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_MSDC30_1_SEL, "ck_msdc30_1_sel", ck_msdc30_1_parents,
+ CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
+ 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_1_SHIFT,
+ CLK_FENC_STATUS_MON_1, 25),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_MSDC30_2_SEL, "ck_msdc30_2_sel", ck_msdc30_2_parents,
+ CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
+ 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_2_SHIFT,
+ CLK_FENC_STATUS_MON_1, 24),
+ /* CLK_CFG_10 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_DISP_PWM_SEL, "ck_disp_pwm_sel", ck_disp_pwm_parents,
+ CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
+ 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_DISP_PWM_SHIFT,
+ CLK_FENC_STATUS_MON_1, 23),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_USB_TOP_1P_SEL, "ck_usb_1p_sel", ck_usb_1p_parents,
+ CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
+ 8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_1P_SHIFT,
+ CLK_FENC_STATUS_MON_1, 22),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_USB_XHCI_1P_SEL, "ck_usb_xhci_1p_sel", ck_usb_xhci_1p_parents,
+ CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
+ 16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_1P_SHIFT,
+ CLK_FENC_STATUS_MON_1, 21),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_USB_FMCNT_P1_SEL, "ck_usb_fmcnt_p1_sel", ck_usb_fmcnt_p1_parents,
+ CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
+ 24, 1, 31, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_FMCNT_P1_SHIFT,
+ CLK_FENC_STATUS_MON_1, 20),
+ /* CLK_CFG_11 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_I2C_P_SEL, "ck_i2c_p_sel", ck_i2c_p_parents,
+ CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
+ 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_I2C_PERI_SHIFT,
+ CLK_FENC_STATUS_MON_1, 19),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_I2C_EAST_SEL, "ck_i2c_east_sel", ck_i2c_east_parents,
+ CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
+ 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_I2C_EAST_SHIFT,
+ CLK_FENC_STATUS_MON_1, 18),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_I2C_WEST_SEL, "ck_i2c_west_sel", ck_i2c_west_parents,
+ CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
+ 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_I2C_WEST_SHIFT,
+ CLK_FENC_STATUS_MON_1, 17),
+ MUX_MULT_VOTE_FENC(CLK_CK_I2C_NORTH_SEL, "ck_i2c_north_sel", ck_i2c_north_parents,
+ CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR, "vote-regmap",
+ VOTE_CG_6_DONE, VOTE_CG_6_SET, VOTE_CG_6_CLR,
+ 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_I2C_NORTH_SHIFT,
+ CLK_FENC_STATUS_MON_1, 16),
+ /* CLK_CFG_12 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_AES_UFSFDE_SEL, "ck_aes_ufsfde_sel", ck_aes_ufsfde_parents,
+ CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
+ 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT,
+ CLK_FENC_STATUS_MON_1, 15),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_SEL, "ck_sel", ck_parents,
+ CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
+ 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT,
+ CLK_FENC_STATUS_MON_1, 14),
+ /* CLK_CFG_13 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_AUD_1_SEL, "ck_aud_1_sel", ck_aud_1_parents,
+ CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
+ 0, 1, 7, CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT,
+ CLK_FENC_STATUS_MON_1, 11),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_AUD_2_SEL, "ck_aud_2_sel", ck_aud_2_parents,
+ CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
+ 8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT,
+ CLK_FENC_STATUS_MON_1, 10),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_ADSP_SEL, "ck_adsp_sel", ck_adsp_parents,
+ CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
+ 16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_ADSP_SHIFT,
+ CLK_FENC_STATUS_MON_1, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_CK_ADSP_UARTHUB_BCLK_SEL, "ck_adsp_uarthub_b_sel",
+ ck_adsp_uarthub_b_parents, CLK_CFG_13, CLK_CFG_13_SET,
+ CLK_CFG_13_CLR, 24, 2, 31,
+ CLK_CFG_UPDATE1, TOP_MUX_ADSP_UARTHUB_BCLK_SHIFT),
+ /* CLK_CFG_14 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_DPMAIF_MAIN_SEL, "ck_dpmaif_main_sel", ck_dpmaif_main_parents,
+ CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
+ 0, 4, 7, CLK_CFG_UPDATE1, TOP_MUX_DPMAIF_MAIN_SHIFT,
+ CLK_FENC_STATUS_MON_1, 7),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_PWM_SEL, "ck_pwm_sel", ck_pwm_parents,
+ CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
+ 8, 2, 15, CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT,
+ CLK_FENC_STATUS_MON_1, 6),
+ MUX_CLR_SET_UPD(CLK_CK_MCUPM_SEL, "ck_mcupm_sel",
+ ck_mcupm_parents, CLK_CFG_14, CLK_CFG_14_SET,
+ CLK_CFG_14_CLR, 16, 3,
+ CLK_CFG_UPDATE1, TOP_MUX_MCUPM_SHIFT),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_SFLASH_SEL, "ck_sflash_sel", ck_sflash_parents,
+ CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
+ 24, 2, 31, CLK_CFG_UPDATE1, TOP_MUX_SFLASH_SHIFT,
+ CLK_FENC_STATUS_MON_1, 4),
+ /* CLK_CFG_15 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_IPSEAST_SEL, "ck_ipseast_sel", ck_ipseast_parents,
+ CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
+ 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_IPSEAST_SHIFT,
+ CLK_FENC_STATUS_MON_1, 3),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_TL_SEL, "ck_tl_sel", ck_tl_parents,
+ CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
+ 16, 2, 23, CLK_CFG_UPDATE2, TOP_MUX_TL_SHIFT,
+ CLK_FENC_STATUS_MON_1, 1),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_TL_P1_SEL, "ck_tl_p1_sel", ck_tl_p1_parents,
+ CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
+ 24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_TL_P1_SHIFT,
+ CLK_FENC_STATUS_MON_1, 0),
+ /* CLK_CFG_16 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_TL_P2_SEL, "ck_tl_p2_sel", ck_tl_p2_parents,
+ CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR,
+ 0, 2, 7, CLK_CFG_UPDATE2, TOP_MUX_TL_P2_SHIFT,
+ CLK_FENC_STATUS_MON_2, 31),
+ MUX_CLR_SET_UPD(CLK_CK_EMI_INTERFACE_546_SEL, "ck_md_emi_sel",
+ ck_md_emi_parents, CLK_CFG_16, CLK_CFG_16_SET,
+ CLK_CFG_16_CLR, 8, 1,
+ CLK_CFG_UPDATE2, TOP_MUX_EMI_INTERFACE_546_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_SDF_SEL, "ck_sdf_sel",
+ ck_sdf_parents, CLK_CFG_16, CLK_CFG_16_SET,
+ CLK_CFG_16_CLR, 16, 3,
+ CLK_CFG_UPDATE2, TOP_MUX_SDF_SHIFT),
+ MUX_MULT_VOTE_FENC(CLK_CK_UARTHUB_BCLK_SEL, "ck_uarthub_b_sel", ck_uarthub_b_parents,
+ CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR, "vote-regmap",
+ VOTE_CG_7_DONE, VOTE_CG_7_SET, VOTE_CG_7_CLR,
+ 24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_UARTHUB_BCLK_SHIFT,
+ CLK_FENC_STATUS_MON_2, 28),
+ /* CLK_CFG_17 */
+ MUX_CLR_SET_UPD(CLK_CK_DPSW_CMP_26M_SEL, "ck_dpsw_cmp_26m_sel",
+ ck_dpsw_cmp_26m_parents, CLK_CFG_17, CLK_CFG_17_SET,
+ CLK_CFG_17_CLR, 0, 1,
+ CLK_CFG_UPDATE2, TOP_MUX_DPSW_CMP_26M_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_SMAPCK_SEL, "ck_smapck_sel",
+ ck_smapck_parents, CLK_CFG_17, CLK_CFG_17_SET,
+ CLK_CFG_17_CLR, 8, 1,
+ CLK_CFG_UPDATE2, TOP_MUX_SMAPCK_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_SSR_PKA_SEL, "ck_ssr_pka_sel",
+ ck_ssr_pka_parents, CLK_CFG_17, CLK_CFG_17_SET,
+ CLK_CFG_17_CLR, 16, 3,
+ CLK_CFG_UPDATE2, TOP_MUX_SSR_PKA_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_SSR_DMA_SEL, "ck_ssr_dma_sel",
+ ck_ssr_dma_parents, CLK_CFG_17, CLK_CFG_17_SET,
+ CLK_CFG_17_CLR, 24, 3,
+ CLK_CFG_UPDATE2, TOP_MUX_SSR_DMA_SHIFT),
+ /* CLK_CFG_18 */
+ MUX_CLR_SET_UPD(CLK_CK_SSR_KDF_SEL, "ck_ssr_kdf_sel",
+ ck_ssr_kdf_parents, CLK_CFG_18, CLK_CFG_18_SET,
+ CLK_CFG_18_CLR, 0, 2,
+ CLK_CFG_UPDATE2, TOP_MUX_SSR_KDF_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_SSR_RNG_SEL, "ck_ssr_rng_sel",
+ ck_ssr_rng_parents, CLK_CFG_18, CLK_CFG_18_SET,
+ CLK_CFG_18_CLR, 8, 2,
+ CLK_CFG_UPDATE2, TOP_MUX_SSR_RNG_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_SPU0_SEL, "ck_spu0_sel",
+ ck_spu0_parents, CLK_CFG_18, CLK_CFG_18_SET,
+ CLK_CFG_18_CLR, 16, 3,
+ CLK_CFG_UPDATE2, TOP_MUX_SPU0_SHIFT),
+ MUX_CLR_SET_UPD(CLK_CK_SPU1_SEL, "ck_spu1_sel",
+ ck_spu1_parents, CLK_CFG_18, CLK_CFG_18_SET,
+ CLK_CFG_18_CLR, 24, 3,
+ CLK_CFG_UPDATE2, TOP_MUX_SPU1_SHIFT),
+ /* CLK_CFG_19 */
+ MUX_CLR_SET_UPD(CLK_CK_DXCC_SEL, "ck_dxcc_sel",
+ ck_dxcc_parents, CLK_CFG_19, CLK_CFG_19_SET,
+ CLK_CFG_19_CLR, 0, 2,
+ CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT),
+};
+
+static const struct mtk_composite ck_composites[] = {
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_CK_APLL_I2SIN0_MCK_SEL, "ck_apll_i2sin0_m_sel",
+ ck_apll_i2sin0_m_parents, 0x020c, 16, 1),
+ MUX(CLK_CK_APLL_I2SIN1_MCK_SEL, "ck_apll_i2sin1_m_sel",
+ ck_apll_i2sin1_m_parents, 0x020c, 17, 1),
+ MUX(CLK_CK_APLL_I2SIN2_MCK_SEL, "ck_apll_i2sin2_m_sel",
+ ck_apll_i2sin2_m_parents, 0x020c, 18, 1),
+ MUX(CLK_CK_APLL_I2SIN3_MCK_SEL, "ck_apll_i2sin3_m_sel",
+ ck_apll_i2sin3_m_parents, 0x020c, 19, 1),
+ MUX(CLK_CK_APLL_I2SIN4_MCK_SEL, "ck_apll_i2sin4_m_sel",
+ ck_apll_i2sin4_m_parents, 0x020c, 20, 1),
+ MUX(CLK_CK_APLL_I2SIN6_MCK_SEL, "ck_apll_i2sin6_m_sel",
+ ck_apll_i2sin6_m_parents, 0x020c, 21, 1),
+ MUX(CLK_CK_APLL_I2SOUT0_MCK_SEL, "ck_apll_i2sout0_m_sel",
+ ck_apll_i2sout0_m_parents, 0x020c, 22, 1),
+ MUX(CLK_CK_APLL_I2SOUT1_MCK_SEL, "ck_apll_i2sout1_m_sel",
+ ck_apll_i2sout1_m_parents, 0x020c, 23, 1),
+ MUX(CLK_CK_APLL_I2SOUT2_MCK_SEL, "ck_apll_i2sout2_m_sel",
+ ck_apll_i2sout2_m_parents, 0x020c, 24, 1),
+ MUX(CLK_CK_APLL_I2SOUT3_MCK_SEL, "ck_apll_i2sout3_m_sel",
+ ck_apll_i2sout3_m_parents, 0x020c, 25, 1),
+ MUX(CLK_CK_APLL_I2SOUT4_MCK_SEL, "ck_apll_i2sout4_m_sel",
+ ck_apll_i2sout4_m_parents, 0x020c, 26, 1),
+ MUX(CLK_CK_APLL_I2SOUT6_MCK_SEL, "ck_apll_i2sout6_m_sel",
+ ck_apll_i2sout6_m_parents, 0x020c, 27, 1),
+ MUX(CLK_CK_APLL_FMI2S_MCK_SEL, "ck_apll_fmi2s_m_sel",
+ ck_apll_fmi2s_m_parents, 0x020c, 28, 1),
+ MUX(CLK_CK_APLL_TDMOUT_MCK_SEL, "ck_apll_tdmout_m_sel",
+ ck_apll_tdmout_m_parents, 0x020c, 29, 1),
+ /* CLK_AUDDIV_2 */
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN0, "ck_apll12_div_i2sin0",
+ "ck_apll_i2sin0_m_sel", 0x020c,
+ 0, CLK_AUDDIV_2, 8, 0),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN1, "ck_apll12_div_i2sin1",
+ "ck_apll_i2sin1_m_sel", 0x020c,
+ 1, CLK_AUDDIV_2, 8, 8),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN2, "ck_apll12_div_i2sin2",
+ "ck_apll_i2sin2_m_sel", 0x020c,
+ 2, CLK_AUDDIV_2, 8, 16),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN3, "ck_apll12_div_i2sin3",
+ "ck_apll_i2sin3_m_sel", 0x020c,
+ 3, CLK_AUDDIV_2, 8, 24),
+ /* CLK_AUDDIV_3 */
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN4, "ck_apll12_div_i2sin4",
+ "ck_apll_i2sin4_m_sel", 0x020c,
+ 4, CLK_AUDDIV_3, 8, 0),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN6, "ck_apll12_div_i2sin6",
+ "ck_apll_i2sin6_m_sel", 0x020c,
+ 5, CLK_AUDDIV_3, 8, 8),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT0, "ck_apll12_div_i2sout0",
+ "ck_apll_i2sout0_m_sel", 0x020c,
+ 6, CLK_AUDDIV_3, 8, 16),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT1, "ck_apll12_div_i2sout1",
+ "ck_apll_i2sout1_m_sel", 0x020c,
+ 7, CLK_AUDDIV_3, 8, 24),
+ /* CLK_AUDDIV_4 */
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT2, "ck_apll12_div_i2sout2",
+ "ck_apll_i2sout2_m_sel", 0x020c,
+ 8, CLK_AUDDIV_4, 8, 0),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT3, "ck_apll12_div_i2sout3",
+ "ck_apll_i2sout3_m_sel", 0x020c,
+ 9, CLK_AUDDIV_4, 8, 8),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT4, "ck_apll12_div_i2sout4",
+ "ck_apll_i2sout4_m_sel", 0x020c,
+ 10, CLK_AUDDIV_4, 8, 16),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT6, "ck_apll12_div_i2sout6",
+ "ck_apll_i2sout6_m_sel", 0x020c,
+ 11, CLK_AUDDIV_4, 8, 24),
+ /* CLK_AUDDIV_5 */
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_FMI2S, "ck_apll12_div_fmi2s",
+ "ck_apll_fmi2s_m_sel", 0x020c,
+ 12, CLK_AUDDIV_5, 8, 0),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_TDMOUT_M, "ck_apll12_div_tdmout_m",
+ "ck_apll_tdmout_m_sel", 0x020c,
+ 13, CLK_AUDDIV_5, 8, 8),
+ DIV_GATE(CLK_CK_APLL12_CK_DIV_TDMOUT_B, "ck_apll12_div_tdmout_b",
+ "ck_apll_tdmout_m_sel", 0x020c,
+ 14, CLK_AUDDIV_5, 8, 16),
+};
+
+static int clk_mt8196_ck_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ dev_err(&pdev->dev, "%s(): ioremap failed\n", __func__);
+ return PTR_ERR(base);
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_CK_NR_CLK);
+
+ mtk_clk_register_factors(ck_divs, ARRAY_SIZE(ck_divs),
+ clk_data);
+
+ mtk_clk_register_muxes(&pdev->dev, ck_muxes, ARRAY_SIZE(ck_muxes), node,
+ &mt8196_clk_ck_lock, clk_data);
+
+ mtk_clk_register_composites(&pdev->dev, ck_composites, ARRAY_SIZE(ck_composites),
+ base, &mt8196_clk_ck_lock, clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev, "%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static void clk_mt8196_ck_remove(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_composites(ck_composites, ARRAY_SIZE(ck_composites), clk_data);
+ mtk_clk_unregister_muxes(ck_muxes, ARRAY_SIZE(ck_muxes), clk_data);
+ mtk_clk_unregister_factors(ck_divs, ARRAY_SIZE(ck_divs), clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8196_ck[] = {
+ { .compatible = "mediatek,mt8196-cksys", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_ck_drv = {
+ .probe = clk_mt8196_ck_probe,
+ .remove = clk_mt8196_ck_remove,
+ .driver = {
+ .name = "clk-mt8196-ck",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8196_ck,
+ },
+};
+
+module_platform_driver(clk_mt8196_ck_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 10/26] clk: mediatek: Add MT8196 topckgen2 clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (8 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 09/26] clk: mediatek: Add MT8196 topckgen " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 11/26] clk: mediatek: Add MT8196 vlpckgen " Guangjie Song
` (15 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 topckgen2 clock controller which provides muxes and dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8196-topckgen2.c | 701 ++++++++++++++++++++
2 files changed, 702 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen2.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index cd6f42a6fd10..5c058b64ff56 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -151,7 +151,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o \
- clk-mt8196-topckgen.o
+ clk-mt8196-topckgen.o clk-mt8196-topckgen2.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-topckgen2.c b/drivers/clk/mediatek/clk-mt8196-topckgen2.c
new file mode 100644
index 000000000000..ae858498db17
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-topckgen2.c
@@ -0,0 +1,701 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+
+/* MUX SEL REG */
+#define CKSYS2_CLK_CFG_UPDATE 0x0004
+#define CKSYS2_CLK_CFG_0 0x0010
+#define CKSYS2_CLK_CFG_0_SET 0x0014
+#define CKSYS2_CLK_CFG_0_CLR 0x0018
+#define CKSYS2_CLK_CFG_1 0x0020
+#define CKSYS2_CLK_CFG_1_SET 0x0024
+#define CKSYS2_CLK_CFG_1_CLR 0x0028
+#define CKSYS2_CLK_CFG_2 0x0030
+#define CKSYS2_CLK_CFG_2_SET 0x0034
+#define CKSYS2_CLK_CFG_2_CLR 0x0038
+#define CKSYS2_CLK_CFG_3 0x0040
+#define CKSYS2_CLK_CFG_3_SET 0x0044
+#define CKSYS2_CLK_CFG_3_CLR 0x0048
+#define CKSYS2_CLK_CFG_4 0x0050
+#define CKSYS2_CLK_CFG_4_SET 0x0054
+#define CKSYS2_CLK_CFG_4_CLR 0x0058
+#define CKSYS2_CLK_CFG_5 0x0060
+#define CKSYS2_CLK_CFG_5_SET 0x0064
+#define CKSYS2_CLK_CFG_5_CLR 0x0068
+#define CKSYS2_CLK_CFG_6 0x0070
+#define CKSYS2_CLK_CFG_6_SET 0x0074
+#define CKSYS2_CLK_CFG_6_CLR 0x0078
+#define CKSYS2_CLK_FENC_STATUS_MON_0 0x0174
+
+/* MUX SHIFT */
+#define TOP_MUX_SENINF0_SHIFT 0
+#define TOP_MUX_SENINF1_SHIFT 1
+#define TOP_MUX_SENINF2_SHIFT 2
+#define TOP_MUX_SENINF3_SHIFT 3
+#define TOP_MUX_SENINF4_SHIFT 4
+#define TOP_MUX_SENINF5_SHIFT 5
+#define TOP_MUX_IMG1_SHIFT 6
+#define TOP_MUX_IPE_SHIFT 7
+#define TOP_MUX_CAM_SHIFT 8
+#define TOP_MUX_CAMTM_SHIFT 9
+#define TOP_MUX_DPE_SHIFT 10
+#define TOP_MUX_VDEC_SHIFT 11
+#define TOP_MUX_CCUSYS_SHIFT 12
+#define TOP_MUX_CCUTM_SHIFT 13
+#define TOP_MUX_VENC_SHIFT 14
+#define TOP_MUX_DVO_SHIFT 15
+#define TOP_MUX_DVO_FAVT_SHIFT 16
+#define TOP_MUX_DP1_SHIFT 17
+#define TOP_MUX_DP0_SHIFT 18
+#define TOP_MUX_DISP_SHIFT 19
+#define TOP_MUX_MDP_SHIFT 20
+#define TOP_MUX_MMINFRA_SHIFT 21
+#define TOP_MUX_MMINFRA_SNOC_SHIFT 22
+#define TOP_MUX_MMUP_SHIFT 23
+#define TOP_MUX_MMINFRA_AO_SHIFT 26
+
+/* HW Voter REG */
+#define VOTE_CG_30_SET 0x0058
+#define VOTE_CG_30_CLR 0x005c
+#define VOTE_CG_30_DONE 0x2c2c
+
+#define MM_VOTE_CG_30_SET 0x00f0
+#define MM_VOTE_CG_30_CLR 0x00f4
+#define MM_VOTE_CG_30_DONE 0x2c78
+#define MM_VOTE_CG_31_SET 0x00f8
+#define MM_VOTE_CG_31_CLR 0x00fc
+#define MM_VOTE_CG_31_DONE 0x2c7c
+#define MM_VOTE_CG_32_SET 0x0100
+#define MM_VOTE_CG_32_CLR 0x0104
+#define MM_VOTE_CG_32_DONE 0x2c80
+#define MM_VOTE_CG_33_SET 0x0108
+#define MM_VOTE_CG_33_CLR 0x010c
+#define MM_VOTE_CG_33_DONE 0x2c84
+#define MM_VOTE_CG_34_SET 0x0110
+#define MM_VOTE_CG_34_CLR 0x0114
+#define MM_VOTE_CG_34_DONE 0x2c88
+#define MM_VOTE_CG_35_SET 0x0118
+#define MM_VOTE_CG_35_CLR 0x011c
+#define MM_VOTE_CG_35_DONE 0x2c8c
+#define MM_VOTE_CG_36_SET 0x0120
+#define MM_VOTE_CG_36_CLR 0x0124
+#define MM_VOTE_CG_36_DONE 0x2c90
+#define MM_VOTE_MUX_UPDATE_31_0 0x0240
+
+static DEFINE_SPINLOCK(mt8196_clk_ck2_lock);
+
+static const struct mtk_fixed_factor ck2_divs[] = {
+ FACTOR(CLK_CK2_MAINPLL2_D2, "ck2_mainpll2_d2", "mainpll2", 1, 2),
+ FACTOR(CLK_CK2_MAINPLL2_D3, "ck2_mainpll2_d3", "mainpll2", 1, 3),
+ FACTOR(CLK_CK2_MAINPLL2_D4, "ck2_mainpll2_d4", "mainpll2", 1, 4),
+ FACTOR(CLK_CK2_MAINPLL2_D4_D2, "ck2_mainpll2_d4_d2", "mainpll2", 1, 8),
+ FACTOR(CLK_CK2_MAINPLL2_D4_D4, "ck2_mainpll2_d4_d4", "mainpll2", 1, 16),
+ FACTOR(CLK_CK2_MAINPLL2_D5, "ck2_mainpll2_d5", "mainpll2", 1, 5),
+ FACTOR(CLK_CK2_MAINPLL2_D5_D2, "ck2_mainpll2_d5_d2", "mainpll2", 1, 10),
+ FACTOR(CLK_CK2_MAINPLL2_D6, "ck2_mainpll2_d6", "mainpll2", 1, 6),
+ FACTOR(CLK_CK2_MAINPLL2_D6_D2, "ck2_mainpll2_d6_d2", "mainpll2", 1, 12),
+ FACTOR(CLK_CK2_MAINPLL2_D7, "ck2_mainpll2_d7", "mainpll2", 1, 7),
+ FACTOR(CLK_CK2_MAINPLL2_D7_D2, "ck2_mainpll2_d7_d2", "mainpll2", 1, 14),
+ FACTOR(CLK_CK2_MAINPLL2_D9, "ck2_mainpll2_d9", "mainpll2", 1, 9),
+ FACTOR(CLK_CK2_UNIVPLL2_D3, "ck2_univpll2_d3", "univpll2", 1, 3),
+ FACTOR(CLK_CK2_UNIVPLL2_D4, "ck2_univpll2_d4", "univpll2", 1, 4),
+ FACTOR(CLK_CK2_UNIVPLL2_D4_D2, "ck2_univpll2_d4_d2", "univpll2", 1, 8),
+ FACTOR(CLK_CK2_UNIVPLL2_D5, "ck2_univpll2_d5", "univpll2", 1, 5),
+ FACTOR(CLK_CK2_UNIVPLL2_D5_D2, "ck2_univpll2_d5_d2", "univpll2", 1, 10),
+ FACTOR(CLK_CK2_UNIVPLL2_D6, "ck2_univpll2_d6", "univpll2", 1, 6),
+ FACTOR(CLK_CK2_UNIVPLL2_D6_D2, "ck2_univpll2_d6_d2", "univpll2", 1, 12),
+ FACTOR(CLK_CK2_UNIVPLL2_D6_D4, "ck2_univpll2_d6_d4", "univpll2", 1, 24),
+ FACTOR(CLK_CK2_UNIVPLL2_D7, "ck2_univpll2_d7", "univpll2", 1, 7),
+ FACTOR(CLK_CK2_IMGPLL_D2, "ck2_imgpll_d2", "imgpll", 1, 2),
+ FACTOR(CLK_CK2_IMGPLL_D4, "ck2_imgpll_d4", "imgpll", 1, 4),
+ FACTOR(CLK_CK2_IMGPLL_D5, "ck2_imgpll_d5", "imgpll", 1, 5),
+ FACTOR(CLK_CK2_IMGPLL_D5_D2, "ck2_imgpll_d5_d2", "imgpll", 1, 10),
+ FACTOR(CLK_CK2_MMPLL2_D3, "ck2_mmpll2_d3", "mmpll2", 1, 3),
+ FACTOR(CLK_CK2_MMPLL2_D4, "ck2_mmpll2_d4", "mmpll2", 1, 4),
+ FACTOR(CLK_CK2_MMPLL2_D4_D2, "ck2_mmpll2_d4_d2", "mmpll2", 1, 8),
+ FACTOR(CLK_CK2_MMPLL2_D5, "ck2_mmpll2_d5", "mmpll2", 1, 5),
+ FACTOR(CLK_CK2_MMPLL2_D5_D2, "ck2_mmpll2_d5_d2", "mmpll2", 1, 10),
+ FACTOR(CLK_CK2_MMPLL2_D6, "ck2_mmpll2_d6", "mmpll2", 1, 6),
+ FACTOR(CLK_CK2_MMPLL2_D6_D2, "ck2_mmpll2_d6_d2", "mmpll2", 1, 12),
+ FACTOR(CLK_CK2_MMPLL2_D7, "ck2_mmpll2_d7", "mmpll2", 1, 7),
+ FACTOR(CLK_CK2_MMPLL2_D9, "ck2_mmpll2_d9", "mmpll2", 1, 9),
+ FACTOR(CLK_CK2_TVDPLL1_D4, "ck2_tvdpll1_d4", "tvdpll1", 1, 4),
+ FACTOR(CLK_CK2_TVDPLL1_D8, "ck2_tvdpll1_d8", "tvdpll1", 1, 8),
+ FACTOR(CLK_CK2_TVDPLL1_D16, "ck2_tvdpll1_d16", "tvdpll1", 1, 16),
+ FACTOR(CLK_CK2_TVDPLL2_D2, "ck2_tvdpll2_d2", "tvdpll2", 1, 2),
+ FACTOR(CLK_CK2_TVDPLL2_D4, "ck2_tvdpll2_d4", "tvdpll2", 1, 4),
+ FACTOR(CLK_CK2_TVDPLL2_D8, "ck2_tvdpll2_d8", "tvdpll2", 1, 8),
+ FACTOR(CLK_CK2_TVDPLL2_D16, "ck2_tvdpll2_d16", "tvdpll2", 92, 1473),
+ FACTOR(CLK_CK2_CCUSYS, "ck2_ccusys_ck", "ck2_ccusys_sel", 1, 1),
+ FACTOR(CLK_CK2_VENC, "ck2_venc_ck", "ck2_venc_sel", 1, 1),
+ FACTOR(CLK_CK2_MMINFRA, "ck2_mminfra_ck", "ck2_mminfra_sel", 1, 1),
+ FACTOR(CLK_CK2_IMG1, "ck2_img1_ck", "ck2_img1_sel", 1, 1),
+ FACTOR(CLK_CK2_IPE, "ck2_ipe_ck", "ck2_ipe_sel", 1, 1),
+ FACTOR(CLK_CK2_CAM, "ck2_cam_ck", "ck2_cam_sel", 1, 1),
+ FACTOR(CLK_CK2_CAMTM, "ck2_camtm_ck", "ck2_camtm_sel", 1, 1),
+ FACTOR(CLK_CK2_DPE, "ck2_dpe_ck", "ck2_dpe_sel", 1, 1),
+ FACTOR(CLK_CK2_VDEC, "ck2_vdec_ck", "ck2_vdec_sel", 1, 1),
+ FACTOR(CLK_CK2_DP1, "ck2_dp1_ck", "ck2_dp1_sel", 1, 1),
+ FACTOR(CLK_CK2_DP0, "ck2_dp0_ck", "ck2_dp0_sel", 1, 1),
+ FACTOR(CLK_CK2_DISP, "ck2_disp_ck", "ck2_disp_sel", 1, 1),
+ FACTOR(CLK_CK2_MDP, "ck2_mdp_ck", "ck2_mdp_sel", 1, 1),
+ FACTOR(CLK_CK2_AVS_IMG, "ck2_avs_img_ck", "ck_tck_26m_mx9_ck", 1, 1),
+ FACTOR(CLK_CK2_AVS_VDEC, "ck2_avs_vdec_ck", "ck_tck_26m_mx9_ck", 1, 1),
+ FACTOR(CLK_CK2_TVDPLL3_D2, "ck2_tvdpll3_d2", "tvdpll3", 1, 2),
+ FACTOR(CLK_CK2_TVDPLL3_D4, "ck2_tvdpll3_d4", "tvdpll3", 1, 4),
+ FACTOR(CLK_CK2_TVDPLL3_D8, "ck2_tvdpll3_d8", "tvdpll3", 1, 8),
+ FACTOR(CLK_CK2_TVDPLL3_D16, "ck2_tvdpll3_d16", "tvdpll3", 92, 1473),
+};
+
+static const char * const ck2_seninf0_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d8",
+ "ck_osc_d5",
+ "ck_osc_d4",
+ "ck2_univpll2_d6_d2",
+ "ck2_mainpll2_d9",
+ "ck_osc_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_univpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_univpll2_d5"
+};
+
+static const char * const ck2_seninf1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d8",
+ "ck_osc_d5",
+ "ck_osc_d4",
+ "ck2_univpll2_d6_d2",
+ "ck2_mainpll2_d9",
+ "ck_osc_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_univpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_univpll2_d5"
+};
+
+static const char * const ck2_seninf2_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d8",
+ "ck_osc_d5",
+ "ck_osc_d4",
+ "ck2_univpll2_d6_d2",
+ "ck2_mainpll2_d9",
+ "ck_osc_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_univpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_univpll2_d5"
+};
+
+static const char * const ck2_seninf3_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d8",
+ "ck_osc_d5",
+ "ck_osc_d4",
+ "ck2_univpll2_d6_d2",
+ "ck2_mainpll2_d9",
+ "ck_osc_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_univpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_univpll2_d5"
+};
+
+static const char * const ck2_seninf4_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d8",
+ "ck_osc_d5",
+ "ck_osc_d4",
+ "ck2_univpll2_d6_d2",
+ "ck2_mainpll2_d9",
+ "ck_osc_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_univpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_univpll2_d5"
+};
+
+static const char * const ck2_seninf5_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d8",
+ "ck_osc_d5",
+ "ck_osc_d4",
+ "ck2_univpll2_d6_d2",
+ "ck2_mainpll2_d9",
+ "ck_osc_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_univpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_univpll2_d5"
+};
+
+static const char * const ck2_img1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_osc_d3",
+ "ck2_mmpll2_d6_d2",
+ "ck_osc_d2",
+ "ck2_imgpll_d5_d2",
+ "ck2_mmpll2_d5_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_mmpll2_d6",
+ "ck2_univpll2_d5",
+ "ck2_mmpll2_d5",
+ "ck2_univpll2_d4",
+ "ck2_imgpll_d4"
+};
+
+static const char * const ck2_ipe_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_osc_d3",
+ "ck_osc_d2",
+ "ck2_univpll2_d6",
+ "ck2_mmpll2_d6",
+ "ck2_univpll2_d5",
+ "ck2_imgpll_d5",
+ "ck_mainpll_d4",
+ "ck2_mmpll2_d5",
+ "ck2_imgpll_d4"
+};
+
+static const char * const ck2_cam_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d4",
+ "ck_osc_d3",
+ "ck_osc_d2",
+ "ck2_mmpll2_d5_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_univpll2_d7",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_mmpll2_d6",
+ "ck2_univpll2_d5",
+ "ck2_mmpll2_d5",
+ "ck2_univpll2_d4",
+ "ck2_imgpll_d4",
+ "ck2_mmpll2_d4"
+};
+
+static const char * const ck2_camtm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_univpll2_d6_d4",
+ "ck_osc_d4",
+ "ck_osc_d3",
+ "ck2_univpll2_d6_d2"
+};
+
+static const char * const ck2_dpe_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_mmpll2_d5_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_mmpll2_d6",
+ "ck2_univpll2_d5",
+ "ck2_mmpll2_d5",
+ "ck2_imgpll_d4",
+ "ck2_mmpll2_d4"
+};
+
+static const char * const ck2_vdec_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d2",
+ "ck2_mainpll2_d4_d4",
+ "ck2_mainpll2_d7_d2",
+ "ck2_mainpll2_d6_d2",
+ "ck2_mainpll2_d5_d2",
+ "ck2_mainpll2_d9",
+ "ck2_mainpll2_d4_d2",
+ "ck2_mainpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_univpll2_d6",
+ "ck2_mainpll2_d5",
+ "ck2_mainpll2_d4",
+ "ck2_imgpll_d2"
+};
+
+static const char * const ck2_ccusys_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_osc_d3",
+ "ck_osc_d2",
+ "ck2_mmpll2_d5_d2",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d7",
+ "ck2_univpll2_d6",
+ "ck2_mmpll2_d6",
+ "ck2_univpll2_d5",
+ "ck2_mainpll2_d4",
+ "ck2_mainpll2_d3",
+ "ck2_univpll2_d3"
+};
+
+static const char * const ck2_ccutm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_univpll2_d6_d4",
+ "ck_osc_d4",
+ "ck_osc_d3",
+ "ck2_univpll2_d6_d2"
+};
+
+static const char * const ck2_venc_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_mainpll2_d5_d2",
+ "ck2_univpll2_d5_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck2_mmpll2_d9",
+ "ck2_univpll2_d4_d2",
+ "ck2_mmpll2_d4_d2",
+ "ck2_mainpll2_d6",
+ "ck2_univpll2_d6",
+ "ck2_mainpll2_d5",
+ "ck2_mmpll2_d6",
+ "ck2_univpll2_d5",
+ "ck2_mainpll2_d4",
+ "ck2_univpll2_d4",
+ "ck2_univpll2_d3"
+};
+
+static const char * const ck2_dp1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_tvdpll2_d16",
+ "ck2_tvdpll2_d8",
+ "ck2_tvdpll2_d4",
+ "ck2_tvdpll2_d2"
+};
+
+static const char * const ck2_dp0_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_tvdpll1_d16",
+ "ck2_tvdpll1_d8",
+ "ck2_tvdpll1_d4",
+ "ck_tvdpll1_d2"
+};
+
+static const char * const ck2_disp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d6",
+ "ck2_mainpll2_d5",
+ "ck2_mmpll2_d6",
+ "ck2_mainpll2_d4",
+ "ck2_univpll2_d4",
+ "ck2_mainpll2_d3"
+};
+
+static const char * const ck2_mdp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d5_d2",
+ "ck2_mainpll2_d5_d2",
+ "ck2_mmpll2_d6_d2",
+ "ck2_mainpll2_d9",
+ "ck2_mainpll2_d4_d2",
+ "ck2_mainpll2_d7",
+ "ck2_mainpll2_d6",
+ "ck2_mainpll2_d5",
+ "ck2_mmpll2_d6",
+ "ck2_mainpll2_d4",
+ "ck2_univpll2_d4",
+ "ck2_mainpll2_d3"
+};
+
+static const char * const ck2_mminfra_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d5_d2",
+ "ck_mainpll_d9",
+ "ck2_mmpll2_d6_d2",
+ "ck2_mainpll2_d4_d2",
+ "ck_mainpll_d6",
+ "ck2_univpll2_d6",
+ "ck2_mainpll2_d5",
+ "ck2_mmpll2_d6",
+ "ck2_univpll2_d5",
+ "ck2_mainpll2_d4",
+ "ck2_univpll2_d4",
+ "ck2_mainpll2_d3",
+ "ck2_univpll2_d3"
+};
+
+static const char * const ck2_mminfra_snoc_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d9",
+ "ck_mainpll_d7",
+ "ck_mainpll_d6",
+ "ck2_mmpll2_d4_d2",
+ "ck_mainpll_d5",
+ "ck_mainpll_d4",
+ "ck2_univpll2_d4",
+ "ck2_mmpll2_d4",
+ "ck2_mainpll2_d3",
+ "ck2_univpll2_d3",
+ "ck2_mmpll2_d3",
+ "ck2_mainpll2_d2"
+};
+
+static const char * const ck2_mmup_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_mainpll2_d6",
+ "ck2_mainpll2_d5",
+ "ck_osc_d2",
+ "ck_osc",
+ "ck_mainpll_d4",
+ "ck2_univpll2_d4",
+ "ck2_mainpll2_d3"
+};
+
+static const char * const ck2_mminfra_ao_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_mainpll_d3"
+};
+
+static const char * const ck2_dvo_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_tvdpll3_d16",
+ "ck2_tvdpll3_d8",
+ "ck2_tvdpll3_d4",
+ "ck2_tvdpll3_d2"
+};
+
+static const char * const ck2_dvo_favt_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck2_tvdpll3_d16",
+ "ck2_tvdpll3_d8",
+ "ck2_tvdpll3_d4",
+ "ck_apll1_ck",
+ "ck_apll2_ck",
+ "ck2_tvdpll3_d2"
+};
+
+static const struct mtk_mux ck2_muxes[] = {
+ /* CKSYS2_CLK_CFG_0 */
+ MUX_MULT_VOTE_FENC(CLK_CK2_SENINF0_SEL, "ck2_seninf0_sel", ck2_seninf0_parents,
+ CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_30_DONE, MM_VOTE_CG_30_SET, MM_VOTE_CG_30_CLR,
+ 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF0_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 31),
+ MUX_MULT_VOTE_FENC(CLK_CK2_SENINF1_SEL, "ck2_seninf1_sel", ck2_seninf1_parents,
+ CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_30_DONE, MM_VOTE_CG_30_SET, MM_VOTE_CG_30_CLR,
+ 8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF1_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 30),
+ MUX_MULT_VOTE_FENC(CLK_CK2_SENINF2_SEL, "ck2_seninf2_sel", ck2_seninf2_parents,
+ CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_30_DONE, MM_VOTE_CG_30_SET, MM_VOTE_CG_30_CLR,
+ 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF2_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 29),
+ MUX_MULT_VOTE_FENC(CLK_CK2_SENINF3_SEL, "ck2_seninf3_sel", ck2_seninf3_parents,
+ CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_30_DONE, MM_VOTE_CG_30_SET, MM_VOTE_CG_30_CLR,
+ 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF3_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 28),
+ /* CKSYS2_CLK_CFG_1 */
+ MUX_MULT_VOTE_FENC(CLK_CK2_SENINF4_SEL, "ck2_seninf4_sel", ck2_seninf4_parents,
+ CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_31_DONE, MM_VOTE_CG_31_SET, MM_VOTE_CG_31_CLR,
+ 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF4_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 27),
+ MUX_MULT_VOTE_FENC(CLK_CK2_SENINF5_SEL, "ck2_seninf5_sel", ck2_seninf5_parents,
+ CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_31_DONE, MM_VOTE_CG_31_SET, MM_VOTE_CG_31_CLR,
+ 8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF5_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 26),
+ MUX_MULT_VOTE_FENC(CLK_CK2_IMG1_SEL, "ck2_img1_sel", ck2_img1_parents,
+ CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_31_DONE, MM_VOTE_CG_31_SET, MM_VOTE_CG_31_CLR,
+ 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IMG1_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 25),
+ MUX_MULT_VOTE_FENC(CLK_CK2_IPE_SEL, "ck2_ipe_sel", ck2_ipe_parents,
+ CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_31_DONE, MM_VOTE_CG_31_SET, MM_VOTE_CG_31_CLR,
+ 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IPE_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 24),
+ /* CKSYS2_CLK_CFG_2 */
+ MUX_MULT_VOTE_FENC(CLK_CK2_CAM_SEL, "ck2_cam_sel", ck2_cam_parents,
+ CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_32_DONE, MM_VOTE_CG_32_SET, MM_VOTE_CG_32_CLR,
+ 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAM_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 23),
+ MUX_MULT_VOTE_FENC(CLK_CK2_CAMTM_SEL, "ck2_camtm_sel", ck2_camtm_parents,
+ CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_32_DONE, MM_VOTE_CG_32_SET, MM_VOTE_CG_32_CLR,
+ 8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAMTM_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 22),
+ MUX_MULT_VOTE_FENC(CLK_CK2_DPE_SEL, "ck2_dpe_sel", ck2_dpe_parents,
+ CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_32_DONE, MM_VOTE_CG_32_SET, MM_VOTE_CG_32_CLR,
+ 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DPE_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 21),
+ MUX_MULT_VOTE_FENC(CLK_CK2_VDEC_SEL, "ck2_vdec_sel", ck2_vdec_parents,
+ CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_32_DONE, MM_VOTE_CG_32_SET, MM_VOTE_CG_32_CLR,
+ 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VDEC_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 20),
+ /* CKSYS2_CLK_CFG_3 */
+ MUX_MULT_VOTE_FENC(CLK_CK2_CCUSYS_SEL, "ck2_ccusys_sel", ck2_ccusys_parents,
+ CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_33_DONE, MM_VOTE_CG_33_SET, MM_VOTE_CG_33_CLR,
+ 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUSYS_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 19),
+ MUX_MULT_VOTE_FENC(CLK_CK2_CCUTM_SEL, "ck2_ccutm_sel", ck2_ccutm_parents,
+ CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_33_DONE, MM_VOTE_CG_33_SET, MM_VOTE_CG_33_CLR,
+ 8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUTM_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 18),
+ MUX_MULT_VOTE_FENC(CLK_CK2_VENC_SEL, "ck2_venc_sel", ck2_venc_parents,
+ CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_33_DONE, MM_VOTE_CG_33_SET, MM_VOTE_CG_33_CLR,
+ 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VENC_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 17),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK2_DVO_SEL, "ck2_dvo_sel", ck2_dvo_parents,
+ CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
+ 24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 16),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK2_DVO_FAVT_SEL, "ck2_dvo_favt_sel", ck2_dvo_favt_parents,
+ CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
+ 0, 3, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_FAVT_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 15),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK2_DP1_SEL, "ck2_dp1_sel", ck2_dp1_parents,
+ CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
+ 8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP1_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 14),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_CK2_DP0_SEL, "ck2_dp0_sel", ck2_dp0_parents,
+ CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
+ 16, 3, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP0_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 13),
+ MUX_MULT_VOTE_FENC(CLK_CK2_DISP_SEL, "ck2_disp_sel", ck2_disp_parents,
+ CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_34_DONE, MM_VOTE_CG_34_SET, MM_VOTE_CG_34_CLR,
+ 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DISP_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 12),
+ /* CKSYS2_CLK_CFG_5 */
+ MUX_MULT_VOTE_FENC(CLK_CK2_MDP_SEL, "ck2_mdp_sel", ck2_mdp_parents,
+ CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_35_DONE, MM_VOTE_CG_35_SET, MM_VOTE_CG_35_CLR,
+ 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MDP_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 11),
+ MUX_MULT_VOTE_FENC(CLK_CK2_MMINFRA_SEL, "ck2_mminfra_sel", ck2_mminfra_parents,
+ CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_35_DONE, MM_VOTE_CG_35_SET, MM_VOTE_CG_35_CLR,
+ 8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 10),
+ MUX_MULT_VOTE_FENC(CLK_CK2_MMINFRA_SNOC_SEL, "ck2_mminfra_snoc_sel", ck2_mminfra_snoc_parents,
+ CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_35_DONE, MM_VOTE_CG_35_SET, MM_VOTE_CG_35_CLR,
+ 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SNOC_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 9),
+ MUX_MULT_VOTE_FENC(CLK_CK2_MMUP_SEL, "ck2_mmup_sel", ck2_mmup_parents,
+ CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR, "vote-regmap",
+ VOTE_CG_30_DONE, VOTE_CG_30_SET, VOTE_CG_30_CLR,
+ 24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMUP_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 8),
+ MUX_MULT_VOTE_FENC(CLK_CK2_MMINFRA_AO_SEL, "ck2_mminfra_ao_sel", ck2_mminfra_ao_parents,
+ CKSYS2_CLK_CFG_6, CKSYS2_CLK_CFG_6_SET, CKSYS2_CLK_CFG_6_CLR, "mm-vote-regmap",
+ MM_VOTE_CG_36_DONE, MM_VOTE_CG_36_SET, MM_VOTE_CG_36_CLR,
+ 16, 2, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_AO_SHIFT,
+ CKSYS2_CLK_FENC_STATUS_MON_0, 5),
+};
+
+static int clk_mt8196_ck2_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_CK2_NR_CLK);
+
+ mtk_clk_register_factors(ck2_divs, ARRAY_SIZE(ck2_divs), clk_data);
+
+ mtk_clk_register_muxes(&pdev->dev, ck2_muxes, ARRAY_SIZE(ck2_muxes), node,
+ &mt8196_clk_ck2_lock, clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev, "%s(): could not register clock provider: %d\n",
+ __func__, r);
+
+ return r;
+}
+
+static void clk_mt8196_ck2_remove(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_muxes(ck2_muxes, ARRAY_SIZE(ck2_muxes), clk_data);
+ mtk_clk_unregister_factors(ck2_divs, ARRAY_SIZE(ck2_divs), clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8196_ck2[] = {
+ { .compatible = "mediatek,mt8196-cksys_gp2", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_ck2_drv = {
+ .probe = clk_mt8196_ck2_probe,
+ .remove = clk_mt8196_ck2_remove,
+ .driver = {
+ .name = "clk-mt8196-ck2",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8196_ck2,
+ },
+};
+
+module_platform_driver(clk_mt8196_ck2_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 11/26] clk: mediatek: Add MT8196 vlpckgen clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (9 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 10/26] clk: mediatek: Add MT8196 topckgen2 " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 12/26] clk: mediatek: Add MT8196 peripheral " Guangjie Song
` (14 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 vlpckgen clock controller which provides muxes and dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 777 +++++++++++++++++++++
2 files changed, 778 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-vlpckgen.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 5c058b64ff56..583e5b9a7d40 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -151,7 +151,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o \
- clk-mt8196-topckgen.o clk-mt8196-topckgen2.o
+ clk-mt8196-topckgen.o clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c
new file mode 100644
index 000000000000..0bd6396a51ca
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c
@@ -0,0 +1,777 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-pll.h"
+
+/* MUX SEL REG */
+#define VLP_CLK_CFG_UPDATE 0x0004
+#define VLP_CLK_CFG_UPDATE1 0x0008
+#define VLP_CLK_CFG_0 0x0010
+#define VLP_CLK_CFG_0_SET 0x0014
+#define VLP_CLK_CFG_0_CLR 0x0018
+#define VLP_CLK_CFG_1 0x0020
+#define VLP_CLK_CFG_1_SET 0x0024
+#define VLP_CLK_CFG_1_CLR 0x0028
+#define VLP_CLK_CFG_2 0x0030
+#define VLP_CLK_CFG_2_SET 0x0034
+#define VLP_CLK_CFG_2_CLR 0x0038
+#define VLP_CLK_CFG_3 0x0040
+#define VLP_CLK_CFG_3_SET 0x0044
+#define VLP_CLK_CFG_3_CLR 0x0048
+#define VLP_CLK_CFG_4 0x0050
+#define VLP_CLK_CFG_4_SET 0x0054
+#define VLP_CLK_CFG_4_CLR 0x0058
+#define VLP_CLK_CFG_5 0x0060
+#define VLP_CLK_CFG_5_SET 0x0064
+#define VLP_CLK_CFG_5_CLR 0x0068
+#define VLP_CLK_CFG_6 0x0070
+#define VLP_CLK_CFG_6_SET 0x0074
+#define VLP_CLK_CFG_6_CLR 0x0078
+#define VLP_CLK_CFG_7 0x0080
+#define VLP_CLK_CFG_7_SET 0x0084
+#define VLP_CLK_CFG_7_CLR 0x0088
+#define VLP_CLK_CFG_8 0x0090
+#define VLP_CLK_CFG_8_SET 0x0094
+#define VLP_CLK_CFG_8_CLR 0x0098
+#define VLP_CLK_CFG_9 0x00a0
+#define VLP_CLK_CFG_9_SET 0x00a4
+#define VLP_CLK_CFG_9_CLR 0x00a8
+#define VLP_CLK_CFG_10 0x00b0
+#define VLP_CLK_CFG_10_SET 0x00b4
+#define VLP_CLK_CFG_10_CLR 0x00b8
+#define VLP_OCIC_FENC_STATUS_MON_0 0x039c
+#define VLP_OCIC_FENC_STATUS_MON_1 0x03a0
+
+/* MUX SHIFT */
+#define TOP_MUX_SCP_SHIFT 0
+#define TOP_MUX_SCP_SPI_SHIFT 1
+#define TOP_MUX_SCP_IIC_SHIFT 2
+#define TOP_MUX_SCP_IIC_HIGH_SPD_SHIFT 3
+#define TOP_MUX_PWRAP_ULPOSC_SHIFT 4
+#define TOP_MUX_SPMI_M_TIA_32K_SHIFT 5
+#define TOP_MUX_APXGPT_26M_BCLK_SHIFT 6
+#define TOP_MUX_DPSW_SHIFT 7
+#define TOP_MUX_DPSW_CENTRAL_SHIFT 8
+#define TOP_MUX_SPMI_M_MST_SHIFT 9
+#define TOP_MUX_DVFSRC_SHIFT 10
+#define TOP_MUX_PWM_VLP_SHIFT 11
+#define TOP_MUX_AXI_VLP_SHIFT 12
+#define TOP_MUX_SYSTIMER_26M_SHIFT 13
+#define TOP_MUX_SSPM_SHIFT 14
+#define TOP_MUX_SRCK_SHIFT 15
+#define TOP_MUX_CAMTG0_SHIFT 16
+#define TOP_MUX_CAMTG1_SHIFT 17
+#define TOP_MUX_CAMTG2_SHIFT 18
+#define TOP_MUX_CAMTG3_SHIFT 19
+#define TOP_MUX_CAMTG4_SHIFT 20
+#define TOP_MUX_CAMTG5_SHIFT 21
+#define TOP_MUX_CAMTG6_SHIFT 22
+#define TOP_MUX_CAMTG7_SHIFT 23
+#define TOP_MUX_SSPM_26M_SHIFT 25
+#define TOP_MUX_ULPOSC_SSPM_SHIFT 26
+#define TOP_MUX_VLP_PBUS_26M_SHIFT 27
+#define TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT 28
+#define TOP_MUX_DPMSRDMA_SHIFT 29
+#define TOP_MUX_VLP_PBUS_156M_SHIFT 30
+#define TOP_MUX_SPM_SHIFT 0
+#define TOP_MUX_MMINFRA_VLP_SHIFT 1
+#define TOP_MUX_USB_TOP_SHIFT 2
+#define TOP_MUX_SSUSB_XHCI_SHIFT 3
+#define TOP_MUX_NOC_VLP_SHIFT 4
+#define TOP_MUX_AUDIO_H_SHIFT 5
+#define TOP_MUX_AUD_ENGEN1_SHIFT 6
+#define TOP_MUX_AUD_ENGEN2_SHIFT 7
+#define TOP_MUX_AUD_INTBUS_SHIFT 8
+#define TOP_MUX_SPU_VLP_26M_SHIFT 9
+#define TOP_MUX_SPU0_VLP_SHIFT 10
+#define TOP_MUX_SPU1_VLP_SHIFT 11
+
+/* CKSTA REG */
+#define VLP_CKSTA_REG0 0x0250
+#define VLP_CKSTA_REG1 0x0254
+
+/* HW Voter REG */
+#define VOTE_CG_9_SET 0x0048
+#define VOTE_CG_9_CLR 0x004c
+#define VOTE_CG_9_DONE 0x2c24
+#define VOTE_CG_10_SET 0x0050
+#define VOTE_CG_10_CLR 0x0054
+#define VOTE_CG_10_DONE 0x2c28
+
+/* PLL REG */
+#define VLP_AP_PLL_CON3 0x264
+#define VLP_APLL1_TUNER_CON0 0x2a4
+#define VLP_APLL2_TUNER_CON0 0x2a8
+#define VLP_APLL1_CON0 0x274
+#define VLP_APLL1_CON1 0x278
+#define VLP_APLL1_CON2 0x27c
+#define VLP_APLL1_CON3 0x280
+#define VLP_APLL2_CON0 0x28c
+#define VLP_APLL2_CON1 0x290
+#define VLP_APLL2_CON2 0x294
+#define VLP_APLL2_CON3 0x298
+
+#define MT8196_PLL_FMAX (3800UL * MHZ)
+#define MT8196_PLL_FMIN (1500UL * MHZ)
+#define MT8196_INTEGER_BITS 8
+
+#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
+ _flags, _pd_reg, _pd_shift, \
+ _pcw_reg, _pcw_shift, _pcwbits) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .fenc_sta_ofs = _fenc_sta_ofs, \
+ .fenc_sta_bit = _fenc_sta_bit, \
+ .flags = (_flags) | CLK_FENC_ENABLE, \
+ .fmax = MT8196_PLL_FMAX, \
+ .fmin = MT8196_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8196_INTEGER_BITS, \
+ }
+
+static DEFINE_SPINLOCK(mt8196_clk_vlp_ck_lock);
+
+static const struct mtk_fixed_factor vlp_ck_divs[] = {
+ FACTOR(CLK_VLP_CK_OSC3, "vlp_osc3", "ulposc3", 1, 1),
+ FACTOR(CLK_VLP_CK_CLKSQ, "vlp_clksq_ck", "clk26m", 1, 1),
+ FACTOR(CLK_VLP_CK_AUDIO_H, "vlp_audio_h_ck", "vlp_audio_h_sel", 1, 1),
+ FACTOR(CLK_VLP_CK_AUD_ENGEN1, "vlp_aud_engen1_ck", "vlp_aud_engen1_sel", 1, 1),
+ FACTOR(CLK_VLP_CK_AUD_ENGEN2, "vlp_aud_engen2_ck", "vlp_aud_engen2_sel", 1, 1),
+ FACTOR(CLK_VLP_CK_INFRA_26M, "vlp_infra_26m_ck", "ck_tck_26m_mx9_ck", 1, 1),
+ FACTOR(CLK_VLP_CK_AUD_CLKSQ, "vlp_aud_clksq_ck", "vlp_clksq_ck", 1, 1),
+};
+
+static const char * const vlp_scp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d6",
+ "ck_mainpll_d4",
+ "ck_mainpll_d3",
+ "ck_apll1_ck"
+};
+
+static const char * const vlp_scp_spi_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d5_d2"
+};
+
+static const char * const vlp_scp_iic_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d5_d4",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const vlp_scp_iic_hs_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d5_d4",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d7"
+};
+
+static const char * const vlp_pwrap_ulposc_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_osc_d14",
+ "ck_osc_d10"
+};
+
+static const char * const vlp_spmi_32ksel_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_clkrtc",
+ "ck_osc_d20",
+ "ck_osc_d14",
+ "ck_osc_d10"
+};
+
+static const char * const vlp_apxgpt_26m_b_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_dpsw_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d7",
+ "ck_mainpll_d7_d4"
+};
+
+static const char * const vlp_dpsw_central_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d10",
+ "ck_osc_d7",
+ "ck_mainpll_d7_d4"
+};
+
+static const char * const vlp_spmi_m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_osc_d14",
+ "ck_osc_d10"
+};
+
+static const char * const vlp_dvfsrc_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_pwm_vlp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_clkrtc",
+ "ck_osc_d20",
+ "ck_osc_d8",
+ "ck_mainpll_d4_d8"
+};
+
+static const char * const vlp_axi_vlp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d7_d4",
+ "ck_osc_d4",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const vlp_systimer_26m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_sspm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d5_d2",
+ "ck_osc_d2",
+ "ck_mainpll_d6"
+};
+
+static const char * const vlp_srck_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_camtg0_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc3",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_camtg1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc3",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_camtg2_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_camtg3_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_camtg4_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_camtg5_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_camtg6_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_camtg7_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_univpll_192m_d32",
+ "ck_univpll_192m_d16",
+ "ck_f26m_d2",
+ "ck_osc_d40",
+ "ck_osc_d32",
+ "ck_univpll_192m_d10",
+ "ck_univpll_192m_d8",
+ "ck_univpll_d6_d16",
+ "ck_osc_d20",
+ "ck2_tvdpll1_d16",
+ "ck_univpll_d6_d8"
+};
+
+static const char * const vlp_sspm_26m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_ulposc_sspm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d2",
+ "ck_mainpll_d4_d2"
+};
+
+static const char * const vlp_vlp_pbus_26m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_debug_err_flag_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_dpmsrdma_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d2"
+};
+
+static const char * const vlp_vlp_pbus_156m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d2",
+ "ck_mainpll_d7_d2",
+ "ck_mainpll_d7"
+};
+
+static const char * const vlp_spm_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d7_d4"
+};
+
+static const char * const vlp_mminfra_vlp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d4",
+ "ck_mainpll_d3"
+};
+
+static const char * const vlp_usb_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d9"
+};
+
+static const char * const vlp_usb_xhci_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_mainpll_d9"
+};
+
+static const char * const vlp_noc_vlp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d9"
+};
+
+static const char * const vlp_audio_h_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "vlp_clksq_ck",
+ "ck_apll1_ck",
+ "ck_apll2_ck"
+};
+
+static const char * const vlp_aud_engen1_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "vlp_clksq_ck",
+ "ck_apll1_d8",
+ "ck_apll1_d4"
+};
+
+static const char * const vlp_aud_engen2_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "vlp_clksq_ck",
+ "ck_apll2_d8",
+ "ck_apll2_d4"
+};
+
+static const char * const vlp_aud_intbus_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "vlp_clksq_ck",
+ "ck_mainpll_d7_d4",
+ "ck_mainpll_d4_d4"
+};
+
+static const char * const vlp_spvlp_26m_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20"
+};
+
+static const char * const vlp_spu0_vlp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d7",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5"
+};
+
+static const char * const vlp_spu1_vlp_parents[] = {
+ "ck_tck_26m_mx9_ck",
+ "ck_osc_d20",
+ "ck_mainpll_d4_d4",
+ "ck_mainpll_d4_d2",
+ "ck_mainpll_d7",
+ "ck_mainpll_d6",
+ "ck_mainpll_d5"
+};
+
+static const struct mtk_mux vlp_ck_muxes[] = {
+ /* VLP_CLK_CFG_0 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, "vlp_scp_sel", vlp_scp_parents,
+ VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET, VLP_CLK_CFG_0_CLR,
+ 0, 3, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 31),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, "vlp_scp_spi_sel",
+ vlp_scp_spi_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
+ VLP_CLK_CFG_0_CLR, 8, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SPI_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, "vlp_scp_iic_sel",
+ vlp_scp_iic_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
+ VLP_CLK_CFG_0_CLR, 16, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, "vlp_scp_iic_hs_sel",
+ vlp_scp_iic_hs_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
+ VLP_CLK_CFG_0_CLR, 24, 3,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_HIGH_SPD_SHIFT),
+ /* VLP_CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, "vlp_pwrap_ulposc_sel",
+ vlp_pwrap_ulposc_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
+ VLP_CLK_CFG_1_CLR, 0, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_PWRAP_ULPOSC_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_M_TIA_32K_SEL, "vlp_spmi_32ksel",
+ vlp_spmi_32ksel_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
+ VLP_CLK_CFG_1_CLR, 8, 3,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_TIA_32K_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_BCLK_SEL, "vlp_apxgpt_26m_b_sel",
+ vlp_apxgpt_26m_b_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
+ VLP_CLK_CFG_1_CLR, 16, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_APXGPT_26M_BCLK_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DPSW_SEL, "vlp_dpsw_sel",
+ vlp_dpsw_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
+ VLP_CLK_CFG_1_CLR, 24, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_SHIFT),
+ /* VLP_CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DPSW_CENTRAL_SEL, "vlp_dpsw_central_sel",
+ vlp_dpsw_central_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
+ VLP_CLK_CFG_2_CLR, 0, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_CENTRAL_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_M_MST_SEL, "vlp_spmi_m_sel",
+ vlp_spmi_m_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
+ VLP_CLK_CFG_2_CLR, 8, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_MST_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, "vlp_dvfsrc_sel",
+ vlp_dvfsrc_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
+ VLP_CLK_CFG_2_CLR, 16, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_DVFSRC_SHIFT),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, "vlp_pwm_vlp_sel", vlp_pwm_vlp_parents,
+ VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET, VLP_CLK_CFG_2_CLR,
+ 24, 3, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_PWM_VLP_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 20),
+ /* VLP_CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, "vlp_axi_vlp_sel",
+ vlp_axi_vlp_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
+ VLP_CLK_CFG_3_CLR, 0, 3,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_AXI_VLP_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, "vlp_systimer_26m_sel",
+ vlp_systimer_26m_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
+ VLP_CLK_CFG_3_CLR, 8, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SYSTIMER_26M_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, "vlp_sspm_sel",
+ vlp_sspm_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
+ VLP_CLK_CFG_3_CLR, 16, 3,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, "vlp_srck_sel",
+ vlp_srck_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
+ VLP_CLK_CFG_3_CLR, 24, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SRCK_SHIFT),
+ /* VLP_CLK_CFG_4 */
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG0_SEL, "vlp_camtg0_sel", vlp_camtg0_parents,
+ VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR, "vote-regmap",
+ VOTE_CG_9_DONE, VOTE_CG_9_SET, VOTE_CG_9_CLR,
+ 0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG0_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 15),
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG1_SEL, "vlp_camtg1_sel", vlp_camtg1_parents,
+ VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR, "vote-regmap",
+ VOTE_CG_9_DONE, VOTE_CG_9_SET, VOTE_CG_9_CLR,
+ 8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG1_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 14),
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG2_SEL, "vlp_camtg2_sel", vlp_camtg2_parents,
+ VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR, "vote-regmap",
+ VOTE_CG_9_DONE, VOTE_CG_9_SET, VOTE_CG_9_CLR,
+ 16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG2_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 13),
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG3_SEL, "vlp_camtg3_sel", vlp_camtg3_parents,
+ VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR, "vote-regmap",
+ VOTE_CG_9_DONE, VOTE_CG_9_SET, VOTE_CG_9_CLR,
+ 24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG3_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 12),
+ /* VLP_CLK_CFG_5 */
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG4_SEL, "vlp_camtg4_sel", vlp_camtg4_parents,
+ VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR, "vote-regmap",
+ VOTE_CG_10_DONE, VOTE_CG_10_SET, VOTE_CG_10_CLR,
+ 0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG4_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 11),
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG5_SEL, "vlp_camtg5_sel", vlp_camtg5_parents,
+ VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR, "vote-regmap",
+ VOTE_CG_10_DONE, VOTE_CG_10_SET, VOTE_CG_10_CLR,
+ 8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG5_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 10),
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG6_SEL, "vlp_camtg6_sel", vlp_camtg6_parents,
+ VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR, "vote-regmap",
+ VOTE_CG_10_DONE, VOTE_CG_10_SET, VOTE_CG_10_CLR,
+ 16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG6_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 9),
+ MUX_MULT_VOTE_FENC(CLK_VLP_CK_CAMTG7_SEL, "vlp_camtg7_sel", vlp_camtg7_parents,
+ VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR, "vote-regmap",
+ VOTE_CG_10_DONE, VOTE_CG_10_SET, VOTE_CG_10_CLR,
+ 24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG7_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_0, 8),
+ /* VLP_CLK_CFG_6 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_26M_SEL, "vlp_sspm_26m_sel",
+ vlp_sspm_26m_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
+ VLP_CLK_CFG_6_CLR, 8, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_26M_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_ULPOSC_SSPM_SEL, "vlp_ulposc_sspm_sel",
+ vlp_ulposc_sspm_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
+ VLP_CLK_CFG_6_CLR, 16, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_ULPOSC_SSPM_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_VLP_PBUS_26M_SEL, "vlp_vlp_pbus_26m_sel",
+ vlp_vlp_pbus_26m_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
+ VLP_CLK_CFG_6_CLR, 24, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_26M_SHIFT),
+ /* VLP_CLK_CFG_7 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DEBUG_ERR_FLAG_SEL, "vlp_debug_err_flag_sel",
+ vlp_debug_err_flag_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
+ VLP_CLK_CFG_7_CLR, 0, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DPMSRDMA_SEL, "vlp_dpmsrdma_sel",
+ vlp_dpmsrdma_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
+ VLP_CLK_CFG_7_CLR, 8, 1,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_DPMSRDMA_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_VLP_PBUS_156M_SEL, "vlp_vlp_pbus_156m_sel",
+ vlp_vlp_pbus_156m_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
+ VLP_CLK_CFG_7_CLR, 16, 2,
+ VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_156M_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPM_SEL, "vlp_spm_sel",
+ vlp_spm_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
+ VLP_CLK_CFG_7_CLR, 24, 1,
+ VLP_CLK_CFG_UPDATE1, TOP_MUX_SPM_SHIFT),
+ /* VLP_CLK_CFG_8 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_MMINFRA_VLP_SEL, "vlp_mminfra_vlp_sel", vlp_mminfra_vlp_parents,
+ VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
+ 0, 2, 7, VLP_CLK_CFG_UPDATE1, TOP_MUX_MMINFRA_VLP_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_1, 31),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_USB_TOP_SEL, "vlp_usb_sel", vlp_usb_parents,
+ VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
+ 8, 1, 15, VLP_CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_1, 30),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_USB_XHCI_SEL, "vlp_usb_xhci_sel", vlp_usb_xhci_parents,
+ VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
+ 16, 1, 23, VLP_CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_1, 29),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_NOC_VLP_SEL, "vlp_noc_vlp_sel",
+ vlp_noc_vlp_parents, VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET,
+ VLP_CLK_CFG_8_CLR, 24, 2,
+ VLP_CLK_CFG_UPDATE1, TOP_MUX_NOC_VLP_SHIFT),
+ /* VLP_CLK_CFG_9 */
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_AUDIO_H_SEL, "vlp_audio_h_sel", vlp_audio_h_parents,
+ VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
+ 0, 2, 7, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUDIO_H_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_1, 27),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_AUD_ENGEN1_SEL, "vlp_aud_engen1_sel", vlp_aud_engen1_parents,
+ VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
+ 8, 2, 15, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN1_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_1, 26),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_AUD_ENGEN2_SEL, "vlp_aud_engen2_sel", vlp_aud_engen2_parents,
+ VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
+ 16, 2, 23, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN2_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_1, 25),
+ MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_CK_AUD_INTBUS_SEL, "vlp_aud_intbus_sel", vlp_aud_intbus_parents,
+ VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
+ 24, 2, 31, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_INTBUS_SHIFT,
+ VLP_OCIC_FENC_STATUS_MON_1, 24),
+ /* VLP_CLK_CFG_10 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPVLP_26M_SEL, "vlp_spvlp_26m_sel",
+ vlp_spvlp_26m_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
+ VLP_CLK_CFG_10_CLR, 0, 1,
+ VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU_VLP_26M_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPU0_VLP_SEL, "vlp_spu0_vlp_sel",
+ vlp_spu0_vlp_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
+ VLP_CLK_CFG_10_CLR, 8, 3,
+ VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU0_VLP_SHIFT),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPU1_VLP_SEL, "vlp_spu1_vlp_sel",
+ vlp_spu1_vlp_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
+ VLP_CLK_CFG_10_CLR, 16, 3,
+ VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU1_VLP_SHIFT),
+};
+
+static const struct mtk_pll_data vlp_ck_plls[] = {
+ PLL_FENC(CLK_VLP_CK_VLP_APLL1, "vlp_apll1", VLP_APLL1_CON0,
+ 0x0358, 1, 0,
+ VLP_APLL1_CON1, 24,
+ VLP_APLL1_CON2, 0, 32),
+ PLL_FENC(CLK_VLP_CK_VLP_APLL2, "vlp_apll2", VLP_APLL2_CON0,
+ 0x0358, 0, 0,
+ VLP_APLL2_CON1, 24,
+ VLP_APLL2_CON2, 0, 32),
+};
+
+static int clk_mt8196_vlp_ck_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VLP_CK_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_factors(vlp_ck_divs, ARRAY_SIZE(vlp_ck_divs), clk_data);
+ if (r)
+ goto free_clk_data;
+
+ r = mtk_clk_register_muxes(&pdev->dev, vlp_ck_muxes, ARRAY_SIZE(vlp_ck_muxes), node,
+ &mt8196_clk_vlp_ck_lock, clk_data);
+ if (r)
+ goto unregister_factors;
+
+ r = mtk_clk_register_plls(node, vlp_ck_plls, ARRAY_SIZE(vlp_ck_plls), clk_data);
+ if (r)
+ goto unregister_muxes;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_plls;
+
+ return 0;
+
+unregister_plls:
+ mtk_clk_unregister_plls(vlp_ck_plls, ARRAY_SIZE(vlp_ck_plls), clk_data);
+unregister_muxes:
+ mtk_clk_unregister_muxes(vlp_ck_muxes, ARRAY_SIZE(vlp_ck_muxes), clk_data);
+unregister_factors:
+ mtk_clk_unregister_factors(vlp_ck_divs, ARRAY_SIZE(vlp_ck_divs), clk_data);
+free_clk_data:
+ mtk_free_clk_data(clk_data);
+
+ return r;
+}
+
+static void clk_mt8196_vlp_ck_remove(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_plls(vlp_ck_plls, ARRAY_SIZE(vlp_ck_plls), clk_data);
+ mtk_clk_unregister_muxes(vlp_ck_muxes, ARRAY_SIZE(vlp_ck_muxes), clk_data);
+ mtk_clk_unregister_factors(vlp_ck_divs, ARRAY_SIZE(vlp_ck_divs), clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8196_vlp_ck[] = {
+ { .compatible = "mediatek,mt8196-vlp_cksys", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_vlp_ck_drv = {
+ .probe = clk_mt8196_vlp_ck_probe,
+ .remove = clk_mt8196_vlp_ck_remove,
+ .driver = {
+ .name = "clk-mt8196-vlp_ck",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8196_vlp_ck,
+ },
+};
+
+module_platform_driver(clk_mt8196_vlp_ck_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 12/26] clk: mediatek: Add MT8196 peripheral clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (10 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 11/26] clk: mediatek: Add MT8196 vlpckgen " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 13/26] clk: mediatek: Add MT8196 adsp " Guangjie Song
` (13 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 peripheral clock controller which provides clock gate control
for dma/flashif/msdc/pwm/spi/uart.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8196-peri_ao.c | 218 ++++++++++++++++++++++
2 files changed, 220 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-peri_ao.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 583e5b9a7d40..c95e45356b78 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -151,7 +151,8 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o \
- clk-mt8196-topckgen.o clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o
+ clk-mt8196-topckgen.o clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
+ clk-mt8196-peri_ao.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-peri_ao.c b/drivers/clk/mediatek/clk-mt8196-peri_ao.c
new file mode 100644
index 000000000000..775d77159641
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-peri_ao.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs perao0_cg_regs = {
+ .set_ofs = 0x24,
+ .clr_ofs = 0x28,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs perao1_cg_regs = {
+ .set_ofs = 0x2c,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs perao1_vote_regs = {
+ .set_ofs = 0x0008,
+ .clr_ofs = 0x000c,
+ .sta_ofs = 0x2c04,
+};
+
+static const struct mtk_gate_regs perao2_cg_regs = {
+ .set_ofs = 0x34,
+ .clr_ofs = 0x38,
+ .sta_ofs = 0x18,
+};
+
+#define GATE_PERAO0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &perao0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERAO0_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_PERAO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &perao1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERAO1_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_PERAO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "vote-regmap", \
+ .regs = &perao1_cg_regs, \
+ .vote_regs = &perao1_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_PERAO2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &perao2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PERAO2_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate perao_clks[] = {
+ /* PERAO0 */
+ GATE_PERAO0(CLK_PERAO_UART0_BCLK, "perao_uart0_bclk", "ck_uart_ck", 0),
+ GATE_PERAO0_V(CLK_PERAO_UART0_BCLK_UART, "perao_uart0_bclk_uart", "perao_uart0_bclk"),
+ GATE_PERAO0(CLK_PERAO_UART1_BCLK, "perao_uart1_bclk", "ck_uart_ck", 1),
+ GATE_PERAO0_V(CLK_PERAO_UART1_BCLK_UART, "perao_uart1_bclk_uart", "perao_uart1_bclk"),
+ GATE_PERAO0(CLK_PERAO_UART2_BCLK, "perao_uart2_bclk", "ck_uart_ck", 2),
+ GATE_PERAO0_V(CLK_PERAO_UART2_BCLK_UART, "perao_uart2_bclk_uart", "perao_uart2_bclk"),
+ GATE_PERAO0(CLK_PERAO_UART3_BCLK, "perao_uart3_bclk", "ck_uart_ck", 3),
+ GATE_PERAO0_V(CLK_PERAO_UART3_BCLK_UART, "perao_uart3_bclk_uart", "perao_uart3_bclk"),
+ GATE_PERAO0(CLK_PERAO_UART4_BCLK, "perao_uart4_bclk", "ck_uart_ck", 4),
+ GATE_PERAO0_V(CLK_PERAO_UART4_BCLK_UART, "perao_uart4_bclk_uart", "perao_uart4_bclk"),
+ GATE_PERAO0(CLK_PERAO_UART5_BCLK, "perao_uart5_bclk", "ck_uart_ck", 5),
+ GATE_PERAO0_V(CLK_PERAO_UART5_BCLK_UART, "perao_uart5_bclk_uart", "perao_uart5_bclk"),
+ GATE_PERAO0(CLK_PERAO_PWM_X16W_HCLK, "perao_pwm_x16w", "ck_p_axi_ck", 12),
+ GATE_PERAO0_V(CLK_PERAO_PWM_X16W_HCLK_PWM, "perao_pwm_x16w_pwm", "perao_pwm_x16w"),
+ GATE_PERAO0(CLK_PERAO_PWM_X16W_BCLK, "perao_pwm_x16w_bclk", "ck_pwm_ck", 13),
+ GATE_PERAO0_V(CLK_PERAO_PWM_X16W_BCLK_PWM, "perao_pwm_x16w_bclk_pwm",
+ "perao_pwm_x16w_bclk"),
+ GATE_PERAO0(CLK_PERAO_PWM_PWM_BCLK0, "perao_pwm_pwm_bclk0", "ck_pwm_ck", 14),
+ GATE_PERAO0_V(CLK_PERAO_PWM_PWM_BCLK0_PWM, "perao_pwm_pwm_bclk0_pwm",
+ "perao_pwm_pwm_bclk0"),
+ GATE_PERAO0(CLK_PERAO_PWM_PWM_BCLK1, "perao_pwm_pwm_bclk1", "ck_pwm_ck", 15),
+ GATE_PERAO0_V(CLK_PERAO_PWM_PWM_BCLK1_PWM, "perao_pwm_pwm_bclk1_pwm",
+ "perao_pwm_pwm_bclk1"),
+ GATE_PERAO0(CLK_PERAO_PWM_PWM_BCLK2, "perao_pwm_pwm_bclk2", "ck_pwm_ck", 16),
+ GATE_PERAO0_V(CLK_PERAO_PWM_PWM_BCLK2_PWM, "perao_pwm_pwm_bclk2_pwm",
+ "perao_pwm_pwm_bclk2"),
+ GATE_PERAO0(CLK_PERAO_PWM_PWM_BCLK3, "perao_pwm_pwm_bclk3", "ck_pwm_ck", 17),
+ GATE_PERAO0_V(CLK_PERAO_PWM_PWM_BCLK3_PWM, "perao_pwm_pwm_bclk3_pwm",
+ "perao_pwm_pwm_bclk3"),
+ /* PERAO1 */
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI0_BCLK, "perao_spi0_bclk", "ck_spi0_b_ck", 0),
+ GATE_PERAO1_V(CLK_PERAO_SPI0_BCLK_SPI, "perao_spi0_bclk_spi", "perao_spi0_bclk"),
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI1_BCLK, "perao_spi1_bclk", "ck_spi1_b_ck", 2),
+ GATE_PERAO1_V(CLK_PERAO_SPI1_BCLK_SPI, "perao_spi1_bclk_spi", "perao_spi1_bclk"),
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI2_BCLK, "perao_spi2_bclk", "ck_spi2_b_ck", 3),
+ GATE_PERAO1_V(CLK_PERAO_SPI2_BCLK_SPI, "perao_spi2_bclk_spi", "perao_spi2_bclk"),
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI3_BCLK, "perao_spi3_bclk", "ck_spi3_b_ck", 4),
+ GATE_PERAO1_V(CLK_PERAO_SPI3_BCLK_SPI, "perao_spi3_bclk_spi", "perao_spi3_bclk"),
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI4_BCLK, "perao_spi4_bclk", "ck_spi4_b_ck", 5),
+ GATE_PERAO1_V(CLK_PERAO_SPI4_BCLK_SPI, "perao_spi4_bclk_spi", "perao_spi4_bclk"),
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI5_BCLK, "perao_spi5_bclk", "ck_spi5_b_ck", 6),
+ GATE_PERAO1_V(CLK_PERAO_SPI5_BCLK_SPI, "perao_spi5_bclk_spi", "perao_spi5_bclk"),
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI6_BCLK, "perao_spi6_bclk", "ck_spi6_b_ck", 7),
+ GATE_PERAO1_V(CLK_PERAO_SPI6_BCLK_SPI, "perao_spi6_bclk_spi", "perao_spi6_bclk"),
+ GATE_VOTE_PERAO1(CLK_PERAO_SPI7_BCLK, "perao_spi7_bclk", "ck_spi7_b_ck", 8),
+ GATE_PERAO1_V(CLK_PERAO_SPI7_BCLK_SPI, "perao_spi7_bclk_spi", "perao_spi7_bclk"),
+ GATE_PERAO1(CLK_PERAO_FLASHIF_FLASH, "perao_flashif_flash", "ck_sflash_ck", 18),
+ GATE_PERAO1_V(CLK_PERAO_FLASHIF_FLASH_FLASHIF, "perao_flashif_flash_flashif",
+ "perao_flashif_flash"),
+ GATE_PERAO1(CLK_PERAO_FLASHIF_27M, "perao_flashif_27m", "ck_sflash_ck", 19),
+ GATE_PERAO1_V(CLK_PERAO_FLASHIF_27M_FLASHIF, "perao_flashif_27m_flashif",
+ "perao_flashif_27m"),
+ GATE_PERAO1(CLK_PERAO_FLASHIF_DRAM, "perao_flashif_dram", "ck_p_axi_ck", 20),
+ GATE_PERAO1_V(CLK_PERAO_FLASHIF_DRAM_FLASHIF, "perao_flashif_dram_flashif",
+ "perao_flashif_dram"),
+ GATE_PERAO1(CLK_PERAO_FLASHIF_AXI, "perao_flashif_axi", "ck_p_axi_ck", 21),
+ GATE_PERAO1_V(CLK_PERAO_FLASHIF_AXI_FLASHIF, "perao_flashif_axi_flashif",
+ "perao_flashif_axi"),
+ GATE_PERAO1(CLK_PERAO_FLASHIF_BCLK, "perao_flashif_bclk", "ck_p_axi_ck", 22),
+ GATE_PERAO1_V(CLK_PERAO_FLASHIF_BCLK_FLASHIF, "perao_flashif_bclk_flashif",
+ "perao_flashif_bclk"),
+ GATE_PERAO1(CLK_PERAO_AP_DMA_X32W_BCLK, "perao_ap_dma_x32w_bclk", "ck_p_axi_ck", 26),
+ GATE_PERAO1_V(CLK_PERAO_AP_DMA_X32W_BCLK_UART, "perao_ap_dma_x32w_bclk_uart",
+ "perao_ap_dma_x32w_bclk"),
+ GATE_PERAO1_V(CLK_PERAO_AP_DMA_X32W_BCLK_I2C, "perao_ap_dma_x32w_bclk_i2c",
+ "perao_ap_dma_x32w_bclk"),
+ /* PERAO2 */
+ GATE_PERAO2(CLK_PERAO_MSDC1_MSDC_SRC, "perao_msdc1_msdc_src", "ck_msdc30_1_ck", 1),
+ GATE_PERAO2_V(CLK_PERAO_MSDC1_MSDC_SRC_MSDC1, "perao_msdc1_msdc_src_msdc1",
+ "perao_msdc1_msdc_src"),
+ GATE_PERAO2(CLK_PERAO_MSDC1_HCLK, "perao_msdc1", "ck_msdc30_1_ck", 2),
+ GATE_PERAO2_V(CLK_PERAO_MSDC1_HCLK_MSDC1, "perao_msdc1_msdc1", "perao_msdc1"),
+ GATE_PERAO2(CLK_PERAO_MSDC1_AXI, "perao_msdc1_axi", "ck_p_axi_ck", 3),
+ GATE_PERAO2_V(CLK_PERAO_MSDC1_AXI_MSDC1, "perao_msdc1_axi_msdc1", "perao_msdc1_axi"),
+ GATE_PERAO2(CLK_PERAO_MSDC1_HCLK_WRAP, "perao_msdc1_h_wrap", "ck_p_axi_ck", 4),
+ GATE_PERAO2_V(CLK_PERAO_MSDC1_HCLK_WRAP_MSDC1, "perao_msdc1_h_wrap_msdc1",
+ "perao_msdc1_h_wrap"),
+ GATE_PERAO2(CLK_PERAO_MSDC2_MSDC_SRC, "perao_msdc2_msdc_src", "ck_msdc30_2_ck", 10),
+ GATE_PERAO2_V(CLK_PERAO_MSDC2_MSDC_SRC_MSDC2, "perao_msdc2_msdc_src_msdc2",
+ "perao_msdc2_msdc_src"),
+ GATE_PERAO2(CLK_PERAO_MSDC2_HCLK, "perao_msdc2", "ck_msdc30_2_ck", 11),
+ GATE_PERAO2_V(CLK_PERAO_MSDC2_HCLK_MSDC2, "perao_msdc2_msdc2", "perao_msdc2"),
+ GATE_PERAO2(CLK_PERAO_MSDC2_AXI, "perao_msdc2_axi", "ck_p_axi_ck", 12),
+ GATE_PERAO2_V(CLK_PERAO_MSDC2_AXI_MSDC2, "perao_msdc2_axi_msdc2", "perao_msdc2_axi"),
+ GATE_PERAO2(CLK_PERAO_MSDC2_HCLK_WRAP, "perao_msdc2_h_wrap", "ck_p_axi_ck", 13),
+ GATE_PERAO2_V(CLK_PERAO_MSDC2_HCLK_WRAP_MSDC2, "perao_msdc2_h_wrap_msdc2",
+ "perao_msdc2_h_wrap"),
+};
+
+static const struct mtk_clk_desc perao_mcd = {
+ .clks = perao_clks,
+ .num_clks = ARRAY_SIZE(perao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8196_peri_ao[] = {
+ { .compatible = "mediatek,mt8196-pericfg_ao", .data = &perao_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_peri_ao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-peri_ao",
+ .of_match_table = of_match_clk_mt8196_peri_ao,
+ },
+};
+
+module_platform_driver(clk_mt8196_peri_ao_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 13/26] clk: mediatek: Add MT8196 adsp clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (11 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 12/26] clk: mediatek: Add MT8196 peripheral " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 14/26] clk: mediatek: Add MT8196 i2c " Guangjie Song
` (12 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 adsp clock controller which provides clock gate control for
Audio DSP.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-adsp.c | 291 +++++++++++++++++++++++++
3 files changed, 299 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-adsp.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 1e0c6f177ecd..fe54dca0062e 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1010,6 +1010,13 @@ config COMMON_CLK_MT8196
help
This driver supports MediaTek MT8196 basic clocks.
+config COMMON_CLK_MT8196_ADSP
+ tristate "Clock driver for MediaTek MT8196 adsp"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 adsp clocks
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index c95e45356b78..c0d676930a80 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -153,6 +153,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o \
clk-mt8196-topckgen.o clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
clk-mt8196-peri_ao.o
+obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) += clk-mt8196-adsp.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-adsp.c b/drivers/clk/mediatek/clk-mt8196-adsp.c
new file mode 100644
index 000000000000..8272fc481cb1
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-adsp.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs afe0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs afe1_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs afe2_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+static const struct mtk_gate_regs afe3_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+static const struct mtk_gate_regs afe4_cg_regs = {
+ .set_ofs = 0xc,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0xc,
+};
+
+#define GATE_AFE0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &afe0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE | \
+ CLK_IGNORE_UNUSED, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AFE0_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_AFE1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &afe1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE | \
+ CLK_IGNORE_UNUSED, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AFE1_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_AFE2(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &afe2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE | \
+ CLK_IGNORE_UNUSED, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AFE2_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_AFE3(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &afe3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE | \
+ CLK_IGNORE_UNUSED, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AFE3_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_AFE4(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &afe4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE | \
+ CLK_IGNORE_UNUSED, \
+ .ops = &mtk_clk_gate_ops_no_setclr, \
+ }
+
+#define GATE_AFE4_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate afe_clks[] = {
+ /* AFE0 */
+ GATE_AFE0(CLK_AFE_PCM1, "afe_pcm1", "vlp_aud_clksq_ck", 13),
+ GATE_AFE0_V(CLK_AFE_PCM1_AFE, "afe_pcm1_afe", "afe_pcm1"),
+ GATE_AFE0(CLK_AFE_PCM0, "afe_pcm0", "vlp_aud_clksq_ck", 14),
+ GATE_AFE0_V(CLK_AFE_PCM0_AFE, "afe_pcm0_afe", "afe_pcm0"),
+ GATE_AFE0(CLK_AFE_CM2, "afe_cm2", "vlp_aud_clksq_ck", 16),
+ GATE_AFE0_V(CLK_AFE_CM2_AFE, "afe_cm2_afe", "afe_cm2"),
+ GATE_AFE0(CLK_AFE_CM1, "afe_cm1", "vlp_aud_clksq_ck", 17),
+ GATE_AFE0_V(CLK_AFE_CM1_AFE, "afe_cm1_afe", "afe_cm1"),
+ GATE_AFE0(CLK_AFE_CM0, "afe_cm0", "vlp_aud_clksq_ck", 18),
+ GATE_AFE0_V(CLK_AFE_CM0_AFE, "afe_cm0_afe", "afe_cm0"),
+ GATE_AFE0(CLK_AFE_STF, "afe_stf", "vlp_aud_clksq_ck", 19),
+ GATE_AFE0_V(CLK_AFE_STF_AFE, "afe_stf_afe", "afe_stf"),
+ GATE_AFE0(CLK_AFE_HW_GAIN23, "afe_hw_gain23", "vlp_aud_clksq_ck", 20),
+ GATE_AFE0_V(CLK_AFE_HW_GAIN23_AFE, "afe_hw_gain23_afe", "afe_hw_gain23"),
+ GATE_AFE0(CLK_AFE_HW_GAIN01, "afe_hw_gain01", "vlp_aud_clksq_ck", 21),
+ GATE_AFE0_V(CLK_AFE_HW_GAIN01_AFE, "afe_hw_gain01_afe", "afe_hw_gain01"),
+ GATE_AFE0(CLK_AFE_FM_I2S, "afe_fm_i2s", "vlp_aud_clksq_ck", 24),
+ GATE_AFE0_V(CLK_AFE_FM_I2S_AFE, "afe_fm_i2s_afe", "afe_fm_i2s"),
+ GATE_AFE0(CLK_AFE_MTKAIFV4, "afe_mtkaifv4", "vlp_aud_clksq_ck", 25),
+ GATE_AFE0_V(CLK_AFE_MTKAIFV4_AFE, "afe_mtkaifv4_afe", "afe_mtkaifv4"),
+ /* AFE1 */
+ GATE_AFE1(CLK_AFE_AUDIO_HOPPING, "afe_audio_hopping_ck", "vlp_aud_clksq_ck", 0),
+ GATE_AFE1_V(CLK_AFE_AUDIO_HOPPING_AFE, "afe_audio_hopping_ck_afe", "afe_audio_hopping_ck"),
+ GATE_AFE1(CLK_AFE_AUDIO_F26M, "afe_audio_f26m_ck", "vlp_aud_clksq_ck", 1),
+ GATE_AFE1_V(CLK_AFE_AUDIO_F26M_AFE, "afe_audio_f26m_ck_afe", "afe_audio_f26m_ck"),
+ GATE_AFE1(CLK_AFE_APLL1, "afe_apll1_ck", "ck_aud_1_ck", 2),
+ GATE_AFE1_V(CLK_AFE_APLL1_AFE, "afe_apll1_ck_afe", "afe_apll1_ck"),
+ GATE_AFE1(CLK_AFE_APLL2, "afe_apll2_ck", "ck_aud_2_ck", 3),
+ GATE_AFE1_V(CLK_AFE_APLL2_AFE, "afe_apll2_ck_afe", "afe_apll2_ck"),
+ GATE_AFE1(CLK_AFE_H208M, "afe_h208m_ck", "vlp_audio_h_ck", 4),
+ GATE_AFE1_V(CLK_AFE_H208M_AFE, "afe_h208m_ck_afe", "afe_h208m_ck"),
+ GATE_AFE1(CLK_AFE_APLL_TUNER2, "afe_apll_tuner2", "vlp_aud_engen2_ck", 12),
+ GATE_AFE1_V(CLK_AFE_APLL_TUNER2_AFE, "afe_apll_tuner2_afe", "afe_apll_tuner2"),
+ GATE_AFE1(CLK_AFE_APLL_TUNER1, "afe_apll_tuner1", "vlp_aud_engen1_ck", 13),
+ GATE_AFE1_V(CLK_AFE_APLL_TUNER1_AFE, "afe_apll_tuner1_afe", "afe_apll_tuner1"),
+ /* AFE2 */
+ GATE_AFE2(CLK_AFE_UL2_ADC_HIRES_TML, "afe_ul2_aht", "vlp_audio_h_ck", 12),
+ GATE_AFE2_V(CLK_AFE_UL2_ADC_HIRES_TML_AFE, "afe_ul2_aht_afe", "afe_ul2_aht"),
+ GATE_AFE2(CLK_AFE_UL2_ADC_HIRES, "afe_ul2_adc_hires", "vlp_audio_h_ck", 13),
+ GATE_AFE2_V(CLK_AFE_UL2_ADC_HIRES_AFE, "afe_ul2_adc_hires_afe", "afe_ul2_adc_hires"),
+ GATE_AFE2(CLK_AFE_UL2_TML, "afe_ul2_tml", "vlp_aud_clksq_ck", 14),
+ GATE_AFE2_V(CLK_AFE_UL2_TML_AFE, "afe_ul2_tml_afe", "afe_ul2_tml"),
+ GATE_AFE2(CLK_AFE_UL2_ADC, "afe_ul2_adc", "vlp_aud_clksq_ck", 15),
+ GATE_AFE2_V(CLK_AFE_UL2_ADC_AFE, "afe_ul2_adc_afe", "afe_ul2_adc"),
+ GATE_AFE2(CLK_AFE_UL1_ADC_HIRES_TML, "afe_ul1_aht", "vlp_audio_h_ck", 16),
+ GATE_AFE2_V(CLK_AFE_UL1_ADC_HIRES_TML_AFE, "afe_ul1_aht_afe", "afe_ul1_aht"),
+ GATE_AFE2(CLK_AFE_UL1_ADC_HIRES, "afe_ul1_adc_hires", "vlp_audio_h_ck", 17),
+ GATE_AFE2_V(CLK_AFE_UL1_ADC_HIRES_AFE, "afe_ul1_adc_hires_afe", "afe_ul1_adc_hires"),
+ GATE_AFE2(CLK_AFE_UL1_TML, "afe_ul1_tml", "vlp_aud_clksq_ck", 18),
+ GATE_AFE2_V(CLK_AFE_UL1_TML_AFE, "afe_ul1_tml_afe", "afe_ul1_tml"),
+ GATE_AFE2(CLK_AFE_UL1_ADC, "afe_ul1_adc", "vlp_aud_clksq_ck", 19),
+ GATE_AFE2_V(CLK_AFE_UL1_ADC_AFE, "afe_ul1_adc_afe", "afe_ul1_adc"),
+ GATE_AFE2(CLK_AFE_UL0_ADC_HIRES_TML, "afe_ul0_aht", "vlp_audio_h_ck", 20),
+ GATE_AFE2_V(CLK_AFE_UL0_ADC_HIRES_TML_AFE, "afe_ul0_aht_afe", "afe_ul0_aht"),
+ GATE_AFE2(CLK_AFE_UL0_ADC_HIRES, "afe_ul0_adc_hires", "vlp_audio_h_ck", 21),
+ GATE_AFE2_V(CLK_AFE_UL0_ADC_HIRES_AFE, "afe_ul0_adc_hires_afe", "afe_ul0_adc_hires"),
+ GATE_AFE2(CLK_AFE_UL0_TML, "afe_ul0_tml", "vlp_aud_clksq_ck", 22),
+ GATE_AFE2_V(CLK_AFE_UL0_TML_AFE, "afe_ul0_tml_afe", "afe_ul0_tml"),
+ GATE_AFE2(CLK_AFE_UL0_ADC, "afe_ul0_adc", "vlp_aud_clksq_ck", 23),
+ GATE_AFE2_V(CLK_AFE_UL0_ADC_AFE, "afe_ul0_adc_afe", "afe_ul0_adc"),
+ /* AFE3 */
+ GATE_AFE3(CLK_AFE_ETDM_IN6, "afe_etdm_in6", "vlp_aud_clksq_ck", 7),
+ GATE_AFE3_V(CLK_AFE_ETDM_IN6_AFE, "afe_etdm_in6_afe", "afe_etdm_in6"),
+ GATE_AFE3(CLK_AFE_ETDM_IN5, "afe_etdm_in5", "vlp_aud_clksq_ck", 8),
+ GATE_AFE3_V(CLK_AFE_ETDM_IN5_AFE, "afe_etdm_in5_afe", "afe_etdm_in5"),
+ GATE_AFE3(CLK_AFE_ETDM_IN4, "afe_etdm_in4", "vlp_aud_clksq_ck", 9),
+ GATE_AFE3_V(CLK_AFE_ETDM_IN4_AFE, "afe_etdm_in4_afe", "afe_etdm_in4"),
+ GATE_AFE3(CLK_AFE_ETDM_IN3, "afe_etdm_in3", "vlp_aud_clksq_ck", 10),
+ GATE_AFE3_V(CLK_AFE_ETDM_IN3_AFE, "afe_etdm_in3_afe", "afe_etdm_in3"),
+ GATE_AFE3(CLK_AFE_ETDM_IN2, "afe_etdm_in2", "vlp_aud_clksq_ck", 11),
+ GATE_AFE3_V(CLK_AFE_ETDM_IN2_AFE, "afe_etdm_in2_afe", "afe_etdm_in2"),
+ GATE_AFE3(CLK_AFE_ETDM_IN1, "afe_etdm_in1", "vlp_aud_clksq_ck", 12),
+ GATE_AFE3_V(CLK_AFE_ETDM_IN1_AFE, "afe_etdm_in1_afe", "afe_etdm_in1"),
+ GATE_AFE3(CLK_AFE_ETDM_IN0, "afe_etdm_in0", "vlp_aud_clksq_ck", 13),
+ GATE_AFE3_V(CLK_AFE_ETDM_IN0_AFE, "afe_etdm_in0_afe", "afe_etdm_in0"),
+ GATE_AFE3(CLK_AFE_ETDM_OUT6, "afe_etdm_out6", "vlp_aud_clksq_ck", 15),
+ GATE_AFE3_V(CLK_AFE_ETDM_OUT6_AFE, "afe_etdm_out6_afe", "afe_etdm_out6"),
+ GATE_AFE3(CLK_AFE_ETDM_OUT5, "afe_etdm_out5", "vlp_aud_clksq_ck", 16),
+ GATE_AFE3_V(CLK_AFE_ETDM_OUT5_AFE, "afe_etdm_out5_afe", "afe_etdm_out5"),
+ GATE_AFE3(CLK_AFE_ETDM_OUT4, "afe_etdm_out4", "vlp_aud_clksq_ck", 17),
+ GATE_AFE3_V(CLK_AFE_ETDM_OUT4_AFE, "afe_etdm_out4_afe", "afe_etdm_out4"),
+ GATE_AFE3(CLK_AFE_ETDM_OUT3, "afe_etdm_out3", "vlp_aud_clksq_ck", 18),
+ GATE_AFE3_V(CLK_AFE_ETDM_OUT3_AFE, "afe_etdm_out3_afe", "afe_etdm_out3"),
+ GATE_AFE3(CLK_AFE_ETDM_OUT2, "afe_etdm_out2", "vlp_aud_clksq_ck", 19),
+ GATE_AFE3_V(CLK_AFE_ETDM_OUT2_AFE, "afe_etdm_out2_afe", "afe_etdm_out2"),
+ GATE_AFE3(CLK_AFE_ETDM_OUT1, "afe_etdm_out1", "vlp_aud_clksq_ck", 20),
+ GATE_AFE3_V(CLK_AFE_ETDM_OUT1_AFE, "afe_etdm_out1_afe", "afe_etdm_out1"),
+ GATE_AFE3(CLK_AFE_ETDM_OUT0, "afe_etdm_out0", "vlp_aud_clksq_ck", 21),
+ GATE_AFE3_V(CLK_AFE_ETDM_OUT0_AFE, "afe_etdm_out0_afe", "afe_etdm_out0"),
+ GATE_AFE3(CLK_AFE_TDM_OUT, "afe_tdm_out", "ck_aud_1_ck", 24),
+ GATE_AFE3_V(CLK_AFE_TDM_OUT_AFE, "afe_tdm_out_afe", "afe_tdm_out"),
+ /* AFE4 */
+ GATE_AFE4(CLK_AFE_GENERAL15_ASRC, "afe_general15_asrc", "vlp_aud_clksq_ck", 9),
+ GATE_AFE4_V(CLK_AFE_GENERAL15_ASRC_AFE, "afe_general15_asrc_afe", "afe_general15_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL14_ASRC, "afe_general14_asrc", "vlp_aud_clksq_ck", 10),
+ GATE_AFE4_V(CLK_AFE_GENERAL14_ASRC_AFE, "afe_general14_asrc_afe", "afe_general14_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL13_ASRC, "afe_general13_asrc", "vlp_aud_clksq_ck", 11),
+ GATE_AFE4_V(CLK_AFE_GENERAL13_ASRC_AFE, "afe_general13_asrc_afe", "afe_general13_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL12_ASRC, "afe_general12_asrc", "vlp_aud_clksq_ck", 12),
+ GATE_AFE4_V(CLK_AFE_GENERAL12_ASRC_AFE, "afe_general12_asrc_afe", "afe_general12_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL11_ASRC, "afe_general11_asrc", "vlp_aud_clksq_ck", 13),
+ GATE_AFE4_V(CLK_AFE_GENERAL11_ASRC_AFE, "afe_general11_asrc_afe", "afe_general11_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL10_ASRC, "afe_general10_asrc", "vlp_aud_clksq_ck", 14),
+ GATE_AFE4_V(CLK_AFE_GENERAL10_ASRC_AFE, "afe_general10_asrc_afe", "afe_general10_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL9_ASRC, "afe_general9_asrc", "vlp_aud_clksq_ck", 15),
+ GATE_AFE4_V(CLK_AFE_GENERAL9_ASRC_AFE, "afe_general9_asrc_afe", "afe_general9_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL8_ASRC, "afe_general8_asrc", "vlp_aud_clksq_ck", 16),
+ GATE_AFE4_V(CLK_AFE_GENERAL8_ASRC_AFE, "afe_general8_asrc_afe", "afe_general8_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL7_ASRC, "afe_general7_asrc", "vlp_aud_clksq_ck", 17),
+ GATE_AFE4_V(CLK_AFE_GENERAL7_ASRC_AFE, "afe_general7_asrc_afe", "afe_general7_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL6_ASRC, "afe_general6_asrc", "vlp_aud_clksq_ck", 18),
+ GATE_AFE4_V(CLK_AFE_GENERAL6_ASRC_AFE, "afe_general6_asrc_afe", "afe_general6_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL5_ASRC, "afe_general5_asrc", "vlp_aud_clksq_ck", 19),
+ GATE_AFE4_V(CLK_AFE_GENERAL5_ASRC_AFE, "afe_general5_asrc_afe", "afe_general5_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL4_ASRC, "afe_general4_asrc", "vlp_aud_clksq_ck", 20),
+ GATE_AFE4_V(CLK_AFE_GENERAL4_ASRC_AFE, "afe_general4_asrc_afe", "afe_general4_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL3_ASRC, "afe_general3_asrc", "vlp_aud_clksq_ck", 21),
+ GATE_AFE4_V(CLK_AFE_GENERAL3_ASRC_AFE, "afe_general3_asrc_afe", "afe_general3_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL2_ASRC, "afe_general2_asrc", "vlp_aud_clksq_ck", 22),
+ GATE_AFE4_V(CLK_AFE_GENERAL2_ASRC_AFE, "afe_general2_asrc_afe", "afe_general2_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL1_ASRC, "afe_general1_asrc", "vlp_aud_clksq_ck", 23),
+ GATE_AFE4_V(CLK_AFE_GENERAL1_ASRC_AFE, "afe_general1_asrc_afe", "afe_general1_asrc"),
+ GATE_AFE4(CLK_AFE_GENERAL0_ASRC, "afe_general0_asrc", "vlp_aud_clksq_ck", 24),
+ GATE_AFE4_V(CLK_AFE_GENERAL0_ASRC_AFE, "afe_general0_asrc_afe", "afe_general0_asrc"),
+ GATE_AFE4(CLK_AFE_CONNSYS_I2S_ASRC, "afe_connsys_i2s_asrc", "vlp_aud_clksq_ck", 25),
+ GATE_AFE4_V(CLK_AFE_CONNSYS_I2S_ASRC_AFE, "afe_connsys_i2s_asrc_afe", "afe_connsys_i2s_asrc"),
+};
+
+static const struct mtk_clk_desc afe_mcd = {
+ .clks = afe_clks,
+ .num_clks = ARRAY_SIZE(afe_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct of_device_id of_match_clk_mt8196_adsp[] = {
+ { .compatible = "mediatek,mt8196-audiosys", .data = &afe_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_adsp_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-adsp",
+ .of_match_table = of_match_clk_mt8196_adsp,
+ },
+};
+
+module_platform_driver(clk_mt8196_adsp_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 14/26] clk: mediatek: Add MT8196 i2c clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (12 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 13/26] clk: mediatek: Add MT8196 adsp " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 15/26] clk: mediatek: Add MT8196 mcu " Guangjie Song
` (11 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 i2c clock controller which provides clock gate control for
i2c.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 +
drivers/clk/mediatek/Makefile | 1 +
.../clk/mediatek/clk-mt8196-imp_iic_wrap.c | 211 ++++++++++++++++++
3 files changed, 219 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index fe54dca0062e..bc373e9ab589 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1017,6 +1017,13 @@ config COMMON_CLK_MT8196_ADSP
help
This driver supports MediaTek MT8196 adsp clocks
+config COMMON_CLK_MT8196_IMP_IIC_WRAP
+ tristate "Clock driver for MediaTek MT8196 imp_iic_wrap"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 i2c clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index c0d676930a80..beea4d8eeebe 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -154,6 +154,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys
clk-mt8196-topckgen.o clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
clk-mt8196-peri_ao.o
obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) += clk-mt8196-adsp.o
+obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
new file mode 100644
index 000000000000..c514882e957e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs impc_cg_regs = {
+ .set_ofs = 0xe08,
+ .clr_ofs = 0xe04,
+ .sta_ofs = 0xe00,
+};
+
+#define GATE_IMPC(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &impc_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_IMPC_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate impc_clks[] = {
+ GATE_IMPC(CLK_IMPC_I2C11, "impc_i2c11", "ck_i2c_p_ck", 0),
+ GATE_IMPC_V(CLK_IMPC_I2C11_I2C, "impc_i2c11_i2c", "impc_i2c11"),
+ GATE_IMPC(CLK_IMPC_I2C12, "impc_i2c12", "ck_i2c_p_ck", 1),
+ GATE_IMPC_V(CLK_IMPC_I2C12_I2C, "impc_i2c12_i2c", "impc_i2c12"),
+ GATE_IMPC(CLK_IMPC_I2C13, "impc_i2c13", "ck_i2c_p_ck", 2),
+ GATE_IMPC_V(CLK_IMPC_I2C13_I2C, "impc_i2c13_i2c", "impc_i2c13"),
+ GATE_IMPC(CLK_IMPC_I2C14, "impc_i2c14", "ck_i2c_p_ck", 3),
+ GATE_IMPC_V(CLK_IMPC_I2C14_I2C, "impc_i2c14_i2c", "impc_i2c14"),
+};
+
+static const struct mtk_clk_desc impc_mcd = {
+ .clks = impc_clks,
+ .num_clks = ARRAY_SIZE(impc_clks),
+};
+
+static const struct mtk_gate_regs impe_cg_regs = {
+ .set_ofs = 0xe08,
+ .clr_ofs = 0xe04,
+ .sta_ofs = 0xe00,
+};
+
+#define GATE_IMPE(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &impe_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_IMPE_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate impe_clks[] = {
+ GATE_IMPE(CLK_IMPE_I2C5, "impe_i2c5", "ck_i2c_east_ck", 0),
+ GATE_IMPE_V(CLK_IMPE_I2C5_I2C, "impe_i2c5_i2c", "impe_i2c5"),
+};
+
+static const struct mtk_clk_desc impe_mcd = {
+ .clks = impe_clks,
+ .num_clks = ARRAY_SIZE(impe_clks),
+};
+
+static const struct mtk_gate_regs impn_cg_regs = {
+ .set_ofs = 0xe08,
+ .clr_ofs = 0xe04,
+ .sta_ofs = 0xe00,
+};
+
+static const struct mtk_gate_regs impn_vote_regs = {
+ .set_ofs = 0x0000,
+ .clr_ofs = 0x0004,
+ .sta_ofs = 0x2c00,
+};
+
+#define GATE_IMPN(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &impn_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_IMPN_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_IMPN(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "vote-regmap", \
+ .regs = &impn_cg_regs, \
+ .vote_regs = &impn_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+static const struct mtk_gate impn_clks[] = {
+ GATE_IMPN(CLK_IMPN_I2C1, "impn_i2c1", "ck_i2c_north_ck", 0),
+ GATE_IMPN_V(CLK_IMPN_I2C1_I2C, "impn_i2c1_i2c", "impn_i2c1"),
+ GATE_IMPN(CLK_IMPN_I2C2, "impn_i2c2", "ck_i2c_north_ck", 1),
+ GATE_IMPN_V(CLK_IMPN_I2C2_I2C, "impn_i2c2_i2c", "impn_i2c2"),
+ GATE_IMPN(CLK_IMPN_I2C4, "impn_i2c4", "ck_i2c_north_ck", 2),
+ GATE_IMPN_V(CLK_IMPN_I2C4_I2C, "impn_i2c4_i2c", "impn_i2c4"),
+ GATE_VOTE_IMPN(CLK_IMPN_I2C7, "impn_i2c7", "ck_i2c_north_ck", 3),
+ GATE_IMPN_V(CLK_IMPN_I2C7_I2C, "impn_i2c7_i2c", "impn_i2c7"),
+ GATE_IMPN(CLK_IMPN_I2C8, "impn_i2c8", "ck_i2c_north_ck", 4),
+ GATE_IMPN_V(CLK_IMPN_I2C8_I2C, "impn_i2c8_i2c", "impn_i2c8"),
+ GATE_IMPN(CLK_IMPN_I2C9, "impn_i2c9", "ck_i2c_north_ck", 5),
+ GATE_IMPN_V(CLK_IMPN_I2C9_I2C, "impn_i2c9_i2c", "impn_i2c9"),
+};
+
+static const struct mtk_clk_desc impn_mcd = {
+ .clks = impn_clks,
+ .num_clks = ARRAY_SIZE(impn_clks),
+};
+
+static const struct mtk_gate_regs impw_cg_regs = {
+ .set_ofs = 0xe08,
+ .clr_ofs = 0xe04,
+ .sta_ofs = 0xe00,
+};
+
+#define GATE_IMPW(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &impw_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_IMPW_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate impw_clks[] = {
+ GATE_IMPW(CLK_IMPW_I2C0, "impw_i2c0", "ck_i2c_west_ck", 0),
+ GATE_IMPW_V(CLK_IMPW_I2C0_I2C, "impw_i2c0_i2c", "impw_i2c0"),
+ GATE_IMPW(CLK_IMPW_I2C3, "impw_i2c3", "ck_i2c_west_ck", 1),
+ GATE_IMPW_V(CLK_IMPW_I2C3_I2C, "impw_i2c3_i2c", "impw_i2c3"),
+ GATE_IMPW(CLK_IMPW_I2C6, "impw_i2c6", "ck_i2c_west_ck", 2),
+ GATE_IMPW_V(CLK_IMPW_I2C6_I2C, "impw_i2c6_i2c", "impw_i2c6"),
+ GATE_IMPW(CLK_IMPW_I2C10, "impw_i2c10", "ck_i2c_west_ck", 3),
+ GATE_IMPW_V(CLK_IMPW_I2C10_I2C, "impw_i2c10_i2c", "impw_i2c10"),
+};
+
+static const struct mtk_clk_desc impw_mcd = {
+ .clks = impw_clks,
+ .num_clks = ARRAY_SIZE(impw_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8196_imp_iic_wrap[] = {
+ { .compatible = "mediatek,mt8196-imp_iic_wrap_c", .data = &impc_mcd, },
+ { .compatible = "mediatek,mt8196-imp_iic_wrap_e", .data = &impe_mcd, },
+ { .compatible = "mediatek,mt8196-imp_iic_wrap_n", .data = &impn_mcd, },
+ { .compatible = "mediatek,mt8196-imp_iic_wrap_w", .data = &impw_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_imp_iic_wrap_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-imp_iic_wrap",
+ .of_match_table = of_match_clk_mt8196_imp_iic_wrap,
+ },
+};
+
+module_platform_driver(clk_mt8196_imp_iic_wrap_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 15/26] clk: mediatek: Add MT8196 mcu clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (13 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 14/26] clk: mediatek: Add MT8196 i2c " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 16/26] clk: mediatek: Add MT8196 mdpsys " Guangjie Song
` (10 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 mcu clock controller which provides pll control for mcu.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-mcu.c | 167 ++++++++++++++++++++++++++
3 files changed, 175 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-mcu.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index bc373e9ab589..4473feebae40 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1024,6 +1024,13 @@ config COMMON_CLK_MT8196_IMP_IIC_WRAP
help
This driver supports MediaTek MT8196 i2c clocks.
+config COMMON_CLK_MT8196_MCUSYS
+ tristate "Clock driver for MediaTek MT8196 mcusys"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 mcusys clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index beea4d8eeebe..1f6717569609 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys
clk-mt8196-peri_ao.o
obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) += clk-mt8196-adsp.o
obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
+obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/clk-mt8196-mcu.c
new file mode 100644
index 000000000000..19d13156794c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-mcu.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+#define ARMPLL_LL_CON0 0x008
+#define ARMPLL_LL_CON1 0x00c
+#define ARMPLL_LL_CON2 0x010
+#define ARMPLL_LL_CON3 0x014
+#define ARMPLL_BL_CON0 0x008
+#define ARMPLL_BL_CON1 0x00c
+#define ARMPLL_BL_CON2 0x010
+#define ARMPLL_BL_CON3 0x014
+#define ARMPLL_B_CON0 0x008
+#define ARMPLL_B_CON1 0x00c
+#define ARMPLL_B_CON2 0x010
+#define ARMPLL_B_CON3 0x014
+#define CCIPLL_CON0 0x008
+#define CCIPLL_CON1 0x00c
+#define CCIPLL_CON2 0x010
+#define CCIPLL_CON3 0x014
+#define PTPPLL_CON0 0x008
+#define PTPPLL_CON1 0x00c
+#define PTPPLL_CON2 0x010
+#define PTPPLL_CON3 0x014
+
+#define MT8196_PLL_FMAX (3800UL * MHZ)
+#define MT8196_PLL_FMIN (1500UL * MHZ)
+#define MT8196_INTEGER_BITS 8
+
+#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
+ _flags, _rst_bar_mask, \
+ _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, \
+ _pcw_reg, _pcw_shift, _pcwbits) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .en_reg = _en_reg, \
+ .en_mask = _en_mask, \
+ .pll_en_bit = _pll_en_bit, \
+ .flags = (_flags) | CLK_FENC_ENABLE, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT8196_PLL_FMAX, \
+ .fmin = MT8196_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8196_INTEGER_BITS, \
+ }
+
+static const struct mtk_pll_data cpu_bl_plls[] = {
+ PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0,
+ ARMPLL_BL_CON0, 0, 0, PLL_AO, BIT(0),
+ ARMPLL_BL_CON1, 24, 0, 0, 0,
+ ARMPLL_BL_CON1, 0, 22),
+};
+
+static const struct mtk_pll_data cpu_b_plls[] = {
+ PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0,
+ ARMPLL_B_CON0, 0, 0, PLL_AO, BIT(0),
+ ARMPLL_B_CON1, 24, 0, 0, 0,
+ ARMPLL_B_CON1, 0, 22),
+};
+
+static const struct mtk_pll_data cpu_ll_plls[] = {
+ PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0,
+ ARMPLL_LL_CON0, 0, 0, PLL_AO, BIT(0),
+ ARMPLL_LL_CON1, 24, 0, 0, 0,
+ ARMPLL_LL_CON1, 0, 22),
+};
+
+static const struct mtk_pll_data cci_plls[] = {
+ PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0,
+ CCIPLL_CON0, 0, 0, PLL_AO, BIT(0),
+ CCIPLL_CON1, 24, 0, 0, 0,
+ CCIPLL_CON1, 0, 22),
+};
+
+static const struct mtk_pll_data ptp_plls[] = {
+ PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0,
+ PTPPLL_CON0, 0, 0, PLL_AO, BIT(0),
+ PTPPLL_CON1, 24, 0, 0, 0,
+ PTPPLL_CON1, 0, 22),
+};
+
+static const struct of_device_id of_match_clk_mt8196_mcu[] = {
+ { .compatible = "mediatek,mt8196-armpll_bl_pll_ctrl", .data = &cpu_bl_plls, },
+ { .compatible = "mediatek,mt8196-armpll_b_pll_ctrl", .data = &cpu_b_plls, },
+ { .compatible = "mediatek,mt8196-armpll_ll_pll_ctrl", .data = &cpu_ll_plls, },
+ { .compatible = "mediatek,mt8196-ccipll_pll_ctrl", .data = &cci_plls, },
+ { .compatible = "mediatek,mt8196-ptppll_pll_ctrl", .data = &ptp_plls, },
+ { /* sentinel */ }
+};
+
+static int clk_mt8196_mcu_probe(struct platform_device *pdev)
+{
+ const struct mtk_pll_data *plls;
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int num_plls = 1;
+ int r;
+
+ plls = of_device_get_match_data(&pdev->dev);
+ if (!plls)
+ return -EINVAL;
+
+ clk_data = mtk_alloc_clk_data(num_plls);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
+ if (r) {
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+ mtk_clk_unregister_plls(plls, num_plls, clk_data);
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ return 0;
+}
+
+static void clk_mt8196_mcu_remove(struct platform_device *pdev)
+{
+ const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+ int num_plls = 1;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_plls(plls, num_plls, clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static struct platform_driver clk_mt8196_mcu_drv = {
+ .probe = clk_mt8196_mcu_probe,
+ .remove = clk_mt8196_mcu_remove,
+ .driver = {
+ .name = "clk-mt8196-mcu",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8196_mcu,
+ },
+};
+
+module_platform_driver(clk_mt8196_mcu_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 16/26] clk: mediatek: Add MT8196 mdpsys clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (14 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 15/26] clk: mediatek: Add MT8196 mcu " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 17/26] clk: mediatek: Add MT8196 mfg " Guangjie Song
` (9 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 mdpsys clock controller which provides clock gate control
for media display.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-mdpsys.c | 357 +++++++++++++++++++++++
3 files changed, 365 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-mdpsys.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 4473feebae40..8763cc1480a3 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1031,6 +1031,13 @@ config COMMON_CLK_MT8196_MCUSYS
help
This driver supports MediaTek MT8196 mcusys clocks.
+config COMMON_CLK_MT8196_MDPSYS
+ tristate "Clock driver for MediaTek MT8196 mdpsys"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 mdpsys clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1f6717569609..dccc6d84941c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -156,6 +156,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys
obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) += clk-mt8196-adsp.o
obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
+obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-mdpsys.c b/drivers/clk/mediatek/clk-mt8196-mdpsys.c
new file mode 100644
index 000000000000..ef591efa9fec
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-mdpsys.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs mdp10_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mdp11_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs mdp12_cg_regs = {
+ .set_ofs = 0x124,
+ .clr_ofs = 0x128,
+ .sta_ofs = 0x120,
+};
+
+#define GATE_MDP10(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mdp10_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MDP10_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_MDP11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mdp11_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MDP11_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_MDP12(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mdp12_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_MDP12_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate mdp1_clks[] = {
+ /* MDP10 */
+ GATE_MDP10(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0", "ck2_mdp_ck", 0),
+ GATE_MDP10_V(CLK_MDP1_MDP_MUTEX0_MML, "mdp1_mdp_mutex0_mml", "mdp1_mdp_mutex0"),
+ GATE_MDP10(CLK_MDP1_SMI0, "mdp1_smi0", "ck2_mdp_ck", 1),
+ GATE_MDP10_V(CLK_MDP1_SMI0_SMI, "mdp1_smi0_smi", "mdp1_smi0"),
+ GATE_MDP10(CLK_MDP1_APB_BUS, "mdp1_apb_bus", "ck2_mdp_ck", 2),
+ GATE_MDP10_V(CLK_MDP1_APB_BUS_MML, "mdp1_apb_bus_mml", "mdp1_apb_bus"),
+ GATE_MDP10(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0", "ck2_mdp_ck", 3),
+ GATE_MDP10_V(CLK_MDP1_MDP_RDMA0_MML, "mdp1_mdp_rdma0_mml", "mdp1_mdp_rdma0"),
+ GATE_MDP10(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1", "ck2_mdp_ck", 4),
+ GATE_MDP10_V(CLK_MDP1_MDP_RDMA1_MML, "mdp1_mdp_rdma1_mml", "mdp1_mdp_rdma1"),
+ GATE_MDP10(CLK_MDP1_MDP_RDMA2, "mdp1_mdp_rdma2", "ck2_mdp_ck", 5),
+ GATE_MDP10_V(CLK_MDP1_MDP_RDMA2_MML, "mdp1_mdp_rdma2_mml", "mdp1_mdp_rdma2"),
+ GATE_MDP10(CLK_MDP1_MDP_BIRSZ0, "mdp1_mdp_birsz0", "ck2_mdp_ck", 6),
+ GATE_MDP10_V(CLK_MDP1_MDP_BIRSZ0_MML, "mdp1_mdp_birsz0_mml", "mdp1_mdp_birsz0"),
+ GATE_MDP10(CLK_MDP1_MDP_HDR0, "mdp1_mdp_hdr0", "ck2_mdp_ck", 7),
+ GATE_MDP10_V(CLK_MDP1_MDP_HDR0_MML, "mdp1_mdp_hdr0_mml", "mdp1_mdp_hdr0"),
+ GATE_MDP10(CLK_MDP1_MDP_AAL0, "mdp1_mdp_aal0", "ck2_mdp_ck", 8),
+ GATE_MDP10_V(CLK_MDP1_MDP_AAL0_MML, "mdp1_mdp_aal0_mml", "mdp1_mdp_aal0"),
+ GATE_MDP10(CLK_MDP1_MDP_RSZ0, "mdp1_mdp_rsz0", "ck2_mdp_ck", 9),
+ GATE_MDP10_V(CLK_MDP1_MDP_RSZ0_MML, "mdp1_mdp_rsz0_mml", "mdp1_mdp_rsz0"),
+ GATE_MDP10(CLK_MDP1_MDP_RSZ2, "mdp1_mdp_rsz2", "ck2_mdp_ck", 10),
+ GATE_MDP10_V(CLK_MDP1_MDP_RSZ2_MML, "mdp1_mdp_rsz2_mml", "mdp1_mdp_rsz2"),
+ GATE_MDP10(CLK_MDP1_MDP_TDSHP0, "mdp1_mdp_tdshp0", "ck2_mdp_ck", 11),
+ GATE_MDP10_V(CLK_MDP1_MDP_TDSHP0_MML, "mdp1_mdp_tdshp0_mml", "mdp1_mdp_tdshp0"),
+ GATE_MDP10(CLK_MDP1_MDP_COLOR0, "mdp1_mdp_color0", "ck2_mdp_ck", 12),
+ GATE_MDP10_V(CLK_MDP1_MDP_COLOR0_MML, "mdp1_mdp_color0_mml", "mdp1_mdp_color0"),
+ GATE_MDP10(CLK_MDP1_MDP_WROT0, "mdp1_mdp_wrot0", "ck2_mdp_ck", 13),
+ GATE_MDP10_V(CLK_MDP1_MDP_WROT0_MML, "mdp1_mdp_wrot0_mml", "mdp1_mdp_wrot0"),
+ GATE_MDP10(CLK_MDP1_MDP_WROT1, "mdp1_mdp_wrot1", "ck2_mdp_ck", 14),
+ GATE_MDP10_V(CLK_MDP1_MDP_WROT1_MML, "mdp1_mdp_wrot1_mml", "mdp1_mdp_wrot1"),
+ GATE_MDP10(CLK_MDP1_MDP_WROT2, "mdp1_mdp_wrot2", "ck2_mdp_ck", 15),
+ GATE_MDP10_V(CLK_MDP1_MDP_WROT2_MML, "mdp1_mdp_wrot2_mml", "mdp1_mdp_wrot2"),
+ GATE_MDP10(CLK_MDP1_MDP_FAKE_ENG0, "mdp1_mdp_fake_eng0", "ck2_mdp_ck", 16),
+ GATE_MDP10_V(CLK_MDP1_MDP_FAKE_ENG0_MML, "mdp1_mdp_fake_eng0_mml", "mdp1_mdp_fake_eng0"),
+ GATE_MDP10(CLK_MDP1_APB_DB, "mdp1_apb_db", "ck2_mdp_ck", 17),
+ GATE_MDP10_V(CLK_MDP1_APB_DB_MML, "mdp1_apb_db_mml", "mdp1_apb_db"),
+ GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC0, "mdp1_mdp_dli_async0", "ck2_mdp_ck", 18),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLI_ASYNC0_MML, "mdp1_mdp_dli_async0_mml", "mdp1_mdp_dli_async0"),
+ GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC1, "mdp1_mdp_dli_async1", "ck2_mdp_ck", 19),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLI_ASYNC1_MML, "mdp1_mdp_dli_async1_mml", "mdp1_mdp_dli_async1"),
+ GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC0, "mdp1_mdp_dlo_async0", "ck2_mdp_ck", 20),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC0_MML, "mdp1_mdp_dlo_async0_mml", "mdp1_mdp_dlo_async0"),
+ GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC1, "mdp1_mdp_dlo_async1", "ck2_mdp_ck", 21),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC1_MML, "mdp1_mdp_dlo_async1_mml", "mdp1_mdp_dlo_async1"),
+ GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC2, "mdp1_mdp_dli_async2", "ck2_mdp_ck", 22),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLI_ASYNC2_MML, "mdp1_mdp_dli_async2_mml", "mdp1_mdp_dli_async2"),
+ GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC2, "mdp1_mdp_dlo_async2", "ck2_mdp_ck", 23),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC2_MML, "mdp1_mdp_dlo_async2_mml", "mdp1_mdp_dlo_async2"),
+ GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC3, "mdp1_mdp_dlo_async3", "ck2_mdp_ck", 24),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC3_MML, "mdp1_mdp_dlo_async3_mml", "mdp1_mdp_dlo_async3"),
+ GATE_MDP10(CLK_MDP1_IMG_DL_ASYNC0, "mdp1_img_dl_async0", "ck2_mdp_ck", 25),
+ GATE_MDP10_V(CLK_MDP1_IMG_DL_ASYNC0_MML, "mdp1_img_dl_async0_mml", "mdp1_img_dl_async0"),
+ GATE_MDP10(CLK_MDP1_MDP_RROT0, "mdp1_mdp_rrot0", "ck2_mdp_ck", 26),
+ GATE_MDP10_V(CLK_MDP1_MDP_RROT0_MML, "mdp1_mdp_rrot0_mml", "mdp1_mdp_rrot0"),
+ GATE_MDP10(CLK_MDP1_MDP_MERGE0, "mdp1_mdp_merge0", "ck2_mdp_ck", 27),
+ GATE_MDP10_V(CLK_MDP1_MDP_MERGE0_MML, "mdp1_mdp_merge0_mml", "mdp1_mdp_merge0"),
+ GATE_MDP10(CLK_MDP1_MDP_C3D0, "mdp1_mdp_c3d0", "ck2_mdp_ck", 28),
+ GATE_MDP10_V(CLK_MDP1_MDP_C3D0_MML, "mdp1_mdp_c3d0_mml", "mdp1_mdp_c3d0"),
+ GATE_MDP10(CLK_MDP1_MDP_FG0, "mdp1_mdp_fg0", "ck2_mdp_ck", 29),
+ GATE_MDP10_V(CLK_MDP1_MDP_FG0_MML, "mdp1_mdp_fg0_mml", "mdp1_mdp_fg0"),
+ GATE_MDP10(CLK_MDP1_MDP_CLA2, "mdp1_mdp_cla2", "ck2_mdp_ck", 30),
+ GATE_MDP10_V(CLK_MDP1_MDP_CLA2_MML, "mdp1_mdp_cla2_mml", "mdp1_mdp_cla2"),
+ GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC4, "mdp1_mdp_dlo_async4", "ck2_mdp_ck", 31),
+ GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC4_MML, "mdp1_mdp_dlo_async4_mml", "mdp1_mdp_dlo_async4"),
+ /* MDP11 */
+ GATE_MDP11(CLK_MDP1_VPP_RSZ0, "mdp1_vpp_rsz0", "ck2_mdp_ck", 0),
+ GATE_MDP11_V(CLK_MDP1_VPP_RSZ0_MML, "mdp1_vpp_rsz0_mml", "mdp1_vpp_rsz0"),
+ GATE_MDP11(CLK_MDP1_VPP_RSZ1, "mdp1_vpp_rsz1", "ck2_mdp_ck", 1),
+ GATE_MDP11_V(CLK_MDP1_VPP_RSZ1_MML, "mdp1_vpp_rsz1_mml", "mdp1_vpp_rsz1"),
+ GATE_MDP11(CLK_MDP1_MDP_DLO_ASYNC5, "mdp1_mdp_dlo_async5", "ck2_mdp_ck", 2),
+ GATE_MDP11_V(CLK_MDP1_MDP_DLO_ASYNC5_MML, "mdp1_mdp_dlo_async5_mml", "mdp1_mdp_dlo_async5"),
+ GATE_MDP11(CLK_MDP1_IMG0, "mdp1_img0", "ck2_mdp_ck", 3),
+ GATE_MDP11_V(CLK_MDP1_IMG0_MML, "mdp1_img0_mml", "mdp1_img0"),
+ GATE_MDP11(CLK_MDP1_F26M, "mdp1_f26m", "ck_f26m_ck", 27),
+ GATE_MDP11_V(CLK_MDP1_F26M_MML, "mdp1_f26m_mml", "mdp1_f26m"),
+ /* MDP12 */
+ GATE_MDP12(CLK_MDP1_IMG_DL_RELAY0, "mdp1_img_dl_relay0", "ck2_mdp_ck", 0),
+ GATE_MDP12_V(CLK_MDP1_IMG_DL_RELAY0_MML, "mdp1_img_dl_relay0_mml", "mdp1_img_dl_relay0"),
+ GATE_MDP12(CLK_MDP1_IMG_DL_RELAY1, "mdp1_img_dl_relay1", "ck2_mdp_ck", 8),
+ GATE_MDP12_V(CLK_MDP1_IMG_DL_RELAY1_MML, "mdp1_img_dl_relay1_mml", "mdp1_img_dl_relay1"),
+};
+
+static const struct mtk_clk_desc mdp1_mcd = {
+ .clks = mdp1_clks,
+ .num_clks = ARRAY_SIZE(mdp1_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct mtk_gate_regs mdp0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mdp1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs mdp2_cg_regs = {
+ .set_ofs = 0x124,
+ .clr_ofs = 0x128,
+ .sta_ofs = 0x120,
+};
+
+#define GATE_MDP0(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mdp0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MDP0_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_MDP1(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mdp1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MDP1_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_MDP2(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mdp2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MDP2_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate mdp_clks[] = {
+ /* MDP0 */
+ GATE_MDP0(CLK_MDP_MDP_MUTEX0, "mdp_mdp_mutex0", "ck2_mdp_ck", 0),
+ GATE_MDP0_V(CLK_MDP_MDP_MUTEX0_MML, "mdp_mdp_mutex0_mml", "mdp_mdp_mutex0"),
+ GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "ck2_mdp_ck", 1),
+ GATE_MDP0_V(CLK_MDP_SMI0_MML, "mdp_smi0_mml", "mdp_smi0"),
+ GATE_MDP0_V(CLK_MDP_SMI0_SMI, "mdp_smi0_smi", "mdp_smi0"),
+ GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "ck2_mdp_ck", 2),
+ GATE_MDP0_V(CLK_MDP_APB_BUS_MML, "mdp_apb_bus_mml", "mdp_apb_bus"),
+ GATE_MDP0(CLK_MDP_MDP_RDMA0, "mdp_mdp_rdma0", "ck2_mdp_ck", 3),
+ GATE_MDP0_V(CLK_MDP_MDP_RDMA0_MML, "mdp_mdp_rdma0_mml", "mdp_mdp_rdma0"),
+ GATE_MDP0(CLK_MDP_MDP_RDMA1, "mdp_mdp_rdma1", "ck2_mdp_ck", 4),
+ GATE_MDP0_V(CLK_MDP_MDP_RDMA1_MML, "mdp_mdp_rdma1_mml", "mdp_mdp_rdma1"),
+ GATE_MDP0(CLK_MDP_MDP_RDMA2, "mdp_mdp_rdma2", "ck2_mdp_ck", 5),
+ GATE_MDP0_V(CLK_MDP_MDP_RDMA2_MML, "mdp_mdp_rdma2_mml", "mdp_mdp_rdma2"),
+ GATE_MDP0(CLK_MDP_MDP_BIRSZ0, "mdp_mdp_birsz0", "ck2_mdp_ck", 6),
+ GATE_MDP0_V(CLK_MDP_MDP_BIRSZ0_MML, "mdp_mdp_birsz0_mml", "mdp_mdp_birsz0"),
+ GATE_MDP0(CLK_MDP_MDP_HDR0, "mdp_mdp_hdr0", "ck2_mdp_ck", 7),
+ GATE_MDP0_V(CLK_MDP_MDP_HDR0_MML, "mdp_mdp_hdr0_mml", "mdp_mdp_hdr0"),
+ GATE_MDP0(CLK_MDP_MDP_AAL0, "mdp_mdp_aal0", "ck2_mdp_ck", 8),
+ GATE_MDP0_V(CLK_MDP_MDP_AAL0_MML, "mdp_mdp_aal0_mml", "mdp_mdp_aal0"),
+ GATE_MDP0(CLK_MDP_MDP_RSZ0, "mdp_mdp_rsz0", "ck2_mdp_ck", 9),
+ GATE_MDP0_V(CLK_MDP_MDP_RSZ0_MML, "mdp_mdp_rsz0_mml", "mdp_mdp_rsz0"),
+ GATE_MDP0(CLK_MDP_MDP_RSZ2, "mdp_mdp_rsz2", "ck2_mdp_ck", 10),
+ GATE_MDP0_V(CLK_MDP_MDP_RSZ2_MML, "mdp_mdp_rsz2_mml", "mdp_mdp_rsz2"),
+ GATE_MDP0(CLK_MDP_MDP_TDSHP0, "mdp_mdp_tdshp0", "ck2_mdp_ck", 11),
+ GATE_MDP0_V(CLK_MDP_MDP_TDSHP0_MML, "mdp_mdp_tdshp0_mml", "mdp_mdp_tdshp0"),
+ GATE_MDP0(CLK_MDP_MDP_COLOR0, "mdp_mdp_color0", "ck2_mdp_ck", 12),
+ GATE_MDP0_V(CLK_MDP_MDP_COLOR0_MML, "mdp_mdp_color0_mml", "mdp_mdp_color0"),
+ GATE_MDP0(CLK_MDP_MDP_WROT0, "mdp_mdp_wrot0", "ck2_mdp_ck", 13),
+ GATE_MDP0_V(CLK_MDP_MDP_WROT0_MML, "mdp_mdp_wrot0_mml", "mdp_mdp_wrot0"),
+ GATE_MDP0(CLK_MDP_MDP_WROT1, "mdp_mdp_wrot1", "ck2_mdp_ck", 14),
+ GATE_MDP0_V(CLK_MDP_MDP_WROT1_MML, "mdp_mdp_wrot1_mml", "mdp_mdp_wrot1"),
+ GATE_MDP0(CLK_MDP_MDP_WROT2, "mdp_mdp_wrot2", "ck2_mdp_ck", 15),
+ GATE_MDP0_V(CLK_MDP_MDP_WROT2_MML, "mdp_mdp_wrot2_mml", "mdp_mdp_wrot2"),
+ GATE_MDP0(CLK_MDP_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "ck2_mdp_ck", 16),
+ GATE_MDP0_V(CLK_MDP_MDP_FAKE_ENG0_MML, "mdp_mdp_fake_eng0_mml", "mdp_mdp_fake_eng0"),
+ GATE_MDP0(CLK_MDP_APB_DB, "mdp_apb_db", "ck2_mdp_ck", 17),
+ GATE_MDP0_V(CLK_MDP_APB_DB_MML, "mdp_apb_db_mml", "mdp_apb_db"),
+ GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC0, "mdp_mdp_dli_async0", "ck2_mdp_ck", 18),
+ GATE_MDP0_V(CLK_MDP_MDP_DLI_ASYNC0_MML, "mdp_mdp_dli_async0_mml", "mdp_mdp_dli_async0"),
+ GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC1, "mdp_mdp_dli_async1", "ck2_mdp_ck", 19),
+ GATE_MDP0_V(CLK_MDP_MDP_DLI_ASYNC1_MML, "mdp_mdp_dli_async1_mml", "mdp_mdp_dli_async1"),
+ GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC0, "mdp_mdp_dlo_async0", "ck2_mdp_ck", 20),
+ GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC0_MML, "mdp_mdp_dlo_async0_mml", "mdp_mdp_dlo_async0"),
+ GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC1, "mdp_mdp_dlo_async1", "ck2_mdp_ck", 21),
+ GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC1_MML, "mdp_mdp_dlo_async1_mml", "mdp_mdp_dlo_async1"),
+ GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC2, "mdp_mdp_dli_async2", "ck2_mdp_ck", 22),
+ GATE_MDP0_V(CLK_MDP_MDP_DLI_ASYNC2_MML, "mdp_mdp_dli_async2_mml", "mdp_mdp_dli_async2"),
+ GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC2, "mdp_mdp_dlo_async2", "ck2_mdp_ck", 23),
+ GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC2_MML, "mdp_mdp_dlo_async2_mml", "mdp_mdp_dlo_async2"),
+ GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC3, "mdp_mdp_dlo_async3", "ck2_mdp_ck", 24),
+ GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC3_MML, "mdp_mdp_dlo_async3_mml", "mdp_mdp_dlo_async3"),
+ GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "ck2_mdp_ck", 25),
+ GATE_MDP0_V(CLK_MDP_IMG_DL_ASYNC0_MML, "mdp_img_dl_async0_mml", "mdp_img_dl_async0"),
+ GATE_MDP0(CLK_MDP_MDP_RROT0, "mdp_mdp_rrot0", "ck2_mdp_ck", 26),
+ GATE_MDP0_V(CLK_MDP_MDP_RROT0_MML, "mdp_mdp_rrot0_mml", "mdp_mdp_rrot0"),
+ GATE_MDP0(CLK_MDP_MDP_MERGE0, "mdp_mdp_merge0", "ck2_mdp_ck", 27),
+ GATE_MDP0_V(CLK_MDP_MDP_MERGE0_MML, "mdp_mdp_merge0_mml", "mdp_mdp_merge0"),
+ GATE_MDP0(CLK_MDP_MDP_C3D0, "mdp_mdp_c3d0", "ck2_mdp_ck", 28),
+ GATE_MDP0_V(CLK_MDP_MDP_C3D0_MML, "mdp_mdp_c3d0_mml", "mdp_mdp_c3d0"),
+ GATE_MDP0(CLK_MDP_MDP_FG0, "mdp_mdp_fg0", "ck2_mdp_ck", 29),
+ GATE_MDP0_V(CLK_MDP_MDP_FG0_MML, "mdp_mdp_fg0_mml", "mdp_mdp_fg0"),
+ GATE_MDP0(CLK_MDP_MDP_CLA2, "mdp_mdp_cla2", "ck2_mdp_ck", 30),
+ GATE_MDP0_V(CLK_MDP_MDP_CLA2_MML, "mdp_mdp_cla2_mml", "mdp_mdp_cla2"),
+ GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC4, "mdp_mdp_dlo_async4", "ck2_mdp_ck", 31),
+ GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC4_MML, "mdp_mdp_dlo_async4_mml", "mdp_mdp_dlo_async4"),
+ /* MDP1 */
+ GATE_MDP1(CLK_MDP_VPP_RSZ0, "mdp_vpp_rsz0", "ck2_mdp_ck", 0),
+ GATE_MDP1_V(CLK_MDP_VPP_RSZ0_MML, "mdp_vpp_rsz0_mml", "mdp_vpp_rsz0"),
+ GATE_MDP1(CLK_MDP_VPP_RSZ1, "mdp_vpp_rsz1", "ck2_mdp_ck", 1),
+ GATE_MDP1_V(CLK_MDP_VPP_RSZ1_MML, "mdp_vpp_rsz1_mml", "mdp_vpp_rsz1"),
+ GATE_MDP1(CLK_MDP_MDP_DLO_ASYNC5, "mdp_mdp_dlo_async5", "ck2_mdp_ck", 2),
+ GATE_MDP1_V(CLK_MDP_MDP_DLO_ASYNC5_MML, "mdp_mdp_dlo_async5_mml", "mdp_mdp_dlo_async5"),
+ GATE_MDP1(CLK_MDP_IMG0, "mdp_img0", "ck2_mdp_ck", 3),
+ GATE_MDP1_V(CLK_MDP_IMG0_MML, "mdp_img0_mml", "mdp_img0"),
+ GATE_MDP1(CLK_MDP_F26M, "mdp_f26m", "ck_f26m_ck", 27),
+ GATE_MDP1_V(CLK_MDP_F26M_MML, "mdp_f26m_mml", "mdp_f26m"),
+ /* MDP2 */
+ GATE_MDP2(CLK_MDP_IMG_DL_RELAY0, "mdp_img_dl_relay0", "ck2_mdp_ck", 0),
+ GATE_MDP2_V(CLK_MDP_IMG_DL_RELAY0_MML, "mdp_img_dl_relay0_mml", "mdp_img_dl_relay0"),
+ GATE_MDP2(CLK_MDP_IMG_DL_RELAY1, "mdp_img_dl_relay1", "ck2_mdp_ck", 8),
+ GATE_MDP2_V(CLK_MDP_IMG_DL_RELAY1_MML, "mdp_img_dl_relay1_mml", "mdp_img_dl_relay1"),
+};
+
+static const struct mtk_clk_desc mdp_mcd = {
+ .clks = mdp_clks,
+ .num_clks = ARRAY_SIZE(mdp_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct of_device_id of_match_clk_mt8196_mdpsys[] = {
+ { .compatible = "mediatek,mt8196-mdpsys1", .data = &mdp1_mcd, },
+ { .compatible = "mediatek,mt8196-mdpsys", .data = &mdp_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_mdpsys_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-mdpsys",
+ .of_match_table = of_match_clk_mt8196_mdpsys,
+ },
+};
+
+module_platform_driver(clk_mt8196_mdpsys_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 17/26] clk: mediatek: Add MT8196 mfg clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (15 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 16/26] clk: mediatek: Add MT8196 mdpsys " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 18/26] clk: mediatek: Add MT8196 disp0 " Guangjie Song
` (8 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 mfg clock controller which provides pll control for GPU.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-mfg.c | 143 ++++++++++++++++++++++++++
3 files changed, 151 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-mfg.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 8763cc1480a3..042de08e0bb1 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1038,6 +1038,13 @@ config COMMON_CLK_MT8196_MDPSYS
help
This driver supports MediaTek MT8196 mdpsys clocks.
+config COMMON_CLK_MT8196_MFGCFG
+ tristate "Clock driver for MediaTek MT8196 mfgcfg"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 mfgcfg clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index dccc6d84941c..ad2de9ee6d15 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -157,6 +157,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) += clk-mt8196-adsp.o
obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
+obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/clk-mt8196-mfg.c
new file mode 100644
index 000000000000..7e87530ef68d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-mfg.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+#define MFGPLL_CON0 0x008
+#define MFGPLL_CON1 0x00c
+#define MFGPLL_CON2 0x010
+#define MFGPLL_CON3 0x014
+#define MFGPLL_SC0_CON0 0x008
+#define MFGPLL_SC0_CON1 0x00c
+#define MFGPLL_SC0_CON2 0x010
+#define MFGPLL_SC0_CON3 0x014
+#define MFGPLL_SC1_CON0 0x008
+#define MFGPLL_SC1_CON1 0x00c
+#define MFGPLL_SC1_CON2 0x010
+#define MFGPLL_SC1_CON3 0x014
+
+#define MT8196_PLL_FMAX (3800UL * MHZ)
+#define MT8196_PLL_FMIN (1500UL * MHZ)
+#define MT8196_INTEGER_BITS 8
+
+#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
+ _flags, _rst_bar_mask, \
+ _pd_reg, _pd_shift, _tuner_reg, \
+ _tuner_en_reg, _tuner_en_bit, \
+ _pcw_reg, _pcw_shift, _pcwbits) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .en_reg = _en_reg, \
+ .en_mask = _en_mask, \
+ .pll_en_bit = _pll_en_bit, \
+ .flags = (_flags) | CLK_FENC_ENABLE, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT8196_PLL_FMAX, \
+ .fmin = MT8196_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8196_INTEGER_BITS, \
+ }
+
+static const struct mtk_pll_data mfg_ao_plls[] = {
+ PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0,
+ MFGPLL_CON0, 0, 0, 0, BIT(0),
+ MFGPLL_CON1, 24, 0, 0, 0,
+ MFGPLL_CON1, 0, 22),
+};
+
+static const struct mtk_pll_data mfgsc0_ao_plls[] = {
+ PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
+ MFGPLL_SC0_CON0, 0, 0, 0, BIT(0),
+ MFGPLL_SC0_CON1, 24, 0, 0, 0,
+ MFGPLL_SC0_CON1, 0, 22),
+};
+
+static const struct mtk_pll_data mfgsc1_ao_plls[] = {
+ PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
+ MFGPLL_SC1_CON0, 0, 0, 0, BIT(0),
+ MFGPLL_SC1_CON1, 24, 0, 0, 0,
+ MFGPLL_SC1_CON1, 0, 22),
+};
+
+static const struct of_device_id of_match_clk_mt8196_mfg[] = {
+ { .compatible = "mediatek,mt8196-mfgpll_pll_ctrl", .data = &mfg_ao_plls, },
+ { .compatible = "mediatek,mt8196-mfgpll_sc0_pll_ctrl", .data = &mfgsc0_ao_plls, },
+ { .compatible = "mediatek,mt8196-mfgpll_sc1_pll_ctrl", .data = &mfgsc1_ao_plls, },
+ { /* sentinel */ }
+};
+
+static int clk_mt8196_mfg_probe(struct platform_device *pdev)
+{
+ const struct mtk_pll_data *plls;
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int num_plls = 1;
+ int r;
+
+ plls = of_device_get_match_data(&pdev->dev);
+ if (!plls)
+ return -EINVAL;
+
+ clk_data = mtk_alloc_clk_data(num_plls);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
+ if (r) {
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+ mtk_clk_unregister_plls(plls, num_plls, clk_data);
+ mtk_free_clk_data(clk_data);
+ return r;
+ }
+
+ return 0;
+}
+
+static void clk_mt8196_mfg_remove(struct platform_device *pdev)
+{
+ const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+ int num_plls = 1;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_plls(plls, num_plls, clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static struct platform_driver clk_mt8196_mfg_drv = {
+ .probe = clk_mt8196_mfg_probe,
+ .remove = clk_mt8196_mfg_remove,
+ .driver = {
+ .name = "clk-mt8196-mfg",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_clk_mt8196_mfg,
+ },
+};
+
+module_platform_driver(clk_mt8196_mfg_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 18/26] clk: mediatek: Add MT8196 disp0 clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (16 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 17/26] clk: mediatek: Add MT8196 mfg " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 19/26] clk: mediatek: Add MT8196 disp1 " Guangjie Song
` (7 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 disp0 clock controller which provides clock gate control in
display system. This is integrated with mtk-mmsys driver which will
populate device by platform_device_register_data to start disp0 clock
driver.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-disp0.c | 247 ++++++++++++++++++++++++
3 files changed, 255 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-disp0.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 042de08e0bb1..dcb660d45bcf 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1045,6 +1045,13 @@ config COMMON_CLK_MT8196_MFGCFG
help
This driver supports MediaTek MT8196 mfgcfg clocks.
+config COMMON_CLK_MT8196_MMSYS
+ tristate "Clock driver for MediaTek MT8196 mmsys"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 mmsys clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index ad2de9ee6d15..881061f1e259 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -158,6 +158,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
+obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-disp0.c b/drivers/clk/mediatek/clk-mt8196-disp0.c
new file mode 100644
index 000000000000..07237a51358f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-disp0.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm0_vote_regs = {
+ .set_ofs = 0x0020,
+ .clr_ofs = 0x0024,
+ .sta_ofs = 0x2c10,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs mm1_vote_regs = {
+ .set_ofs = 0x0028,
+ .clr_ofs = 0x002c,
+ .sta_ofs = 0x2c14,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MM0_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_MM0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &mm0_cg_regs, \
+ .vote_regs = &mm0_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE \
+ }
+
+#define GATE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MM1_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_MM1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &mm1_cg_regs, \
+ .vote_regs = &mm1_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+static const struct mtk_gate mm_clks[] = {
+ /* MM0 */
+ GATE_VOTE_MM0(CLK_MM_CONFIG, "mm_config", "ck2_disp_ck", 0),
+ GATE_MM0_V(CLK_MM_CONFIG_DISP, "mm_config_disp", "mm_config"),
+ GATE_VOTE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "ck2_disp_ck", 1),
+ GATE_MM0_V(CLK_MM_DISP_MUTEX0_DISP, "mm_disp_mutex0_disp", "mm_disp_mutex0"),
+ GATE_VOTE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "ck2_disp_ck", 2),
+ GATE_MM0_V(CLK_MM_DISP_AAL0_PQ, "mm_disp_aal0_pq", "mm_disp_aal0"),
+ GATE_VOTE_MM0(CLK_MM_DISP_AAL1, "mm_disp_aal1", "ck2_disp_ck", 3),
+ GATE_MM0_V(CLK_MM_DISP_AAL1_PQ, "mm_disp_aal1_pq", "mm_disp_aal1"),
+ GATE_MM0(CLK_MM_DISP_C3D0, "mm_disp_c3d0", "ck2_disp_ck", 4),
+ GATE_MM0_V(CLK_MM_DISP_C3D0_PQ, "mm_disp_c3d0_pq", "mm_disp_c3d0"),
+ GATE_MM0(CLK_MM_DISP_C3D1, "mm_disp_c3d1", "ck2_disp_ck", 5),
+ GATE_MM0_V(CLK_MM_DISP_C3D1_PQ, "mm_disp_c3d1_pq", "mm_disp_c3d1"),
+ GATE_MM0(CLK_MM_DISP_C3D2, "mm_disp_c3d2", "ck2_disp_ck", 6),
+ GATE_MM0_V(CLK_MM_DISP_C3D2_PQ, "mm_disp_c3d2_pq", "mm_disp_c3d2"),
+ GATE_MM0(CLK_MM_DISP_C3D3, "mm_disp_c3d3", "ck2_disp_ck", 7),
+ GATE_MM0_V(CLK_MM_DISP_C3D3_PQ, "mm_disp_c3d3_pq", "mm_disp_c3d3"),
+ GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "ck2_disp_ck", 8),
+ GATE_MM0_V(CLK_MM_DISP_CCORR0_PQ, "mm_disp_ccorr0_pq", "mm_disp_ccorr0"),
+ GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "ck2_disp_ck", 9),
+ GATE_MM0_V(CLK_MM_DISP_CCORR1_PQ, "mm_disp_ccorr1_pq", "mm_disp_ccorr1"),
+ GATE_MM0(CLK_MM_DISP_CCORR2, "mm_disp_ccorr2", "ck2_disp_ck", 10),
+ GATE_MM0_V(CLK_MM_DISP_CCORR2_PQ, "mm_disp_ccorr2_pq", "mm_disp_ccorr2"),
+ GATE_MM0(CLK_MM_DISP_CCORR3, "mm_disp_ccorr3", "ck2_disp_ck", 11),
+ GATE_MM0_V(CLK_MM_DISP_CCORR3_PQ, "mm_disp_ccorr3_pq", "mm_disp_ccorr3"),
+ GATE_MM0(CLK_MM_DISP_CHIST0, "mm_disp_chist0", "ck2_disp_ck", 12),
+ GATE_MM0_V(CLK_MM_DISP_CHIST0_PQ, "mm_disp_chist0_pq", "mm_disp_chist0"),
+ GATE_MM0(CLK_MM_DISP_CHIST1, "mm_disp_chist1", "ck2_disp_ck", 13),
+ GATE_MM0_V(CLK_MM_DISP_CHIST1_PQ, "mm_disp_chist1_pq", "mm_disp_chist1"),
+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "ck2_disp_ck", 14),
+ GATE_MM0_V(CLK_MM_DISP_COLOR0_PQ, "mm_disp_color0_pq", "mm_disp_color0"),
+ GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "ck2_disp_ck", 15),
+ GATE_MM0_V(CLK_MM_DISP_COLOR1_PQ, "mm_disp_color1_pq", "mm_disp_color1"),
+ GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "ck2_disp_ck", 16),
+ GATE_MM0_V(CLK_MM_DISP_DITHER0_PQ, "mm_disp_dither0_pq", "mm_disp_dither0"),
+ GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "ck2_disp_ck", 17),
+ GATE_MM0_V(CLK_MM_DISP_DITHER1_PQ, "mm_disp_dither1_pq", "mm_disp_dither1"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC0, "mm_disp_dli_async0", "ck2_disp_ck", 18),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC0_DISP, "mm_disp_dli_async0_disp", "mm_disp_dli_async0"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC1, "mm_disp_dli_async1", "ck2_disp_ck", 19),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC1_DISP, "mm_disp_dli_async1_disp", "mm_disp_dli_async1"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC2, "mm_disp_dli_async2", "ck2_disp_ck", 20),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC2_DISP, "mm_disp_dli_async2_disp", "mm_disp_dli_async2"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC3, "mm_disp_dli_async3", "ck2_disp_ck", 21),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC3_DISP, "mm_disp_dli_async3_disp", "mm_disp_dli_async3"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC4, "mm_disp_dli_async4", "ck2_disp_ck", 22),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC4_DISP, "mm_disp_dli_async4_disp", "mm_disp_dli_async4"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC5, "mm_disp_dli_async5", "ck2_disp_ck", 23),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC5_DISP, "mm_disp_dli_async5_disp", "mm_disp_dli_async5"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC6, "mm_disp_dli_async6", "ck2_disp_ck", 24),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC6_DISP, "mm_disp_dli_async6_disp", "mm_disp_dli_async6"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC7, "mm_disp_dli_async7", "ck2_disp_ck", 25),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC7_DISP, "mm_disp_dli_async7_disp", "mm_disp_dli_async7"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC8, "mm_disp_dli_async8", "ck2_disp_ck", 26),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC8_DISP, "mm_disp_dli_async8_disp", "mm_disp_dli_async8"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC9, "mm_disp_dli_async9", "ck2_disp_ck", 27),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC9_DISP, "mm_disp_dli_async9_disp", "mm_disp_dli_async9"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC10, "mm_disp_dli_async10", "ck2_disp_ck", 28),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC10_DISP, "mm_disp_dli_async10_disp", "mm_disp_dli_async10"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC11, "mm_disp_dli_async11", "ck2_disp_ck", 29),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC11_DISP, "mm_disp_dli_async11_disp", "mm_disp_dli_async11"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC12, "mm_disp_dli_async12", "ck2_disp_ck", 30),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC12_DISP, "mm_disp_dli_async12_disp", "mm_disp_dli_async12"),
+ GATE_VOTE_MM0(CLK_MM_DISP_DLI_ASYNC13, "mm_disp_dli_async13", "ck2_disp_ck", 31),
+ GATE_MM0_V(CLK_MM_DISP_DLI_ASYNC13_DISP, "mm_disp_dli_async13_disp", "mm_disp_dli_async13"),
+ /* MM1 */
+ GATE_VOTE_MM1(CLK_MM_DISP_DLI_ASYNC14, "mm_disp_dli_async14", "ck2_disp_ck", 0),
+ GATE_MM1_V(CLK_MM_DISP_DLI_ASYNC14_DISP, "mm_disp_dli_async14_disp", "mm_disp_dli_async14"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLI_ASYNC15, "mm_disp_dli_async15", "ck2_disp_ck", 1),
+ GATE_MM1_V(CLK_MM_DISP_DLI_ASYNC15_DISP, "mm_disp_dli_async15_disp", "mm_disp_dli_async15"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC0, "mm_disp_dlo_async0", "ck2_disp_ck", 2),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC0_DISP, "mm_disp_dlo_async0_disp", "mm_disp_dlo_async0"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC1, "mm_disp_dlo_async1", "ck2_disp_ck", 3),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC1_DISP, "mm_disp_dlo_async1_disp", "mm_disp_dlo_async1"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC2, "mm_disp_dlo_async2", "ck2_disp_ck", 4),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC2_DISP, "mm_disp_dlo_async2_disp", "mm_disp_dlo_async2"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC3, "mm_disp_dlo_async3", "ck2_disp_ck", 5),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC3_DISP, "mm_disp_dlo_async3_disp", "mm_disp_dlo_async3"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC4, "mm_disp_dlo_async4", "ck2_disp_ck", 6),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC4_DISP, "mm_disp_dlo_async4_disp", "mm_disp_dlo_async4"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC5, "mm_disp_dlo_async5", "ck2_disp_ck", 7),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC5_DISP, "mm_disp_dlo_async5_disp", "mm_disp_dlo_async5"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC6, "mm_disp_dlo_async6", "ck2_disp_ck", 8),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC6_DISP, "mm_disp_dlo_async6_disp", "mm_disp_dlo_async6"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC7, "mm_disp_dlo_async7", "ck2_disp_ck", 9),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC7_DISP, "mm_disp_dlo_async7_disp", "mm_disp_dlo_async7"),
+ GATE_VOTE_MM1(CLK_MM_DISP_DLO_ASYNC8, "mm_disp_dlo_async8", "ck2_disp_ck", 10),
+ GATE_MM1_V(CLK_MM_DISP_DLO_ASYNC8_DISP, "mm_disp_dlo_async8_disp", "mm_disp_dlo_async8"),
+ GATE_MM1(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "ck2_disp_ck", 11),
+ GATE_MM1_V(CLK_MM_DISP_GAMMA0_PQ, "mm_disp_gamma0_pq", "mm_disp_gamma0"),
+ GATE_MM1(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "ck2_disp_ck", 12),
+ GATE_MM1_V(CLK_MM_DISP_GAMMA1_PQ, "mm_disp_gamma1_pq", "mm_disp_gamma1"),
+ GATE_MM1(CLK_MM_MDP_AAL0, "mm_mdp_aal0", "ck2_disp_ck", 13),
+ GATE_MM1_V(CLK_MM_MDP_AAL0_PQ, "mm_mdp_aal0_pq", "mm_mdp_aal0"),
+ GATE_MM1(CLK_MM_MDP_AAL1, "mm_mdp_aal1", "ck2_disp_ck", 14),
+ GATE_MM1_V(CLK_MM_MDP_AAL1_PQ, "mm_mdp_aal1_pq", "mm_mdp_aal1"),
+ GATE_VOTE_MM1(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "ck2_disp_ck", 15),
+ GATE_MM1_V(CLK_MM_MDP_RDMA0_DISP, "mm_mdp_rdma0_disp", "mm_mdp_rdma0"),
+ GATE_VOTE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "ck2_disp_ck", 16),
+ GATE_MM1_V(CLK_MM_DISP_POSTMASK0_DISP, "mm_disp_postmask0_disp", "mm_disp_postmask0"),
+ GATE_VOTE_MM1(CLK_MM_DISP_POSTMASK1, "mm_disp_postmask1", "ck2_disp_ck", 17),
+ GATE_MM1_V(CLK_MM_DISP_POSTMASK1_DISP, "mm_disp_postmask1_disp", "mm_disp_postmask1"),
+ GATE_VOTE_MM1(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "ck2_disp_ck", 18),
+ GATE_MM1_V(CLK_MM_MDP_RSZ0_DISP, "mm_mdp_rsz0_disp", "mm_mdp_rsz0"),
+ GATE_VOTE_MM1(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "ck2_disp_ck", 19),
+ GATE_MM1_V(CLK_MM_MDP_RSZ1_DISP, "mm_mdp_rsz1_disp", "mm_mdp_rsz1"),
+ GATE_VOTE_MM1(CLK_MM_DISP_SPR0, "mm_disp_spr0", "ck2_disp_ck", 20),
+ GATE_MM1_V(CLK_MM_DISP_SPR0_DISP, "mm_disp_spr0_disp", "mm_disp_spr0"),
+ GATE_MM1(CLK_MM_DISP_TDSHP0, "mm_disp_tdshp0", "ck2_disp_ck", 21),
+ GATE_MM1_V(CLK_MM_DISP_TDSHP0_PQ, "mm_disp_tdshp0_pq", "mm_disp_tdshp0"),
+ GATE_MM1(CLK_MM_DISP_TDSHP1, "mm_disp_tdshp1", "ck2_disp_ck", 22),
+ GATE_MM1_V(CLK_MM_DISP_TDSHP1_PQ, "mm_disp_tdshp1_pq", "mm_disp_tdshp1"),
+ GATE_VOTE_MM1(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "ck2_disp_ck", 23),
+ GATE_MM1_V(CLK_MM_DISP_WDMA0_DISP, "mm_disp_wdma0_disp", "mm_disp_wdma0"),
+ GATE_VOTE_MM1(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "ck2_disp_ck", 24),
+ GATE_MM1_V(CLK_MM_DISP_Y2R0_DISP, "mm_disp_y2r0_disp", "mm_disp_y2r0"),
+ GATE_VOTE_MM1(CLK_MM_SMI_SUB_COMM0, "mm_ssc", "ck2_disp_ck", 25),
+ GATE_MM1_V(CLK_MM_SMI_SUB_COMM0_SMI, "mm_ssc_smi", "mm_ssc"),
+ GATE_VOTE_MM1(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "ck2_disp_ck", 26),
+ GATE_MM1_V(CLK_MM_DISP_FAKE_ENG0_DISP, "mm_disp_fake_eng0_disp", "mm_disp_fake_eng0"),
+};
+
+static const struct mtk_clk_desc mm_mcd = {
+ .clks = mm_clks,
+ .num_clks = ARRAY_SIZE(mm_clks),
+};
+
+static const struct platform_device_id clk_mt8196_disp0_id_table[] = {
+ { .name = "clk-mt8196-disp0", .driver_data = (kernel_ulong_t)&mm_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, clk_mt8196_disp0_id_table);
+
+static struct platform_driver clk_mt8196_disp0_drv = {
+ .probe = mtk_clk_pdev_probe,
+ .remove = mtk_clk_pdev_remove,
+ .driver = {
+ .name = "clk-mt8196-disp0",
+ },
+ .id_table = clk_mt8196_disp0_id_table,
+};
+
+module_platform_driver(clk_mt8196_disp0_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 19/26] clk: mediatek: Add MT8196 disp1 clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (17 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 18/26] clk: mediatek: Add MT8196 disp0 " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 20/26] clk: mediatek: Add MT8196 disp-ao " Guangjie Song
` (6 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 disp1 clock controller which provides clock gate control in
display system. This is integrated with mtk-mmsys driver which will
populate device by platform_device_register_data to start disp1 clock
driver.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8196-disp1.c | 260 ++++++++++++++++++++++++
2 files changed, 261 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-disp1.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 881061f1e259..7eb4af39029c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -158,7 +158,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
-obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o
+obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-disp1.c b/drivers/clk/mediatek/clk-mt8196-disp1.c
new file mode 100644
index 000000000000..5acc589812be
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-disp1.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs mm10_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm10_vote_regs = {
+ .set_ofs = 0x0010,
+ .clr_ofs = 0x0014,
+ .sta_ofs = 0x2c08,
+};
+
+static const struct mtk_gate_regs mm11_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs mm11_vote_regs = {
+ .set_ofs = 0x0018,
+ .clr_ofs = 0x001c,
+ .sta_ofs = 0x2c0c,
+};
+
+#define GATE_MM10(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm10_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MM10_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_MM10(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &mm10_cg_regs, \
+ .vote_regs = &mm10_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_MM11(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm11_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MM11_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_MM11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &mm11_cg_regs, \
+ .vote_regs = &mm11_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+static const struct mtk_gate mm1_clks[] = {
+ /* MM10 */
+ GATE_VOTE_MM10(CLK_MM1_DISPSYS1_CONFIG, "mm1_dispsys1_config", "ck2_disp_ck", 0),
+ GATE_MM10_V(CLK_MM1_DISPSYS1_CONFIG_DISP, "mm1_dispsys1_config_disp",
+ "mm1_dispsys1_config"),
+ GATE_VOTE_MM10(CLK_MM1_DISPSYS1_S_CONFIG, "mm1_dispsys1_s_config", "ck2_disp_ck", 1),
+ GATE_MM10_V(CLK_MM1_DISPSYS1_S_CONFIG_DISP, "mm1_dispsys1_s_config_disp",
+ "mm1_dispsys1_s_config"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_MUTEX0, "mm1_disp_mutex0", "ck2_disp_ck", 2),
+ GATE_MM10_V(CLK_MM1_DISP_MUTEX0_DISP, "mm1_disp_mutex0_disp", "mm1_disp_mutex0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC20, "mm1_disp_dli_async20", "ck2_disp_ck", 3),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC20_DISP, "mm1_disp_dli_async20_disp",
+ "mm1_disp_dli_async20"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC21, "mm1_disp_dli_async21", "ck2_disp_ck", 4),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC21_DISP, "mm1_disp_dli_async21_disp",
+ "mm1_disp_dli_async21"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC22, "mm1_disp_dli_async22", "ck2_disp_ck", 5),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC22_DISP, "mm1_disp_dli_async22_disp",
+ "mm1_disp_dli_async22"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC23, "mm1_disp_dli_async23", "ck2_disp_ck", 6),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC23_DISP, "mm1_disp_dli_async23_disp",
+ "mm1_disp_dli_async23"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC24, "mm1_disp_dli_async24", "ck2_disp_ck", 7),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC24_DISP, "mm1_disp_dli_async24_disp",
+ "mm1_disp_dli_async24"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC25, "mm1_disp_dli_async25", "ck2_disp_ck", 8),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC25_DISP, "mm1_disp_dli_async25_disp",
+ "mm1_disp_dli_async25"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC26, "mm1_disp_dli_async26", "ck2_disp_ck", 9),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC26_DISP, "mm1_disp_dli_async26_disp",
+ "mm1_disp_dli_async26"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC27, "mm1_disp_dli_async27", "ck2_disp_ck", 10),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC27_DISP, "mm1_disp_dli_async27_disp",
+ "mm1_disp_dli_async27"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DLI_ASYNC28, "mm1_disp_dli_async28", "ck2_disp_ck", 11),
+ GATE_MM10_V(CLK_MM1_DISP_DLI_ASYNC28_DISP, "mm1_disp_dli_async28_disp",
+ "mm1_disp_dli_async28"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_RELAY0, "mm1_disp_relay0", "ck2_disp_ck", 12),
+ GATE_MM10_V(CLK_MM1_DISP_RELAY0_DISP, "mm1_disp_relay0_disp", "mm1_disp_relay0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_RELAY1, "mm1_disp_relay1", "ck2_disp_ck", 13),
+ GATE_MM10_V(CLK_MM1_DISP_RELAY1_DISP, "mm1_disp_relay1_disp", "mm1_disp_relay1"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_RELAY2, "mm1_disp_relay2", "ck2_disp_ck", 14),
+ GATE_MM10_V(CLK_MM1_DISP_RELAY2_DISP, "mm1_disp_relay2_disp", "mm1_disp_relay2"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_RELAY3, "mm1_disp_relay3", "ck2_disp_ck", 15),
+ GATE_MM10_V(CLK_MM1_DISP_RELAY3_DISP, "mm1_disp_relay3_disp", "mm1_disp_relay3"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DP_INTF0, "mm1_DP_CLK", "ck2_disp_ck", 16),
+ GATE_MM10_V(CLK_MM1_DISP_DP_INTF0_DISP, "mm1_dp_clk_disp", "mm1_DP_CLK"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DP_INTF1, "mm1_disp_dp_intf1", "ck2_disp_ck", 17),
+ GATE_MM10_V(CLK_MM1_DISP_DP_INTF1_DISP, "mm1_disp_dp_intf1_disp", "mm1_disp_dp_intf1"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DSC_WRAP0, "mm1_disp_dsc_wrap0", "ck2_disp_ck", 18),
+ GATE_MM10_V(CLK_MM1_DISP_DSC_WRAP0_DISP, "mm1_disp_dsc_wrap0_disp", "mm1_disp_dsc_wrap0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DSC_WRAP1, "mm1_disp_dsc_wrap1", "ck2_disp_ck", 19),
+ GATE_MM10_V(CLK_MM1_DISP_DSC_WRAP1_DISP, "mm1_disp_dsc_wrap1_disp", "mm1_disp_dsc_wrap1"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DSC_WRAP2, "mm1_disp_dsc_wrap2", "ck2_disp_ck", 20),
+ GATE_MM10_V(CLK_MM1_DISP_DSC_WRAP2_DISP, "mm1_disp_dsc_wrap2_disp", "mm1_disp_dsc_wrap2"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DSC_WRAP3, "mm1_disp_dsc_wrap3", "ck2_disp_ck", 21),
+ GATE_MM10_V(CLK_MM1_DISP_DSC_WRAP3_DISP, "mm1_disp_dsc_wrap3_disp", "mm1_disp_dsc_wrap3"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DSI0, "mm1_CLK0", "ck2_disp_ck", 22),
+ GATE_MM10_V(CLK_MM1_DISP_DSI0_DISP, "mm1_clk0_disp", "mm1_CLK0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DSI1, "mm1_CLK1", "ck2_disp_ck", 23),
+ GATE_MM10_V(CLK_MM1_DISP_DSI1_DISP, "mm1_clk1_disp", "mm1_CLK1"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DSI2, "mm1_CLK2", "ck2_disp_ck", 24),
+ GATE_MM10_V(CLK_MM1_DISP_DSI2_DISP, "mm1_clk2_disp", "mm1_CLK2"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_DVO0, "mm1_disp_dvo0", "ck2_disp_ck", 25),
+ GATE_MM10_V(CLK_MM1_DISP_DVO0_DISP, "mm1_disp_dvo0_disp", "mm1_disp_dvo0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_GDMA0, "mm1_disp_gdma0", "ck2_disp_ck", 26),
+ GATE_MM10_V(CLK_MM1_DISP_GDMA0_DISP, "mm1_disp_gdma0_disp", "mm1_disp_gdma0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_MERGE0, "mm1_disp_merge0", "ck2_disp_ck", 27),
+ GATE_MM10_V(CLK_MM1_DISP_MERGE0_DISP, "mm1_disp_merge0_disp", "mm1_disp_merge0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_MERGE1, "mm1_disp_merge1", "ck2_disp_ck", 28),
+ GATE_MM10_V(CLK_MM1_DISP_MERGE1_DISP, "mm1_disp_merge1_disp", "mm1_disp_merge1"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_MERGE2, "mm1_disp_merge2", "ck2_disp_ck", 29),
+ GATE_MM10_V(CLK_MM1_DISP_MERGE2_DISP, "mm1_disp_merge2_disp", "mm1_disp_merge2"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_ODDMR0, "mm1_disp_oddmr0", "ck2_disp_ck", 30),
+ GATE_MM10_V(CLK_MM1_DISP_ODDMR0_PQ, "mm1_disp_oddmr0_pq", "mm1_disp_oddmr0"),
+ GATE_VOTE_MM10(CLK_MM1_DISP_POSTALIGN0, "mm1_disp_postalign0", "ck2_disp_ck", 31),
+ GATE_MM10_V(CLK_MM1_DISP_POSTALIGN0_PQ, "mm1_disp_postalign0_pq", "mm1_disp_postalign0"),
+ /* MM11 */
+ GATE_VOTE_MM11(CLK_MM1_DISP_DITHER2, "mm1_disp_dither2", "ck2_disp_ck", 0),
+ GATE_MM11_V(CLK_MM1_DISP_DITHER2_PQ, "mm1_disp_dither2_pq", "mm1_disp_dither2"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_R2Y0, "mm1_disp_r2y0", "ck2_disp_ck", 1),
+ GATE_MM11_V(CLK_MM1_DISP_R2Y0_DISP, "mm1_disp_r2y0_disp", "mm1_disp_r2y0"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_SPLITTER0, "mm1_disp_splitter0", "ck2_disp_ck", 2),
+ GATE_MM11_V(CLK_MM1_DISP_SPLITTER0_DISP, "mm1_disp_splitter0_disp", "mm1_disp_splitter0"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_SPLITTER1, "mm1_disp_splitter1", "ck2_disp_ck", 3),
+ GATE_MM11_V(CLK_MM1_DISP_SPLITTER1_DISP, "mm1_disp_splitter1_disp", "mm1_disp_splitter1"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_SPLITTER2, "mm1_disp_splitter2", "ck2_disp_ck", 4),
+ GATE_MM11_V(CLK_MM1_DISP_SPLITTER2_DISP, "mm1_disp_splitter2_disp", "mm1_disp_splitter2"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_SPLITTER3, "mm1_disp_splitter3", "ck2_disp_ck", 5),
+ GATE_MM11_V(CLK_MM1_DISP_SPLITTER3_DISP, "mm1_disp_splitter3_disp", "mm1_disp_splitter3"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_VDCM0, "mm1_disp_vdcm0", "ck2_disp_ck", 6),
+ GATE_MM11_V(CLK_MM1_DISP_VDCM0_DISP, "mm1_disp_vdcm0_disp", "mm1_disp_vdcm0"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_WDMA1, "mm1_disp_wdma1", "ck2_disp_ck", 7),
+ GATE_MM11_V(CLK_MM1_DISP_WDMA1_DISP, "mm1_disp_wdma1_disp", "mm1_disp_wdma1"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_WDMA2, "mm1_disp_wdma2", "ck2_disp_ck", 8),
+ GATE_MM11_V(CLK_MM1_DISP_WDMA2_DISP, "mm1_disp_wdma2_disp", "mm1_disp_wdma2"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_WDMA3, "mm1_disp_wdma3", "ck2_disp_ck", 9),
+ GATE_MM11_V(CLK_MM1_DISP_WDMA3_DISP, "mm1_disp_wdma3_disp", "mm1_disp_wdma3"),
+ GATE_VOTE_MM11(CLK_MM1_DISP_WDMA4, "mm1_disp_wdma4", "ck2_disp_ck", 10),
+ GATE_MM11_V(CLK_MM1_DISP_WDMA4_DISP, "mm1_disp_wdma4_disp", "mm1_disp_wdma4"),
+ GATE_VOTE_MM11(CLK_MM1_MDP_RDMA1, "mm1_mdp_rdma1", "ck2_disp_ck", 11),
+ GATE_MM11_V(CLK_MM1_MDP_RDMA1_DISP, "mm1_mdp_rdma1_disp", "mm1_mdp_rdma1"),
+ GATE_VOTE_MM11(CLK_MM1_SMI_LARB0, "mm1_smi_larb0", "ck2_disp_ck", 12),
+ GATE_MM11_V(CLK_MM1_SMI_LARB0_SMI, "mm1_smi_larb0_smi", "mm1_smi_larb0"),
+ GATE_VOTE_MM11(CLK_MM1_MOD1, "mm1_mod1", "ck_f26m_ck", 13),
+ GATE_MM11_V(CLK_MM1_MOD1_DISP, "mm1_mod1_disp", "mm1_mod1"),
+ GATE_VOTE_MM11(CLK_MM1_MOD2, "mm1_mod2", "ck_f26m_ck", 14),
+ GATE_MM11_V(CLK_MM1_MOD2_DISP, "mm1_mod2_disp", "mm1_mod2"),
+ GATE_VOTE_MM11(CLK_MM1_MOD3, "mm1_mod3", "ck_f26m_ck", 15),
+ GATE_MM11_V(CLK_MM1_MOD3_DISP, "mm1_mod3_disp", "mm1_mod3"),
+ GATE_VOTE_MM11(CLK_MM1_MOD4, "mm1_mod4", "ck2_dp0_ck", 16),
+ GATE_MM11_V(CLK_MM1_MOD4_DISP, "mm1_mod4_disp", "mm1_mod4"),
+ GATE_VOTE_MM11(CLK_MM1_MOD5, "mm1_mod5", "ck2_dp1_ck", 17),
+ GATE_MM11_V(CLK_MM1_MOD5_DISP, "mm1_mod5_disp", "mm1_mod5"),
+ GATE_VOTE_MM11(CLK_MM1_MOD6, "mm1_mod6", "ck2_dp1_ck", 18),
+ GATE_MM11_V(CLK_MM1_MOD6_DISP, "mm1_mod6_disp", "mm1_mod6"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG0, "mm1_cg0", "ck2_disp_ck", 20),
+ GATE_MM11_V(CLK_MM1_CK_CG0_DISP, "mm1_cg0_disp", "mm1_cg0"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG1, "mm1_cg1", "ck2_disp_ck", 21),
+ GATE_MM11_V(CLK_MM1_CK_CG1_DISP, "mm1_cg1_disp", "mm1_cg1"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG2, "mm1_cg2", "ck2_disp_ck", 22),
+ GATE_MM11_V(CLK_MM1_CK_CG2_DISP, "mm1_cg2_disp", "mm1_cg2"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG3, "mm1_cg3", "ck2_disp_ck", 23),
+ GATE_MM11_V(CLK_MM1_CK_CG3_DISP, "mm1_cg3_disp", "mm1_cg3"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG4, "mm1_cg4", "ck2_disp_ck", 24),
+ GATE_MM11_V(CLK_MM1_CK_CG4_DISP, "mm1_cg4_disp", "mm1_cg4"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG5, "mm1_cg5", "ck2_disp_ck", 25),
+ GATE_MM11_V(CLK_MM1_CK_CG5_DISP, "mm1_cg5_disp", "mm1_cg5"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG6, "mm1_cg6", "ck2_disp_ck", 26),
+ GATE_MM11_V(CLK_MM1_CK_CG6_DISP, "mm1_cg6_disp", "mm1_cg6"),
+ GATE_VOTE_MM11(CLK_MM1_CK_CG7, "mm1_cg7", "ck2_disp_ck", 27),
+ GATE_MM11_V(CLK_MM1_CK_CG7_DISP, "mm1_cg7_disp", "mm1_cg7"),
+ GATE_VOTE_MM11(CLK_MM1_F26M, "mm1_f26m_ck", "ck_f26m_ck", 28),
+ GATE_MM11_V(CLK_MM1_F26M_DISP, "mm1_f26m_ck_disp", "mm1_f26m_ck"),
+};
+
+static const struct mtk_clk_desc mm1_mcd = {
+ .clks = mm1_clks,
+ .num_clks = ARRAY_SIZE(mm1_clks),
+};
+
+static const struct platform_device_id clk_mt8196_disp1_id_table[] = {
+ { .name = "clk-mt8196-disp1", .driver_data = (kernel_ulong_t)&mm1_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, clk_mt8196_disp1_id_table);
+
+static struct platform_driver clk_mt8196_disp1_drv = {
+ .probe = mtk_clk_pdev_probe,
+ .remove = mtk_clk_pdev_remove,
+ .driver = {
+ .name = "clk-mt8196-disp1",
+ },
+ .id_table = clk_mt8196_disp1_id_table,
+};
+
+module_platform_driver(clk_mt8196_disp1_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 20/26] clk: mediatek: Add MT8196 disp-ao clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (18 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 19/26] clk: mediatek: Add MT8196 disp1 " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 21/26] clk: mediatek: Add MT8196 ovl0 " Guangjie Song
` (5 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 disp-ao clock controller which provides clock gate control in
display system. This is integrated with mtk-mmsys driver which will
populate device by platform_device_register_data to start disp-ao clock
driver.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c | 100 +++++++++++++++++++++
2 files changed, 101 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 7eb4af39029c..fab6a0944501 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -158,7 +158,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
-obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o
+obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-vdisp_ao.c b/drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
new file mode 100644
index 000000000000..6965c30dad4c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs mm_v_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm_v_vote_regs = {
+ .set_ofs = 0x0030,
+ .clr_ofs = 0x0034,
+ .sta_ofs = 0x2c18,
+};
+
+#define GATE_MM_V(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm_v_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_MM_V_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_MM_AO_V(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &mm_v_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr_enable, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VOTE_MM_V(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &mm_v_cg_regs, \
+ .vote_regs = &mm_v_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+static const struct mtk_gate mm_v_clks[] = {
+ GATE_VOTE_MM_V(CLK_MM_V_DISP_VDISP_AO_CONFIG, "mm_v_disp_vdisp_ao_config", "ck2_disp_ck", 0),
+ GATE_MM_V_V(CLK_MM_V_DISP_VDISP_AO_CONFIG_DISP, "mm_v_disp_vdisp_ao_config_disp",
+ "mm_v_disp_vdisp_ao_config"),
+ GATE_VOTE_MM_V(CLK_MM_V_DISP_DPC, "mm_v_disp_dpc", "ck2_disp_ck", 16),
+ GATE_MM_V_V(CLK_MM_V_DISP_DPC_DISP, "mm_v_disp_dpc_disp", "mm_v_disp_dpc"),
+ GATE_MM_AO_V(CLK_MM_V_SMI_SUB_SOMM0, "mm_v_smi_sub_somm0", "ck2_disp_ck", 2),
+ GATE_MM_V_V(CLK_MM_V_SMI_SUB_SOMM0_SMI, "mm_v_smi_sub_somm0_smi", "mm_v_smi_sub_somm0"),
+};
+
+static const struct mtk_clk_desc mm_v_mcd = {
+ .clks = mm_v_clks,
+ .num_clks = ARRAY_SIZE(mm_v_clks),
+};
+
+static const struct platform_device_id clk_mt8196_vdisp_ao_id_table[] = {
+ { .name = "clk-mt8196-vdisp_ao", .driver_data = (kernel_ulong_t)&mm_v_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, clk_mt8196_vdisp_ao_id_table);
+
+static struct platform_driver clk_mt8196_vdisp_ao_drv = {
+ .probe = mtk_clk_pdev_probe,
+ .remove = mtk_clk_pdev_remove,
+ .driver = {
+ .name = "clk-mt8196-vdisp_ao",
+ },
+ .id_table = clk_mt8196_vdisp_ao_id_table,
+};
+
+module_platform_driver(clk_mt8196_vdisp_ao_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 21/26] clk: mediatek: Add MT8196 ovl0 clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (19 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 20/26] clk: mediatek: Add MT8196 disp-ao " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 7:29 ` Krzysztof Kozlowski
2025-03-07 3:27 ` [PATCH 22/26] clk: mediatek: Add MT8196 ovl1 " Guangjie Song
` (4 subsequent siblings)
25 siblings, 1 reply; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 ovl0 clock controller which provides clock gate control in
display system. This is integrated with mtk-mmsys driver which will
populate device by platform_device_register_data to start ovl0 clock
driver.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8196-ovl0.c | 256 +++++++++++++++++++++++++
2 files changed, 258 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl0.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index fab6a0944501..6766811e67d9 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -158,7 +158,8 @@ obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
-obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o
+obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o \
+ clk-mt8196-ovl0.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-ovl0.c b/drivers/clk/mediatek/clk-mt8196-ovl0.c
new file mode 100644
index 000000000000..5a9ae157ec35
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-ovl0.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs ovl0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs ovl0_vote_regs = {
+ .set_ofs = 0x0060,
+ .clr_ofs = 0x0064,
+ .sta_ofs = 0x2c30,
+};
+
+static const struct mtk_gate_regs ovl1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs ovl1_vote_regs = {
+ .set_ofs = 0x0068,
+ .clr_ofs = 0x006c,
+ .sta_ofs = 0x2c34,
+};
+
+#define GATE_OVL0(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ovl0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_OVL0_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_OVL0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ovl0_cg_regs, \
+ .vote_regs = &ovl0_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_OVL1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ovl1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_OVL1_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_OVL1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ovl1_cg_regs, \
+ .vote_regs = &ovl1_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+static const struct mtk_gate ovl_clks[] = {
+ /* OVL0 */
+ GATE_VOTE_OVL0(CLK_OVLSYS_CONFIG, "ovlsys_config", "ck2_disp_ck", 0),
+ GATE_OVL0_V(CLK_OVLSYS_CONFIG_DISP, "ovlsys_config_disp", "ovlsys_config"),
+ GATE_VOTE_OVL0(CLK_OVL_FAKE_ENG0, "ovl_fake_eng0", "ck2_disp_ck", 1),
+ GATE_OVL0_V(CLK_OVL_FAKE_ENG0_DISP, "ovl_fake_eng0_disp", "ovl_fake_eng0"),
+ GATE_VOTE_OVL0(CLK_OVL_FAKE_ENG1, "ovl_fake_eng1", "ck2_disp_ck", 2),
+ GATE_OVL0_V(CLK_OVL_FAKE_ENG1_DISP, "ovl_fake_eng1_disp", "ovl_fake_eng1"),
+ GATE_VOTE_OVL0(CLK_OVL_MUTEX0, "ovl_mutex0", "ck2_disp_ck", 3),
+ GATE_OVL0_V(CLK_OVL_MUTEX0_DISP, "ovl_mutex0_disp", "ovl_mutex0"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA0, "ovl_exdma0", "ck2_disp_ck", 4),
+ GATE_OVL0_V(CLK_OVL_EXDMA0_DISP, "ovl_exdma0_disp", "ovl_exdma0"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA1, "ovl_exdma1", "ck2_disp_ck", 5),
+ GATE_OVL0_V(CLK_OVL_EXDMA1_DISP, "ovl_exdma1_disp", "ovl_exdma1"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA2, "ovl_exdma2", "ck2_disp_ck", 6),
+ GATE_OVL0_V(CLK_OVL_EXDMA2_DISP, "ovl_exdma2_disp", "ovl_exdma2"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA3, "ovl_exdma3", "ck2_disp_ck", 7),
+ GATE_OVL0_V(CLK_OVL_EXDMA3_DISP, "ovl_exdma3_disp", "ovl_exdma3"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA4, "ovl_exdma4", "ck2_disp_ck", 8),
+ GATE_OVL0_V(CLK_OVL_EXDMA4_DISP, "ovl_exdma4_disp", "ovl_exdma4"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA5, "ovl_exdma5", "ck2_disp_ck", 9),
+ GATE_OVL0_V(CLK_OVL_EXDMA5_DISP, "ovl_exdma5_disp", "ovl_exdma5"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA6, "ovl_exdma6", "ck2_disp_ck", 10),
+ GATE_OVL0_V(CLK_OVL_EXDMA6_DISP, "ovl_exdma6_disp", "ovl_exdma6"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA7, "ovl_exdma7", "ck2_disp_ck", 11),
+ GATE_OVL0_V(CLK_OVL_EXDMA7_DISP, "ovl_exdma7_disp", "ovl_exdma7"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA8, "ovl_exdma8", "ck2_disp_ck", 12),
+ GATE_OVL0_V(CLK_OVL_EXDMA8_DISP, "ovl_exdma8_disp", "ovl_exdma8"),
+ GATE_VOTE_OVL0(CLK_OVL_EXDMA9, "ovl_exdma9", "ck2_disp_ck", 13),
+ GATE_OVL0_V(CLK_OVL_EXDMA9_DISP, "ovl_exdma9_disp", "ovl_exdma9"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER0, "ovl_blender0", "ck2_disp_ck", 14),
+ GATE_OVL0_V(CLK_OVL_BLENDER0_DISP, "ovl_blender0_disp", "ovl_blender0"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER1, "ovl_blender1", "ck2_disp_ck", 15),
+ GATE_OVL0_V(CLK_OVL_BLENDER1_DISP, "ovl_blender1_disp", "ovl_blender1"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER2, "ovl_blender2", "ck2_disp_ck", 16),
+ GATE_OVL0_V(CLK_OVL_BLENDER2_DISP, "ovl_blender2_disp", "ovl_blender2"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER3, "ovl_blender3", "ck2_disp_ck", 17),
+ GATE_OVL0_V(CLK_OVL_BLENDER3_DISP, "ovl_blender3_disp", "ovl_blender3"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER4, "ovl_blender4", "ck2_disp_ck", 18),
+ GATE_OVL0_V(CLK_OVL_BLENDER4_DISP, "ovl_blender4_disp", "ovl_blender4"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER5, "ovl_blender5", "ck2_disp_ck", 19),
+ GATE_OVL0_V(CLK_OVL_BLENDER5_DISP, "ovl_blender5_disp", "ovl_blender5"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER6, "ovl_blender6", "ck2_disp_ck", 20),
+ GATE_OVL0_V(CLK_OVL_BLENDER6_DISP, "ovl_blender6_disp", "ovl_blender6"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER7, "ovl_blender7", "ck2_disp_ck", 21),
+ GATE_OVL0_V(CLK_OVL_BLENDER7_DISP, "ovl_blender7_disp", "ovl_blender7"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER8, "ovl_blender8", "ck2_disp_ck", 22),
+ GATE_OVL0_V(CLK_OVL_BLENDER8_DISP, "ovl_blender8_disp", "ovl_blender8"),
+ GATE_VOTE_OVL0(CLK_OVL_BLENDER9, "ovl_blender9", "ck2_disp_ck", 23),
+ GATE_OVL0_V(CLK_OVL_BLENDER9_DISP, "ovl_blender9_disp", "ovl_blender9"),
+ GATE_VOTE_OVL0(CLK_OVL_OUTPROC0, "ovl_outproc0", "ck2_disp_ck", 24),
+ GATE_OVL0_V(CLK_OVL_OUTPROC0_DISP, "ovl_outproc0_disp", "ovl_outproc0"),
+ GATE_VOTE_OVL0(CLK_OVL_OUTPROC1, "ovl_outproc1", "ck2_disp_ck", 25),
+ GATE_OVL0_V(CLK_OVL_OUTPROC1_DISP, "ovl_outproc1_disp", "ovl_outproc1"),
+ GATE_VOTE_OVL0(CLK_OVL_OUTPROC2, "ovl_outproc2", "ck2_disp_ck", 26),
+ GATE_OVL0_V(CLK_OVL_OUTPROC2_DISP, "ovl_outproc2_disp", "ovl_outproc2"),
+ GATE_VOTE_OVL0(CLK_OVL_OUTPROC3, "ovl_outproc3", "ck2_disp_ck", 27),
+ GATE_OVL0_V(CLK_OVL_OUTPROC3_DISP, "ovl_outproc3_disp", "ovl_outproc3"),
+ GATE_VOTE_OVL0(CLK_OVL_OUTPROC4, "ovl_outproc4", "ck2_disp_ck", 28),
+ GATE_OVL0_V(CLK_OVL_OUTPROC4_DISP, "ovl_outproc4_disp", "ovl_outproc4"),
+ GATE_VOTE_OVL0(CLK_OVL_OUTPROC5, "ovl_outproc5", "ck2_disp_ck", 29),
+ GATE_OVL0_V(CLK_OVL_OUTPROC5_DISP, "ovl_outproc5_disp", "ovl_outproc5"),
+ GATE_VOTE_OVL0(CLK_OVL_MDP_RSZ0, "ovl_mdp_rsz0", "ck2_disp_ck", 30),
+ GATE_OVL0_V(CLK_OVL_MDP_RSZ0_DISP, "ovl_mdp_rsz0_disp", "ovl_mdp_rsz0"),
+ GATE_VOTE_OVL0(CLK_OVL_MDP_RSZ1, "ovl_mdp_rsz1", "ck2_disp_ck", 31),
+ GATE_OVL0_V(CLK_OVL_MDP_RSZ1_DISP, "ovl_mdp_rsz1_disp", "ovl_mdp_rsz1"),
+ /* OVL1 */
+ GATE_VOTE_OVL1(CLK_OVL_DISP_WDMA0, "ovl_disp_wdma0", "ck2_disp_ck", 0),
+ GATE_OVL1_V(CLK_OVL_DISP_WDMA0_DISP, "ovl_disp_wdma0_disp", "ovl_disp_wdma0"),
+ GATE_VOTE_OVL1(CLK_OVL_DISP_WDMA1, "ovl_disp_wdma1", "ck2_disp_ck", 1),
+ GATE_OVL1_V(CLK_OVL_DISP_WDMA1_DISP, "ovl_disp_wdma1_disp", "ovl_disp_wdma1"),
+ GATE_VOTE_OVL1(CLK_OVL_UFBC_WDMA0, "ovl_ufbc_wdma0", "ck2_disp_ck", 2),
+ GATE_OVL1_V(CLK_OVL_UFBC_WDMA0_DISP, "ovl_ufbc_wdma0_disp", "ovl_ufbc_wdma0"),
+ GATE_VOTE_OVL1(CLK_OVL_MDP_RDMA0, "ovl_mdp_rdma0", "ck2_disp_ck", 3),
+ GATE_OVL1_V(CLK_OVL_MDP_RDMA0_DISP, "ovl_mdp_rdma0_disp", "ovl_mdp_rdma0"),
+ GATE_VOTE_OVL1(CLK_OVL_MDP_RDMA1, "ovl_mdp_rdma1", "ck2_disp_ck", 4),
+ GATE_OVL1_V(CLK_OVL_MDP_RDMA1_DISP, "ovl_mdp_rdma1_disp", "ovl_mdp_rdma1"),
+ GATE_VOTE_OVL1(CLK_OVL_BWM0, "ovl_bwm0", "ck2_disp_ck", 5),
+ GATE_OVL1_V(CLK_OVL_BWM0_DISP, "ovl_bwm0_disp", "ovl_bwm0"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI0, "ovl_dli0", "ck2_disp_ck", 6),
+ GATE_OVL1_V(CLK_OVL_DLI0_DISP, "ovl_dli0_disp", "ovl_dli0"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI1, "ovl_dli1", "ck2_disp_ck", 7),
+ GATE_OVL1_V(CLK_OVL_DLI1_DISP, "ovl_dli1_disp", "ovl_dli1"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI2, "ovl_dli2", "ck2_disp_ck", 8),
+ GATE_OVL1_V(CLK_OVL_DLI2_DISP, "ovl_dli2_disp", "ovl_dli2"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI3, "ovl_dli3", "ck2_disp_ck", 9),
+ GATE_OVL1_V(CLK_OVL_DLI3_DISP, "ovl_dli3_disp", "ovl_dli3"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI4, "ovl_dli4", "ck2_disp_ck", 10),
+ GATE_OVL1_V(CLK_OVL_DLI4_DISP, "ovl_dli4_disp", "ovl_dli4"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI5, "ovl_dli5", "ck2_disp_ck", 11),
+ GATE_OVL1_V(CLK_OVL_DLI5_DISP, "ovl_dli5_disp", "ovl_dli5"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI6, "ovl_dli6", "ck2_disp_ck", 12),
+ GATE_OVL1_V(CLK_OVL_DLI6_DISP, "ovl_dli6_disp", "ovl_dli6"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI7, "ovl_dli7", "ck2_disp_ck", 13),
+ GATE_OVL1_V(CLK_OVL_DLI7_DISP, "ovl_dli7_disp", "ovl_dli7"),
+ GATE_VOTE_OVL1(CLK_OVL_DLI8, "ovl_dli8", "ck2_disp_ck", 14),
+ GATE_OVL1_V(CLK_OVL_DLI8_DISP, "ovl_dli8_disp", "ovl_dli8"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO0, "ovl_dlo0", "ck2_disp_ck", 15),
+ GATE_OVL1_V(CLK_OVL_DLO0_DISP, "ovl_dlo0_disp", "ovl_dlo0"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO1, "ovl_dlo1", "ck2_disp_ck", 16),
+ GATE_OVL1_V(CLK_OVL_DLO1_DISP, "ovl_dlo1_disp", "ovl_dlo1"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO2, "ovl_dlo2", "ck2_disp_ck", 17),
+ GATE_OVL1_V(CLK_OVL_DLO2_DISP, "ovl_dlo2_disp", "ovl_dlo2"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO3, "ovl_dlo3", "ck2_disp_ck", 18),
+ GATE_OVL1_V(CLK_OVL_DLO3_DISP, "ovl_dlo3_disp", "ovl_dlo3"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO4, "ovl_dlo4", "ck2_disp_ck", 19),
+ GATE_OVL1_V(CLK_OVL_DLO4_DISP, "ovl_dlo4_disp", "ovl_dlo4"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO5, "ovl_dlo5", "ck2_disp_ck", 20),
+ GATE_OVL1_V(CLK_OVL_DLO5_DISP, "ovl_dlo5_disp", "ovl_dlo5"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO6, "ovl_dlo6", "ck2_disp_ck", 21),
+ GATE_OVL1_V(CLK_OVL_DLO6_DISP, "ovl_dlo6_disp", "ovl_dlo6"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO7, "ovl_dlo7", "ck2_disp_ck", 22),
+ GATE_OVL1_V(CLK_OVL_DLO7_DISP, "ovl_dlo7_disp", "ovl_dlo7"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO8, "ovl_dlo8", "ck2_disp_ck", 23),
+ GATE_OVL1_V(CLK_OVL_DLO8_DISP, "ovl_dlo8_disp", "ovl_dlo8"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO9, "ovl_dlo9", "ck2_disp_ck", 24),
+ GATE_OVL1_V(CLK_OVL_DLO9_DISP, "ovl_dlo9_disp", "ovl_dlo9"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO10, "ovl_dlo10", "ck2_disp_ck", 25),
+ GATE_OVL1_V(CLK_OVL_DLO10_DISP, "ovl_dlo10_disp", "ovl_dlo10"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO11, "ovl_dlo11", "ck2_disp_ck", 26),
+ GATE_OVL1_V(CLK_OVL_DLO11_DISP, "ovl_dlo11_disp", "ovl_dlo11"),
+ GATE_VOTE_OVL1(CLK_OVL_DLO12, "ovl_dlo12", "ck2_disp_ck", 27),
+ GATE_OVL1_V(CLK_OVL_DLO12_DISP, "ovl_dlo12_disp", "ovl_dlo12"),
+ GATE_VOTE_OVL1(CLK_OVLSYS_RELAY0, "ovlsys_relay0", "ck2_disp_ck", 28),
+ GATE_OVL1_V(CLK_OVLSYS_RELAY0_DISP, "ovlsys_relay0_disp", "ovlsys_relay0"),
+ GATE_VOTE_OVL1(CLK_OVL_INLINEROT0, "ovl_inlinerot0", "ck2_disp_ck", 29),
+ GATE_OVL1_V(CLK_OVL_INLINEROT0_DISP, "ovl_inlinerot0_disp", "ovl_inlinerot0"),
+ GATE_VOTE_OVL1(CLK_OVL_SMI, "ovl_smi", "ck2_disp_ck", 30),
+ GATE_OVL1_V(CLK_OVL_SMI_SMI, "ovl_smi_smi", "ovl_smi"),
+};
+
+static const struct mtk_clk_desc ovl_mcd = {
+ .clks = ovl_clks,
+ .num_clks = ARRAY_SIZE(ovl_clks),
+};
+
+static const struct platform_device_id clk_mt8196_ovl0_id_table[] = {
+ { .name = "clk-mt8196-ovl0", .driver_data = (kernel_ulong_t)&ovl_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl0_id_table);
+
+static struct platform_driver clk_mt8196_ovl0_drv = {
+ .probe = mtk_clk_pdev_probe,
+ .remove = mtk_clk_pdev_remove,
+ .driver = {
+ .name = "clk-mt8196-ovl0",
+ },
+ .id_table = clk_mt8196_ovl0_id_table,
+};
+
+module_platform_driver(clk_mt8196_ovl0_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 22/26] clk: mediatek: Add MT8196 ovl1 clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (20 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 21/26] clk: mediatek: Add MT8196 ovl0 " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 23/26] clk: mediatek: Add MT8196 pextpsys " Guangjie Song
` (3 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 ovl1 clock controller which provides clock gate control in
display system. This is integrated with mtk-mmsys driver which will
populate device by platform_device_register_data to start ovl1 clock
driver.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8196-ovl1.c | 255 +++++++++++++++++++++++++
2 files changed, 256 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl1.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6766811e67d9..472462cd8711 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -159,7 +159,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o \
- clk-mt8196-ovl0.o
+ clk-mt8196-ovl0.o clk-mt8196-ovl1.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-ovl1.c b/drivers/clk/mediatek/clk-mt8196-ovl1.c
new file mode 100644
index 000000000000..ca590be53199
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-ovl1.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs ovl10_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs ovl10_vote_regs = {
+ .set_ofs = 0x0050,
+ .clr_ofs = 0x0054,
+ .sta_ofs = 0x2c28,
+};
+
+static const struct mtk_gate_regs ovl11_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs ovl11_vote_regs = {
+ .set_ofs = 0x0058,
+ .clr_ofs = 0x005c,
+ .sta_ofs = 0x2c2c,
+};
+
+#define GATE_OVL10(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ovl10_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_OVL10_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_OVL10(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ovl10_cg_regs, \
+ .vote_regs = &ovl10_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_OVL11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ovl11_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_OVL11_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_OVL11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ovl11_cg_regs, \
+ .vote_regs = &ovl11_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+static const struct mtk_gate ovl1_clks[] = {
+ /* OVL10 */
+ GATE_VOTE_OVL10(CLK_OVL1_OVLSYS_CONFIG, "ovl1_ovlsys_config", "ck2_disp_ck", 0),
+ GATE_OVL10_V(CLK_OVL1_OVLSYS_CONFIG_DISP, "ovl1_ovlsys_config_disp", "ovl1_ovlsys_config"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_FAKE_ENG0, "ovl1_ovl_fake_eng0", "ck2_disp_ck", 1),
+ GATE_OVL10_V(CLK_OVL1_OVL_FAKE_ENG0_DISP, "ovl1_ovl_fake_eng0_disp", "ovl1_ovl_fake_eng0"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_FAKE_ENG1, "ovl1_ovl_fake_eng1", "ck2_disp_ck", 2),
+ GATE_OVL10_V(CLK_OVL1_OVL_FAKE_ENG1_DISP, "ovl1_ovl_fake_eng1_disp", "ovl1_ovl_fake_eng1"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_MUTEX0, "ovl1_ovl_mutex0", "ck2_disp_ck", 3),
+ GATE_OVL10_V(CLK_OVL1_OVL_MUTEX0_DISP, "ovl1_ovl_mutex0_disp", "ovl1_ovl_mutex0"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA0, "ovl1_ovl_exdma0", "ck2_disp_ck", 4),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA0_DISP, "ovl1_ovl_exdma0_disp", "ovl1_ovl_exdma0"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA1, "ovl1_ovl_exdma1", "ck2_disp_ck", 5),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA1_DISP, "ovl1_ovl_exdma1_disp", "ovl1_ovl_exdma1"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA2, "ovl1_ovl_exdma2", "ck2_disp_ck", 6),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA2_DISP, "ovl1_ovl_exdma2_disp", "ovl1_ovl_exdma2"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA3, "ovl1_ovl_exdma3", "ck2_disp_ck", 7),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA3_DISP, "ovl1_ovl_exdma3_disp", "ovl1_ovl_exdma3"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA4, "ovl1_ovl_exdma4", "ck2_disp_ck", 8),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA4_DISP, "ovl1_ovl_exdma4_disp", "ovl1_ovl_exdma4"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA5, "ovl1_ovl_exdma5", "ck2_disp_ck", 9),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA5_DISP, "ovl1_ovl_exdma5_disp", "ovl1_ovl_exdma5"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA6, "ovl1_ovl_exdma6", "ck2_disp_ck", 10),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA6_DISP, "ovl1_ovl_exdma6_disp", "ovl1_ovl_exdma6"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA7, "ovl1_ovl_exdma7", "ck2_disp_ck", 11),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA7_DISP, "ovl1_ovl_exdma7_disp", "ovl1_ovl_exdma7"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA8, "ovl1_ovl_exdma8", "ck2_disp_ck", 12),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA8_DISP, "ovl1_ovl_exdma8_disp", "ovl1_ovl_exdma8"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_EXDMA9, "ovl1_ovl_exdma9", "ck2_disp_ck", 13),
+ GATE_OVL10_V(CLK_OVL1_OVL_EXDMA9_DISP, "ovl1_ovl_exdma9_disp", "ovl1_ovl_exdma9"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER0, "ovl1_ovl_blender0", "ck2_disp_ck", 14),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER0_DISP, "ovl1_ovl_blender0_disp", "ovl1_ovl_blender0"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER1, "ovl1_ovl_blender1", "ck2_disp_ck", 15),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER1_DISP, "ovl1_ovl_blender1_disp", "ovl1_ovl_blender1"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER2, "ovl1_ovl_blender2", "ck2_disp_ck", 16),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER2_DISP, "ovl1_ovl_blender2_disp", "ovl1_ovl_blender2"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER3, "ovl1_ovl_blender3", "ck2_disp_ck", 17),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER3_DISP, "ovl1_ovl_blender3_disp", "ovl1_ovl_blender3"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER4, "ovl1_ovl_blender4", "ck2_disp_ck", 18),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER4_DISP, "ovl1_ovl_blender4_disp", "ovl1_ovl_blender4"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER5, "ovl1_ovl_blender5", "ck2_disp_ck", 19),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER5_DISP, "ovl1_ovl_blender5_disp", "ovl1_ovl_blender5"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER6, "ovl1_ovl_blender6", "ck2_disp_ck", 20),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER6_DISP, "ovl1_ovl_blender6_disp", "ovl1_ovl_blender6"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER7, "ovl1_ovl_blender7", "ck2_disp_ck", 21),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER7_DISP, "ovl1_ovl_blender7_disp", "ovl1_ovl_blender7"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER8, "ovl1_ovl_blender8", "ck2_disp_ck", 22),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER8_DISP, "ovl1_ovl_blender8_disp", "ovl1_ovl_blender8"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_BLENDER9, "ovl1_ovl_blender9", "ck2_disp_ck", 23),
+ GATE_OVL10_V(CLK_OVL1_OVL_BLENDER9_DISP, "ovl1_ovl_blender9_disp", "ovl1_ovl_blender9"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_OUTPROC0, "ovl1_ovl_outproc0", "ck2_disp_ck", 24),
+ GATE_OVL10_V(CLK_OVL1_OVL_OUTPROC0_DISP, "ovl1_ovl_outproc0_disp", "ovl1_ovl_outproc0"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_OUTPROC1, "ovl1_ovl_outproc1", "ck2_disp_ck", 25),
+ GATE_OVL10_V(CLK_OVL1_OVL_OUTPROC1_DISP, "ovl1_ovl_outproc1_disp", "ovl1_ovl_outproc1"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_OUTPROC2, "ovl1_ovl_outproc2", "ck2_disp_ck", 26),
+ GATE_OVL10_V(CLK_OVL1_OVL_OUTPROC2_DISP, "ovl1_ovl_outproc2_disp", "ovl1_ovl_outproc2"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_OUTPROC3, "ovl1_ovl_outproc3", "ck2_disp_ck", 27),
+ GATE_OVL10_V(CLK_OVL1_OVL_OUTPROC3_DISP, "ovl1_ovl_outproc3_disp", "ovl1_ovl_outproc3"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_OUTPROC4, "ovl1_ovl_outproc4", "ck2_disp_ck", 28),
+ GATE_OVL10_V(CLK_OVL1_OVL_OUTPROC4_DISP, "ovl1_ovl_outproc4_disp", "ovl1_ovl_outproc4"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_OUTPROC5, "ovl1_ovl_outproc5", "ck2_disp_ck", 29),
+ GATE_OVL10_V(CLK_OVL1_OVL_OUTPROC5_DISP, "ovl1_ovl_outproc5_disp", "ovl1_ovl_outproc5"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_MDP_RSZ0, "ovl1_ovl_mdp_rsz0", "ck2_disp_ck", 30),
+ GATE_OVL10_V(CLK_OVL1_OVL_MDP_RSZ0_DISP, "ovl1_ovl_mdp_rsz0_disp", "ovl1_ovl_mdp_rsz0"),
+ GATE_VOTE_OVL10(CLK_OVL1_OVL_MDP_RSZ1, "ovl1_ovl_mdp_rsz1", "ck2_disp_ck", 31),
+ GATE_OVL10_V(CLK_OVL1_OVL_MDP_RSZ1_DISP, "ovl1_ovl_mdp_rsz1_disp", "ovl1_ovl_mdp_rsz1"),
+ /* OVL11 */
+ GATE_VOTE_OVL11(CLK_OVL1_OVL_DISP_WDMA0, "ovl1_ovl_disp_wdma0", "ck2_disp_ck", 0),
+ GATE_OVL11_V(CLK_OVL1_OVL_DISP_WDMA0_DISP, "ovl1_ovl_disp_wdma0_disp", "ovl1_ovl_disp_wdma0"),
+ GATE_VOTE_OVL11(CLK_OVL1_OVL_DISP_WDMA1, "ovl1_ovl_disp_wdma1", "ck2_disp_ck", 1),
+ GATE_OVL11_V(CLK_OVL1_OVL_DISP_WDMA1_DISP, "ovl1_ovl_disp_wdma1_disp", "ovl1_ovl_disp_wdma1"),
+ GATE_VOTE_OVL11(CLK_OVL1_OVL_UFBC_WDMA0, "ovl1_ovl_ufbc_wdma0", "ck2_disp_ck", 2),
+ GATE_OVL11_V(CLK_OVL1_OVL_UFBC_WDMA0_DISP, "ovl1_ovl_ufbc_wdma0_disp", "ovl1_ovl_ufbc_wdma0"),
+ GATE_VOTE_OVL11(CLK_OVL1_OVL_MDP_RDMA0, "ovl1_ovl_mdp_rdma0", "ck2_disp_ck", 3),
+ GATE_OVL11_V(CLK_OVL1_OVL_MDP_RDMA0_DISP, "ovl1_ovl_mdp_rdma0_disp", "ovl1_ovl_mdp_rdma0"),
+ GATE_VOTE_OVL11(CLK_OVL1_OVL_MDP_RDMA1, "ovl1_ovl_mdp_rdma1", "ck2_disp_ck", 4),
+ GATE_OVL11_V(CLK_OVL1_OVL_MDP_RDMA1_DISP, "ovl1_ovl_mdp_rdma1_disp", "ovl1_ovl_mdp_rdma1"),
+ GATE_VOTE_OVL11(CLK_OVL1_OVL_BWM0, "ovl1_ovl_bwm0", "ck2_disp_ck", 5),
+ GATE_OVL11_V(CLK_OVL1_OVL_BWM0_DISP, "ovl1_ovl_bwm0_disp", "ovl1_ovl_bwm0"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI0, "ovl1_dli0", "ck2_disp_ck", 6),
+ GATE_OVL11_V(CLK_OVL1_DLI0_DISP, "ovl1_dli0_disp", "ovl1_dli0"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI1, "ovl1_dli1", "ck2_disp_ck", 7),
+ GATE_OVL11_V(CLK_OVL1_DLI1_DISP, "ovl1_dli1_disp", "ovl1_dli1"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI2, "ovl1_dli2", "ck2_disp_ck", 8),
+ GATE_OVL11_V(CLK_OVL1_DLI2_DISP, "ovl1_dli2_disp", "ovl1_dli2"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI3, "ovl1_dli3", "ck2_disp_ck", 9),
+ GATE_OVL11_V(CLK_OVL1_DLI3_DISP, "ovl1_dli3_disp", "ovl1_dli3"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI4, "ovl1_dli4", "ck2_disp_ck", 10),
+ GATE_OVL11_V(CLK_OVL1_DLI4_DISP, "ovl1_dli4_disp", "ovl1_dli4"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI5, "ovl1_dli5", "ck2_disp_ck", 11),
+ GATE_OVL11_V(CLK_OVL1_DLI5_DISP, "ovl1_dli5_disp", "ovl1_dli5"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI6, "ovl1_dli6", "ck2_disp_ck", 12),
+ GATE_OVL11_V(CLK_OVL1_DLI6_DISP, "ovl1_dli6_disp", "ovl1_dli6"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI7, "ovl1_dli7", "ck2_disp_ck", 13),
+ GATE_OVL11_V(CLK_OVL1_DLI7_DISP, "ovl1_dli7_disp", "ovl1_dli7"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLI8, "ovl1_dli8", "ck2_disp_ck", 14),
+ GATE_OVL11_V(CLK_OVL1_DLI8_DISP, "ovl1_dli8_disp", "ovl1_dli8"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO0, "ovl1_dlo0", "ck2_disp_ck", 15),
+ GATE_OVL11_V(CLK_OVL1_DLO0_DISP, "ovl1_dlo0_disp", "ovl1_dlo0"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO1, "ovl1_dlo1", "ck2_disp_ck", 16),
+ GATE_OVL11_V(CLK_OVL1_DLO1_DISP, "ovl1_dlo1_disp", "ovl1_dlo1"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO2, "ovl1_dlo2", "ck2_disp_ck", 17),
+ GATE_OVL11_V(CLK_OVL1_DLO2_DISP, "ovl1_dlo2_disp", "ovl1_dlo2"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO3, "ovl1_dlo3", "ck2_disp_ck", 18),
+ GATE_OVL11_V(CLK_OVL1_DLO3_DISP, "ovl1_dlo3_disp", "ovl1_dlo3"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO4, "ovl1_dlo4", "ck2_disp_ck", 19),
+ GATE_OVL11_V(CLK_OVL1_DLO4_DISP, "ovl1_dlo4_disp", "ovl1_dlo4"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO5, "ovl1_dlo5", "ck2_disp_ck", 20),
+ GATE_OVL11_V(CLK_OVL1_DLO5_DISP, "ovl1_dlo5_disp", "ovl1_dlo5"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO6, "ovl1_dlo6", "ck2_disp_ck", 21),
+ GATE_OVL11_V(CLK_OVL1_DLO6_DISP, "ovl1_dlo6_disp", "ovl1_dlo6"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO7, "ovl1_dlo7", "ck2_disp_ck", 22),
+ GATE_OVL11_V(CLK_OVL1_DLO7_DISP, "ovl1_dlo7_disp", "ovl1_dlo7"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO8, "ovl1_dlo8", "ck2_disp_ck", 23),
+ GATE_OVL11_V(CLK_OVL1_DLO8_DISP, "ovl1_dlo8_disp", "ovl1_dlo8"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO9, "ovl1_dlo9", "ck2_disp_ck", 24),
+ GATE_OVL11_V(CLK_OVL1_DLO9_DISP, "ovl1_dlo9_disp", "ovl1_dlo9"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO10, "ovl1_dlo10", "ck2_disp_ck", 25),
+ GATE_OVL11_V(CLK_OVL1_DLO10_DISP, "ovl1_dlo10_disp", "ovl1_dlo10"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO11, "ovl1_dlo11", "ck2_disp_ck", 26),
+ GATE_OVL11_V(CLK_OVL1_DLO11_DISP, "ovl1_dlo11_disp", "ovl1_dlo11"),
+ GATE_VOTE_OVL11(CLK_OVL1_DLO12, "ovl1_dlo12", "ck2_disp_ck", 27),
+ GATE_OVL11_V(CLK_OVL1_DLO12_DISP, "ovl1_dlo12_disp", "ovl1_dlo12"),
+ GATE_VOTE_OVL11(CLK_OVL1_OVLSYS_RELAY0, "ovl1_ovlsys_relay0", "ck2_disp_ck", 28),
+ GATE_OVL11_V(CLK_OVL1_OVLSYS_RELAY0_DISP, "ovl1_ovlsys_relay0_disp", "ovl1_ovlsys_relay0"),
+ GATE_VOTE_OVL11(CLK_OVL1_OVL_INLINEROT0, "ovl1_ovl_inlinerot0", "ck2_disp_ck", 29),
+ GATE_OVL11_V(CLK_OVL1_OVL_INLINEROT0_DISP, "ovl1_ovl_inlinerot0_disp", "ovl1_ovl_inlinerot0"),
+ GATE_VOTE_OVL11(CLK_OVL1_SMI, "ovl1_smi", "ck2_disp_ck", 30),
+ GATE_OVL11_V(CLK_OVL1_SMI_SMI, "ovl1_smi_smi", "ovl1_smi"),
+};
+
+static const struct mtk_clk_desc ovl1_mcd = {
+ .clks = ovl1_clks,
+ .num_clks = ARRAY_SIZE(ovl1_clks),
+};
+
+static const struct platform_device_id clk_mt8196_ovl1_id_table[] = {
+ { .name = "clk-mt8196-ovl1", .driver_data = (kernel_ulong_t)&ovl1_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl1_id_table);
+
+static struct platform_driver clk_mt8196_ovl1_drv = {
+ .probe = mtk_clk_pdev_probe,
+ .remove = mtk_clk_pdev_remove,
+ .driver = {
+ .name = "clk-mt8196-ovl1",
+ },
+ .id_table = clk_mt8196_ovl1_id_table,
+};
+
+module_platform_driver(clk_mt8196_ovl1_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 23/26] clk: mediatek: Add MT8196 pextpsys clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (21 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 22/26] clk: mediatek: Add MT8196 ovl1 " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 24/26] clk: mediatek: Add MT8196 ufssys " Guangjie Song
` (2 subsequent siblings)
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 pextpsys clock controller which provides clock gate control
for pcie.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-pextp.c | 162 ++++++++++++++++++++++++
3 files changed, 170 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index dcb660d45bcf..2aafba083835 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1052,6 +1052,13 @@ config COMMON_CLK_MT8196_MMSYS
help
This driver supports MediaTek MT8196 mmsys clocks.
+config COMMON_CLK_MT8196_PEXTPSYS
+ tristate "Clock driver for MediaTek MT8196 pextpsys"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 pextpsys clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 472462cd8711..3058e7855ff3 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -160,6 +160,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o \
clk-mt8196-ovl0.o clk-mt8196-ovl1.o
+obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-pextp.c b/drivers/clk/mediatek/clk-mt8196-pextp.c
new file mode 100644
index 000000000000..8b394e18d0eb
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-pextp.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs pext_cg_regs = {
+ .set_ofs = 0x18,
+ .clr_ofs = 0x1c,
+ .sta_ofs = 0x14,
+};
+
+#define GATE_PEXT(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &pext_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr,\
+ }
+
+#define GATE_PEXT_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate pext_clks[] = {
+ GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_TL, "pext_pm0_tl", "ck_tl_ck", 0),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_MAC_P0_TL_PCIE, "pext_pm0_tl_pcie", "pext_pm0_tl"),
+ GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_REF, "pext_pm0_ref", "ck_f26m_ck", 1),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_MAC_P0_REF_PCIE, "pext_pm0_ref_pcie", "pext_pm0_ref"),
+ GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_MCU_BUS, "pext_pp0_mcu_bus", "ck_f26m_ck", 6),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_PHY_P0_MCU_BUS_PCIE, "pext_pp0_mcu_bus_pcie",
+ "pext_pp0_mcu_bus"),
+ GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF, "pext_pp0_pextp_ref", "ck_f26m_ck", 7),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF_PCIE, "pext_pp0_pextp_ref_pcie",
+ "pext_pp0_pextp_ref"),
+ GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AXI_250, "pext_pm0_axi_250", "ck_pexpt0_mem_sub_ck", 12),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_MAC_P0_AXI_250_PCIE, "pext_pm0_axi_250_pcie",
+ "pext_pm0_axi_250"),
+ GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AHB_APB, "pext_pm0_ahb_apb", "ck_pextp0_axi_ck", 13),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_MAC_P0_AHB_APB_PCIE, "pext_pm0_ahb_apb_pcie",
+ "pext_pm0_ahb_apb"),
+ GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_PL_P, "pext_pm0_pl_p", "ck_f26m_ck", 14),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_MAC_P0_PL_P_PCIE, "pext_pm0_pl_p_pcie", "pext_pm0_pl_p"),
+ GATE_PEXT(CLK_PEXT_PEXTP_VLP_AO_P0_LP, "pext_pextp_vlp_ao_p0_lp", "ck_f26m_ck", 19),
+ GATE_PEXT_V(CLK_PEXT_PEXTP_VLP_AO_P0_LP_PCIE, "pext_pextp_vlp_ao_p0_lp_pcie",
+ "pext_pextp_vlp_ao_p0_lp"),
+};
+
+static const struct mtk_clk_desc pext_mcd = {
+ .clks = pext_clks,
+ .num_clks = ARRAY_SIZE(pext_clks),
+};
+
+static const struct mtk_gate_regs pext1_cg_regs = {
+ .set_ofs = 0x18,
+ .clr_ofs = 0x1c,
+ .sta_ofs = 0x14,
+};
+
+#define GATE_PEXT1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &pext1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_PEXT1_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate pext1_clks[] = {
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P1_TL, "pext1_pm1_tl", "ck_tl_p1_ck", 0),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P1_TL_PCIE, "pext1_pm1_tl_pcie", "pext1_pm1_tl"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P1_REF, "pext1_pm1_ref", "ck_f26m_ck", 1),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P1_REF_PCIE, "pext1_pm1_ref_pcie", "pext1_pm1_ref"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P2_TL, "pext1_pm2_tl", "ck_tl_p2_ck", 2),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P2_TL_PCIE, "pext1_pm2_tl_pcie", "pext1_pm2_tl"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P2_REF, "pext1_pm2_ref", "ck_f26m_ck", 3),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P2_REF_PCIE, "pext1_pm2_ref_pcie", "pext1_pm2_ref"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS, "pext1_pp1_mcu_bus", "ck_f26m_ck", 8),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS_PCIE, "pext1_pp1_mcu_bus_pcie",
+ "pext1_pp1_mcu_bus"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF, "pext1_pp1_pextp_ref", "ck_f26m_ck", 9),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF_PCIE, "pext1_pp1_pextp_ref_pcie",
+ "pext1_pp1_pextp_ref"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS, "pext1_pp2_mcu_bus", "ck_f26m_ck", 10),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS_PCIE, "pext1_pp2_mcu_bus_pcie",
+ "pext1_pp2_mcu_bus"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF, "pext1_pp2_pextp_ref", "ck_f26m_ck", 11),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF_PCIE, "pext1_pp2_pextp_ref_pcie",
+ "pext1_pp2_pextp_ref"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P1_AXI_250, "pext1_pm1_axi_250",
+ "ck_pextp1_usb_axi_ck", 16),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P1_AXI_250_PCIE, "pext1_pm1_axi_250_pcie",
+ "pext1_pm1_axi_250"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P1_AHB_APB, "pext1_pm1_ahb_apb",
+ "ck_pextp1_usb_mem_sub_ck", 17),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P1_AHB_APB_PCIE, "pext1_pm1_ahb_apb_pcie",
+ "pext1_pm1_ahb_apb"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P1_PL_P, "pext1_pm1_pl_p", "ck_f26m_ck", 18),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P1_PL_P_PCIE, "pext1_pm1_pl_p_pcie", "pext1_pm1_pl_p"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P2_AXI_250, "pext1_pm2_axi_250",
+ "ck_pextp1_usb_axi_ck", 19),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P2_AXI_250_PCIE, "pext1_pm2_axi_250_pcie",
+ "pext1_pm2_axi_250"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P2_AHB_APB, "pext1_pm2_ahb_apb",
+ "ck_pextp1_usb_mem_sub_ck", 20),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P2_AHB_APB_PCIE, "pext1_pm2_ahb_apb_pcie",
+ "pext1_pm2_ahb_apb"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_MAC_P2_PL_P, "pext1_pm2_pl_p", "ck_f26m_ck", 21),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_MAC_P2_PL_P_PCIE, "pext1_pm2_pl_p_pcie", "pext1_pm2_pl_p"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_VLP_AO_P1_LP, "pext1_pextp_vlp_ao_p1_lp", "ck_f26m_ck", 26),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_VLP_AO_P1_LP_PCIE, "pext1_pextp_vlp_ao_p1_lp_pcie",
+ "pext1_pextp_vlp_ao_p1_lp"),
+ GATE_PEXT1(CLK_PEXT1_PEXTP_VLP_AO_P2_LP, "pext1_pextp_vlp_ao_p2_lp", "ck_f26m_ck", 27),
+ GATE_PEXT1_V(CLK_PEXT1_PEXTP_VLP_AO_P2_LP_PCIE, "pext1_pextp_vlp_ao_p2_lp_pcie",
+ "pext1_pextp_vlp_ao_p2_lp"),
+};
+
+static const struct mtk_clk_desc pext1_mcd = {
+ .clks = pext1_clks,
+ .num_clks = ARRAY_SIZE(pext1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8196_pextp[] = {
+ { .compatible = "mediatek,mt8196-pextp0cfg_ao", .data = &pext_mcd, },
+ { .compatible = "mediatek,mt8196-pextp1cfg_ao", .data = &pext1_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_pextp_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-pextp",
+ .of_match_table = of_match_clk_mt8196_pextp,
+ },
+};
+
+module_platform_driver(clk_mt8196_pextp_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 24/26] clk: mediatek: Add MT8196 ufssys clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (22 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 23/26] clk: mediatek: Add MT8196 pextpsys " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 25/26] clk: mediatek: Add MT8196 vdecsys " Guangjie Song
2025-03-07 3:27 ` [PATCH 26/26] clk: mediatek: Add MT8196 vencsys " Guangjie Song
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 ufssys clock controller which provides clock gate control
for ufs.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 107 +++++++++++++++++++++++
3 files changed, 115 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 2aafba083835..5fc24f52762a 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1059,6 +1059,13 @@ config COMMON_CLK_MT8196_PEXTPSYS
help
This driver supports MediaTek MT8196 pextpsys clocks.
+config COMMON_CLK_MT8196_UFSSYS
+ tristate "Clock driver for MediaTek MT8196 ufssys"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 ufssys clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 3058e7855ff3..e5b4a3a61ef7 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -161,6 +161,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o \
clk-mt8196-ovl0.o clk-mt8196-ovl1.o
obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
+obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-ufs_ao.c b/drivers/clk/mediatek/clk-mt8196-ufs_ao.c
new file mode 100644
index 000000000000..107522759bd2
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-ufs_ao.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs ufsao0_cg_regs = {
+ .set_ofs = 0x108,
+ .clr_ofs = 0x10c,
+ .sta_ofs = 0x104,
+};
+
+static const struct mtk_gate_regs ufsao1_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_UFSAO0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ufsao0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_UFSAO0_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_UFSAO1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ufsao1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_UFSAO1_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+static const struct mtk_gate ufsao_clks[] = {
+ /* UFSAO0 */
+ GATE_UFSAO0(CLK_UFSAO_UFSHCI_UFS, "ufsao_ufshci_ufs", "ck_ck", 0),
+ GATE_UFSAO0_V(CLK_UFSAO_UFSHCI_UFS_UFS, "ufsao_ufshci_ufs_ufs", "ufsao_ufshci_ufs"),
+ GATE_UFSAO0(CLK_UFSAO_UFSHCI_AES, "ufsao_ufshci_aes", "ck_aes_ufsfde_ck", 1),
+ GATE_UFSAO0_V(CLK_UFSAO_UFSHCI_AES_UFS, "ufsao_ufshci_aes_ufs", "ufsao_ufshci_aes"),
+ /* UFSAO1 */
+ GATE_UFSAO1(CLK_UFSAO_UNIPRO_TX_SYM, "ufsao_unipro_tx_sym", "ck_f26m_ck", 0),
+ GATE_UFSAO1_V(CLK_UFSAO_UNIPRO_TX_SYM_UFS, "ufsao_unipro_tx_sym_ufs",
+ "ufsao_unipro_tx_sym"),
+ GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM0, "ufsao_unipro_rx_sym0", "ck_f26m_ck", 1),
+ GATE_UFSAO1_V(CLK_UFSAO_UNIPRO_RX_SYM0_UFS, "ufsao_unipro_rx_sym0_ufs",
+ "ufsao_unipro_rx_sym0"),
+ GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM1, "ufsao_unipro_rx_sym1", "ck_f26m_ck", 2),
+ GATE_UFSAO1_V(CLK_UFSAO_UNIPRO_RX_SYM1_UFS, "ufsao_unipro_rx_sym1_ufs",
+ "ufsao_unipro_rx_sym1"),
+ GATE_UFSAO1(CLK_UFSAO_UNIPRO_SYS, "ufsao_unipro_sys", "ck_ck", 3),
+ GATE_UFSAO1_V(CLK_UFSAO_UNIPRO_SYS_UFS, "ufsao_unipro_sys_ufs", "ufsao_unipro_sys"),
+ GATE_UFSAO1(CLK_UFSAO_UNIPRO_SAP, "ufsao_unipro_sap", "ck_f26m_ck", 4),
+ GATE_UFSAO1_V(CLK_UFSAO_UNIPRO_SAP_UFS, "ufsao_unipro_sap_ufs", "ufsao_unipro_sap"),
+ GATE_UFSAO1(CLK_UFSAO_PHY_SAP, "ufsao_phy_sap", "ck_f26m_ck", 8),
+ GATE_UFSAO1_V(CLK_UFSAO_PHY_SAP_UFS, "ufsao_phy_sap_ufs", "ufsao_phy_sap"),
+};
+
+static const struct mtk_clk_desc ufsao_mcd = {
+ .clks = ufsao_clks,
+ .num_clks = ARRAY_SIZE(ufsao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8196_ufs_ao[] = {
+ { .compatible = "mediatek,mt8196-ufscfg_ao", .data = &ufsao_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_ufs_ao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-ufs_ao",
+ .of_match_table = of_match_clk_mt8196_ufs_ao,
+ },
+};
+
+module_platform_driver(clk_mt8196_ufs_ao_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 25/26] clk: mediatek: Add MT8196 vdecsys clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (23 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 24/26] clk: mediatek: Add MT8196 ufssys " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
2025-03-07 3:27 ` [PATCH 26/26] clk: mediatek: Add MT8196 vencsys " Guangjie Song
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 vdecsys clock controller which provides clock gate control
for video decoder.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-vdec.c | 449 +++++++++++++++++++++++++
3 files changed, 457 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-vdec.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 5fc24f52762a..0c508a8a9959 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1066,6 +1066,13 @@ config COMMON_CLK_MT8196_UFSSYS
help
This driver supports MediaTek MT8196 ufssys clocks.
+config COMMON_CLK_MT8196_VDECSYS
+ tristate "Clock driver for MediaTek MT8196 vdecsys"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 vdecsys clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e5b4a3a61ef7..b8bf3f5f8530 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -162,6 +162,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o c
clk-mt8196-ovl0.o clk-mt8196-ovl1.o
obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
+obj-$(CONFIG_COMMON_CLK_MT8196_VDECSYS) += clk-mt8196-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-vdec.c b/drivers/clk/mediatek/clk-mt8196-vdec.c
new file mode 100644
index 000000000000..52accb5b4fb8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-vdec.c
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs vde20_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vde20_vote_regs = {
+ .set_ofs = 0x0088,
+ .clr_ofs = 0x008c,
+ .sta_ofs = 0x2c44,
+};
+
+static const struct mtk_gate_regs vde21_cg_regs = {
+ .set_ofs = 0x200,
+ .clr_ofs = 0x204,
+ .sta_ofs = 0x200,
+};
+
+static const struct mtk_gate_regs vde21_vote_regs = {
+ .set_ofs = 0x0080,
+ .clr_ofs = 0x0084,
+ .sta_ofs = 0x2c40,
+};
+
+static const struct mtk_gate_regs vde22_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x8,
+};
+
+static const struct mtk_gate_regs vde22_vote_regs = {
+ .set_ofs = 0x0078,
+ .clr_ofs = 0x007c,
+ .sta_ofs = 0x2c3c,
+};
+
+#define GATE_VDE20(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde20_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDE20_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE20(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde20_cg_regs, \
+ .vote_regs = &vde20_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VDE21(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde21_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDE21_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE21(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde21_cg_regs, \
+ .vote_regs = &vde21_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VDE22(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde22_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDE22_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE22(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde22_cg_regs, \
+ .vote_regs = &vde22_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE | \
+ CLK_IGNORE_UNUSED, \
+ }
+
+static const struct mtk_gate vde2_clks[] = {
+ /* VDE20 */
+ GATE_VOTE_VDE20(CLK_VDE2_VDEC_CKEN, "vde2_vdec_cken", "ck2_vdec_ck", 0),
+ GATE_VDE20_V(CLK_VDE2_VDEC_CKEN_VDEC, "vde2_vdec_cken_vdec", "vde2_vdec_cken"),
+ GATE_VOTE_VDE20(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "ck2_vdec_ck", 4),
+ GATE_VDE20_V(CLK_VDE2_VDEC_ACTIVE_VDEC, "vde2_vdec_active_vdec", "vde2_vdec_active"),
+ GATE_VOTE_VDE20(CLK_VDE2_VDEC_CKEN_ENG, "vde2_vdec_cken_eng", "ck2_vdec_ck", 8),
+ GATE_VDE20_V(CLK_VDE2_VDEC_CKEN_ENG_VDEC, "vde2_vdec_cken_eng_vdec", "vde2_vdec_cken_eng"),
+ /* VDE21 */
+ GATE_VOTE_VDE21(CLK_VDE2_LAT_CKEN, "vde2_lat_cken", "ck2_vdec_ck", 0),
+ GATE_VDE21_V(CLK_VDE2_LAT_CKEN_VDEC, "vde2_lat_cken_vdec", "vde2_lat_cken"),
+ GATE_VOTE_VDE21(CLK_VDE2_LAT_ACTIVE, "vde2_lat_active", "ck2_vdec_ck", 4),
+ GATE_VDE21_V(CLK_VDE2_LAT_ACTIVE_VDEC, "vde2_lat_active_vdec", "vde2_lat_active"),
+ GATE_VOTE_VDE21(CLK_VDE2_LAT_CKEN_ENG, "vde2_lat_cken_eng", "ck2_vdec_ck", 8),
+ GATE_VDE21_V(CLK_VDE2_LAT_CKEN_ENG_VDEC, "vde2_lat_cken_eng_vdec", "vde2_lat_cken_eng"),
+ /* VDE22 */
+ GATE_VOTE_VDE22(CLK_VDE2_LARB1_CKEN, "vde2_larb1_cken", "ck2_vdec_ck", 0),
+ GATE_VDE22_V(CLK_VDE2_LARB1_CKEN_VDEC, "vde2_larb1_cken_vdec", "vde2_larb1_cken"),
+ GATE_VDE22_V(CLK_VDE2_LARB1_CKEN_SMI, "vde2_larb1_cken_smi", "vde2_larb1_cken"),
+};
+
+static const struct mtk_clk_desc vde2_mcd = {
+ .clks = vde2_clks,
+ .num_clks = ARRAY_SIZE(vde2_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct mtk_gate_regs vde10_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vde10_vote_regs = {
+ .set_ofs = 0x00a0,
+ .clr_ofs = 0x00a4,
+ .sta_ofs = 0x2c50,
+};
+
+static const struct mtk_gate_regs vde11_cg_regs = {
+ .set_ofs = 0x1e0,
+ .clr_ofs = 0x1e0,
+ .sta_ofs = 0x1e0,
+};
+
+static const struct mtk_gate_regs vde11_vote_regs = {
+ .set_ofs = 0x00b0,
+ .clr_ofs = 0x00b4,
+ .sta_ofs = 0x2c58,
+};
+
+static const struct mtk_gate_regs vde12_cg_regs = {
+ .set_ofs = 0x1ec,
+ .clr_ofs = 0x1ec,
+ .sta_ofs = 0x1ec,
+};
+
+static const struct mtk_gate_regs vde12_vote_regs = {
+ .set_ofs = 0x00a8,
+ .clr_ofs = 0x00ac,
+ .sta_ofs = 0x2c54,
+};
+
+static const struct mtk_gate_regs vde13_cg_regs = {
+ .set_ofs = 0x200,
+ .clr_ofs = 0x204,
+ .sta_ofs = 0x200,
+};
+
+static const struct mtk_gate_regs vde13_vote_regs = {
+ .set_ofs = 0x0098,
+ .clr_ofs = 0x009c,
+ .sta_ofs = 0x2c4c,
+};
+
+static const struct mtk_gate_regs vde14_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x8,
+};
+
+static const struct mtk_gate_regs vde14_vote_regs = {
+ .set_ofs = 0x0090,
+ .clr_ofs = 0x0094,
+ .sta_ofs = 0x2c48,
+};
+
+#define GATE_VDE10(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde10_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDE10_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE10(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde10_cg_regs, \
+ .vote_regs = &vde10_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VDE11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde11_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_VDE11_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde11_cg_regs, \
+ .vote_regs = &vde11_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VDE12(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde12_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+#define GATE_VDE12_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE12(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde12_cg_regs, \
+ .vote_regs = &vde12_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE \
+ }
+
+#define GATE_VDE13(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde13_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDE13_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE13(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde13_cg_regs, \
+ .vote_regs = &vde13_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VDE14(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vde14_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VDE14_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VDE14(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &vde14_cg_regs, \
+ .vote_regs = &vde14_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE | \
+ CLK_IGNORE_UNUSED, \
+ }
+
+static const struct mtk_gate vde1_clks[] = {
+ /* VDE10 */
+ GATE_VOTE_VDE10(CLK_VDE1_VDEC_CKEN, "vde1_vdec_cken", "ck2_vdec_ck", 0),
+ GATE_VDE10_V(CLK_VDE1_VDEC_CKEN_VDEC, "vde1_vdec_cken_vdec", "vde1_vdec_cken"),
+ GATE_VOTE_VDE10(CLK_VDE1_VDEC_ACTIVE, "vde1_vdec_active", "ck2_vdec_ck", 4),
+ GATE_VDE10_V(CLK_VDE1_VDEC_ACTIVE_VDEC, "vde1_vdec_active_vdec", "vde1_vdec_active"),
+ GATE_VOTE_VDE10(CLK_VDE1_VDEC_CKEN_ENG, "vde1_vdec_cken_eng", "ck2_vdec_ck", 8),
+ GATE_VDE10_V(CLK_VDE1_VDEC_CKEN_ENG_VDEC, "vde1_vdec_cken_eng_vdec", "vde1_vdec_cken_eng"),
+ /* VDE11 */
+ GATE_VOTE_VDE11(CLK_VDE1_VDEC_SOC_IPS_EN, "vde1_vdec_soc_ips_en", "ck2_vdec_ck", 0),
+ GATE_VDE11_V(CLK_VDE1_VDEC_SOC_IPS_EN_VDEC, "vde1_vdec_soc_ips_en_vdec",
+ "vde1_vdec_soc_ips_en"),
+ /* VDE12 */
+ GATE_VOTE_VDE12(CLK_VDE1_VDEC_SOC_APTV_EN, "vde1_aptv_en", "ck2_avs_vdec_ck", 0),
+ GATE_VDE12_V(CLK_VDE1_VDEC_SOC_APTV_EN_VDEC, "vde1_aptv_en_vdec", "vde1_aptv_en"),
+ GATE_VOTE_VDE12(CLK_VDE1_VDEC_SOC_APTV_TOP_EN, "vde1_aptv_topen", "ck2_avs_vdec_ck", 1),
+ GATE_VDE12_V(CLK_VDE1_VDEC_SOC_APTV_TOP_EN_VDEC, "vde1_aptv_topen_vdec", "vde1_aptv_topen"),
+ /* VDE13 */
+ GATE_VOTE_VDE13(CLK_VDE1_LAT_CKEN, "vde1_lat_cken", "ck2_vdec_ck", 0),
+ GATE_VDE13_V(CLK_VDE1_LAT_CKEN_VDEC, "vde1_lat_cken_vdec", "vde1_lat_cken"),
+ GATE_VOTE_VDE13(CLK_VDE1_LAT_ACTIVE, "vde1_lat_active", "ck2_vdec_ck", 4),
+ GATE_VDE13_V(CLK_VDE1_LAT_ACTIVE_VDEC, "vde1_lat_active_vdec", "vde1_lat_active"),
+ GATE_VOTE_VDE13(CLK_VDE1_LAT_CKEN_ENG, "vde1_lat_cken_eng", "ck2_vdec_ck", 8),
+ GATE_VDE13_V(CLK_VDE1_LAT_CKEN_ENG_VDEC, "vde1_lat_cken_eng_vdec", "vde1_lat_cken_eng"),
+ /* VDE14 */
+ GATE_VOTE_VDE14(CLK_VDE1_LARB1_CKEN, "vde1_larb1_cken", "ck2_vdec_ck", 0),
+ GATE_VDE14_V(CLK_VDE1_LARB1_CKEN_VDEC, "vde1_larb1_cken_vdec", "vde1_larb1_cken"),
+ GATE_VDE14_V(CLK_VDE1_LARB1_CKEN_SMI, "vde1_larb1_cken_smi", "vde1_larb1_cken"),
+};
+
+static const struct mtk_clk_desc vde1_mcd = {
+ .clks = vde1_clks,
+ .num_clks = ARRAY_SIZE(vde1_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct of_device_id of_match_clk_mt8196_vdec[] = {
+ { .compatible = "mediatek,mt8196-vdecsys", .data = &vde2_mcd, },
+ { .compatible = "mediatek,mt8196-vdecsys_soc", .data = &vde1_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_vdec_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-vdec",
+ .of_match_table = of_match_clk_mt8196_vdec,
+ },
+};
+
+module_platform_driver(clk_mt8196_vdec_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 26/26] clk: mediatek: Add MT8196 vencsys clock support
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
` (24 preceding siblings ...)
2025-03-07 3:27 ` [PATCH 25/26] clk: mediatek: Add MT8196 vdecsys " Guangjie Song
@ 2025-03-07 3:27 ` Guangjie Song
25 siblings, 0 replies; 34+ messages in thread
From: Guangjie Song @ 2025-03-07 3:27 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Guangjie Song,
Project_Global_Chrome_Upstream_Group
Add MT8196 vencsys clock controller which provides clock gate control
for video encoder.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 7 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8196-venc.c | 413 +++++++++++++++++++++++++
3 files changed, 421 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8196-venc.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 0c508a8a9959..3184b2186561 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -1073,6 +1073,13 @@ config COMMON_CLK_MT8196_VDECSYS
help
This driver supports MediaTek MT8196 vdecsys clocks.
+config COMMON_CLK_MT8196_VENCSYS
+ tristate "Clock driver for MediaTek MT8196 vencsys"
+ depends on COMMON_CLK_MT8196
+ default COMMON_CLK_MT8196
+ help
+ This driver supports MediaTek MT8196 vencsys clocks.
+
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b8bf3f5f8530..7bded296d0ca 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -163,6 +163,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o c
obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
obj-$(CONFIG_COMMON_CLK_MT8196_VDECSYS) += clk-mt8196-vdec.o
+obj-$(CONFIG_COMMON_CLK_MT8196_VENCSYS) += clk-mt8196-venc.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-venc.c b/drivers/clk/mediatek/clk-mt8196-venc.c
new file mode 100644
index 000000000000..f8fcdf7b47df
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-venc.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Guangjie Song <guangjie.song@mediatek.com>
+ */
+#include <dt-bindings/clock/mt8196-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs ven10_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs ven10_vote_regs = {
+ .set_ofs = 0x00b8,
+ .clr_ofs = 0x00bc,
+ .sta_ofs = 0x2c5c,
+};
+
+static const struct mtk_gate_regs ven11_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs ven11_vote_regs = {
+ .set_ofs = 0x00c0,
+ .clr_ofs = 0x00c4,
+ .sta_ofs = 0x2c60,
+};
+
+#define GATE_VEN10(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ven10_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VEN10_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ven10_cg_regs, \
+ .vote_regs = &ven10_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = (_flags) | \
+ CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VOTE_VEN10(_id, _name, _parent, _shift) \
+ GATE_VOTE_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_VEN11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ven11_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_VEN11_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VEN11(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ven11_cg_regs, \
+ .vote_regs = &ven11_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE \
+ }
+
+static const struct mtk_gate ven1_clks[] = {
+ /* VEN10 */
+ GATE_VOTE_VEN10(CLK_VEN1_CKE0_LARB, "ven1_larb", "ck2_venc_ck", 0),
+ GATE_VEN10_V(CLK_VEN1_CKE0_LARB_VENC, "ven1_larb_venc", "ven1_larb"),
+ GATE_VEN10_V(CLK_VEN1_CKE0_LARB_JPGENC, "ven1_larb_jpgenc", "ven1_larb"),
+ GATE_VEN10_V(CLK_VEN1_CKE0_LARB_JPGDEC, "ven1_larb_jpgdec", "ven1_larb"),
+ GATE_VEN10_V(CLK_VEN1_CKE0_LARB_SMI, "ven1_larb_smi", "ven1_larb"),
+ GATE_VOTE_VEN10(CLK_VEN1_CKE1_VENC, "ven1_venc", "ck2_venc_ck", 4),
+ GATE_VEN10_V(CLK_VEN1_CKE1_VENC_VENC, "ven1_venc_venc", "ven1_venc"),
+ GATE_VEN10_V(CLK_VEN1_CKE1_VENC_SMI, "ven1_venc_smi", "ven1_venc"),
+ GATE_VEN10(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "ck2_venc_ck", 8),
+ GATE_VEN10_V(CLK_VEN1_CKE2_JPGENC_JPGENC, "ven1_jpgenc_jpgenc", "ven1_jpgenc"),
+ GATE_VEN10(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "ck2_venc_ck", 12),
+ GATE_VEN10_V(CLK_VEN1_CKE3_JPGDEC_JPGDEC, "ven1_jpgdec_jpgdec", "ven1_jpgdec"),
+ GATE_VEN10(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "ck2_venc_ck", 16),
+ GATE_VEN10_V(CLK_VEN1_CKE4_JPGDEC_C1_JPGDEC, "ven1_jpgdec_c1_jpgdec", "ven1_jpgdec_c1"),
+ GATE_VOTE_VEN10(CLK_VEN1_CKE5_GALS, "ven1_gals", "ck2_venc_ck", 28),
+ GATE_VEN10_V(CLK_VEN1_CKE5_GALS_VENC, "ven1_gals_venc", "ven1_gals"),
+ GATE_VEN10_V(CLK_VEN1_CKE5_GALS_JPGENC, "ven1_gals_jpgenc", "ven1_gals"),
+ GATE_VEN10_V(CLK_VEN1_CKE5_GALS_JPGDEC, "ven1_gals_jpgdec", "ven1_gals"),
+ GATE_VOTE_VEN10(CLK_VEN1_CKE29_VENC_ADAB_CTRL, "ven1_venc_adab_ctrl", "ck2_venc_ck", 29),
+ GATE_VEN10_V(CLK_VEN1_CKE29_VENC_ADAB_CTRL_VENC, "ven1_venc_adab_ctrl_venc",
+ "ven1_venc_adab_ctrl"),
+ GATE_VOTE_VEN10_FLAGS(CLK_VEN1_CKE29_VENC_XPC_CTRL, "ven1_venc_xpc_ctrl",
+ "ck2_venc_ck", 30, CLK_IGNORE_UNUSED),
+ GATE_VEN10_V(CLK_VEN1_CKE29_VENC_XPC_CTRL_VENC, "ven1_venc_xpc_ctrl_venc",
+ "ven1_venc_xpc_ctrl"),
+ GATE_VEN10_V(CLK_VEN1_CKE29_VENC_XPC_CTRL_JPGENC, "ven1_venc_xpc_ctrl_jpgenc",
+ "ven1_venc_xpc_ctrl"),
+ GATE_VEN10_V(CLK_VEN1_CKE29_VENC_XPC_CTRL_JPGDEC, "ven1_venc_xpc_ctrl_jpgdec",
+ "ven1_venc_xpc_ctrl"),
+ GATE_VOTE_VEN10(CLK_VEN1_CKE6_GALS_SRAM, "ven1_gals_sram", "ck2_venc_ck", 31),
+ GATE_VEN10_V(CLK_VEN1_CKE6_GALS_SRAM_VENC, "ven1_gals_sram_venc", "ven1_gals_sram"),
+ /* VEN11 */
+ GATE_VOTE_VEN11(CLK_VEN1_RES_FLAT, "ven1_res_flat", "ck2_venc_ck", 0),
+ GATE_VEN11_V(CLK_VEN1_RES_FLAT_VENC, "ven1_res_flat_venc", "ven1_res_flat"),
+ GATE_VEN11_V(CLK_VEN1_RES_FLAT_JPGENC, "ven1_res_flat_jpgenc", "ven1_res_flat"),
+ GATE_VEN11_V(CLK_VEN1_RES_FLAT_JPGDEC, "ven1_res_flat_jpgdec", "ven1_res_flat"),
+};
+
+static const struct mtk_clk_desc ven1_mcd = {
+ .clks = ven1_clks,
+ .num_clks = ARRAY_SIZE(ven1_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct mtk_gate_regs ven20_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs ven20_vote_regs = {
+ .set_ofs = 0x00c8,
+ .clr_ofs = 0x00cc,
+ .sta_ofs = 0x2c64,
+};
+
+static const struct mtk_gate_regs ven21_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs ven21_vote_regs = {
+ .set_ofs = 0x00d0,
+ .clr_ofs = 0x00d4,
+ .sta_ofs = 0x2c68,
+};
+
+#define GATE_VEN20(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ven20_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VEN20_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VEN20(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ven20_cg_regs, \
+ .vote_regs = &ven20_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VEN21(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ven21_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_VEN21_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VEN21(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ven21_cg_regs, \
+ .vote_regs = &ven21_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE \
+ }
+
+static const struct mtk_gate ven2_clks[] = {
+ /* VEN20 */
+ GATE_VOTE_VEN20(CLK_VEN2_CKE0_LARB, "ven2_larb", "ck2_venc_ck", 0),
+ GATE_VEN20_V(CLK_VEN2_CKE0_LARB_VENC, "ven2_larb_venc", "ven2_larb"),
+ GATE_VEN20_V(CLK_VEN2_CKE0_LARB_JPGENC, "ven2_larb_jpgenc", "ven2_larb"),
+ GATE_VEN20_V(CLK_VEN2_CKE0_LARB_JPGDEC, "ven2_larb_jpgdec", "ven2_larb"),
+ GATE_VEN20_V(CLK_VEN2_CKE0_LARB_SMI, "ven2_larb_smi", "ven2_larb"),
+ GATE_VOTE_VEN20(CLK_VEN2_CKE1_VENC, "ven2_venc", "ck2_venc_ck", 4),
+ GATE_VEN20_V(CLK_VEN2_CKE1_VENC_VENC, "ven2_venc_venc", "ven2_venc"),
+ GATE_VEN20_V(CLK_VEN2_CKE1_VENC_SMI, "ven2_venc_smi", "ven2_venc"),
+ GATE_VEN20(CLK_VEN2_CKE2_JPGENC, "ven2_jpgenc", "ck2_venc_ck", 8),
+ GATE_VEN20_V(CLK_VEN2_CKE2_JPGENC_JPGENC, "ven2_jpgenc_jpgenc", "ven2_jpgenc"),
+ GATE_VEN20(CLK_VEN2_CKE3_JPGDEC, "ven2_jpgdec", "ck2_venc_ck", 12),
+ GATE_VEN20_V(CLK_VEN2_CKE3_JPGDEC_JPGDEC, "ven2_jpgdec_jpgdec", "ven2_jpgdec"),
+ GATE_VOTE_VEN20(CLK_VEN2_CKE5_GALS, "ven2_gals", "ck2_venc_ck", 28),
+ GATE_VEN20_V(CLK_VEN2_CKE5_GALS_VENC, "ven2_gals_venc", "ven2_gals"),
+ GATE_VEN20_V(CLK_VEN2_CKE5_GALS_JPGENC, "ven2_gals_jpgenc", "ven2_gals"),
+ GATE_VEN20_V(CLK_VEN2_CKE5_GALS_JPGDEC, "ven2_gals_jpgdec", "ven2_gals"),
+ GATE_VOTE_VEN20(CLK_VEN2_CKE29_VENC_XPC_CTRL, "ven2_venc_xpc_ctrl", "ck2_venc_ck", 30),
+ GATE_VEN20_V(CLK_VEN2_CKE29_VENC_XPC_CTRL_VENC, "ven2_venc_xpc_ctrl_venc",
+ "ven2_venc_xpc_ctrl"),
+ GATE_VEN20_V(CLK_VEN2_CKE29_VENC_XPC_CTRL_JPGENC, "ven2_venc_xpc_ctrl_jpgenc",
+ "ven2_venc_xpc_ctrl"),
+ GATE_VEN20_V(CLK_VEN2_CKE29_VENC_XPC_CTRL_JPGDEC, "ven2_venc_xpc_ctrl_jpgdec",
+ "ven2_venc_xpc_ctrl"),
+ GATE_VOTE_VEN20(CLK_VEN2_CKE6_GALS_SRAM, "ven2_gals_sram", "ck2_venc_ck", 31),
+ GATE_VEN20_V(CLK_VEN2_CKE6_GALS_SRAM_VENC, "ven2_gals_sram_venc", "ven2_gals_sram"),
+ /* VEN21 */
+ GATE_VOTE_VEN21(CLK_VEN2_RES_FLAT, "ven2_res_flat", "ck2_venc_ck", 0),
+ GATE_VEN21_V(CLK_VEN2_RES_FLAT_VENC, "ven2_res_flat_venc", "ven2_res_flat"),
+ GATE_VEN21_V(CLK_VEN2_RES_FLAT_JPGENC, "ven2_res_flat_jpgenc", "ven2_res_flat"),
+ GATE_VEN21_V(CLK_VEN2_RES_FLAT_JPGDEC, "ven2_res_flat_jpgdec", "ven2_res_flat"),
+};
+
+static const struct mtk_clk_desc ven2_mcd = {
+ .clks = ven2_clks,
+ .num_clks = ARRAY_SIZE(ven2_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct mtk_gate_regs ven_c20_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs ven_c20_vote_regs = {
+ .set_ofs = 0x00d8,
+ .clr_ofs = 0x00dc,
+ .sta_ofs = 0x2c6c,
+};
+
+static const struct mtk_gate_regs ven_c21_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs ven_c21_vote_regs = {
+ .set_ofs = 0x00e0,
+ .clr_ofs = 0x00e4,
+ .sta_ofs = 0x2c70,
+};
+
+#define GATE_VEN_C20(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ven_c20_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VEN_C20_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VEN_C20(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ven_c20_cg_regs, \
+ .vote_regs = &ven_c20_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote_inv, \
+ .dma_ops = &mtk_clk_gate_ops_setclr_inv,\
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+#define GATE_VEN_C21(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &ven_c21_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_OPS_PARENT_ENABLE, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_VEN_C21_V(_id, _name, _parent) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
+#define GATE_VOTE_VEN_C21(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .vote_comp = "mm-vote-regmap", \
+ .regs = &ven_c21_cg_regs, \
+ .vote_regs = &ven_c21_vote_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_vote, \
+ .dma_ops = &mtk_clk_gate_ops_setclr, \
+ .flags = CLK_USE_VOTE | \
+ CLK_OPS_PARENT_ENABLE, \
+ }
+
+static const struct mtk_gate ven_c2_clks[] = {
+ /* VEN_C20 */
+ GATE_VOTE_VEN_C20(CLK_VEN_C2_CKE0_LARB, "ven_c2_larb", "ck2_venc_ck", 0),
+ GATE_VEN_C20_V(CLK_VEN_C2_CKE0_LARB_VENC, "ven_c2_larb_venc", "ven_c2_larb"),
+ GATE_VEN_C20_V(CLK_VEN_C2_CKE0_LARB_SMI, "ven_c2_larb_smi", "ven_c2_larb"),
+ GATE_VOTE_VEN_C20(CLK_VEN_C2_CKE1_VENC, "ven_c2_venc", "ck2_venc_ck", 4),
+ GATE_VEN_C20_V(CLK_VEN_C2_CKE1_VENC_VENC, "ven_c2_venc_venc", "ven_c2_venc"),
+ GATE_VEN_C20_V(CLK_VEN_C2_CKE1_VENC_SMI, "ven_c2_venc_smi", "ven_c2_venc"),
+ GATE_VOTE_VEN_C20(CLK_VEN_C2_CKE5_GALS, "ven_c2_gals", "ck2_venc_ck", 28),
+ GATE_VEN_C20_V(CLK_VEN_C2_CKE5_GALS_VENC, "ven_c2_gals_venc", "ven_c2_gals"),
+ GATE_VOTE_VEN_C20(CLK_VEN_C2_CKE29_VENC_XPC_CTRL, "ven_c2_venc_xpc_ctrl",
+ "ck2_venc_ck", 30),
+ GATE_VEN_C20_V(CLK_VEN_C2_CKE29_VENC_XPC_CTRL_VENC, "ven_c2_venc_xpc_ctrl_venc",
+ "ven_c2_venc_xpc_ctrl"),
+ GATE_VOTE_VEN_C20(CLK_VEN_C2_CKE6_GALS_SRAM, "ven_c2_gals_sram", "ck2_venc_ck", 31),
+ GATE_VEN_C20_V(CLK_VEN_C2_CKE6_GALS_SRAM_VENC, "ven_c2_gals_sram_venc", "ven_c2_gals_sram"),
+ /* VEN_C21 */
+ GATE_VOTE_VEN_C21(CLK_VEN_C2_RES_FLAT, "ven_c2_res_flat", "ck2_venc_ck", 0),
+ GATE_VEN_C21_V(CLK_VEN_C2_RES_FLAT_VENC, "ven_c2_res_flat_venc", "ven_c2_res_flat"),
+};
+
+static const struct mtk_clk_desc ven_c2_mcd = {
+ .clks = ven_c2_clks,
+ .num_clks = ARRAY_SIZE(ven_c2_clks),
+ .need_runtime_pm = true,
+};
+
+static const struct of_device_id of_match_clk_mt8196_venc[] = {
+ { .compatible = "mediatek,mt8196-vencsys", .data = &ven1_mcd, },
+ { .compatible = "mediatek,mt8196-vencsys_c1", .data = &ven2_mcd, },
+ { .compatible = "mediatek,mt8196-vencsys_c2", .data = &ven_c2_mcd, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8196_venc_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8196-venc",
+ .of_match_table = of_match_clk_mt8196_venc,
+ },
+};
+
+module_platform_driver(clk_mt8196_venc_drv);
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock
2025-03-07 3:27 ` [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock Guangjie Song
@ 2025-03-07 4:16 ` Rob Herring (Arm)
2025-03-07 7:29 ` Krzysztof Kozlowski
2025-04-16 9:20 ` Chen-Yu Tsai
2 siblings, 0 replies; 34+ messages in thread
From: Rob Herring (Arm) @ 2025-03-07 4:16 UTC (permalink / raw)
To: Guangjie Song
Cc: Conor Dooley, Michael Turquette, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
AngeloGioacchino Del Regno, Stephen Boyd, Krzysztof Kozlowski,
linux-kernel, linux-mediatek, Richard Cochran, linux-clk, netdev,
devicetree
On Fri, 07 Mar 2025 11:27:02 +0800, Guangjie Song wrote:
> Add the new binding documentation for system clock and functional clock
> on Mediatek MT8196.
>
> Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
> ---
> .../bindings/clock/mediatek,mt8196-clock.yaml | 66 +
> .../clock/mediatek,mt8196-sys-clock.yaml | 63 +
> include/dt-bindings/clock/mt8196-clk.h | 1503 +++++++++++++++++
> 3 files changed, 1632 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
> create mode 100644 include/dt-bindings/clock/mt8196-clk.h
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.example.dtb: clock-controller@10000800: reg: [[0, 268437504], [0, 4096]] is too long
from schema $id: http://devicetree.org/schemas/mfd/syscon-common.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250307032942.10447-7-guangjie.song@mediatek.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock
2025-03-07 3:27 ` [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock Guangjie Song
2025-03-07 4:16 ` Rob Herring (Arm)
@ 2025-03-07 7:29 ` Krzysztof Kozlowski
2025-04-16 9:20 ` Chen-Yu Tsai
2 siblings, 0 replies; 34+ messages in thread
From: Krzysztof Kozlowski @ 2025-03-07 7:29 UTC (permalink / raw)
To: Guangjie Song
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, netdev,
Project_Global_Chrome_Upstream_Group
On Fri, Mar 07, 2025 at 11:27:02AM +0800, Guangjie Song wrote:
> Add the new binding documentation for system clock and functional clock
> on Mediatek MT8196.
>
> Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
> ---
> .../bindings/clock/mediatek,mt8196-clock.yaml | 66 +
> .../clock/mediatek,mt8196-sys-clock.yaml | 63 +
> include/dt-bindings/clock/mt8196-clk.h | 1503 +++++++++++++++++
Filename matching binding, so mediatek,mt8196-clock.h
I would not even dream about people testing patches before sending
them...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 21/26] clk: mediatek: Add MT8196 ovl0 clock support
2025-03-07 3:27 ` [PATCH 21/26] clk: mediatek: Add MT8196 ovl0 " Guangjie Song
@ 2025-03-07 7:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 34+ messages in thread
From: Krzysztof Kozlowski @ 2025-03-07 7:29 UTC (permalink / raw)
To: Guangjie Song
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, netdev,
Project_Global_Chrome_Upstream_Group
On Fri, Mar 07, 2025 at 11:27:17AM +0800, Guangjie Song wrote:
> +
> +static struct platform_driver clk_mt8196_ovl0_drv = {
> + .probe = mtk_clk_pdev_probe,
> + .remove = mtk_clk_pdev_remove,
> + .driver = {
> + .name = "clk-mt8196-ovl0",
> + },
> + .id_table = clk_mt8196_ovl0_id_table,
> +};
> +
> +module_platform_driver(clk_mt8196_ovl0_drv);
> +MODULE_LICENSE("GPL");
You have warnings here about missing description. Build your code with
W=1.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 03/26] clk: mediatek: Support voting for mux
2025-03-07 3:26 ` [PATCH 03/26] clk: mediatek: Support voting for mux Guangjie Song
@ 2025-03-10 14:12 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 34+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-03-10 14:12 UTC (permalink / raw)
To: Guangjie Song, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Project_Global_Chrome_Upstream_Group
Il 07/03/25 04:26, Guangjie Song ha scritto:
> Add data fields, defines and ops to support voting for mux.
>
The main thing that is missing here is an answer to an obvious question....
...what are the advantages of hardware voting, and why do we need to use
HW voting instead of the refcount that is already kept by the common clock
framework?
As far as I can see here, the only difference is that the enable/disable
is more complex, losing more time for polling after writes and nothing else?
Is this to synchronize the clock voting between SCP and AP or what?!
If this is the answer, I don't see why we should use this HW voter for all
clocks, since it's simply more expensive (so the clock drivers are wrong as
they enable the voter for all clocks).
> Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
> ---
> drivers/clk/mediatek/clk-mux.c | 198 ++++++++++++++++++++++++++++++++-
> drivers/clk/mediatek/clk-mux.h | 79 +++++++++++++
> 2 files changed, 275 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
> index 60990296450b..8a2c89cb3cd5 100644
> --- a/drivers/clk/mediatek/clk-mux.c
> +++ b/drivers/clk/mediatek/clk-mux.c
> @@ -15,11 +15,13 @@
> #include <linux/spinlock.h>
> #include <linux/slab.h>
>
> +#include "clk-mtk.h"
> #include "clk-mux.h"
>
> struct mtk_clk_mux {
> struct clk_hw hw;
> struct regmap *regmap;
> + struct regmap *vote_regmap;
> const struct mtk_mux *data;
> spinlock_t *lock;
> bool reparent;
> @@ -30,6 +32,46 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
> return container_of(hw, struct mtk_clk_mux, hw);
> }
>
> +static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + unsigned long flags = 0;
> + u32 val = 0;
> + int i = 0;
> + int ret = 0;
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_write(mux->regmap, mux->data->clr_ofs, BIT(mux->data->gate_shift));
> +
> + while (1) {
> + regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
Why are you reinventing the wheel instead of just using regmap_read_poll_timeout()?
> +
> + if ((val & BIT(mux->data->fenc_shift)) != 0)
> + break;
> +
> + if (i < MTK_WAIT_FENC_DONE_CNT) {
> + udelay(MTK_WAIT_FENC_DONE_US);
> + } else {
> + pr_err("%s wait fenc done timeout\n", clk_hw_get_name(hw));
> + ret = -EBUSY;
> + break;
> + }
> +
> + i++;
> + }
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return ret;
> +}
> +
> static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
> {
> struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> @@ -70,6 +112,16 @@ static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
> BIT(mux->data->gate_shift));
> }
>
> +static int mtk_clk_mux_fenc_is_enabled(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val = 0;
> +
> + regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
> +
> + return (val & BIT(mux->data->fenc_shift)) != 0;
That's just `return val & BIT(mux->data->fenc_shift);` ...
> +}
> +
> static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
> {
> struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> @@ -80,6 +132,106 @@ static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
> return (val & BIT(mux->data->gate_shift)) == 0;
> }
>
> +static int mtk_clk_vote_mux_is_enabled(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val = 0;
> +
> + regmap_read(mux->vote_regmap, mux->data->vote_set_ofs, &val);
> +
> + return (val & BIT(mux->data->gate_shift)) != 0;
same
> +}
> +
> +static int mtk_clk_vote_mux_is_done(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val = 0;
> +
> + regmap_read(mux->vote_regmap, mux->data->vote_sta_ofs, &val);
> +
> + return (val & BIT(mux->data->gate_shift)) != 0;
ditto
> +}
> +
> +static int mtk_clk_mux_vote_fenc_enable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val = 0, val2 = 0;
> + bool is_done = false;
> + int i = 0;
> +
> + regmap_write(mux->vote_regmap, mux->data->vote_set_ofs, BIT(mux->data->gate_shift));
> +
> + while (!mtk_clk_vote_mux_is_enabled(hw)) {
> + if (i < MTK_WAIT_VOTE_PREPARE_CNT) {
> + udelay(MTK_WAIT_VOTE_PREPARE_US);
regmap_readl_poll_timeout().....
> + } else {
> + pr_err("%s mux prepare timeout(%x)\n", clk_hw_get_name(hw), val);
> + return -EBUSY;
> + }
> +
> + i++;
> + }
> +
> + i = 0;
> +
> + while (1) {
> + if (!is_done)
> + regmap_read(mux->vote_regmap, mux->data->vote_sta_ofs, &val);
> +
> + if (((val & BIT(mux->data->gate_shift)) != 0))
> + is_done = true;
> +
and again - twice.
> + if (is_done) {
> + regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val2);
> + if ((val2 & BIT(mux->data->fenc_shift)) != 0)
> + break;
> + }
> +
> + if (i < MTK_WAIT_VOTE_DONE_CNT) {
> + udelay(MTK_WAIT_VOTE_DONE_US);
> + } else {
> + pr_err("%s mux enable timeout(%x %x)\n", clk_hw_get_name(hw), val, val2);
> + return -EBUSY;
> + }
> +
> + i++;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_clk_mux_vote_disable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + int i = 0;
> +
> + regmap_write(mux->vote_regmap, mux->data->vote_clr_ofs, BIT(mux->data->gate_shift));
> +
> + while (mtk_clk_vote_mux_is_enabled(hw)) {
> + if (i < MTK_WAIT_VOTE_PREPARE_CNT) {
> + udelay(MTK_WAIT_VOTE_PREPARE_US);
> + } else {
> + pr_err("%s mux unprepare timeout\n", clk_hw_get_name(hw));
> + return;
> + }
> +
....and again....
> + i++;
> + }
> +
> + i = 0;
> +
> + while (!mtk_clk_vote_mux_is_done(hw)) {
> + if (i < MTK_WAIT_VOTE_DONE_CNT) {
> + udelay(MTK_WAIT_VOTE_DONE_US);
> + } else {
> + pr_err("%s mux disable timeout\n", clk_hw_get_name(hw));
> + return;
> + }
> +
> + i++;
> + }
> +}
> +
> static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
> {
> struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> @@ -151,6 +303,12 @@ static int mtk_clk_mux_determine_rate(struct clk_hw *hw,
> return clk_mux_determine_rate_flags(hw, req, mux->data->flags);
> }
>
> +static void mtk_clk_mux_vote_fenc_disable_unused(struct clk_hw *hw)
> +{
> + mtk_clk_mux_vote_fenc_enable(hw);
> + mtk_clk_mux_vote_disable(hw);
Why would you need to enable and disable?
If this is not a mistake... this definitely needs a comment in the code.
> +}
> +
> const struct clk_ops mtk_mux_clr_set_upd_ops = {
> .get_parent = mtk_clk_mux_get_parent,
> .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> @@ -168,9 +326,31 @@ const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
> };
> EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
>
> +const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops = {
> + .enable = mtk_clk_mux_fenc_enable_setclr,
> + .disable = mtk_clk_mux_disable_setclr,
> + .is_enabled = mtk_clk_mux_fenc_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> + .determine_rate = mtk_clk_mux_determine_rate,
> +};
> +EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops);
> +
> +const struct clk_ops mtk_mux_vote_fenc_ops = {
> + .enable = mtk_clk_mux_vote_fenc_enable,
> + .disable = mtk_clk_mux_vote_disable,
> + .is_enabled = mtk_clk_mux_fenc_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> + .determine_rate = mtk_clk_mux_determine_rate,
> + .disable_unused = mtk_clk_mux_vote_fenc_disable_unused,
> +};
> +EXPORT_SYMBOL_GPL(mtk_mux_vote_fenc_ops);
> +
> static struct clk_hw *mtk_clk_register_mux(struct device *dev,
> const struct mtk_mux *mux,
> struct regmap *regmap,
> + struct regmap *vote_regmap,
> spinlock_t *lock)
> {
> struct mtk_clk_mux *clk_mux;
> @@ -185,9 +365,17 @@ static struct clk_hw *mtk_clk_register_mux(struct device *dev,
> init.flags = mux->flags;
> init.parent_names = mux->parent_names;
> init.num_parents = mux->num_parents;
> - init.ops = mux->ops;
> + if (mux->flags & CLK_USE_VOTE) {
> + if (vote_regmap)
> + init.ops = mux->ops;
> + else
> + init.ops = mux->dma_ops;
Sorry why is this called dma_ops?!
That's at least confusing, if not simply wrong.... please explain.
> + } else {
> + init.ops = mux->ops;
> + }
>
> clk_mux->regmap = regmap;
> + clk_mux->vote_regmap = vote_regmap;
> clk_mux->data = mux;
> clk_mux->lock = lock;
> clk_mux->hw.init = &init;
> @@ -220,6 +408,7 @@ int mtk_clk_register_muxes(struct device *dev,
> struct clk_hw_onecell_data *clk_data)
> {
> struct regmap *regmap;
> + struct regmap *vote_regmap = NULL;
> struct clk_hw *hw;
> int i;
>
> @@ -238,8 +427,13 @@ int mtk_clk_register_muxes(struct device *dev,
> continue;
> }
>
> - hw = mtk_clk_register_mux(dev, mux, regmap, lock);
> + if (mux->vote_comp) {
> + vote_regmap = syscon_regmap_lookup_by_phandle(node, mux->vote_comp);
> + if (IS_ERR(vote_regmap))
> + vote_regmap = NULL;
> + }
>
> + hw = mtk_clk_register_mux(dev, mux, regmap, vote_regmap, lock);
...and this change just breaks each and every MediaTek SoC that is currently
supported upstream.
Please test your changes on older platforms before submitting upstream.
Regards,
Angelo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 07/26] clk: mediatek: Add MT8196 apmixedsys clock support
2025-03-07 3:27 ` [PATCH 07/26] clk: mediatek: Add MT8196 apmixedsys clock support Guangjie Song
@ 2025-03-11 17:05 ` Jeff Johnson
0 siblings, 0 replies; 34+ messages in thread
From: Jeff Johnson @ 2025-03-11 17:05 UTC (permalink / raw)
To: Guangjie Song, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Richard Cochran
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Project_Global_Chrome_Upstream_Group
On 3/6/25 19:27, Guangjie Song wrote:
> +module_platform_driver(clk_mt8196_apmixed_drv);
> +MODULE_LICENSE("GPL");
Since commit 1fffe7a34c89 ("script: modpost: emit a warning when the
description is missing"), a module without a MODULE_DESCRIPTION() will
result in a warning with make W=1. Please add a MODULE_DESCRIPTION()
to avoid this warning.
This is a canned review based upon finding a MODULE_LICENSE without a
MODULE_DESCRIPTION.
Note this issue appears in multiple patches in this series, so please
fix all instances.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 09/26] clk: mediatek: Add MT8196 topckgen clock support
2025-03-07 3:27 ` [PATCH 09/26] clk: mediatek: Add MT8196 topckgen " Guangjie Song
@ 2025-04-16 9:04 ` Chen-Yu Tsai
0 siblings, 0 replies; 34+ messages in thread
From: Chen-Yu Tsai @ 2025-04-16 9:04 UTC (permalink / raw)
To: Guangjie Song
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, netdev,
Project_Global_Chrome_Upstream_Group
On Fri, Mar 7, 2025 at 11:35 AM Guangjie Song
<guangjie.song@mediatek.com> wrote:
>
> Add MT8196 topckgen clock controller which provides muxes and dividers
> to handle variety clock selection in other IP blocks.
>
> Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 3 +-
> drivers/clk/mediatek/clk-mt8196-topckgen.c | 1373 ++++++++++++++++++++
> 2 files changed, 1375 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 247bad396cfb..cd6f42a6fd10 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -150,7 +150,8 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o
> obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
> obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
> obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
> -obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o
> +obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys_gp2.o \
> + clk-mt8196-topckgen.o
> obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
> obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
> obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8196-topckgen.c b/drivers/clk/mediatek/clk-mt8196-topckgen.c
> new file mode 100644
> index 000000000000..41c5431561fe
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8196-topckgen.c
> @@ -0,0 +1,1373 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + * Author: Guangjie Song <guangjie.song@mediatek.com>
> + */
> +#include <dt-bindings/clock/mt8196-clk.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +/* MUX SEL REG */
> +#define CLK_CFG_UPDATE 0x0004
> +#define CLK_CFG_UPDATE1 0x0008
> +#define CLK_CFG_UPDATE2 0x000c
> +#define CLK_CFG_0 0x0010
> +#define CLK_CFG_0_SET 0x0014
> +#define CLK_CFG_0_CLR 0x0018
> +#define CLK_CFG_1 0x0020
> +#define CLK_CFG_1_SET 0x0024
> +#define CLK_CFG_1_CLR 0x0028
> +#define CLK_CFG_2 0x0030
> +#define CLK_CFG_2_SET 0x0034
> +#define CLK_CFG_2_CLR 0x0038
> +#define CLK_CFG_3 0x0040
> +#define CLK_CFG_3_SET 0x0044
> +#define CLK_CFG_3_CLR 0x0048
> +#define CLK_CFG_4 0x0050
> +#define CLK_CFG_4_SET 0x0054
> +#define CLK_CFG_4_CLR 0x0058
> +#define CLK_CFG_5 0x0060
> +#define CLK_CFG_5_SET 0x0064
> +#define CLK_CFG_5_CLR 0x0068
> +#define CLK_CFG_6 0x0070
> +#define CLK_CFG_6_SET 0x0074
> +#define CLK_CFG_6_CLR 0x0078
> +#define CLK_CFG_7 0x0080
> +#define CLK_CFG_7_SET 0x0084
> +#define CLK_CFG_7_CLR 0x0088
> +#define CLK_CFG_8 0x0090
> +#define CLK_CFG_8_SET 0x0094
> +#define CLK_CFG_8_CLR 0x0098
> +#define CLK_CFG_9 0x00a0
> +#define CLK_CFG_9_SET 0x00a4
> +#define CLK_CFG_9_CLR 0x00a8
> +#define CLK_CFG_10 0x00b0
> +#define CLK_CFG_10_SET 0x00b4
> +#define CLK_CFG_10_CLR 0x00b8
> +#define CLK_CFG_11 0x00c0
> +#define CLK_CFG_11_SET 0x00c4
> +#define CLK_CFG_11_CLR 0x00c8
> +#define CLK_CFG_12 0x00d0
> +#define CLK_CFG_12_SET 0x00d4
> +#define CLK_CFG_12_CLR 0x00d8
> +#define CLK_CFG_13 0x00e0
> +#define CLK_CFG_13_SET 0x00e4
> +#define CLK_CFG_13_CLR 0x00e8
> +#define CLK_CFG_14 0x00f0
> +#define CLK_CFG_14_SET 0x00f4
> +#define CLK_CFG_14_CLR 0x00f8
> +#define CLK_CFG_15 0x0100
> +#define CLK_CFG_15_SET 0x0104
> +#define CLK_CFG_15_CLR 0x0108
> +#define CLK_CFG_16 0x0110
> +#define CLK_CFG_16_SET 0x0114
> +#define CLK_CFG_16_CLR 0x0118
> +#define CLK_CFG_17 0x0120
> +#define CLK_CFG_17_SET 0x0124
> +#define CLK_CFG_17_CLR 0x0128
> +#define CLK_CFG_18 0x0130
> +#define CLK_CFG_18_SET 0x0134
> +#define CLK_CFG_18_CLR 0x0138
> +#define CLK_CFG_19 0x0140
> +#define CLK_CFG_19_SET 0x0144
> +#define CLK_CFG_19_CLR 0x0148
> +#define CLK_AUDDIV_0 0x020c
> +#define CLK_FENC_STATUS_MON_0 0x0270
> +#define CLK_FENC_STATUS_MON_1 0x0274
> +#define CLK_FENC_STATUS_MON_2 0x0278
> +
> +/* MUX SHIFT */
> +#define TOP_MUX_AXI_SHIFT 0
> +#define TOP_MUX_MEM_SUB_SHIFT 1
> +#define TOP_MUX_IO_NOC_SHIFT 2
> +#define TOP_MUX_PERI_AXI_SHIFT 3
> +#define TOP_MUX_UFS_PEXTP0_AXI_SHIFT 4
> +#define TOP_MUX_PEXTP1_USB_AXI_SHIFT 5
> +#define TOP_MUX_PERI_FMEM_SUB_SHIFT 6
> +#define TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT 7
> +#define TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT 8
> +#define TOP_MUX_PERI_NOC_SHIFT 9
> +#define TOP_MUX_EMI_N_SHIFT 10
> +#define TOP_MUX_EMI_S_SHIFT 11
> +#define TOP_MUX_AP2CONN_HOST_SHIFT 14
> +#define TOP_MUX_ATB_SHIFT 15
> +#define TOP_MUX_CIRQ_SHIFT 16
> +#define TOP_MUX_PBUS_156M_SHIFT 17
> +#define TOP_MUX_EFUSE_SHIFT 20
> +#define TOP_MUX_MCU_L3GIC_SHIFT 21
> +#define TOP_MUX_MCU_INFRA_SHIFT 22
> +#define TOP_MUX_DSP_SHIFT 23
> +#define TOP_MUX_MFG_REF_SHIFT 24
> +#define TOP_MUX_MFG_EB_SHIFT 26
> +#define TOP_MUX_UART_SHIFT 27
> +#define TOP_MUX_SPI0_BCLK_SHIFT 28
> +#define TOP_MUX_SPI1_BCLK_SHIFT 29
> +#define TOP_MUX_SPI2_BCLK_SHIFT 30
> +#define TOP_MUX_SPI3_BCLK_SHIFT 0
> +#define TOP_MUX_SPI4_BCLK_SHIFT 1
> +#define TOP_MUX_SPI5_BCLK_SHIFT 2
> +#define TOP_MUX_SPI6_BCLK_SHIFT 3
> +#define TOP_MUX_SPI7_BCLK_SHIFT 4
> +#define TOP_MUX_MSDC30_1_SHIFT 7
> +#define TOP_MUX_MSDC30_2_SHIFT 8
> +#define TOP_MUX_DISP_PWM_SHIFT 9
> +#define TOP_MUX_USB_TOP_1P_SHIFT 10
> +#define TOP_MUX_SSUSB_XHCI_1P_SHIFT 11
> +#define TOP_MUX_SSUSB_FMCNT_P1_SHIFT 12
> +#define TOP_MUX_I2C_PERI_SHIFT 13
> +#define TOP_MUX_I2C_EAST_SHIFT 14
> +#define TOP_MUX_I2C_WEST_SHIFT 15
> +#define TOP_MUX_I2C_NORTH_SHIFT 16
> +#define TOP_MUX_AES_UFSFDE_SHIFT 17
> +#define TOP_MUX_UFS_SHIFT 18
> +#define TOP_MUX_AUD_1_SHIFT 21
> +#define TOP_MUX_AUD_2_SHIFT 22
> +#define TOP_MUX_ADSP_SHIFT 23
> +#define TOP_MUX_ADSP_UARTHUB_BCLK_SHIFT 24
> +#define TOP_MUX_DPMAIF_MAIN_SHIFT 25
> +#define TOP_MUX_PWM_SHIFT 26
> +#define TOP_MUX_MCUPM_SHIFT 27
> +#define TOP_MUX_SFLASH_SHIFT 28
> +#define TOP_MUX_IPSEAST_SHIFT 29
> +#define TOP_MUX_TL_SHIFT 0
> +#define TOP_MUX_TL_P1_SHIFT 1
> +#define TOP_MUX_TL_P2_SHIFT 2
> +#define TOP_MUX_EMI_INTERFACE_546_SHIFT 3
> +#define TOP_MUX_SDF_SHIFT 4
> +#define TOP_MUX_UARTHUB_BCLK_SHIFT 5
> +#define TOP_MUX_DPSW_CMP_26M_SHIFT 6
> +#define TOP_MUX_SMAPCK_SHIFT 7
> +#define TOP_MUX_SSR_PKA_SHIFT 8
> +#define TOP_MUX_SSR_DMA_SHIFT 9
> +#define TOP_MUX_SSR_KDF_SHIFT 10
> +#define TOP_MUX_SSR_RNG_SHIFT 11
> +#define TOP_MUX_SPU0_SHIFT 12
> +#define TOP_MUX_SPU1_SHIFT 13
> +#define TOP_MUX_DXCC_SHIFT 14
> +
> +/* CKSTA REG */
> +#define CKSTA_REG 0x01c8
> +#define CKSTA_REG1 0x01cc
> +#define CKSTA_REG2 0x01d0
> +
> +/* DIVIDER REG */
> +#define CLK_AUDDIV_2 0x0214
> +#define CLK_AUDDIV_3 0x0220
> +#define CLK_AUDDIV_4 0x0224
> +#define CLK_AUDDIV_5 0x0228
> +
> +/* HW Voter REG */
> +#define VOTE_CG_0_SET 0x0000
> +#define VOTE_CG_0_CLR 0x0004
> +#define VOTE_CG_0_DONE 0x2c00
> +#define VOTE_CG_1_SET 0x0008
> +#define VOTE_CG_1_CLR 0x000c
> +#define VOTE_CG_1_DONE 0x2c04
> +#define VOTE_CG_2_SET 0x0010
> +#define VOTE_CG_2_CLR 0x0014
> +#define VOTE_CG_2_DONE 0x2c08
> +#define VOTE_CG_3_SET 0x0018
> +#define VOTE_CG_3_CLR 0x001c
> +#define VOTE_CG_3_DONE 0x2c0c
> +#define VOTE_CG_4_SET 0x0020
> +#define VOTE_CG_4_CLR 0x0024
> +#define VOTE_CG_4_DONE 0x2c10
> +#define VOTE_CG_5_SET 0x0028
> +#define VOTE_CG_5_CLR 0x002c
> +#define VOTE_CG_5_DONE 0x2c14
> +#define VOTE_CG_6_SET 0x0030
> +#define VOTE_CG_6_CLR 0x0034
> +#define VOTE_CG_6_DONE 0x2c18
> +#define VOTE_CG_7_SET 0x0038
> +#define VOTE_CG_7_CLR 0x003c
> +#define VOTE_CG_7_DONE 0x2c1c
> +#define VOTE_CG_8_SET 0x0040
> +#define VOTE_CG_8_CLR 0x0044
> +#define VOTE_CG_8_DONE 0x2c20
> +
> +static DEFINE_SPINLOCK(mt8196_clk_ck_lock);
> +
> +static const struct mtk_fixed_factor ck_divs[] = {
> + FACTOR(CLK_CK_MAINPLL_D3, "ck_mainpll_d3", "mainpll", 1, 3),
Please drop the "ck_" prefix from all clock names. Within the clock
framework and namespace, all names refer to clocks.
> + FACTOR(CLK_CK_MAINPLL_D4, "ck_mainpll_d4", "mainpll", 1, 4),
> + FACTOR(CLK_CK_MAINPLL_D4_D2, "ck_mainpll_d4_d2", "mainpll", 1, 8),
> + FACTOR(CLK_CK_MAINPLL_D4_D4, "ck_mainpll_d4_d4", "mainpll", 1, 16),
> + FACTOR(CLK_CK_MAINPLL_D4_D8, "ck_mainpll_d4_d8", "mainpll", 1, 32),
> + FACTOR(CLK_CK_MAINPLL_D5, "ck_mainpll_d5", "mainpll", 1, 5),
> + FACTOR(CLK_CK_MAINPLL_D5_D2, "ck_mainpll_d5_d2", "mainpll", 1, 10),
> + FACTOR(CLK_CK_MAINPLL_D5_D4, "ck_mainpll_d5_d4", "mainpll", 1, 20),
> + FACTOR(CLK_CK_MAINPLL_D5_D8, "ck_mainpll_d5_d8", "mainpll", 1, 40),
> + FACTOR(CLK_CK_MAINPLL_D6, "ck_mainpll_d6", "mainpll", 1, 6),
> + FACTOR(CLK_CK_MAINPLL_D6_D2, "ck_mainpll_d6_d2", "mainpll", 1, 12),
> + FACTOR(CLK_CK_MAINPLL_D7, "ck_mainpll_d7", "mainpll", 1, 7),
> + FACTOR(CLK_CK_MAINPLL_D7_D2, "ck_mainpll_d7_d2", "mainpll", 1, 14),
> + FACTOR(CLK_CK_MAINPLL_D7_D4, "ck_mainpll_d7_d4", "mainpll", 1, 28),
> + FACTOR(CLK_CK_MAINPLL_D7_D8, "ck_mainpll_d7_d8", "mainpll", 1, 56),
> + FACTOR(CLK_CK_MAINPLL_D9, "ck_mainpll_d9", "mainpll", 1, 9),
> + FACTOR(CLK_CK_UNIVPLL_D4, "ck_univpll_d4", "univpll", 1, 4),
> + FACTOR(CLK_CK_UNIVPLL_D4_D2, "ck_univpll_d4_d2", "univpll", 1, 8),
> + FACTOR(CLK_CK_UNIVPLL_D4_D4, "ck_univpll_d4_d4", "univpll", 1, 16),
> + FACTOR(CLK_CK_UNIVPLL_D4_D8, "ck_univpll_d4_d8", "univpll", 1, 32),
> + FACTOR(CLK_CK_UNIVPLL_D5, "ck_univpll_d5", "univpll", 1, 5),
> + FACTOR(CLK_CK_UNIVPLL_D5_D2, "ck_univpll_d5_d2", "univpll", 1, 10),
> + FACTOR(CLK_CK_UNIVPLL_D5_D4, "ck_univpll_d5_d4", "univpll", 1, 20),
> + FACTOR(CLK_CK_UNIVPLL_D6, "ck_univpll_d6", "univpll", 1, 6),
> + FACTOR(CLK_CK_UNIVPLL_D6_D2, "ck_univpll_d6_d2", "univpll", 1, 12),
> + FACTOR(CLK_CK_UNIVPLL_D6_D4, "ck_univpll_d6_d4", "univpll", 1, 24),
> + FACTOR(CLK_CK_UNIVPLL_D6_D8, "ck_univpll_d6_d8", "univpll", 1, 48),
> + FACTOR(CLK_CK_UNIVPLL_D6_D16, "ck_univpll_d6_d16", "univpll", 1, 96),
> + FACTOR(CLK_CK_UNIVPLL_192M, "ck_univpll_192m", "univpll", 1, 13),
> + FACTOR(CLK_CK_UNIVPLL_192M_D4, "ck_univpll_192m_d4", "univpll", 1, 52),
> + FACTOR(CLK_CK_UNIVPLL_192M_D8, "ck_univpll_192m_d8", "univpll", 1, 104),
> + FACTOR(CLK_CK_UNIVPLL_192M_D16, "ck_univpll_192m_d16", "univpll", 1, 208),
> + FACTOR(CLK_CK_UNIVPLL_192M_D32, "ck_univpll_192m_d32", "univpll", 1, 416),
> + FACTOR(CLK_CK_UNIVPLL_192M_D10, "ck_univpll_192m_d10", "univpll", 1, 130),
> + FACTOR(CLK_CK_APLL1, "ck_apll1_ck", "vlp_apll1", 1, 1),
Drop this, unless this actually depends on the topckgen block in some
way, such as power.
> + FACTOR(CLK_CK_APLL1_D4, "ck_apll1_d4", "vlp_apll1", 1, 4),
> + FACTOR(CLK_CK_APLL1_D8, "ck_apll1_d8", "vlp_apll1", 1, 8),
> + FACTOR(CLK_CK_APLL2, "ck_apll2_ck", "vlp_apll2", 1, 1),
Same.
> + FACTOR(CLK_CK_APLL2_D4, "ck_apll2_d4", "vlp_apll2", 1, 4),
> + FACTOR(CLK_CK_APLL2_D8, "ck_apll2_d8", "vlp_apll2", 1, 8),
> + FACTOR(CLK_CK_ADSPPLL, "ck_adsppll_ck", "adsppll", 1, 1),
> + FACTOR(CLK_CK_EMIPLL1, "ck_emipll1_ck", "emipll", 1, 1),
Same for these two.
> + FACTOR(CLK_CK_TVDPLL1_D2, "ck_tvdpll1_d2", "tvdpll1", 1, 2),
> + FACTOR(CLK_CK_MSDCPLL_D2, "ck_msdcpll_d2", "msdcpll", 1, 2),
> + FACTOR(CLK_CK_CLKRTC, "ck_clkrtc", "clk32k", 1, 1),
> + FACTOR(CLK_CK_TCK_26M_MX9, "ck_tck_26m_mx9_ck", "clk26m", 1, 1),
> + FACTOR(CLK_CK_F26M, "ck_f26m_ck", "clk26m", 1, 1),
> + FACTOR(CLK_CK_F26M_CK_D2, "ck_f26m_d2", "clk13m", 1, 1),
> + FACTOR(CLK_CK_OSC, "ck_osc", "ulposc", 1, 1),
Same for these five.
> + FACTOR(CLK_CK_OSC_D2, "ck_osc_d2", "ulposc", 1, 2),
> + FACTOR(CLK_CK_OSC_D3, "ck_osc_d3", "ulposc", 1, 3),
> + FACTOR(CLK_CK_OSC_D4, "ck_osc_d4", "ulposc", 1, 4),
> + FACTOR(CLK_CK_OSC_D5, "ck_osc_d5", "ulposc", 1, 5),
> + FACTOR(CLK_CK_OSC_D7, "ck_osc_d7", "ulposc", 1, 7),
> + FACTOR(CLK_CK_OSC_D8, "ck_osc_d8", "ulposc", 1, 8),
> + FACTOR(CLK_CK_OSC_D10, "ck_osc_d10", "ulposc", 1, 10),
> + FACTOR(CLK_CK_OSC_D14, "ck_osc_d14", "ulposc", 1, 14),
> + FACTOR(CLK_CK_OSC_D20, "ck_osc_d20", "ulposc", 1, 20),
> + FACTOR(CLK_CK_OSC_D32, "ck_osc_d32", "ulposc", 1, 32),
> + FACTOR(CLK_CK_OSC_D40, "ck_osc_d40", "ulposc", 1, 40),
Starting from here:
> + FACTOR(CLK_CK_OSC3, "ck_osc3", "ulposc3", 1, 1),
> + FACTOR(CLK_CK_P_AXI, "ck_p_axi_ck", "ck_p_axi_sel", 1, 1),
> + FACTOR(CLK_CK_PEXTP0_AXI, "ck_pextp0_axi_ck", "ck_pextp0_axi_sel", 1, 1),
> + FACTOR(CLK_CK_PEXTP1_USB_AXI, "ck_pextp1_usb_axi_ck", "ck_pextp1_usb_axi_sel", 1, 1),
> + FACTOR(CLK_CK_PEXPT0_MEM_SUB, "ck_pexpt0_mem_sub_ck", "ck_pexpt0_mem_sub_sel", 1, 1),
> + FACTOR(CLK_CK_PEXTP1_USB_MEM_SUB, "ck_pextp1_usb_mem_sub_ck", "ck_pextp1_usb_mem_sub_sel", 1, 1),
> + FACTOR(CLK_CK_UART, "ck_uart_ck", "ck_uart_sel", 1, 1),
> + FACTOR(CLK_CK_SPI0_BCLK, "ck_spi0_b_ck", "ck_spi0_b_sel", 1, 1),
> + FACTOR(CLK_CK_SPI1_BCLK, "ck_spi1_b_ck", "ck_spi1_b_sel", 1, 1),
> + FACTOR(CLK_CK_SPI2_BCLK, "ck_spi2_b_ck", "ck_spi2_b_sel", 1, 1),
> + FACTOR(CLK_CK_SPI3_BCLK, "ck_spi3_b_ck", "ck_spi3_b_sel", 1, 1),
> + FACTOR(CLK_CK_SPI4_BCLK, "ck_spi4_b_ck", "ck_spi4_b_sel", 1, 1),
> + FACTOR(CLK_CK_SPI5_BCLK, "ck_spi5_b_ck", "ck_spi5_b_sel", 1, 1),
> + FACTOR(CLK_CK_SPI6_BCLK, "ck_spi6_b_ck", "ck_spi6_b_sel", 1, 1),
> + FACTOR(CLK_CK_SPI7_BCLK, "ck_spi7_b_ck", "ck_spi7_b_sel", 1, 1),
> + FACTOR(CLK_CK_MSDC30_1, "ck_msdc30_1_ck", "ck_msdc30_1_sel", 1, 1),
> + FACTOR(CLK_CK_MSDC30_2, "ck_msdc30_2_ck", "ck_msdc30_2_sel", 1, 1),
> + FACTOR(CLK_CK_I2C_PERI, "ck_i2c_p_ck", "ck_i2c_p_sel", 1, 1),
> + FACTOR(CLK_CK_I2C_EAST, "ck_i2c_east_ck", "ck_i2c_east_sel", 1, 1),
> + FACTOR(CLK_CK_I2C_WEST, "ck_i2c_west_ck", "ck_i2c_west_sel", 1, 1),
> + FACTOR(CLK_CK_I2C_NORTH, "ck_i2c_north_ck", "ck_i2c_north_sel", 1, 1),
> + FACTOR(CLK_CK_AES_UFSFDE, "ck_aes_ufsfde_ck", "ck_aes_ufsfde_sel", 1, 1),
> + FACTOR(CLK_CK_UFS, "ck_ck", "ck_sel", 1, 1),
> + FACTOR(CLK_CK_AUD_1, "ck_aud_1_ck", "ck_aud_1_sel", 1, 1),
> + FACTOR(CLK_CK_AUD_2, "ck_aud_2_ck", "ck_aud_2_sel", 1, 1),
> + FACTOR(CLK_CK_DPMAIF_MAIN, "ck_dpmaif_main_ck", "ck_dpmaif_main_sel", 1, 1),
> + FACTOR(CLK_CK_PWM, "ck_pwm_ck", "ck_pwm_sel", 1, 1),
> + FACTOR(CLK_CK_TL, "ck_tl_ck", "ck_tl_sel", 1, 1),
> + FACTOR(CLK_CK_TL_P1, "ck_tl_p1_ck", "ck_tl_p1_sel", 1, 1),
> + FACTOR(CLK_CK_TL_P2, "ck_tl_p2_ck", "ck_tl_p2_sel", 1, 1),
> + FACTOR(CLK_CK_SSR_RNG, "ck_ssr_rng_ck", "ck_ssr_rng_sel", 1, 1),
> + FACTOR(CLK_CK_SFLASH, "ck_sflash_ck", "ck_sflash_sel", 1, 1),
Please remove all the 1:1 placeholder clocks. These serve no purpose other
than bloating the binding and driver.
> +};
> +
> +static const char * const ck_axi_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d20",
> + "ck_osc_d8",
> + "ck_osc_d4",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d7_d2"
> +};
> +
> +static const char * const ck_mem_sub_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d20",
> + "ck_osc_d4",
> + "ck_univpll_d4_d4",
> + "ck_osc_d3",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5",
> + "ck_univpll_d5",
> + "ck_mainpll_d4",
> + "ck_mainpll_d3"
> +};
> +
> +static const char * const ck_io_noc_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d20",
> + "ck_osc_d8",
> + "ck_osc_d4",
> + "ck_mainpll_d6_d2",
> + "ck_mainpll_d9"
> +};
> +
> +static const char * const ck_p_axi_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d8",
> + "ck_mainpll_d5_d8",
> + "ck_osc_d8",
> + "ck_mainpll_d7_d4",
> + "ck_mainpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d7_d2"
> +};
> +
> +static const char * const ck_pextp0_axi_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d8",
> + "ck_mainpll_d5_d8",
> + "ck_osc_d8",
> + "ck_mainpll_d7_d4",
> + "ck_mainpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d7_d2"
> +};
> +
> +static const char * const ck_pextp1_usb_axi_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d8",
> + "ck_mainpll_d5_d8",
> + "ck_osc_d8",
> + "ck_mainpll_d7_d4",
> + "ck_mainpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d7_d2"
> +};
> +
> +static const char * const ck_p_fmem_sub_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d5_d8",
> + "ck_mainpll_d5_d4",
> + "ck_osc_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5",
> + "ck_univpll_d5",
> + "ck_mainpll_d4"
> +};
> +
> +static const char * const ck_pexpt0_mem_sub_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d5_d8",
> + "ck_mainpll_d5_d4",
> + "ck_osc_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5",
> + "ck_univpll_d5",
> + "ck_mainpll_d4"
> +};
> +
> +static const char * const ck_pextp1_usb_mem_sub_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d5_d8",
> + "ck_mainpll_d5_d4",
> + "ck_osc_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5",
> + "ck_univpll_d5",
> + "ck_mainpll_d4"
> +};
> +
> +static const char * const ck_p_noc_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d5_d8",
> + "ck_mainpll_d5_d4",
> + "ck_osc_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5",
> + "ck_univpll_d5",
> + "ck_mainpll_d4",
> + "ck_mainpll_d3"
> +};
> +
> +static const char * const ck_emi_n_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d4",
> + "ck_mainpll_d5_d8",
> + "ck_mainpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_emipll1_ck"
> +};
> +
> +static const char * const ck_emi_s_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d4",
> + "ck_mainpll_d5_d8",
> + "ck_mainpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_emipll1_ck"
> +};
> +
> +static const char * const ck_ap2conn_host_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d4"
> +};
> +
> +static const char * const ck_atb_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d6"
> +};
> +
> +static const char * const ck_cirq_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d20",
> + "ck_mainpll_d7_d4"
> +};
> +
> +static const char * const ck_pbus_156m_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d2",
> + "ck_osc_d2",
> + "ck_mainpll_d7"
> +};
> +
> +static const char * const ck_efuse_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d20"
> +};
> +
> +static const char * const ck_mcl3gic_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d8",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d7_d2"
> +};
> +
> +static const char * const ck_mcinfra_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d20",
> + "ck_mainpll_d7_d2",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d9",
> + "ck_mainpll_d6"
> +};
> +
> +static const char * const ck_dsp_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d5",
> + "ck_osc_d4",
> + "ck_osc_d3",
> + "ck_univpll_d6_d2",
> + "ck_osc_d2",
> + "ck_univpll_d5",
> + "ck_osc"
> +};
> +
> +static const char * const ck_mfg_ref_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d2"
> +};
> +
> +static const char * const ck_mfg_eb_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d2",
> + "ck_mainpll_d6_d2",
> + "ck_mainpll_d5_d2"
> +};
> +
> +static const char * const ck_uart_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d8",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi0_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi1_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi2_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi3_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi4_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi5_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi6_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_spi7_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d4_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_192m",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_msdc30_1_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_d6_d2",
> + "ck_msdcpll_d2"
> +};
> +
> +static const char * const ck_msdc30_2_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_d6_d2",
> + "ck_msdcpll_d2"
> +};
> +
> +static const char * const ck_disp_pwm_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d32",
> + "ck_osc_d8",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d5_d4",
> + "ck_osc_d4",
> + "ck_mainpll_d4_d4"
> +};
> +
> +static const char * const ck_usb_1p_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d5_d4"
> +};
> +
> +static const char * const ck_usb_xhci_1p_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d5_d4"
> +};
> +
> +static const char * const ck_usb_fmcnt_p1_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_192m_d4"
> +};
> +
> +static const char * const ck_i2c_p_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d8",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d5_d2"
> +};
> +
> +static const char * const ck_i2c_east_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d8",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d5_d2"
> +};
> +
> +static const char * const ck_i2c_west_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d8",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d5_d2"
> +};
> +
> +static const char * const ck_i2c_north_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d8",
> + "ck_univpll_d5_d4",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d5_d2"
> +};
> +
> +static const char * const ck_aes_ufsfde_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d6_d2",
> + "ck_mainpll_d4_d2",
> + "ck_univpll_d6",
> + "ck_mainpll_d4"
> +};
> +
> +static const char * const ck_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_univpll_d6_d2",
> + "ck_mainpll_d4_d2",
> + "ck_univpll_d6",
> + "ck_mainpll_d5",
> + "ck_univpll_d5"
> +};
> +
> +static const char * const ck_aud_1_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_apll1_ck"
> +};
> +
> +static const char * const ck_aud_2_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_apll2_ck"
> +};
> +
> +static const char * const ck_adsp_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_adsppll_ck"
> +};
> +
> +static const char * const ck_adsp_uarthub_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_dpmaif_main_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d4_d4",
> + "ck_univpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_univpll_d4_d2",
> + "ck_mainpll_d6",
> + "ck_univpll_d6",
> + "ck_mainpll_d5",
> + "ck_univpll_d5"
> +};
> +
> +static const char * const ck_pwm_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d4",
> + "ck_univpll_d4_d8"
> +};
> +
> +static const char * const ck_mcupm_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d2",
> + "ck_mainpll_d6_d2",
> + "ck_univpll_d6_d2",
> + "ck_mainpll_d5_d2"
> +};
> +
> +static const char * const ck_ipseast_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5",
> + "ck_mainpll_d4",
> + "ck_mainpll_d3"
> +};
> +
> +static const char * const ck_tl_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d4",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d5_d2"
> +};
> +
> +static const char * const ck_tl_p1_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d4",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d5_d2"
> +};
> +
> +static const char * const ck_tl_p2_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d4",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d5_d2"
> +};
> +
> +static const char * const ck_md_emi_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4"
> +};
> +
> +static const char * const ck_sdf_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d6",
> + "ck_mainpll_d4",
> + "ck_univpll_d4"
> +};
> +
> +static const char * const ck_uarthub_b_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_univpll_d6_d4",
> + "ck_univpll_d6_d2"
> +};
> +
> +static const char * const ck_dpsw_cmp_26m_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_osc_d20"
> +};
> +
> +static const char * const ck_smapck_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d8"
> +};
> +
> +static const char * const ck_ssr_pka_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d7",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5"
> +};
> +
> +static const char * const ck_ssr_dma_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d7",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5"
> +};
> +
> +static const char * const ck_ssr_kdf_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d7"
> +};
> +
> +static const char * const ck_ssr_rng_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d5_d2",
> + "ck_mainpll_d4_d2"
> +};
> +
> +static const char * const ck_spu0_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d7",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5"
> +};
> +
> +static const char * const ck_spu1_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d4_d2",
> + "ck_mainpll_d7",
> + "ck_mainpll_d6",
> + "ck_mainpll_d5"
> +};
> +
> +static const char * const ck_dxcc_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d4_d8",
> + "ck_mainpll_d4_d4",
> + "ck_mainpll_d4_d2"
> +};
> +
> +static const char * const ck_apll_i2sin0_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sin1_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sin2_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sin3_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sin4_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sin6_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sout0_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sout1_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sout2_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sout3_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sout4_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_i2sout6_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_fmi2s_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_apll_tdmout_m_parents[] = {
> + "ck_aud_1_sel",
> + "ck_aud_2_sel"
> +};
> +
> +static const char * const ck_sflash_parents[] = {
> + "ck_tck_26m_mx9_ck",
> + "ck_mainpll_d7_d8",
> + "ck_univpll_d6_d8"
> +};
> +
> +static const struct mtk_mux ck_muxes[] = {
> + /* CLK_CFG_0 */
> + MUX_CLR_SET_UPD(CLK_CK_AXI_SEL, "ck_axi_sel",
> + ck_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
> + CLK_CFG_0_CLR, 0, 3,
> + CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT),
Please drop the "_sel" suffix from clock names. That is derived from the
register field, not the clock name.
For example, for this "ck_axi_sel" clock, the name given in the datasheet
is "hf_faxi_ck". I already mentioned that the "_ck" suffix adds no value
and should be removed. The "hf_f" prefix seems to be related to
classification, as I see "f_f" and "f_" prefixes as well. These could
be dropped as well.
So I think this clock should simply be named "axi".
Please apply this logic to _all_ clocks in this series.
> + MUX_CLR_SET_UPD(CLK_CK_MEM_SUB_SEL, "ck_mem_sub_sel",
> + ck_mem_sub_parents, CLK_CFG_0, CLK_CFG_0_SET,
> + CLK_CFG_0_CLR, 8, 4,
> + CLK_CFG_UPDATE, TOP_MUX_MEM_SUB_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_IO_NOC_SEL, "ck_io_noc_sel",
> + ck_io_noc_parents, CLK_CFG_0, CLK_CFG_0_SET,
> + CLK_CFG_0_CLR, 16, 3,
> + CLK_CFG_UPDATE, TOP_MUX_IO_NOC_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_P_AXI_SEL, "ck_p_axi_sel",
> + ck_p_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
> + CLK_CFG_0_CLR, 24, 3,
> + CLK_CFG_UPDATE, TOP_MUX_PERI_AXI_SHIFT),
> + /* CLK_CFG_1 */
> + MUX_CLR_SET_UPD(CLK_CK_PEXTP0_AXI_SEL, "ck_pextp0_axi_sel",
> + ck_pextp0_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
> + CLK_CFG_1_CLR, 0, 3,
> + CLK_CFG_UPDATE, TOP_MUX_UFS_PEXTP0_AXI_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_PEXTP1_USB_AXI_SEL, "ck_pextp1_usb_axi_sel",
> + ck_pextp1_usb_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
> + CLK_CFG_1_CLR, 8, 3,
> + CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_AXI_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_P_FMEM_SUB_SEL, "ck_p_fmem_sub_sel",
> + ck_p_fmem_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
> + CLK_CFG_1_CLR, 16, 4,
> + CLK_CFG_UPDATE, TOP_MUX_PERI_FMEM_SUB_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_PEXPT0_MEM_SUB_SEL, "ck_pexpt0_mem_sub_sel",
> + ck_pexpt0_mem_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
> + CLK_CFG_1_CLR, 24, 4,
> + CLK_CFG_UPDATE, TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT),
> + /* CLK_CFG_2 */
> + MUX_CLR_SET_UPD(CLK_CK_PEXTP1_USB_MEM_SUB_SEL, "ck_pextp1_usb_mem_sub_sel",
> + ck_pextp1_usb_mem_sub_parents, CLK_CFG_2, CLK_CFG_2_SET,
> + CLK_CFG_2_CLR, 0, 4,
> + CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_P_NOC_SEL, "ck_p_noc_sel",
> + ck_p_noc_parents, CLK_CFG_2, CLK_CFG_2_SET,
> + CLK_CFG_2_CLR, 8, 4,
> + CLK_CFG_UPDATE, TOP_MUX_PERI_NOC_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_EMI_N_SEL, "ck_emi_n_sel",
> + ck_emi_n_parents, CLK_CFG_2, CLK_CFG_2_SET,
> + CLK_CFG_2_CLR, 16, 3,
> + CLK_CFG_UPDATE, TOP_MUX_EMI_N_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_EMI_S_SEL, "ck_emi_s_sel",
> + ck_emi_s_parents, CLK_CFG_2, CLK_CFG_2_SET,
> + CLK_CFG_2_CLR, 24, 3,
> + CLK_CFG_UPDATE, TOP_MUX_EMI_S_SHIFT),
> + /* CLK_CFG_3 */
> + MUX_CLR_SET_UPD(CLK_CK_AP2CONN_HOST_SEL, "ck_ap2conn_host_sel",
> + ck_ap2conn_host_parents, CLK_CFG_3, CLK_CFG_3_SET,
> + CLK_CFG_3_CLR, 16, 1,
> + CLK_CFG_UPDATE, TOP_MUX_AP2CONN_HOST_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_ATB_SEL, "ck_atb_sel",
> + ck_atb_parents, CLK_CFG_3, CLK_CFG_3_SET,
> + CLK_CFG_3_CLR, 24, 2,
> + CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT),
> + /* CLK_CFG_4 */
> + MUX_CLR_SET_UPD(CLK_CK_CIRQ_SEL, "ck_cirq_sel",
> + ck_cirq_parents, CLK_CFG_4, CLK_CFG_4_SET,
> + CLK_CFG_4_CLR, 0, 2,
> + CLK_CFG_UPDATE, TOP_MUX_CIRQ_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_PBUS_156M_SEL, "ck_pbus_156m_sel",
> + ck_pbus_156m_parents, CLK_CFG_4, CLK_CFG_4_SET,
> + CLK_CFG_4_CLR, 8, 2,
> + CLK_CFG_UPDATE, TOP_MUX_PBUS_156M_SHIFT),
> + /* CLK_CFG_5 */
> + MUX_CLR_SET_UPD(CLK_CK_EFUSE_SEL, "ck_efuse_sel",
> + ck_efuse_parents, CLK_CFG_5, CLK_CFG_5_SET,
> + CLK_CFG_5_CLR, 0, 1,
> + CLK_CFG_UPDATE, TOP_MUX_EFUSE_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_MCL3GIC_SEL, "ck_mcl3gic_sel",
> + ck_mcl3gic_parents, CLK_CFG_5, CLK_CFG_5_SET,
> + CLK_CFG_5_CLR, 8, 2,
> + CLK_CFG_UPDATE, TOP_MUX_MCU_L3GIC_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_MCINFRA_SEL, "ck_mcinfra_sel",
> + ck_mcinfra_parents, CLK_CFG_5, CLK_CFG_5_SET,
> + CLK_CFG_5_CLR, 16, 3,
> + CLK_CFG_UPDATE, TOP_MUX_MCU_INFRA_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_DSP_SEL, "ck_dsp_sel",
> + ck_dsp_parents, CLK_CFG_5, CLK_CFG_5_SET,
> + CLK_CFG_5_CLR, 24, 3,
> + CLK_CFG_UPDATE, TOP_MUX_DSP_SHIFT),
> + /* CLK_CFG_6 */
> + MUX_GATE_FENC_CLR_SET_UPD_FLAGS(CLK_CK_MFG_REF_SEL, "ck_mfg_ref_sel", ck_mfg_ref_parents,
> + CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR,
> + 0, 1, 7, CLK_CFG_UPDATE, TOP_MUX_MFG_REF_SHIFT,
> + CLK_FENC_STATUS_MON_0, 7, CLK_IGNORE_UNUSED),
> + MUX_CLR_SET_UPD(CLK_CK_MFG_EB_SEL, "ck_mfg_eb_sel",
> + ck_mfg_eb_parents, CLK_CFG_6, CLK_CFG_6_SET,
> + CLK_CFG_6_CLR, 16, 2,
> + CLK_CFG_UPDATE, TOP_MUX_MFG_EB_SHIFT),
> + MUX_MULT_VOTE_FENC(CLK_CK_UART_SEL, "ck_uart_sel", ck_uart_parents,
> + CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, "vote-regmap",
> + VOTE_CG_3_DONE, VOTE_CG_3_SET, VOTE_CG_3_CLR,
> + 24, 2, 31, CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT,
> + CLK_FENC_STATUS_MON_0, 4),
> + /* CLK_CFG_7 */
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI0_BCLK_SEL, "ck_spi0_b_sel", ck_spi0_b_parents,
> + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
> + VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
> + 0, 3, 7, CLK_CFG_UPDATE, TOP_MUX_SPI0_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_0, 3),
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI1_BCLK_SEL, "ck_spi1_b_sel", ck_spi1_b_parents,
> + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
> + VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
> + 8, 3, 15, CLK_CFG_UPDATE, TOP_MUX_SPI1_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_0, 2),
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI2_BCLK_SEL, "ck_spi2_b_sel", ck_spi2_b_parents,
> + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
> + VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
> + 16, 3, 23, CLK_CFG_UPDATE, TOP_MUX_SPI2_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_0, 1),
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI3_BCLK_SEL, "ck_spi3_b_sel", ck_spi3_b_parents,
> + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, "vote-regmap",
> + VOTE_CG_4_DONE, VOTE_CG_4_SET, VOTE_CG_4_CLR,
> + 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI3_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_0, 0),
> + /* CLK_CFG_8 */
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI4_BCLK_SEL, "ck_spi4_b_sel", ck_spi4_b_parents,
> + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
> + VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
> + 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_SPI4_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_1, 31),
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI5_BCLK_SEL, "ck_spi5_b_sel", ck_spi5_b_parents,
> + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
> + VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
> + 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_SPI5_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_1, 30),
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI6_BCLK_SEL, "ck_spi6_b_sel", ck_spi6_b_parents,
> + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
> + VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
> + 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_SPI6_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_1, 29),
> + MUX_MULT_VOTE_FENC(CLK_CK_SPI7_BCLK_SEL, "ck_spi7_b_sel", ck_spi7_b_parents,
> + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, "vote-regmap",
> + VOTE_CG_5_DONE, VOTE_CG_5_SET, VOTE_CG_5_CLR,
> + 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI7_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_1, 28),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_MSDC30_1_SEL, "ck_msdc30_1_sel", ck_msdc30_1_parents,
> + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
> + 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_1_SHIFT,
> + CLK_FENC_STATUS_MON_1, 25),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_MSDC30_2_SEL, "ck_msdc30_2_sel", ck_msdc30_2_parents,
> + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
> + 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_2_SHIFT,
> + CLK_FENC_STATUS_MON_1, 24),
> + /* CLK_CFG_10 */
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_DISP_PWM_SEL, "ck_disp_pwm_sel", ck_disp_pwm_parents,
> + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
> + 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_DISP_PWM_SHIFT,
> + CLK_FENC_STATUS_MON_1, 23),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_USB_TOP_1P_SEL, "ck_usb_1p_sel", ck_usb_1p_parents,
> + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
> + 8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_1P_SHIFT,
> + CLK_FENC_STATUS_MON_1, 22),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_USB_XHCI_1P_SEL, "ck_usb_xhci_1p_sel", ck_usb_xhci_1p_parents,
> + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
> + 16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_1P_SHIFT,
> + CLK_FENC_STATUS_MON_1, 21),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_USB_FMCNT_P1_SEL, "ck_usb_fmcnt_p1_sel", ck_usb_fmcnt_p1_parents,
> + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
> + 24, 1, 31, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_FMCNT_P1_SHIFT,
> + CLK_FENC_STATUS_MON_1, 20),
> + /* CLK_CFG_11 */
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_I2C_P_SEL, "ck_i2c_p_sel", ck_i2c_p_parents,
> + CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
> + 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_I2C_PERI_SHIFT,
> + CLK_FENC_STATUS_MON_1, 19),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_I2C_EAST_SEL, "ck_i2c_east_sel", ck_i2c_east_parents,
> + CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
> + 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_I2C_EAST_SHIFT,
> + CLK_FENC_STATUS_MON_1, 18),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_I2C_WEST_SEL, "ck_i2c_west_sel", ck_i2c_west_parents,
> + CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
> + 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_I2C_WEST_SHIFT,
> + CLK_FENC_STATUS_MON_1, 17),
> + MUX_MULT_VOTE_FENC(CLK_CK_I2C_NORTH_SEL, "ck_i2c_north_sel", ck_i2c_north_parents,
> + CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR, "vote-regmap",
> + VOTE_CG_6_DONE, VOTE_CG_6_SET, VOTE_CG_6_CLR,
> + 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_I2C_NORTH_SHIFT,
> + CLK_FENC_STATUS_MON_1, 16),
> + /* CLK_CFG_12 */
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_AES_UFSFDE_SEL, "ck_aes_ufsfde_sel", ck_aes_ufsfde_parents,
> + CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
> + 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT,
> + CLK_FENC_STATUS_MON_1, 15),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_SEL, "ck_sel", ck_parents,
> + CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
> + 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT,
> + CLK_FENC_STATUS_MON_1, 14),
> + /* CLK_CFG_13 */
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_AUD_1_SEL, "ck_aud_1_sel", ck_aud_1_parents,
> + CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
> + 0, 1, 7, CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT,
> + CLK_FENC_STATUS_MON_1, 11),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_AUD_2_SEL, "ck_aud_2_sel", ck_aud_2_parents,
> + CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
> + 8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT,
> + CLK_FENC_STATUS_MON_1, 10),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_ADSP_SEL, "ck_adsp_sel", ck_adsp_parents,
> + CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
> + 16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_ADSP_SHIFT,
> + CLK_FENC_STATUS_MON_1, 9),
> + MUX_GATE_CLR_SET_UPD(CLK_CK_ADSP_UARTHUB_BCLK_SEL, "ck_adsp_uarthub_b_sel",
> + ck_adsp_uarthub_b_parents, CLK_CFG_13, CLK_CFG_13_SET,
> + CLK_CFG_13_CLR, 24, 2, 31,
> + CLK_CFG_UPDATE1, TOP_MUX_ADSP_UARTHUB_BCLK_SHIFT),
> + /* CLK_CFG_14 */
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_DPMAIF_MAIN_SEL, "ck_dpmaif_main_sel", ck_dpmaif_main_parents,
> + CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
> + 0, 4, 7, CLK_CFG_UPDATE1, TOP_MUX_DPMAIF_MAIN_SHIFT,
> + CLK_FENC_STATUS_MON_1, 7),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_PWM_SEL, "ck_pwm_sel", ck_pwm_parents,
> + CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
> + 8, 2, 15, CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT,
> + CLK_FENC_STATUS_MON_1, 6),
> + MUX_CLR_SET_UPD(CLK_CK_MCUPM_SEL, "ck_mcupm_sel",
> + ck_mcupm_parents, CLK_CFG_14, CLK_CFG_14_SET,
> + CLK_CFG_14_CLR, 16, 3,
> + CLK_CFG_UPDATE1, TOP_MUX_MCUPM_SHIFT),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_SFLASH_SEL, "ck_sflash_sel", ck_sflash_parents,
> + CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
> + 24, 2, 31, CLK_CFG_UPDATE1, TOP_MUX_SFLASH_SHIFT,
> + CLK_FENC_STATUS_MON_1, 4),
> + /* CLK_CFG_15 */
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_IPSEAST_SEL, "ck_ipseast_sel", ck_ipseast_parents,
> + CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
> + 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_IPSEAST_SHIFT,
> + CLK_FENC_STATUS_MON_1, 3),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_TL_SEL, "ck_tl_sel", ck_tl_parents,
> + CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
> + 16, 2, 23, CLK_CFG_UPDATE2, TOP_MUX_TL_SHIFT,
> + CLK_FENC_STATUS_MON_1, 1),
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_TL_P1_SEL, "ck_tl_p1_sel", ck_tl_p1_parents,
> + CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
> + 24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_TL_P1_SHIFT,
> + CLK_FENC_STATUS_MON_1, 0),
> + /* CLK_CFG_16 */
> + MUX_GATE_FENC_CLR_SET_UPD(CLK_CK_TL_P2_SEL, "ck_tl_p2_sel", ck_tl_p2_parents,
> + CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR,
> + 0, 2, 7, CLK_CFG_UPDATE2, TOP_MUX_TL_P2_SHIFT,
> + CLK_FENC_STATUS_MON_2, 31),
> + MUX_CLR_SET_UPD(CLK_CK_EMI_INTERFACE_546_SEL, "ck_md_emi_sel",
> + ck_md_emi_parents, CLK_CFG_16, CLK_CFG_16_SET,
> + CLK_CFG_16_CLR, 8, 1,
> + CLK_CFG_UPDATE2, TOP_MUX_EMI_INTERFACE_546_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_SDF_SEL, "ck_sdf_sel",
> + ck_sdf_parents, CLK_CFG_16, CLK_CFG_16_SET,
> + CLK_CFG_16_CLR, 16, 3,
> + CLK_CFG_UPDATE2, TOP_MUX_SDF_SHIFT),
> + MUX_MULT_VOTE_FENC(CLK_CK_UARTHUB_BCLK_SEL, "ck_uarthub_b_sel", ck_uarthub_b_parents,
> + CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR, "vote-regmap",
> + VOTE_CG_7_DONE, VOTE_CG_7_SET, VOTE_CG_7_CLR,
> + 24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_UARTHUB_BCLK_SHIFT,
> + CLK_FENC_STATUS_MON_2, 28),
> + /* CLK_CFG_17 */
> + MUX_CLR_SET_UPD(CLK_CK_DPSW_CMP_26M_SEL, "ck_dpsw_cmp_26m_sel",
> + ck_dpsw_cmp_26m_parents, CLK_CFG_17, CLK_CFG_17_SET,
> + CLK_CFG_17_CLR, 0, 1,
> + CLK_CFG_UPDATE2, TOP_MUX_DPSW_CMP_26M_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_SMAPCK_SEL, "ck_smapck_sel",
> + ck_smapck_parents, CLK_CFG_17, CLK_CFG_17_SET,
> + CLK_CFG_17_CLR, 8, 1,
> + CLK_CFG_UPDATE2, TOP_MUX_SMAPCK_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_SSR_PKA_SEL, "ck_ssr_pka_sel",
> + ck_ssr_pka_parents, CLK_CFG_17, CLK_CFG_17_SET,
> + CLK_CFG_17_CLR, 16, 3,
> + CLK_CFG_UPDATE2, TOP_MUX_SSR_PKA_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_SSR_DMA_SEL, "ck_ssr_dma_sel",
> + ck_ssr_dma_parents, CLK_CFG_17, CLK_CFG_17_SET,
> + CLK_CFG_17_CLR, 24, 3,
> + CLK_CFG_UPDATE2, TOP_MUX_SSR_DMA_SHIFT),
> + /* CLK_CFG_18 */
> + MUX_CLR_SET_UPD(CLK_CK_SSR_KDF_SEL, "ck_ssr_kdf_sel",
> + ck_ssr_kdf_parents, CLK_CFG_18, CLK_CFG_18_SET,
> + CLK_CFG_18_CLR, 0, 2,
> + CLK_CFG_UPDATE2, TOP_MUX_SSR_KDF_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_SSR_RNG_SEL, "ck_ssr_rng_sel",
> + ck_ssr_rng_parents, CLK_CFG_18, CLK_CFG_18_SET,
> + CLK_CFG_18_CLR, 8, 2,
> + CLK_CFG_UPDATE2, TOP_MUX_SSR_RNG_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_SPU0_SEL, "ck_spu0_sel",
> + ck_spu0_parents, CLK_CFG_18, CLK_CFG_18_SET,
> + CLK_CFG_18_CLR, 16, 3,
> + CLK_CFG_UPDATE2, TOP_MUX_SPU0_SHIFT),
> + MUX_CLR_SET_UPD(CLK_CK_SPU1_SEL, "ck_spu1_sel",
> + ck_spu1_parents, CLK_CFG_18, CLK_CFG_18_SET,
> + CLK_CFG_18_CLR, 24, 3,
> + CLK_CFG_UPDATE2, TOP_MUX_SPU1_SHIFT),
> + /* CLK_CFG_19 */
> + MUX_CLR_SET_UPD(CLK_CK_DXCC_SEL, "ck_dxcc_sel",
> + ck_dxcc_parents, CLK_CFG_19, CLK_CFG_19_SET,
> + CLK_CFG_19_CLR, 0, 2,
> + CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT),
> +};
> +
> +static const struct mtk_composite ck_composites[] = {
> + /* CLK_AUDDIV_0 */
> + MUX(CLK_CK_APLL_I2SIN0_MCK_SEL, "ck_apll_i2sin0_m_sel",
> + ck_apll_i2sin0_m_parents, 0x020c, 16, 1),
> + MUX(CLK_CK_APLL_I2SIN1_MCK_SEL, "ck_apll_i2sin1_m_sel",
> + ck_apll_i2sin1_m_parents, 0x020c, 17, 1),
> + MUX(CLK_CK_APLL_I2SIN2_MCK_SEL, "ck_apll_i2sin2_m_sel",
> + ck_apll_i2sin2_m_parents, 0x020c, 18, 1),
> + MUX(CLK_CK_APLL_I2SIN3_MCK_SEL, "ck_apll_i2sin3_m_sel",
> + ck_apll_i2sin3_m_parents, 0x020c, 19, 1),
> + MUX(CLK_CK_APLL_I2SIN4_MCK_SEL, "ck_apll_i2sin4_m_sel",
> + ck_apll_i2sin4_m_parents, 0x020c, 20, 1),
> + MUX(CLK_CK_APLL_I2SIN6_MCK_SEL, "ck_apll_i2sin6_m_sel",
> + ck_apll_i2sin6_m_parents, 0x020c, 21, 1),
> + MUX(CLK_CK_APLL_I2SOUT0_MCK_SEL, "ck_apll_i2sout0_m_sel",
> + ck_apll_i2sout0_m_parents, 0x020c, 22, 1),
> + MUX(CLK_CK_APLL_I2SOUT1_MCK_SEL, "ck_apll_i2sout1_m_sel",
> + ck_apll_i2sout1_m_parents, 0x020c, 23, 1),
> + MUX(CLK_CK_APLL_I2SOUT2_MCK_SEL, "ck_apll_i2sout2_m_sel",
> + ck_apll_i2sout2_m_parents, 0x020c, 24, 1),
> + MUX(CLK_CK_APLL_I2SOUT3_MCK_SEL, "ck_apll_i2sout3_m_sel",
> + ck_apll_i2sout3_m_parents, 0x020c, 25, 1),
> + MUX(CLK_CK_APLL_I2SOUT4_MCK_SEL, "ck_apll_i2sout4_m_sel",
> + ck_apll_i2sout4_m_parents, 0x020c, 26, 1),
> + MUX(CLK_CK_APLL_I2SOUT6_MCK_SEL, "ck_apll_i2sout6_m_sel",
> + ck_apll_i2sout6_m_parents, 0x020c, 27, 1),
> + MUX(CLK_CK_APLL_FMI2S_MCK_SEL, "ck_apll_fmi2s_m_sel",
> + ck_apll_fmi2s_m_parents, 0x020c, 28, 1),
> + MUX(CLK_CK_APLL_TDMOUT_MCK_SEL, "ck_apll_tdmout_m_sel",
> + ck_apll_tdmout_m_parents, 0x020c, 29, 1),
> + /* CLK_AUDDIV_2 */
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN0, "ck_apll12_div_i2sin0",
> + "ck_apll_i2sin0_m_sel", 0x020c,
> + 0, CLK_AUDDIV_2, 8, 0),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN1, "ck_apll12_div_i2sin1",
> + "ck_apll_i2sin1_m_sel", 0x020c,
> + 1, CLK_AUDDIV_2, 8, 8),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN2, "ck_apll12_div_i2sin2",
> + "ck_apll_i2sin2_m_sel", 0x020c,
> + 2, CLK_AUDDIV_2, 8, 16),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN3, "ck_apll12_div_i2sin3",
> + "ck_apll_i2sin3_m_sel", 0x020c,
> + 3, CLK_AUDDIV_2, 8, 24),
> + /* CLK_AUDDIV_3 */
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN4, "ck_apll12_div_i2sin4",
> + "ck_apll_i2sin4_m_sel", 0x020c,
> + 4, CLK_AUDDIV_3, 8, 0),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SIN6, "ck_apll12_div_i2sin6",
> + "ck_apll_i2sin6_m_sel", 0x020c,
> + 5, CLK_AUDDIV_3, 8, 8),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT0, "ck_apll12_div_i2sout0",
> + "ck_apll_i2sout0_m_sel", 0x020c,
> + 6, CLK_AUDDIV_3, 8, 16),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT1, "ck_apll12_div_i2sout1",
> + "ck_apll_i2sout1_m_sel", 0x020c,
> + 7, CLK_AUDDIV_3, 8, 24),
> + /* CLK_AUDDIV_4 */
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT2, "ck_apll12_div_i2sout2",
> + "ck_apll_i2sout2_m_sel", 0x020c,
> + 8, CLK_AUDDIV_4, 8, 0),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT3, "ck_apll12_div_i2sout3",
> + "ck_apll_i2sout3_m_sel", 0x020c,
> + 9, CLK_AUDDIV_4, 8, 8),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT4, "ck_apll12_div_i2sout4",
> + "ck_apll_i2sout4_m_sel", 0x020c,
> + 10, CLK_AUDDIV_4, 8, 16),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_I2SOUT6, "ck_apll12_div_i2sout6",
> + "ck_apll_i2sout6_m_sel", 0x020c,
> + 11, CLK_AUDDIV_4, 8, 24),
> + /* CLK_AUDDIV_5 */
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_FMI2S, "ck_apll12_div_fmi2s",
> + "ck_apll_fmi2s_m_sel", 0x020c,
> + 12, CLK_AUDDIV_5, 8, 0),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_TDMOUT_M, "ck_apll12_div_tdmout_m",
> + "ck_apll_tdmout_m_sel", 0x020c,
> + 13, CLK_AUDDIV_5, 8, 8),
> + DIV_GATE(CLK_CK_APLL12_CK_DIV_TDMOUT_B, "ck_apll12_div_tdmout_b",
> + "ck_apll_tdmout_m_sel", 0x020c,
> + 14, CLK_AUDDIV_5, 8, 16),
Composite clocks support all three types (mux, divider, gate) combined.
Please merge them so that there is just one clock for each interface
instead of two.
Thanks
ChenYu
> +};
> +
> +static int clk_mt8196_ck_probe(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *clk_data;
> + int r;
> + struct device_node *node = pdev->dev.of_node;
> +
> + void __iomem *base;
> + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base)) {
> + dev_err(&pdev->dev, "%s(): ioremap failed\n", __func__);
> + return PTR_ERR(base);
> + }
> +
> + clk_data = mtk_alloc_clk_data(CLK_CK_NR_CLK);
> +
> + mtk_clk_register_factors(ck_divs, ARRAY_SIZE(ck_divs),
> + clk_data);
> +
> + mtk_clk_register_muxes(&pdev->dev, ck_muxes, ARRAY_SIZE(ck_muxes), node,
> + &mt8196_clk_ck_lock, clk_data);
> +
> + mtk_clk_register_composites(&pdev->dev, ck_composites, ARRAY_SIZE(ck_composites),
> + base, &mt8196_clk_ck_lock, clk_data);
> +
> + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> + if (r)
> + dev_err(&pdev->dev, "%s(): could not register clock provider: %d\n",
> + __func__, r);
> +
> + return r;
> +}
> +
> +static void clk_mt8196_ck_remove(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> + struct device_node *node = pdev->dev.of_node;
> +
> + of_clk_del_provider(node);
> + mtk_clk_unregister_composites(ck_composites, ARRAY_SIZE(ck_composites), clk_data);
> + mtk_clk_unregister_muxes(ck_muxes, ARRAY_SIZE(ck_muxes), clk_data);
> + mtk_clk_unregister_factors(ck_divs, ARRAY_SIZE(ck_divs), clk_data);
> + mtk_free_clk_data(clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8196_ck[] = {
> + { .compatible = "mediatek,mt8196-cksys", },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8196_ck_drv = {
> + .probe = clk_mt8196_ck_probe,
> + .remove = clk_mt8196_ck_remove,
> + .driver = {
> + .name = "clk-mt8196-ck",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_clk_mt8196_ck,
> + },
> +};
> +
> +module_platform_driver(clk_mt8196_ck_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.45.2
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock
2025-03-07 3:27 ` [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock Guangjie Song
2025-03-07 4:16 ` Rob Herring (Arm)
2025-03-07 7:29 ` Krzysztof Kozlowski
@ 2025-04-16 9:20 ` Chen-Yu Tsai
2 siblings, 0 replies; 34+ messages in thread
From: Chen-Yu Tsai @ 2025-04-16 9:20 UTC (permalink / raw)
To: Guangjie Song
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Richard Cochran, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, netdev,
Project_Global_Chrome_Upstream_Group
Hi,
On Fri, Mar 7, 2025 at 11:34 AM Guangjie Song
<guangjie.song@mediatek.com> wrote:
>
> Add the new binding documentation for system clock and functional clock
> on Mediatek MT8196.
>
> Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
> ---
> .../bindings/clock/mediatek,mt8196-clock.yaml | 66 +
> .../clock/mediatek,mt8196-sys-clock.yaml | 63 +
> include/dt-bindings/clock/mt8196-clk.h | 1503 +++++++++++++++++
> 3 files changed, 1632 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
> create mode 100644 include/dt-bindings/clock/mt8196-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
> new file mode 100644
> index 000000000000..014c6c4840f1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Functional Clock Controller for MT8196
> +
> +maintainers:
> + - Guangjie Song <guangjie.song@mediatek.com>
> +
> +description:
> + The clock architecture in MediaTek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The devices provide clock gate control in different IP blocks.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8196-audiosys
> + - mediatek,mt8196-dispsys0
> + - mediatek,mt8196-dispsys1
> + - mediatek,mt8196-disp_vdisp_ao_config
> + - mediatek,mt8196-imp_iic_wrap_c
> + - mediatek,mt8196-imp_iic_wrap_e
> + - mediatek,mt8196-imp_iic_wrap_n
> + - mediatek,mt8196-imp_iic_wrap_w
> + - mediatek,mt8196-mdpsys
> + - mediatek,mt8196-mdpsys1
> + - mediatek,mt8196-ovlsys0
> + - mediatek,mt8196-ovlsys1
> + - mediatek,mt8196-pericfg_ao
> + - mediatek,mt8196-pextp0cfg_ao
> + - mediatek,mt8196-pextp1cfg_ao
> + - mediatek,mt8196-ufscfg_ao
> + - mediatek,mt8196-vdecsys
> + - mediatek,mt8196-vdecsys_soc
> + - mediatek,mt8196-vencsys
> + - mediatek,mt8196-vencsys_c1
> + - mediatek,mt8196-vencsys_c2
> +
> + reg:
> + description: Address range of the subsys.
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@16300000 {
> + compatible = "mediatek,mt8196-imp_iic_wrap_c";
> + reg = <0x16300000 0x1000>;
> + #clock-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
> new file mode 100644
> index 000000000000..0909b9f1ee52
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek System Clock Controller for MT8196
> +
> +maintainers:
> + - Guangjie Song <guangjie.song@mediatek.com>
> +
> +description:
> + The clock architecture in MediaTek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The apmixedsys, vlp_cksys, armpll, ccipll, mfgpll and ptppll provides most of PLLs
> + which generated from SoC 26m.
> + The cksys, cksys_gp2 and vlp_cksys provides dividers and muxes which provide the
> + clock source to other IP blocks.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8196-armpll_ll_pll_ctrl
> + - mediatek,mt8196-armpll_bl_pll_ctrl
> + - mediatek,mt8196-armpll_b_pll_ctrl
> + - mediatek,mt8196-apmixedsys
> + - mediatek,mt8196-apmixedsys_gp2
> + - mediatek,mt8196-ccipll_pll_ctrl
> + - mediatek,mt8196-cksys
> + - mediatek,mt8196-cksys_gp2
> + - mediatek,mt8196-mfgpll_pll_ctrl
> + - mediatek,mt8196-mfgpll_sc0_pll_ctrl
> + - mediatek,mt8196-mfgpll_sc1_pll_ctrl
> + - mediatek,mt8196-ptppll_pll_ctrl
> + - mediatek,mt8196-vlp_cksys
> + - const: syscon
> +
> + reg:
> + description: Address range of the subsys.
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@10000800 {
> + compatible = "mediatek,mt8196-apmixedsys", "syscon";
> + reg = <0 0x10000800 0 0x1000>;
> + #clock-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/mt8196-clk.h b/include/dt-bindings/clock/mt8196-clk.h
> new file mode 100644
> index 000000000000..9bd33c46f7de
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt8196-clk.h
> @@ -0,0 +1,1503 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + * Author: Guangjie Song <guangjie.song@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MT8196_H
> +#define _DT_BINDINGS_CLK_MT8196_H
> +
> +/* CKSYS */
> +#define CLK_CK_AXI_SEL 0
> +#define CLK_CK_MEM_SUB_SEL 1
> +#define CLK_CK_IO_NOC_SEL 2
> +#define CLK_CK_P_AXI_SEL 3
> +#define CLK_CK_PEXTP0_AXI_SEL 4
> +#define CLK_CK_PEXTP1_USB_AXI_SEL 5
> +#define CLK_CK_P_FMEM_SUB_SEL 6
> +#define CLK_CK_PEXPT0_MEM_SUB_SEL 7
> +#define CLK_CK_PEXTP1_USB_MEM_SUB_SEL 8
> +#define CLK_CK_P_NOC_SEL 9
> +#define CLK_CK_EMI_N_SEL 10
> +#define CLK_CK_EMI_S_SEL 11
> +#define CLK_CK_AP2CONN_HOST_SEL 12
> +#define CLK_CK_ATB_SEL 13
> +#define CLK_CK_CIRQ_SEL 14
> +#define CLK_CK_PBUS_156M_SEL 15
> +#define CLK_CK_EFUSE_SEL 16
> +#define CLK_CK_MCL3GIC_SEL 17
> +#define CLK_CK_MCINFRA_SEL 18
> +#define CLK_CK_DSP_SEL 19
> +#define CLK_CK_MFG_REF_SEL 20
> +#define CLK_CK_MFG_EB_SEL 21
> +#define CLK_CK_UART_SEL 22
> +#define CLK_CK_SPI0_BCLK_SEL 23
> +#define CLK_CK_SPI1_BCLK_SEL 24
> +#define CLK_CK_SPI2_BCLK_SEL 25
> +#define CLK_CK_SPI3_BCLK_SEL 26
> +#define CLK_CK_SPI4_BCLK_SEL 27
> +#define CLK_CK_SPI5_BCLK_SEL 28
> +#define CLK_CK_SPI6_BCLK_SEL 29
> +#define CLK_CK_SPI7_BCLK_SEL 30
> +#define CLK_CK_MSDC30_1_SEL 31
> +#define CLK_CK_MSDC30_2_SEL 32
> +#define CLK_CK_DISP_PWM_SEL 33
> +#define CLK_CK_USB_TOP_1P_SEL 34
> +#define CLK_CK_USB_XHCI_1P_SEL 35
> +#define CLK_CK_USB_FMCNT_P1_SEL 36
> +#define CLK_CK_I2C_P_SEL 37
> +#define CLK_CK_I2C_EAST_SEL 38
> +#define CLK_CK_I2C_WEST_SEL 39
> +#define CLK_CK_I2C_NORTH_SEL 40
> +#define CLK_CK_AES_UFSFDE_SEL 41
> +#define CLK_CK_SEL 42
> +#define CLK_CK_AUD_1_SEL 43
> +#define CLK_CK_AUD_2_SEL 44
> +#define CLK_CK_ADSP_SEL 45
> +#define CLK_CK_ADSP_UARTHUB_BCLK_SEL 46
> +#define CLK_CK_DPMAIF_MAIN_SEL 47
> +#define CLK_CK_PWM_SEL 48
> +#define CLK_CK_MCUPM_SEL 49
> +#define CLK_CK_IPSEAST_SEL 50
> +#define CLK_CK_TL_SEL 51
> +#define CLK_CK_TL_P1_SEL 52
> +#define CLK_CK_TL_P2_SEL 53
> +#define CLK_CK_EMI_INTERFACE_546_SEL 54
> +#define CLK_CK_SDF_SEL 55
> +#define CLK_CK_UARTHUB_BCLK_SEL 56
> +#define CLK_CK_DPSW_CMP_26M_SEL 57
> +#define CLK_CK_SMAPCK_SEL 58
> +#define CLK_CK_SSR_PKA_SEL 59
> +#define CLK_CK_SSR_DMA_SEL 60
> +#define CLK_CK_SSR_KDF_SEL 61
> +#define CLK_CK_SSR_RNG_SEL 62
> +#define CLK_CK_SPU0_SEL 63
> +#define CLK_CK_SPU1_SEL 64
> +#define CLK_CK_DXCC_SEL 65
> +#define CLK_CK_APLL_I2SIN0_MCK_SEL 66
> +#define CLK_CK_APLL_I2SIN1_MCK_SEL 67
> +#define CLK_CK_APLL_I2SIN2_MCK_SEL 68
> +#define CLK_CK_APLL_I2SIN3_MCK_SEL 69
> +#define CLK_CK_APLL_I2SIN4_MCK_SEL 70
> +#define CLK_CK_APLL_I2SIN6_MCK_SEL 71
> +#define CLK_CK_APLL_I2SOUT0_MCK_SEL 72
> +#define CLK_CK_APLL_I2SOUT1_MCK_SEL 73
> +#define CLK_CK_APLL_I2SOUT2_MCK_SEL 74
> +#define CLK_CK_APLL_I2SOUT3_MCK_SEL 75
> +#define CLK_CK_APLL_I2SOUT4_MCK_SEL 76
> +#define CLK_CK_APLL_I2SOUT6_MCK_SEL 77
> +#define CLK_CK_APLL_FMI2S_MCK_SEL 78
> +#define CLK_CK_APLL_TDMOUT_MCK_SEL 79
> +#define CLK_CK_APLL12_CK_DIV_I2SIN0 80
> +#define CLK_CK_APLL12_CK_DIV_I2SIN1 81
> +#define CLK_CK_APLL12_CK_DIV_I2SIN2 82
> +#define CLK_CK_APLL12_CK_DIV_I2SIN3 83
> +#define CLK_CK_APLL12_CK_DIV_I2SIN4 84
> +#define CLK_CK_APLL12_CK_DIV_I2SIN6 85
> +#define CLK_CK_APLL12_CK_DIV_I2SOUT0 86
> +#define CLK_CK_APLL12_CK_DIV_I2SOUT1 87
> +#define CLK_CK_APLL12_CK_DIV_I2SOUT2 88
> +#define CLK_CK_APLL12_CK_DIV_I2SOUT3 89
> +#define CLK_CK_APLL12_CK_DIV_I2SOUT4 90
> +#define CLK_CK_APLL12_CK_DIV_I2SOUT6 91
> +#define CLK_CK_APLL12_CK_DIV_FMI2S 92
> +#define CLK_CK_APLL12_CK_DIV_TDMOUT_M 93
As mentioned in the topckgen clock driver patch, these should
be merged together. I2SOUT0 is one clock unit with gate, mux
and divider controls. No need to split them into two parts.
> +#define CLK_CK_APLL12_CK_DIV_TDMOUT_B 94
> +#define CLK_CK_MAINPLL_D3 95
> +#define CLK_CK_MAINPLL_D4 96
> +#define CLK_CK_MAINPLL_D4_D2 97
> +#define CLK_CK_MAINPLL_D4_D4 98
> +#define CLK_CK_MAINPLL_D4_D8 99
> +#define CLK_CK_MAINPLL_D5 100
> +#define CLK_CK_MAINPLL_D5_D2 101
> +#define CLK_CK_MAINPLL_D5_D4 102
> +#define CLK_CK_MAINPLL_D5_D8 103
> +#define CLK_CK_MAINPLL_D6 104
> +#define CLK_CK_MAINPLL_D6_D2 105
> +#define CLK_CK_MAINPLL_D7 106
> +#define CLK_CK_MAINPLL_D7_D2 107
> +#define CLK_CK_MAINPLL_D7_D4 108
> +#define CLK_CK_MAINPLL_D7_D8 109
> +#define CLK_CK_MAINPLL_D9 110
> +#define CLK_CK_UNIVPLL_D4 111
> +#define CLK_CK_UNIVPLL_D4_D2 112
> +#define CLK_CK_UNIVPLL_D4_D4 113
> +#define CLK_CK_UNIVPLL_D4_D8 114
> +#define CLK_CK_UNIVPLL_D5 115
> +#define CLK_CK_UNIVPLL_D5_D2 116
> +#define CLK_CK_UNIVPLL_D5_D4 117
> +#define CLK_CK_UNIVPLL_D6 118
> +#define CLK_CK_UNIVPLL_D6_D2 119
> +#define CLK_CK_UNIVPLL_D6_D4 120
> +#define CLK_CK_UNIVPLL_D6_D8 121
> +#define CLK_CK_UNIVPLL_D6_D16 122
> +#define CLK_CK_UNIVPLL_192M 123
> +#define CLK_CK_UNIVPLL_192M_D4 124
> +#define CLK_CK_UNIVPLL_192M_D8 125
> +#define CLK_CK_UNIVPLL_192M_D16 126
> +#define CLK_CK_UNIVPLL_192M_D32 127
> +#define CLK_CK_UNIVPLL_192M_D10 128
> +#define CLK_CK_APLL1 129
> +#define CLK_CK_APLL1_D4 130
> +#define CLK_CK_APLL1_D8 131
> +#define CLK_CK_APLL2 132
> +#define CLK_CK_APLL2_D4 133
> +#define CLK_CK_APLL2_D8 134
> +#define CLK_CK_ADSPPLL 135
> +#define CLK_CK_EMIPLL1 136
> +#define CLK_CK_TVDPLL1_D2 137
> +#define CLK_CK_MSDCPLL_D2 138
> +#define CLK_CK_CLKRTC 139
> +#define CLK_CK_TCK_26M_MX9 140
> +#define CLK_CK_F26M 141
> +#define CLK_CK_F26M_CK_D2 142
> +#define CLK_CK_OSC 143
> +#define CLK_CK_OSC_D2 144
> +#define CLK_CK_OSC_D3 145
> +#define CLK_CK_OSC_D4 146
> +#define CLK_CK_OSC_D5 147
> +#define CLK_CK_OSC_D7 148
> +#define CLK_CK_OSC_D8 149
> +#define CLK_CK_OSC_D10 150
> +#define CLK_CK_OSC_D14 151
> +#define CLK_CK_OSC_D20 152
> +#define CLK_CK_OSC_D32 153
> +#define CLK_CK_OSC_D40 154
The following:
> +#define CLK_CK_OSC3 155
> +#define CLK_CK_P_AXI 156
> +#define CLK_CK_PEXTP0_AXI 157
> +#define CLK_CK_PEXTP1_USB_AXI 158
> +#define CLK_CK_PEXPT0_MEM_SUB 159
> +#define CLK_CK_PEXTP1_USB_MEM_SUB 160
> +#define CLK_CK_UART 161
> +#define CLK_CK_SPI0_BCLK 162
> +#define CLK_CK_SPI1_BCLK 163
> +#define CLK_CK_SPI2_BCLK 164
> +#define CLK_CK_SPI3_BCLK 165
> +#define CLK_CK_SPI4_BCLK 166
> +#define CLK_CK_SPI5_BCLK 167
> +#define CLK_CK_SPI6_BCLK 168
> +#define CLK_CK_SPI7_BCLK 169
> +#define CLK_CK_MSDC30_1 170
> +#define CLK_CK_MSDC30_2 171
> +#define CLK_CK_I2C_PERI 172
> +#define CLK_CK_I2C_EAST 173
> +#define CLK_CK_I2C_WEST 174
> +#define CLK_CK_I2C_NORTH 175
> +#define CLK_CK_AES_UFSFDE 176
> +#define CLK_CK_UFS 177
> +#define CLK_CK_AUD_1 178
> +#define CLK_CK_AUD_2 179
> +#define CLK_CK_DPMAIF_MAIN 180
> +#define CLK_CK_PWM 181
> +#define CLK_CK_TL 182
> +#define CLK_CK_TL_P1 183
> +#define CLK_CK_TL_P2 184
> +#define CLK_CK_SSR_RNG 185
> +#define CLK_CK_SPU0 186
> +#define CLK_CK_DXCC 187
> +#define CLK_CK_SFLASH_SEL 188
> +#define CLK_CK_SFLASH 189
are all 1:1 placeholder clocks. Don't add these. The consumer can
directly reference the clock that these route to.
> +#define CLK_CK_NR_CLK 190
> +
> +/* APMIXEDSYS */
> +#define CLK_APMIXED_MAINPLL 0
> +#define CLK_APMIXED_UNIVPLL 1
> +#define CLK_APMIXED_MSDCPLL 2
> +#define CLK_APMIXED_ADSPPLL 3
> +#define CLK_APMIXED_EMIPLL 4
> +#define CLK_APMIXED_EMIPLL2 5
> +#define CLK_APMIXED_NR_CLK 6
> +
> +/* CKSYS_GP2 */
> +#define CLK_CK2_SENINF0_SEL 0
> +#define CLK_CK2_SENINF1_SEL 1
> +#define CLK_CK2_SENINF2_SEL 2
> +#define CLK_CK2_SENINF3_SEL 3
> +#define CLK_CK2_SENINF4_SEL 4
> +#define CLK_CK2_SENINF5_SEL 5
> +#define CLK_CK2_IMG1_SEL 6
> +#define CLK_CK2_IPE_SEL 7
> +#define CLK_CK2_CAM_SEL 8
> +#define CLK_CK2_CAMTM_SEL 9
> +#define CLK_CK2_DPE_SEL 10
> +#define CLK_CK2_VDEC_SEL 11
> +#define CLK_CK2_CCUSYS_SEL 12
> +#define CLK_CK2_CCUTM_SEL 13
> +#define CLK_CK2_VENC_SEL 14
> +#define CLK_CK2_DP1_SEL 15
> +#define CLK_CK2_DP0_SEL 16
> +#define CLK_CK2_DISP_SEL 17
> +#define CLK_CK2_MDP_SEL 18
> +#define CLK_CK2_MMINFRA_SEL 19
> +#define CLK_CK2_MMINFRA_SNOC_SEL 20
> +#define CLK_CK2_MMUP_SEL 21
> +#define CLK_CK2_MMINFRA_AO_SEL 22
> +#define CLK_CK2_MAINPLL2_D2 23
> +#define CLK_CK2_MAINPLL2_D3 24
> +#define CLK_CK2_MAINPLL2_D4 25
> +#define CLK_CK2_MAINPLL2_D4_D2 26
> +#define CLK_CK2_MAINPLL2_D4_D4 27
> +#define CLK_CK2_MAINPLL2_D5 28
> +#define CLK_CK2_MAINPLL2_D5_D2 29
> +#define CLK_CK2_MAINPLL2_D6 30
> +#define CLK_CK2_MAINPLL2_D6_D2 31
> +#define CLK_CK2_MAINPLL2_D7 32
> +#define CLK_CK2_MAINPLL2_D7_D2 33
> +#define CLK_CK2_MAINPLL2_D9 34
> +#define CLK_CK2_UNIVPLL2_D3 35
> +#define CLK_CK2_UNIVPLL2_D4 36
> +#define CLK_CK2_UNIVPLL2_D4_D2 37
> +#define CLK_CK2_UNIVPLL2_D5 38
> +#define CLK_CK2_UNIVPLL2_D5_D2 39
> +#define CLK_CK2_UNIVPLL2_D6 40
> +#define CLK_CK2_UNIVPLL2_D6_D2 41
> +#define CLK_CK2_UNIVPLL2_D6_D4 42
> +#define CLK_CK2_UNIVPLL2_D7 43
> +#define CLK_CK2_IMGPLL_D2 44
> +#define CLK_CK2_IMGPLL_D4 45
> +#define CLK_CK2_IMGPLL_D5 46
> +#define CLK_CK2_IMGPLL_D5_D2 47
> +#define CLK_CK2_MMPLL2_D3 48
> +#define CLK_CK2_MMPLL2_D4 49
> +#define CLK_CK2_MMPLL2_D4_D2 50
> +#define CLK_CK2_MMPLL2_D5 51
> +#define CLK_CK2_MMPLL2_D5_D2 52
> +#define CLK_CK2_MMPLL2_D6 53
> +#define CLK_CK2_MMPLL2_D6_D2 54
> +#define CLK_CK2_MMPLL2_D7 55
> +#define CLK_CK2_MMPLL2_D9 56
> +#define CLK_CK2_TVDPLL1_D4 57
> +#define CLK_CK2_TVDPLL1_D8 58
> +#define CLK_CK2_TVDPLL1_D16 59
> +#define CLK_CK2_TVDPLL2_D2 60
> +#define CLK_CK2_TVDPLL2_D4 61
> +#define CLK_CK2_TVDPLL2_D8 62
> +#define CLK_CK2_TVDPLL2_D16 63
> +#define CLK_CK2_CCUSYS 64
> +#define CLK_CK2_VENC 65
> +#define CLK_CK2_MMINFRA 66
> +#define CLK_CK2_IMG1 67
> +#define CLK_CK2_IPE 68
> +#define CLK_CK2_CAM 69
> +#define CLK_CK2_CAMTM 70
> +#define CLK_CK2_DPE 71
> +#define CLK_CK2_VDEC 72
> +#define CLK_CK2_DP1 73
> +#define CLK_CK2_DP0 74
> +#define CLK_CK2_MDP 75
> +#define CLK_CK2_DISP 76
> +#define CLK_CK2_AVS_IMG 77
> +#define CLK_CK2_AVS_VDEC 78
> +#define CLK_CK2_DVO_SEL 79
> +#define CLK_CK2_DVO_FAVT_SEL 80
> +#define CLK_CK2_TVDPLL3_D2 81
> +#define CLK_CK2_TVDPLL3_D4 82
> +#define CLK_CK2_TVDPLL3_D8 83
> +#define CLK_CK2_TVDPLL3_D16 84
> +#define CLK_CK2_NR_CLK 85
> +
> +/* APMIXEDSYS_GP2 */
> +#define CLK_APMIXED2_MAINPLL2 0
> +#define CLK_APMIXED2_UNIVPLL2 1
> +#define CLK_APMIXED2_MMPLL2 2
> +#define CLK_APMIXED2_IMGPLL 3
> +#define CLK_APMIXED2_TVDPLL1 4
> +#define CLK_APMIXED2_TVDPLL2 5
> +#define CLK_APMIXED2_TVDPLL3 6
> +#define CLK_APMIXED2_NR_CLK 7
> +
> +/* IMP_IIC_WRAP_E */
> +#define CLK_IMPE_I2C5 0
> +#define CLK_IMPE_I2C5_I2C 1
> +#define CLK_IMPE_NR_CLK 2
> +
> +/* IMP_IIC_WRAP_W */
> +#define CLK_IMPW_I2C0 0
> +#define CLK_IMPW_I2C0_I2C 1
> +#define CLK_IMPW_I2C3 2
> +#define CLK_IMPW_I2C3_I2C 3
> +#define CLK_IMPW_I2C6 4
> +#define CLK_IMPW_I2C6_I2C 5
> +#define CLK_IMPW_I2C10 6
> +#define CLK_IMPW_I2C10_I2C 7
Half of these (the ones with the "_I2C" suffix) are dummy clocks as seen
in the driver. Don't add them. The binding should list only what the
hardware has.
Same goes for all the other groups below.
> +#define CLK_IMPW_NR_CLK 8
> +
> +/* IMP_IIC_WRAP_N */
> +#define CLK_IMPN_I2C1 0
> +#define CLK_IMPN_I2C1_I2C 1
> +#define CLK_IMPN_I2C2 2
> +#define CLK_IMPN_I2C2_I2C 3
> +#define CLK_IMPN_I2C4 4
> +#define CLK_IMPN_I2C4_I2C 5
> +#define CLK_IMPN_I2C7 6
> +#define CLK_IMPN_I2C7_I2C 7
> +#define CLK_IMPN_I2C8 8
> +#define CLK_IMPN_I2C8_I2C 9
> +#define CLK_IMPN_I2C9 10
> +#define CLK_IMPN_I2C9_I2C 11
> +#define CLK_IMPN_NR_CLK 12
> +
> +/* IMP_IIC_WRAP_C */
> +#define CLK_IMPC_I2C11 0
> +#define CLK_IMPC_I2C11_I2C 1
> +#define CLK_IMPC_I2C12 2
> +#define CLK_IMPC_I2C12_I2C 3
> +#define CLK_IMPC_I2C13 4
> +#define CLK_IMPC_I2C13_I2C 5
> +#define CLK_IMPC_I2C14 6
> +#define CLK_IMPC_I2C14_I2C 7
> +#define CLK_IMPC_NR_CLK 8
> +
> +/* PERICFG_AO */
> +#define CLK_PERAO_UART0_BCLK 0
> +#define CLK_PERAO_UART0_BCLK_UART 1
> +#define CLK_PERAO_UART1_BCLK 2
> +#define CLK_PERAO_UART1_BCLK_UART 3
> +#define CLK_PERAO_UART2_BCLK 4
> +#define CLK_PERAO_UART2_BCLK_UART 5
> +#define CLK_PERAO_UART3_BCLK 6
> +#define CLK_PERAO_UART3_BCLK_UART 7
> +#define CLK_PERAO_UART4_BCLK 8
> +#define CLK_PERAO_UART4_BCLK_UART 9
> +#define CLK_PERAO_UART5_BCLK 10
> +#define CLK_PERAO_UART5_BCLK_UART 11
> +#define CLK_PERAO_PWM_X16W_HCLK 12
> +#define CLK_PERAO_PWM_X16W_HCLK_PWM 13
> +#define CLK_PERAO_PWM_X16W_BCLK 14
> +#define CLK_PERAO_PWM_X16W_BCLK_PWM 15
> +#define CLK_PERAO_PWM_PWM_BCLK0 16
> +#define CLK_PERAO_PWM_PWM_BCLK0_PWM 17
> +#define CLK_PERAO_PWM_PWM_BCLK1 18
> +#define CLK_PERAO_PWM_PWM_BCLK1_PWM 19
> +#define CLK_PERAO_PWM_PWM_BCLK2 20
> +#define CLK_PERAO_PWM_PWM_BCLK2_PWM 21
> +#define CLK_PERAO_PWM_PWM_BCLK3 22
> +#define CLK_PERAO_PWM_PWM_BCLK3_PWM 23
> +#define CLK_PERAO_SPI0_BCLK 24
> +#define CLK_PERAO_SPI0_BCLK_SPI 25
> +#define CLK_PERAO_SPI1_BCLK 26
> +#define CLK_PERAO_SPI1_BCLK_SPI 27
> +#define CLK_PERAO_SPI2_BCLK 28
> +#define CLK_PERAO_SPI2_BCLK_SPI 29
> +#define CLK_PERAO_SPI3_BCLK 30
> +#define CLK_PERAO_SPI3_BCLK_SPI 31
> +#define CLK_PERAO_SPI4_BCLK 32
> +#define CLK_PERAO_SPI4_BCLK_SPI 33
> +#define CLK_PERAO_SPI5_BCLK 34
> +#define CLK_PERAO_SPI5_BCLK_SPI 35
> +#define CLK_PERAO_SPI6_BCLK 36
> +#define CLK_PERAO_SPI6_BCLK_SPI 37
> +#define CLK_PERAO_SPI7_BCLK 38
> +#define CLK_PERAO_SPI7_BCLK_SPI 39
> +#define CLK_PERAO_AP_DMA_X32W_BCLK 40
> +#define CLK_PERAO_AP_DMA_X32W_BCLK_UART 41
> +#define CLK_PERAO_AP_DMA_X32W_BCLK_I2C 42
> +#define CLK_PERAO_MSDC1_MSDC_SRC 43
> +#define CLK_PERAO_MSDC1_MSDC_SRC_MSDC1 44
> +#define CLK_PERAO_MSDC1_HCLK 45
> +#define CLK_PERAO_MSDC1_HCLK_MSDC1 46
> +#define CLK_PERAO_MSDC1_AXI 47
> +#define CLK_PERAO_MSDC1_AXI_MSDC1 48
> +#define CLK_PERAO_MSDC1_HCLK_WRAP 49
> +#define CLK_PERAO_MSDC1_HCLK_WRAP_MSDC1 50
> +#define CLK_PERAO_MSDC2_MSDC_SRC 51
> +#define CLK_PERAO_MSDC2_MSDC_SRC_MSDC2 52
> +#define CLK_PERAO_MSDC2_HCLK 53
> +#define CLK_PERAO_MSDC2_HCLK_MSDC2 54
> +#define CLK_PERAO_MSDC2_AXI 55
> +#define CLK_PERAO_MSDC2_AXI_MSDC2 56
> +#define CLK_PERAO_MSDC2_HCLK_WRAP 57
> +#define CLK_PERAO_MSDC2_HCLK_WRAP_MSDC2 58
> +#define CLK_PERAO_FLASHIF_FLASH 59
> +#define CLK_PERAO_FLASHIF_FLASH_FLASHIF 60
> +#define CLK_PERAO_FLASHIF_27M 61
> +#define CLK_PERAO_FLASHIF_27M_FLASHIF 62
> +#define CLK_PERAO_FLASHIF_DRAM 63
> +#define CLK_PERAO_FLASHIF_DRAM_FLASHIF 64
> +#define CLK_PERAO_FLASHIF_AXI 65
> +#define CLK_PERAO_FLASHIF_AXI_FLASHIF 66
> +#define CLK_PERAO_FLASHIF_BCLK 67
> +#define CLK_PERAO_FLASHIF_BCLK_FLASHIF 68
> +#define CLK_PERAO_NR_CLK 69
> +
> +/* UFSCFG_AO */
> +#define CLK_UFSAO_UNIPRO_TX_SYM 0
> +#define CLK_UFSAO_UNIPRO_TX_SYM_UFS 1
> +#define CLK_UFSAO_UNIPRO_RX_SYM0 2
> +#define CLK_UFSAO_UNIPRO_RX_SYM0_UFS 3
> +#define CLK_UFSAO_UNIPRO_RX_SYM1 4
> +#define CLK_UFSAO_UNIPRO_RX_SYM1_UFS 5
> +#define CLK_UFSAO_UNIPRO_SYS 6
> +#define CLK_UFSAO_UNIPRO_SYS_UFS 7
> +#define CLK_UFSAO_UNIPRO_SAP 8
> +#define CLK_UFSAO_UNIPRO_SAP_UFS 9
> +#define CLK_UFSAO_PHY_SAP 10
> +#define CLK_UFSAO_PHY_SAP_UFS 11
> +#define CLK_UFSAO_UFSHCI_UFS 12
> +#define CLK_UFSAO_UFSHCI_UFS_UFS 13
> +#define CLK_UFSAO_UFSHCI_AES 14
> +#define CLK_UFSAO_UFSHCI_AES_UFS 15
> +#define CLK_UFSAO_NR_CLK 16
> +
> +/* PEXTP0CFG_AO */
> +#define CLK_PEXT_PEXTP_MAC_P0_TL 0
> +#define CLK_PEXT_PEXTP_MAC_P0_TL_PCIE 1
> +#define CLK_PEXT_PEXTP_MAC_P0_REF 2
> +#define CLK_PEXT_PEXTP_MAC_P0_REF_PCIE 3
> +#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS 4
> +#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS_PCIE 5
> +#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF 6
> +#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF_PCIE 7
> +#define CLK_PEXT_PEXTP_MAC_P0_AXI_250 8
> +#define CLK_PEXT_PEXTP_MAC_P0_AXI_250_PCIE 9
> +#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB 10
> +#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB_PCIE 11
> +#define CLK_PEXT_PEXTP_MAC_P0_PL_P 12
> +#define CLK_PEXT_PEXTP_MAC_P0_PL_P_PCIE 13
> +#define CLK_PEXT_PEXTP_VLP_AO_P0_LP 14
> +#define CLK_PEXT_PEXTP_VLP_AO_P0_LP_PCIE 15
> +#define CLK_PEXT_NR_CLK 16
> +
> +/* PEXTP1CFG_AO */
> +#define CLK_PEXT1_PEXTP_MAC_P1_TL 0
> +#define CLK_PEXT1_PEXTP_MAC_P1_TL_PCIE 1
> +#define CLK_PEXT1_PEXTP_MAC_P1_REF 2
> +#define CLK_PEXT1_PEXTP_MAC_P1_REF_PCIE 3
> +#define CLK_PEXT1_PEXTP_MAC_P2_TL 4
> +#define CLK_PEXT1_PEXTP_MAC_P2_TL_PCIE 5
> +#define CLK_PEXT1_PEXTP_MAC_P2_REF 6
> +#define CLK_PEXT1_PEXTP_MAC_P2_REF_PCIE 7
> +#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS 8
> +#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS_PCIE 9
> +#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF 10
> +#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF_PCIE 11
> +#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS 12
> +#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS_PCIE 13
> +#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF 14
> +#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF_PCIE 15
> +#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250 16
> +#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250_PCIE 17
> +#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB 18
> +#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB_PCIE 19
> +#define CLK_PEXT1_PEXTP_MAC_P1_PL_P 20
> +#define CLK_PEXT1_PEXTP_MAC_P1_PL_P_PCIE 21
> +#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250 22
> +#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250_PCIE 23
> +#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB 24
> +#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB_PCIE 25
> +#define CLK_PEXT1_PEXTP_MAC_P2_PL_P 26
> +#define CLK_PEXT1_PEXTP_MAC_P2_PL_P_PCIE 27
> +#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP 28
> +#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP_PCIE 29
> +#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP 30
> +#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP_PCIE 31
> +#define CLK_PEXT1_NR_CLK 32
> +
> +/* VLP_CKSYS */
> +#define CLK_VLP_CK_VLP_APLL1 0
> +#define CLK_VLP_CK_VLP_APLL2 1
> +#define CLK_VLP_CK_SCP_SEL 2
> +#define CLK_VLP_CK_SCP_SPI_SEL 3
> +#define CLK_VLP_CK_SCP_IIC_SEL 4
> +#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 5
> +#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 6
> +#define CLK_VLP_CK_SPMI_M_TIA_32K_SEL 7
> +#define CLK_VLP_CK_APXGPT_26M_BCLK_SEL 8
> +#define CLK_VLP_CK_DPSW_SEL 9
> +#define CLK_VLP_CK_DPSW_CENTRAL_SEL 10
> +#define CLK_VLP_CK_SPMI_M_MST_SEL 11
> +#define CLK_VLP_CK_DVFSRC_SEL 12
> +#define CLK_VLP_CK_PWM_VLP_SEL 13
> +#define CLK_VLP_CK_AXI_VLP_SEL 14
> +#define CLK_VLP_CK_SYSTIMER_26M_SEL 15
> +#define CLK_VLP_CK_SSPM_SEL 16
> +#define CLK_VLP_CK_SRCK_SEL 17
> +#define CLK_VLP_CK_CAMTG0_SEL 18
> +#define CLK_VLP_CK_CAMTG1_SEL 19
> +#define CLK_VLP_CK_CAMTG2_SEL 20
> +#define CLK_VLP_CK_CAMTG3_SEL 21
> +#define CLK_VLP_CK_CAMTG4_SEL 22
> +#define CLK_VLP_CK_CAMTG5_SEL 23
> +#define CLK_VLP_CK_CAMTG6_SEL 24
> +#define CLK_VLP_CK_CAMTG7_SEL 25
> +#define CLK_VLP_CK_SSPM_26M_SEL 26
> +#define CLK_VLP_CK_ULPOSC_SSPM_SEL 27
> +#define CLK_VLP_CK_VLP_PBUS_26M_SEL 28
> +#define CLK_VLP_CK_DEBUG_ERR_FLAG_SEL 29
> +#define CLK_VLP_CK_DPMSRDMA_SEL 30
> +#define CLK_VLP_CK_VLP_PBUS_156M_SEL 31
> +#define CLK_VLP_CK_SPM_SEL 32
> +#define CLK_VLP_CK_MMINFRA_VLP_SEL 33
> +#define CLK_VLP_CK_USB_TOP_SEL 34
> +#define CLK_VLP_CK_USB_XHCI_SEL 35
> +#define CLK_VLP_CK_NOC_VLP_SEL 36
> +#define CLK_VLP_CK_AUDIO_H_SEL 37
> +#define CLK_VLP_CK_AUD_ENGEN1_SEL 38
> +#define CLK_VLP_CK_AUD_ENGEN2_SEL 39
> +#define CLK_VLP_CK_AUD_INTBUS_SEL 40
> +#define CLK_VLP_CK_SPVLP_26M_SEL 41
> +#define CLK_VLP_CK_SPU0_VLP_SEL 42
> +#define CLK_VLP_CK_SPU1_VLP_SEL 43
> +#define CLK_VLP_CK_OSC3 44
> +#define CLK_VLP_CK_CLKSQ 45
> +#define CLK_VLP_CK_AUDIO_H 46
> +#define CLK_VLP_CK_AUD_ENGEN1 47
> +#define CLK_VLP_CK_AUD_ENGEN2 48
> +#define CLK_VLP_CK_INFRA_26M 49
> +#define CLK_VLP_CK_AUD_CLKSQ 50
> +#define CLK_VLP_CK_NR_CLK 51
> +
> +/* AFE */
This is part of the afe block, and should be handled internally, i.e.
it should not be a separate binding from the audio parts.
> +#define CLK_AFE_PCM1 0
> +#define CLK_AFE_PCM1_AFE 1
> +#define CLK_AFE_PCM0 2
> +#define CLK_AFE_PCM0_AFE 3
> +#define CLK_AFE_CM2 4
> +#define CLK_AFE_CM2_AFE 5
> +#define CLK_AFE_CM1 6
> +#define CLK_AFE_CM1_AFE 7
> +#define CLK_AFE_CM0 8
> +#define CLK_AFE_CM0_AFE 9
> +#define CLK_AFE_STF 10
> +#define CLK_AFE_STF_AFE 11
> +#define CLK_AFE_HW_GAIN23 12
> +#define CLK_AFE_HW_GAIN23_AFE 13
> +#define CLK_AFE_HW_GAIN01 14
> +#define CLK_AFE_HW_GAIN01_AFE 15
> +#define CLK_AFE_FM_I2S 16
> +#define CLK_AFE_FM_I2S_AFE 17
> +#define CLK_AFE_MTKAIFV4 18
> +#define CLK_AFE_MTKAIFV4_AFE 19
> +#define CLK_AFE_UL2_ADC_HIRES_TML 20
> +#define CLK_AFE_UL2_ADC_HIRES_TML_AFE 21
> +#define CLK_AFE_UL2_ADC_HIRES 22
> +#define CLK_AFE_UL2_ADC_HIRES_AFE 23
> +#define CLK_AFE_UL2_TML 24
> +#define CLK_AFE_UL2_TML_AFE 25
> +#define CLK_AFE_UL2_ADC 26
> +#define CLK_AFE_UL2_ADC_AFE 27
> +#define CLK_AFE_UL1_ADC_HIRES_TML 28
> +#define CLK_AFE_UL1_ADC_HIRES_TML_AFE 29
> +#define CLK_AFE_UL1_ADC_HIRES 30
> +#define CLK_AFE_UL1_ADC_HIRES_AFE 31
> +#define CLK_AFE_UL1_TML 32
> +#define CLK_AFE_UL1_TML_AFE 33
> +#define CLK_AFE_UL1_ADC 34
> +#define CLK_AFE_UL1_ADC_AFE 35
> +#define CLK_AFE_UL0_ADC_HIRES_TML 36
> +#define CLK_AFE_UL0_ADC_HIRES_TML_AFE 37
> +#define CLK_AFE_UL0_ADC_HIRES 38
> +#define CLK_AFE_UL0_ADC_HIRES_AFE 39
> +#define CLK_AFE_UL0_TML 40
> +#define CLK_AFE_UL0_TML_AFE 41
> +#define CLK_AFE_UL0_ADC 42
> +#define CLK_AFE_UL0_ADC_AFE 43
> +#define CLK_AFE_ETDM_IN6 44
> +#define CLK_AFE_ETDM_IN6_AFE 45
> +#define CLK_AFE_ETDM_IN5 46
> +#define CLK_AFE_ETDM_IN5_AFE 47
> +#define CLK_AFE_ETDM_IN4 48
> +#define CLK_AFE_ETDM_IN4_AFE 49
> +#define CLK_AFE_ETDM_IN3 50
> +#define CLK_AFE_ETDM_IN3_AFE 51
> +#define CLK_AFE_ETDM_IN2 52
> +#define CLK_AFE_ETDM_IN2_AFE 53
> +#define CLK_AFE_ETDM_IN1 54
> +#define CLK_AFE_ETDM_IN1_AFE 55
> +#define CLK_AFE_ETDM_IN0 56
> +#define CLK_AFE_ETDM_IN0_AFE 57
> +#define CLK_AFE_ETDM_OUT6 58
> +#define CLK_AFE_ETDM_OUT6_AFE 59
> +#define CLK_AFE_ETDM_OUT5 60
> +#define CLK_AFE_ETDM_OUT5_AFE 61
> +#define CLK_AFE_ETDM_OUT4 62
> +#define CLK_AFE_ETDM_OUT4_AFE 63
> +#define CLK_AFE_ETDM_OUT3 64
> +#define CLK_AFE_ETDM_OUT3_AFE 65
> +#define CLK_AFE_ETDM_OUT2 66
> +#define CLK_AFE_ETDM_OUT2_AFE 67
> +#define CLK_AFE_ETDM_OUT1 68
> +#define CLK_AFE_ETDM_OUT1_AFE 69
> +#define CLK_AFE_ETDM_OUT0 70
> +#define CLK_AFE_ETDM_OUT0_AFE 71
> +#define CLK_AFE_TDM_OUT 72
> +#define CLK_AFE_TDM_OUT_AFE 73
> +#define CLK_AFE_GENERAL15_ASRC 74
> +#define CLK_AFE_GENERAL15_ASRC_AFE 75
> +#define CLK_AFE_GENERAL14_ASRC 76
> +#define CLK_AFE_GENERAL14_ASRC_AFE 77
> +#define CLK_AFE_GENERAL13_ASRC 78
> +#define CLK_AFE_GENERAL13_ASRC_AFE 79
> +#define CLK_AFE_GENERAL12_ASRC 80
> +#define CLK_AFE_GENERAL12_ASRC_AFE 81
> +#define CLK_AFE_GENERAL11_ASRC 82
> +#define CLK_AFE_GENERAL11_ASRC_AFE 83
> +#define CLK_AFE_GENERAL10_ASRC 84
> +#define CLK_AFE_GENERAL10_ASRC_AFE 85
> +#define CLK_AFE_GENERAL9_ASRC 86
> +#define CLK_AFE_GENERAL9_ASRC_AFE 87
> +#define CLK_AFE_GENERAL8_ASRC 88
> +#define CLK_AFE_GENERAL8_ASRC_AFE 89
> +#define CLK_AFE_GENERAL7_ASRC 90
> +#define CLK_AFE_GENERAL7_ASRC_AFE 91
> +#define CLK_AFE_GENERAL6_ASRC 92
> +#define CLK_AFE_GENERAL6_ASRC_AFE 93
> +#define CLK_AFE_GENERAL5_ASRC 94
> +#define CLK_AFE_GENERAL5_ASRC_AFE 95
> +#define CLK_AFE_GENERAL4_ASRC 96
> +#define CLK_AFE_GENERAL4_ASRC_AFE 97
> +#define CLK_AFE_GENERAL3_ASRC 98
> +#define CLK_AFE_GENERAL3_ASRC_AFE 99
> +#define CLK_AFE_GENERAL2_ASRC 100
> +#define CLK_AFE_GENERAL2_ASRC_AFE 101
> +#define CLK_AFE_GENERAL1_ASRC 102
> +#define CLK_AFE_GENERAL1_ASRC_AFE 103
> +#define CLK_AFE_GENERAL0_ASRC 104
> +#define CLK_AFE_GENERAL0_ASRC_AFE 105
> +#define CLK_AFE_CONNSYS_I2S_ASRC 106
> +#define CLK_AFE_CONNSYS_I2S_ASRC_AFE 107
> +#define CLK_AFE_AUDIO_HOPPING 108
> +#define CLK_AFE_AUDIO_HOPPING_AFE 109
> +#define CLK_AFE_AUDIO_F26M 110
> +#define CLK_AFE_AUDIO_F26M_AFE 111
> +#define CLK_AFE_APLL1 112
> +#define CLK_AFE_APLL1_AFE 113
> +#define CLK_AFE_APLL2 114
> +#define CLK_AFE_APLL2_AFE 115
> +#define CLK_AFE_H208M 116
> +#define CLK_AFE_H208M_AFE 117
> +#define CLK_AFE_APLL_TUNER2 118
> +#define CLK_AFE_APLL_TUNER2_AFE 119
> +#define CLK_AFE_APLL_TUNER1 120
> +#define CLK_AFE_APLL_TUNER1_AFE 121
> +#define CLK_AFE_NR_CLK 122
Thanks
ChenYu
> +
> +/* DISPSYS_CONFIG */
> +#define CLK_MM_CONFIG 0
> +#define CLK_MM_CONFIG_DISP 1
> +#define CLK_MM_DISP_MUTEX0 2
> +#define CLK_MM_DISP_MUTEX0_DISP 3
> +#define CLK_MM_DISP_AAL0 4
> +#define CLK_MM_DISP_AAL0_PQ 5
> +#define CLK_MM_DISP_AAL1 6
> +#define CLK_MM_DISP_AAL1_PQ 7
> +#define CLK_MM_DISP_C3D0 8
> +#define CLK_MM_DISP_C3D0_PQ 9
> +#define CLK_MM_DISP_C3D1 10
> +#define CLK_MM_DISP_C3D1_PQ 11
> +#define CLK_MM_DISP_C3D2 12
> +#define CLK_MM_DISP_C3D2_PQ 13
> +#define CLK_MM_DISP_C3D3 14
> +#define CLK_MM_DISP_C3D3_PQ 15
> +#define CLK_MM_DISP_CCORR0 16
> +#define CLK_MM_DISP_CCORR0_PQ 17
> +#define CLK_MM_DISP_CCORR1 18
> +#define CLK_MM_DISP_CCORR1_PQ 19
> +#define CLK_MM_DISP_CCORR2 20
> +#define CLK_MM_DISP_CCORR2_PQ 21
> +#define CLK_MM_DISP_CCORR3 22
> +#define CLK_MM_DISP_CCORR3_PQ 23
> +#define CLK_MM_DISP_CHIST0 24
> +#define CLK_MM_DISP_CHIST0_PQ 25
> +#define CLK_MM_DISP_CHIST1 26
> +#define CLK_MM_DISP_CHIST1_PQ 27
> +#define CLK_MM_DISP_COLOR0 28
> +#define CLK_MM_DISP_COLOR0_PQ 29
> +#define CLK_MM_DISP_COLOR1 30
> +#define CLK_MM_DISP_COLOR1_PQ 31
> +#define CLK_MM_DISP_DITHER0 32
> +#define CLK_MM_DISP_DITHER0_PQ 33
> +#define CLK_MM_DISP_DITHER1 34
> +#define CLK_MM_DISP_DITHER1_PQ 35
> +#define CLK_MM_DISP_DLI_ASYNC0 36
> +#define CLK_MM_DISP_DLI_ASYNC0_DISP 37
> +#define CLK_MM_DISP_DLI_ASYNC1 38
> +#define CLK_MM_DISP_DLI_ASYNC1_DISP 39
> +#define CLK_MM_DISP_DLI_ASYNC2 40
> +#define CLK_MM_DISP_DLI_ASYNC2_DISP 41
> +#define CLK_MM_DISP_DLI_ASYNC3 42
> +#define CLK_MM_DISP_DLI_ASYNC3_DISP 43
> +#define CLK_MM_DISP_DLI_ASYNC4 44
> +#define CLK_MM_DISP_DLI_ASYNC4_DISP 45
> +#define CLK_MM_DISP_DLI_ASYNC5 46
> +#define CLK_MM_DISP_DLI_ASYNC5_DISP 47
> +#define CLK_MM_DISP_DLI_ASYNC6 48
> +#define CLK_MM_DISP_DLI_ASYNC6_DISP 49
> +#define CLK_MM_DISP_DLI_ASYNC7 50
> +#define CLK_MM_DISP_DLI_ASYNC7_DISP 51
> +#define CLK_MM_DISP_DLI_ASYNC8 52
> +#define CLK_MM_DISP_DLI_ASYNC8_DISP 53
> +#define CLK_MM_DISP_DLI_ASYNC9 54
> +#define CLK_MM_DISP_DLI_ASYNC9_DISP 55
> +#define CLK_MM_DISP_DLI_ASYNC10 56
> +#define CLK_MM_DISP_DLI_ASYNC10_DISP 57
> +#define CLK_MM_DISP_DLI_ASYNC11 58
> +#define CLK_MM_DISP_DLI_ASYNC11_DISP 59
> +#define CLK_MM_DISP_DLI_ASYNC12 60
> +#define CLK_MM_DISP_DLI_ASYNC12_DISP 61
> +#define CLK_MM_DISP_DLI_ASYNC13 62
> +#define CLK_MM_DISP_DLI_ASYNC13_DISP 63
> +#define CLK_MM_DISP_DLI_ASYNC14 64
> +#define CLK_MM_DISP_DLI_ASYNC14_DISP 65
> +#define CLK_MM_DISP_DLI_ASYNC15 66
> +#define CLK_MM_DISP_DLI_ASYNC15_DISP 67
> +#define CLK_MM_DISP_DLO_ASYNC0 68
> +#define CLK_MM_DISP_DLO_ASYNC0_DISP 69
> +#define CLK_MM_DISP_DLO_ASYNC1 70
> +#define CLK_MM_DISP_DLO_ASYNC1_DISP 71
> +#define CLK_MM_DISP_DLO_ASYNC2 72
> +#define CLK_MM_DISP_DLO_ASYNC2_DISP 73
> +#define CLK_MM_DISP_DLO_ASYNC3 74
> +#define CLK_MM_DISP_DLO_ASYNC3_DISP 75
> +#define CLK_MM_DISP_DLO_ASYNC4 76
> +#define CLK_MM_DISP_DLO_ASYNC4_DISP 77
> +#define CLK_MM_DISP_DLO_ASYNC5 78
> +#define CLK_MM_DISP_DLO_ASYNC5_DISP 79
> +#define CLK_MM_DISP_DLO_ASYNC6 80
> +#define CLK_MM_DISP_DLO_ASYNC6_DISP 81
> +#define CLK_MM_DISP_DLO_ASYNC7 82
> +#define CLK_MM_DISP_DLO_ASYNC7_DISP 83
> +#define CLK_MM_DISP_DLO_ASYNC8 84
> +#define CLK_MM_DISP_DLO_ASYNC8_DISP 85
> +#define CLK_MM_DISP_GAMMA0 86
> +#define CLK_MM_DISP_GAMMA0_PQ 87
> +#define CLK_MM_DISP_GAMMA1 88
> +#define CLK_MM_DISP_GAMMA1_PQ 89
> +#define CLK_MM_MDP_AAL0 90
> +#define CLK_MM_MDP_AAL0_PQ 91
> +#define CLK_MM_MDP_AAL1 92
> +#define CLK_MM_MDP_AAL1_PQ 93
> +#define CLK_MM_MDP_RDMA0 94
> +#define CLK_MM_MDP_RDMA0_DISP 95
> +#define CLK_MM_DISP_POSTMASK0 96
> +#define CLK_MM_DISP_POSTMASK0_DISP 97
> +#define CLK_MM_DISP_POSTMASK1 98
> +#define CLK_MM_DISP_POSTMASK1_DISP 99
> +#define CLK_MM_MDP_RSZ0 100
> +#define CLK_MM_MDP_RSZ0_DISP 101
> +#define CLK_MM_MDP_RSZ1 102
> +#define CLK_MM_MDP_RSZ1_DISP 103
> +#define CLK_MM_DISP_SPR0 104
> +#define CLK_MM_DISP_SPR0_DISP 105
> +#define CLK_MM_DISP_TDSHP0 106
> +#define CLK_MM_DISP_TDSHP0_PQ 107
> +#define CLK_MM_DISP_TDSHP1 108
> +#define CLK_MM_DISP_TDSHP1_PQ 109
> +#define CLK_MM_DISP_WDMA0 110
> +#define CLK_MM_DISP_WDMA0_DISP 111
> +#define CLK_MM_DISP_Y2R0 112
> +#define CLK_MM_DISP_Y2R0_DISP 113
> +#define CLK_MM_SMI_SUB_COMM0 114
> +#define CLK_MM_SMI_SUB_COMM0_SMI 115
> +#define CLK_MM_DISP_FAKE_ENG0 116
> +#define CLK_MM_DISP_FAKE_ENG0_DISP 117
> +#define CLK_MM_NR_CLK 118
> +
> +/* DISPSYS1_CONFIG */
> +#define CLK_MM1_DISPSYS1_CONFIG 0
> +#define CLK_MM1_DISPSYS1_CONFIG_DISP 1
> +#define CLK_MM1_DISPSYS1_S_CONFIG 2
> +#define CLK_MM1_DISPSYS1_S_CONFIG_DISP 3
> +#define CLK_MM1_DISP_MUTEX0 4
> +#define CLK_MM1_DISP_MUTEX0_DISP 5
> +#define CLK_MM1_DISP_DLI_ASYNC20 6
> +#define CLK_MM1_DISP_DLI_ASYNC20_DISP 7
> +#define CLK_MM1_DISP_DLI_ASYNC21 8
> +#define CLK_MM1_DISP_DLI_ASYNC21_DISP 9
> +#define CLK_MM1_DISP_DLI_ASYNC22 10
> +#define CLK_MM1_DISP_DLI_ASYNC22_DISP 11
> +#define CLK_MM1_DISP_DLI_ASYNC23 12
> +#define CLK_MM1_DISP_DLI_ASYNC23_DISP 13
> +#define CLK_MM1_DISP_DLI_ASYNC24 14
> +#define CLK_MM1_DISP_DLI_ASYNC24_DISP 15
> +#define CLK_MM1_DISP_DLI_ASYNC25 16
> +#define CLK_MM1_DISP_DLI_ASYNC25_DISP 17
> +#define CLK_MM1_DISP_DLI_ASYNC26 18
> +#define CLK_MM1_DISP_DLI_ASYNC26_DISP 19
> +#define CLK_MM1_DISP_DLI_ASYNC27 20
> +#define CLK_MM1_DISP_DLI_ASYNC27_DISP 21
> +#define CLK_MM1_DISP_DLI_ASYNC28 22
> +#define CLK_MM1_DISP_DLI_ASYNC28_DISP 23
> +#define CLK_MM1_DISP_RELAY0 24
> +#define CLK_MM1_DISP_RELAY0_DISP 25
> +#define CLK_MM1_DISP_RELAY1 26
> +#define CLK_MM1_DISP_RELAY1_DISP 27
> +#define CLK_MM1_DISP_RELAY2 28
> +#define CLK_MM1_DISP_RELAY2_DISP 29
> +#define CLK_MM1_DISP_RELAY3 30
> +#define CLK_MM1_DISP_RELAY3_DISP 31
> +#define CLK_MM1_DISP_DP_INTF0 32
> +#define CLK_MM1_DISP_DP_INTF0_DISP 33
> +#define CLK_MM1_DISP_DP_INTF1 34
> +#define CLK_MM1_DISP_DP_INTF1_DISP 35
> +#define CLK_MM1_DISP_DSC_WRAP0 36
> +#define CLK_MM1_DISP_DSC_WRAP0_DISP 37
> +#define CLK_MM1_DISP_DSC_WRAP1 38
> +#define CLK_MM1_DISP_DSC_WRAP1_DISP 39
> +#define CLK_MM1_DISP_DSC_WRAP2 40
> +#define CLK_MM1_DISP_DSC_WRAP2_DISP 41
> +#define CLK_MM1_DISP_DSC_WRAP3 42
> +#define CLK_MM1_DISP_DSC_WRAP3_DISP 43
> +#define CLK_MM1_DISP_DSI0 44
> +#define CLK_MM1_DISP_DSI0_DISP 45
> +#define CLK_MM1_DISP_DSI1 46
> +#define CLK_MM1_DISP_DSI1_DISP 47
> +#define CLK_MM1_DISP_DSI2 48
> +#define CLK_MM1_DISP_DSI2_DISP 49
> +#define CLK_MM1_DISP_DVO0 50
> +#define CLK_MM1_DISP_DVO0_DISP 51
> +#define CLK_MM1_DISP_GDMA0 52
> +#define CLK_MM1_DISP_GDMA0_DISP 53
> +#define CLK_MM1_DISP_MERGE0 54
> +#define CLK_MM1_DISP_MERGE0_DISP 55
> +#define CLK_MM1_DISP_MERGE1 56
> +#define CLK_MM1_DISP_MERGE1_DISP 57
> +#define CLK_MM1_DISP_MERGE2 58
> +#define CLK_MM1_DISP_MERGE2_DISP 59
> +#define CLK_MM1_DISP_ODDMR0 60
> +#define CLK_MM1_DISP_ODDMR0_PQ 61
> +#define CLK_MM1_DISP_POSTALIGN0 62
> +#define CLK_MM1_DISP_POSTALIGN0_PQ 63
> +#define CLK_MM1_DISP_DITHER2 64
> +#define CLK_MM1_DISP_DITHER2_PQ 65
> +#define CLK_MM1_DISP_R2Y0 66
> +#define CLK_MM1_DISP_R2Y0_DISP 67
> +#define CLK_MM1_DISP_SPLITTER0 68
> +#define CLK_MM1_DISP_SPLITTER0_DISP 69
> +#define CLK_MM1_DISP_SPLITTER1 70
> +#define CLK_MM1_DISP_SPLITTER1_DISP 71
> +#define CLK_MM1_DISP_SPLITTER2 72
> +#define CLK_MM1_DISP_SPLITTER2_DISP 73
> +#define CLK_MM1_DISP_SPLITTER3 74
> +#define CLK_MM1_DISP_SPLITTER3_DISP 75
> +#define CLK_MM1_DISP_VDCM0 76
> +#define CLK_MM1_DISP_VDCM0_DISP 77
> +#define CLK_MM1_DISP_WDMA1 78
> +#define CLK_MM1_DISP_WDMA1_DISP 79
> +#define CLK_MM1_DISP_WDMA2 80
> +#define CLK_MM1_DISP_WDMA2_DISP 81
> +#define CLK_MM1_DISP_WDMA3 82
> +#define CLK_MM1_DISP_WDMA3_DISP 83
> +#define CLK_MM1_DISP_WDMA4 84
> +#define CLK_MM1_DISP_WDMA4_DISP 85
> +#define CLK_MM1_MDP_RDMA1 86
> +#define CLK_MM1_MDP_RDMA1_DISP 87
> +#define CLK_MM1_SMI_LARB0 88
> +#define CLK_MM1_SMI_LARB0_SMI 89
> +#define CLK_MM1_MOD1 90
> +#define CLK_MM1_MOD1_DISP 91
> +#define CLK_MM1_MOD2 92
> +#define CLK_MM1_MOD2_DISP 93
> +#define CLK_MM1_MOD3 94
> +#define CLK_MM1_MOD3_DISP 95
> +#define CLK_MM1_MOD4 96
> +#define CLK_MM1_MOD4_DISP 97
> +#define CLK_MM1_MOD5 98
> +#define CLK_MM1_MOD5_DISP 99
> +#define CLK_MM1_MOD6 100
> +#define CLK_MM1_MOD6_DISP 101
> +#define CLK_MM1_CK_CG0 102
> +#define CLK_MM1_CK_CG0_DISP 103
> +#define CLK_MM1_CK_CG1 104
> +#define CLK_MM1_CK_CG1_DISP 105
> +#define CLK_MM1_CK_CG2 106
> +#define CLK_MM1_CK_CG2_DISP 107
> +#define CLK_MM1_CK_CG3 108
> +#define CLK_MM1_CK_CG3_DISP 109
> +#define CLK_MM1_CK_CG4 110
> +#define CLK_MM1_CK_CG4_DISP 111
> +#define CLK_MM1_CK_CG5 112
> +#define CLK_MM1_CK_CG5_DISP 113
> +#define CLK_MM1_CK_CG6 114
> +#define CLK_MM1_CK_CG6_DISP 115
> +#define CLK_MM1_CK_CG7 116
> +#define CLK_MM1_CK_CG7_DISP 117
> +#define CLK_MM1_F26M 118
> +#define CLK_MM1_F26M_DISP 119
> +#define CLK_MM1_NR_CLK 120
> +
> +/* OVLSYS_CONFIG */
> +#define CLK_OVLSYS_CONFIG 0
> +#define CLK_OVLSYS_CONFIG_DISP 1
> +#define CLK_OVL_FAKE_ENG0 2
> +#define CLK_OVL_FAKE_ENG0_DISP 3
> +#define CLK_OVL_FAKE_ENG1 4
> +#define CLK_OVL_FAKE_ENG1_DISP 5
> +#define CLK_OVL_MUTEX0 6
> +#define CLK_OVL_MUTEX0_DISP 7
> +#define CLK_OVL_EXDMA0 8
> +#define CLK_OVL_EXDMA0_DISP 9
> +#define CLK_OVL_EXDMA1 10
> +#define CLK_OVL_EXDMA1_DISP 11
> +#define CLK_OVL_EXDMA2 12
> +#define CLK_OVL_EXDMA2_DISP 13
> +#define CLK_OVL_EXDMA3 14
> +#define CLK_OVL_EXDMA3_DISP 15
> +#define CLK_OVL_EXDMA4 16
> +#define CLK_OVL_EXDMA4_DISP 17
> +#define CLK_OVL_EXDMA5 18
> +#define CLK_OVL_EXDMA5_DISP 19
> +#define CLK_OVL_EXDMA6 20
> +#define CLK_OVL_EXDMA6_DISP 21
> +#define CLK_OVL_EXDMA7 22
> +#define CLK_OVL_EXDMA7_DISP 23
> +#define CLK_OVL_EXDMA8 24
> +#define CLK_OVL_EXDMA8_DISP 25
> +#define CLK_OVL_EXDMA9 26
> +#define CLK_OVL_EXDMA9_DISP 27
> +#define CLK_OVL_BLENDER0 28
> +#define CLK_OVL_BLENDER0_DISP 29
> +#define CLK_OVL_BLENDER1 30
> +#define CLK_OVL_BLENDER1_DISP 31
> +#define CLK_OVL_BLENDER2 32
> +#define CLK_OVL_BLENDER2_DISP 33
> +#define CLK_OVL_BLENDER3 34
> +#define CLK_OVL_BLENDER3_DISP 35
> +#define CLK_OVL_BLENDER4 36
> +#define CLK_OVL_BLENDER4_DISP 37
> +#define CLK_OVL_BLENDER5 38
> +#define CLK_OVL_BLENDER5_DISP 39
> +#define CLK_OVL_BLENDER6 40
> +#define CLK_OVL_BLENDER6_DISP 41
> +#define CLK_OVL_BLENDER7 42
> +#define CLK_OVL_BLENDER7_DISP 43
> +#define CLK_OVL_BLENDER8 44
> +#define CLK_OVL_BLENDER8_DISP 45
> +#define CLK_OVL_BLENDER9 46
> +#define CLK_OVL_BLENDER9_DISP 47
> +#define CLK_OVL_OUTPROC0 48
> +#define CLK_OVL_OUTPROC0_DISP 49
> +#define CLK_OVL_OUTPROC1 50
> +#define CLK_OVL_OUTPROC1_DISP 51
> +#define CLK_OVL_OUTPROC2 52
> +#define CLK_OVL_OUTPROC2_DISP 53
> +#define CLK_OVL_OUTPROC3 54
> +#define CLK_OVL_OUTPROC3_DISP 55
> +#define CLK_OVL_OUTPROC4 56
> +#define CLK_OVL_OUTPROC4_DISP 57
> +#define CLK_OVL_OUTPROC5 58
> +#define CLK_OVL_OUTPROC5_DISP 59
> +#define CLK_OVL_MDP_RSZ0 60
> +#define CLK_OVL_MDP_RSZ0_DISP 61
> +#define CLK_OVL_MDP_RSZ1 62
> +#define CLK_OVL_MDP_RSZ1_DISP 63
> +#define CLK_OVL_DISP_WDMA0 64
> +#define CLK_OVL_DISP_WDMA0_DISP 65
> +#define CLK_OVL_DISP_WDMA1 66
> +#define CLK_OVL_DISP_WDMA1_DISP 67
> +#define CLK_OVL_UFBC_WDMA0 68
> +#define CLK_OVL_UFBC_WDMA0_DISP 69
> +#define CLK_OVL_MDP_RDMA0 70
> +#define CLK_OVL_MDP_RDMA0_DISP 71
> +#define CLK_OVL_MDP_RDMA1 72
> +#define CLK_OVL_MDP_RDMA1_DISP 73
> +#define CLK_OVL_BWM0 74
> +#define CLK_OVL_BWM0_DISP 75
> +#define CLK_OVL_DLI0 76
> +#define CLK_OVL_DLI0_DISP 77
> +#define CLK_OVL_DLI1 78
> +#define CLK_OVL_DLI1_DISP 79
> +#define CLK_OVL_DLI2 80
> +#define CLK_OVL_DLI2_DISP 81
> +#define CLK_OVL_DLI3 82
> +#define CLK_OVL_DLI3_DISP 83
> +#define CLK_OVL_DLI4 84
> +#define CLK_OVL_DLI4_DISP 85
> +#define CLK_OVL_DLI5 86
> +#define CLK_OVL_DLI5_DISP 87
> +#define CLK_OVL_DLI6 88
> +#define CLK_OVL_DLI6_DISP 89
> +#define CLK_OVL_DLI7 90
> +#define CLK_OVL_DLI7_DISP 91
> +#define CLK_OVL_DLI8 92
> +#define CLK_OVL_DLI8_DISP 93
> +#define CLK_OVL_DLO0 94
> +#define CLK_OVL_DLO0_DISP 95
> +#define CLK_OVL_DLO1 96
> +#define CLK_OVL_DLO1_DISP 97
> +#define CLK_OVL_DLO2 98
> +#define CLK_OVL_DLO2_DISP 99
> +#define CLK_OVL_DLO3 100
> +#define CLK_OVL_DLO3_DISP 101
> +#define CLK_OVL_DLO4 102
> +#define CLK_OVL_DLO4_DISP 103
> +#define CLK_OVL_DLO5 104
> +#define CLK_OVL_DLO5_DISP 105
> +#define CLK_OVL_DLO6 106
> +#define CLK_OVL_DLO6_DISP 107
> +#define CLK_OVL_DLO7 108
> +#define CLK_OVL_DLO7_DISP 109
> +#define CLK_OVL_DLO8 110
> +#define CLK_OVL_DLO8_DISP 111
> +#define CLK_OVL_DLO9 112
> +#define CLK_OVL_DLO9_DISP 113
> +#define CLK_OVL_DLO10 114
> +#define CLK_OVL_DLO10_DISP 115
> +#define CLK_OVL_DLO11 116
> +#define CLK_OVL_DLO11_DISP 117
> +#define CLK_OVL_DLO12 118
> +#define CLK_OVL_DLO12_DISP 119
> +#define CLK_OVLSYS_RELAY0 120
> +#define CLK_OVLSYS_RELAY0_DISP 121
> +#define CLK_OVL_INLINEROT0 122
> +#define CLK_OVL_INLINEROT0_DISP 123
> +#define CLK_OVL_SMI 124
> +#define CLK_OVL_SMI_SMI 125
> +#define CLK_OVL_NR_CLK 126
> +
> +/* OVLSYS1_CONFIG */
> +#define CLK_OVL1_OVLSYS_CONFIG 0
> +#define CLK_OVL1_OVLSYS_CONFIG_DISP 1
> +#define CLK_OVL1_OVL_FAKE_ENG0 2
> +#define CLK_OVL1_OVL_FAKE_ENG0_DISP 3
> +#define CLK_OVL1_OVL_FAKE_ENG1 4
> +#define CLK_OVL1_OVL_FAKE_ENG1_DISP 5
> +#define CLK_OVL1_OVL_MUTEX0 6
> +#define CLK_OVL1_OVL_MUTEX0_DISP 7
> +#define CLK_OVL1_OVL_EXDMA0 8
> +#define CLK_OVL1_OVL_EXDMA0_DISP 9
> +#define CLK_OVL1_OVL_EXDMA1 10
> +#define CLK_OVL1_OVL_EXDMA1_DISP 11
> +#define CLK_OVL1_OVL_EXDMA2 12
> +#define CLK_OVL1_OVL_EXDMA2_DISP 13
> +#define CLK_OVL1_OVL_EXDMA3 14
> +#define CLK_OVL1_OVL_EXDMA3_DISP 15
> +#define CLK_OVL1_OVL_EXDMA4 16
> +#define CLK_OVL1_OVL_EXDMA4_DISP 17
> +#define CLK_OVL1_OVL_EXDMA5 18
> +#define CLK_OVL1_OVL_EXDMA5_DISP 19
> +#define CLK_OVL1_OVL_EXDMA6 20
> +#define CLK_OVL1_OVL_EXDMA6_DISP 21
> +#define CLK_OVL1_OVL_EXDMA7 22
> +#define CLK_OVL1_OVL_EXDMA7_DISP 23
> +#define CLK_OVL1_OVL_EXDMA8 24
> +#define CLK_OVL1_OVL_EXDMA8_DISP 25
> +#define CLK_OVL1_OVL_EXDMA9 26
> +#define CLK_OVL1_OVL_EXDMA9_DISP 27
> +#define CLK_OVL1_OVL_BLENDER0 28
> +#define CLK_OVL1_OVL_BLENDER0_DISP 29
> +#define CLK_OVL1_OVL_BLENDER1 30
> +#define CLK_OVL1_OVL_BLENDER1_DISP 31
> +#define CLK_OVL1_OVL_BLENDER2 32
> +#define CLK_OVL1_OVL_BLENDER2_DISP 33
> +#define CLK_OVL1_OVL_BLENDER3 34
> +#define CLK_OVL1_OVL_BLENDER3_DISP 35
> +#define CLK_OVL1_OVL_BLENDER4 36
> +#define CLK_OVL1_OVL_BLENDER4_DISP 37
> +#define CLK_OVL1_OVL_BLENDER5 38
> +#define CLK_OVL1_OVL_BLENDER5_DISP 39
> +#define CLK_OVL1_OVL_BLENDER6 40
> +#define CLK_OVL1_OVL_BLENDER6_DISP 41
> +#define CLK_OVL1_OVL_BLENDER7 42
> +#define CLK_OVL1_OVL_BLENDER7_DISP 43
> +#define CLK_OVL1_OVL_BLENDER8 44
> +#define CLK_OVL1_OVL_BLENDER8_DISP 45
> +#define CLK_OVL1_OVL_BLENDER9 46
> +#define CLK_OVL1_OVL_BLENDER9_DISP 47
> +#define CLK_OVL1_OVL_OUTPROC0 48
> +#define CLK_OVL1_OVL_OUTPROC0_DISP 49
> +#define CLK_OVL1_OVL_OUTPROC1 50
> +#define CLK_OVL1_OVL_OUTPROC1_DISP 51
> +#define CLK_OVL1_OVL_OUTPROC2 52
> +#define CLK_OVL1_OVL_OUTPROC2_DISP 53
> +#define CLK_OVL1_OVL_OUTPROC3 54
> +#define CLK_OVL1_OVL_OUTPROC3_DISP 55
> +#define CLK_OVL1_OVL_OUTPROC4 56
> +#define CLK_OVL1_OVL_OUTPROC4_DISP 57
> +#define CLK_OVL1_OVL_OUTPROC5 58
> +#define CLK_OVL1_OVL_OUTPROC5_DISP 59
> +#define CLK_OVL1_OVL_MDP_RSZ0 60
> +#define CLK_OVL1_OVL_MDP_RSZ0_DISP 61
> +#define CLK_OVL1_OVL_MDP_RSZ1 62
> +#define CLK_OVL1_OVL_MDP_RSZ1_DISP 63
> +#define CLK_OVL1_OVL_DISP_WDMA0 64
> +#define CLK_OVL1_OVL_DISP_WDMA0_DISP 65
> +#define CLK_OVL1_OVL_DISP_WDMA1 66
> +#define CLK_OVL1_OVL_DISP_WDMA1_DISP 67
> +#define CLK_OVL1_OVL_UFBC_WDMA0 68
> +#define CLK_OVL1_OVL_UFBC_WDMA0_DISP 69
> +#define CLK_OVL1_OVL_MDP_RDMA0 70
> +#define CLK_OVL1_OVL_MDP_RDMA0_DISP 71
> +#define CLK_OVL1_OVL_MDP_RDMA1 72
> +#define CLK_OVL1_OVL_MDP_RDMA1_DISP 73
> +#define CLK_OVL1_OVL_BWM0 74
> +#define CLK_OVL1_OVL_BWM0_DISP 75
> +#define CLK_OVL1_DLI0 76
> +#define CLK_OVL1_DLI0_DISP 77
> +#define CLK_OVL1_DLI1 78
> +#define CLK_OVL1_DLI1_DISP 79
> +#define CLK_OVL1_DLI2 80
> +#define CLK_OVL1_DLI2_DISP 81
> +#define CLK_OVL1_DLI3 82
> +#define CLK_OVL1_DLI3_DISP 83
> +#define CLK_OVL1_DLI4 84
> +#define CLK_OVL1_DLI4_DISP 85
> +#define CLK_OVL1_DLI5 86
> +#define CLK_OVL1_DLI5_DISP 87
> +#define CLK_OVL1_DLI6 88
> +#define CLK_OVL1_DLI6_DISP 89
> +#define CLK_OVL1_DLI7 90
> +#define CLK_OVL1_DLI7_DISP 91
> +#define CLK_OVL1_DLI8 92
> +#define CLK_OVL1_DLI8_DISP 93
> +#define CLK_OVL1_DLO0 94
> +#define CLK_OVL1_DLO0_DISP 95
> +#define CLK_OVL1_DLO1 96
> +#define CLK_OVL1_DLO1_DISP 97
> +#define CLK_OVL1_DLO2 98
> +#define CLK_OVL1_DLO2_DISP 99
> +#define CLK_OVL1_DLO3 100
> +#define CLK_OVL1_DLO3_DISP 101
> +#define CLK_OVL1_DLO4 102
> +#define CLK_OVL1_DLO4_DISP 103
> +#define CLK_OVL1_DLO5 104
> +#define CLK_OVL1_DLO5_DISP 105
> +#define CLK_OVL1_DLO6 106
> +#define CLK_OVL1_DLO6_DISP 107
> +#define CLK_OVL1_DLO7 108
> +#define CLK_OVL1_DLO7_DISP 109
> +#define CLK_OVL1_DLO8 110
> +#define CLK_OVL1_DLO8_DISP 111
> +#define CLK_OVL1_DLO9 112
> +#define CLK_OVL1_DLO9_DISP 113
> +#define CLK_OVL1_DLO10 114
> +#define CLK_OVL1_DLO10_DISP 115
> +#define CLK_OVL1_DLO11 116
> +#define CLK_OVL1_DLO11_DISP 117
> +#define CLK_OVL1_DLO12 118
> +#define CLK_OVL1_DLO12_DISP 119
> +#define CLK_OVL1_OVLSYS_RELAY0 120
> +#define CLK_OVL1_OVLSYS_RELAY0_DISP 121
> +#define CLK_OVL1_OVL_INLINEROT0 122
> +#define CLK_OVL1_OVL_INLINEROT0_DISP 123
> +#define CLK_OVL1_SMI 124
> +#define CLK_OVL1_SMI_SMI 125
> +#define CLK_OVL1_NR_CLK 126
> +
> +/* VDEC_SOC_GCON_BASE */
> +#define CLK_VDE1_LARB1_CKEN 0
> +#define CLK_VDE1_LARB1_CKEN_VDEC 1
> +#define CLK_VDE1_LARB1_CKEN_SMI 2
> +#define CLK_VDE1_LAT_CKEN 3
> +#define CLK_VDE1_LAT_CKEN_VDEC 4
> +#define CLK_VDE1_LAT_ACTIVE 5
> +#define CLK_VDE1_LAT_ACTIVE_VDEC 6
> +#define CLK_VDE1_LAT_CKEN_ENG 7
> +#define CLK_VDE1_LAT_CKEN_ENG_VDEC 8
> +#define CLK_VDE1_VDEC_CKEN 9
> +#define CLK_VDE1_VDEC_CKEN_VDEC 10
> +#define CLK_VDE1_VDEC_ACTIVE 11
> +#define CLK_VDE1_VDEC_ACTIVE_VDEC 12
> +#define CLK_VDE1_VDEC_CKEN_ENG 13
> +#define CLK_VDE1_VDEC_CKEN_ENG_VDEC 14
> +#define CLK_VDE1_VDEC_SOC_APTV_EN 15
> +#define CLK_VDE1_VDEC_SOC_APTV_EN_VDEC 16
> +#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN 17
> +#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN_VDEC 18
> +#define CLK_VDE1_VDEC_SOC_IPS_EN 19
> +#define CLK_VDE1_VDEC_SOC_IPS_EN_VDEC 20
> +#define CLK_VDE1_NR_CLK 21
> +
> +/* VDEC_GCON_BASE */
> +#define CLK_VDE2_LARB1_CKEN 0
> +#define CLK_VDE2_LARB1_CKEN_VDEC 1
> +#define CLK_VDE2_LARB1_CKEN_SMI 2
> +#define CLK_VDE2_LAT_CKEN 3
> +#define CLK_VDE2_LAT_CKEN_VDEC 4
> +#define CLK_VDE2_LAT_ACTIVE 5
> +#define CLK_VDE2_LAT_ACTIVE_VDEC 6
> +#define CLK_VDE2_LAT_CKEN_ENG 7
> +#define CLK_VDE2_LAT_CKEN_ENG_VDEC 8
> +#define CLK_VDE2_VDEC_CKEN 9
> +#define CLK_VDE2_VDEC_CKEN_VDEC 10
> +#define CLK_VDE2_VDEC_ACTIVE 11
> +#define CLK_VDE2_VDEC_ACTIVE_VDEC 12
> +#define CLK_VDE2_VDEC_CKEN_ENG 13
> +#define CLK_VDE2_VDEC_CKEN_ENG_VDEC 14
> +#define CLK_VDE2_NR_CLK 15
> +
> +/* VENC_GCON */
> +#define CLK_VEN1_CKE0_LARB 0
> +#define CLK_VEN1_CKE0_LARB_VENC 1
> +#define CLK_VEN1_CKE0_LARB_JPGENC 2
> +#define CLK_VEN1_CKE0_LARB_JPGDEC 3
> +#define CLK_VEN1_CKE0_LARB_SMI 4
> +#define CLK_VEN1_CKE1_VENC 5
> +#define CLK_VEN1_CKE1_VENC_VENC 6
> +#define CLK_VEN1_CKE1_VENC_SMI 7
> +#define CLK_VEN1_CKE2_JPGENC 8
> +#define CLK_VEN1_CKE2_JPGENC_JPGENC 9
> +#define CLK_VEN1_CKE3_JPGDEC 10
> +#define CLK_VEN1_CKE3_JPGDEC_JPGDEC 11
> +#define CLK_VEN1_CKE4_JPGDEC_C1 12
> +#define CLK_VEN1_CKE4_JPGDEC_C1_JPGDEC 13
> +#define CLK_VEN1_CKE5_GALS 14
> +#define CLK_VEN1_CKE5_GALS_VENC 15
> +#define CLK_VEN1_CKE5_GALS_JPGENC 16
> +#define CLK_VEN1_CKE5_GALS_JPGDEC 17
> +#define CLK_VEN1_CKE29_VENC_ADAB_CTRL 18
> +#define CLK_VEN1_CKE29_VENC_ADAB_CTRL_VENC 19
> +#define CLK_VEN1_CKE29_VENC_XPC_CTRL 20
> +#define CLK_VEN1_CKE29_VENC_XPC_CTRL_VENC 21
> +#define CLK_VEN1_CKE29_VENC_XPC_CTRL_JPGENC 22
> +#define CLK_VEN1_CKE29_VENC_XPC_CTRL_JPGDEC 23
> +#define CLK_VEN1_CKE6_GALS_SRAM 24
> +#define CLK_VEN1_CKE6_GALS_SRAM_VENC 25
> +#define CLK_VEN1_RES_FLAT 26
> +#define CLK_VEN1_RES_FLAT_VENC 27
> +#define CLK_VEN1_RES_FLAT_JPGENC 28
> +#define CLK_VEN1_RES_FLAT_JPGDEC 29
> +#define CLK_VEN1_NR_CLK 30
> +
> +/* VENC_GCON_CORE1 */
> +#define CLK_VEN2_CKE0_LARB 0
> +#define CLK_VEN2_CKE0_LARB_VENC 1
> +#define CLK_VEN2_CKE0_LARB_JPGENC 2
> +#define CLK_VEN2_CKE0_LARB_JPGDEC 3
> +#define CLK_VEN2_CKE0_LARB_SMI 4
> +#define CLK_VEN2_CKE1_VENC 5
> +#define CLK_VEN2_CKE1_VENC_VENC 6
> +#define CLK_VEN2_CKE1_VENC_SMI 7
> +#define CLK_VEN2_CKE2_JPGENC 8
> +#define CLK_VEN2_CKE2_JPGENC_JPGENC 9
> +#define CLK_VEN2_CKE3_JPGDEC 10
> +#define CLK_VEN2_CKE3_JPGDEC_JPGDEC 11
> +#define CLK_VEN2_CKE5_GALS 12
> +#define CLK_VEN2_CKE5_GALS_VENC 13
> +#define CLK_VEN2_CKE5_GALS_JPGENC 14
> +#define CLK_VEN2_CKE5_GALS_JPGDEC 15
> +#define CLK_VEN2_CKE29_VENC_XPC_CTRL 16
> +#define CLK_VEN2_CKE29_VENC_XPC_CTRL_VENC 17
> +#define CLK_VEN2_CKE29_VENC_XPC_CTRL_JPGENC 18
> +#define CLK_VEN2_CKE29_VENC_XPC_CTRL_JPGDEC 19
> +#define CLK_VEN2_CKE6_GALS_SRAM 20
> +#define CLK_VEN2_CKE6_GALS_SRAM_VENC 21
> +#define CLK_VEN2_RES_FLAT 22
> +#define CLK_VEN2_RES_FLAT_VENC 23
> +#define CLK_VEN2_RES_FLAT_JPGENC 24
> +#define CLK_VEN2_RES_FLAT_JPGDEC 25
> +#define CLK_VEN2_NR_CLK 26
> +
> +/* VENC_GCON_CORE2 */
> +#define CLK_VEN_C2_CKE0_LARB 0
> +#define CLK_VEN_C2_CKE0_LARB_VENC 1
> +#define CLK_VEN_C2_CKE0_LARB_SMI 2
> +#define CLK_VEN_C2_CKE1_VENC 3
> +#define CLK_VEN_C2_CKE1_VENC_VENC 4
> +#define CLK_VEN_C2_CKE1_VENC_SMI 5
> +#define CLK_VEN_C2_CKE5_GALS 6
> +#define CLK_VEN_C2_CKE5_GALS_VENC 7
> +#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL 8
> +#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL_VENC 9
> +#define CLK_VEN_C2_CKE6_GALS_SRAM 10
> +#define CLK_VEN_C2_CKE6_GALS_SRAM_VENC 11
> +#define CLK_VEN_C2_RES_FLAT 12
> +#define CLK_VEN_C2_RES_FLAT_VENC 13
> +#define CLK_VEN_C2_NR_CLK 14
> +
> +/* MDPSYS_CONFIG */
> +#define CLK_MDP_MDP_MUTEX0 0
> +#define CLK_MDP_MDP_MUTEX0_MML 1
> +#define CLK_MDP_SMI0 2
> +#define CLK_MDP_SMI0_MML 3
> +#define CLK_MDP_SMI0_SMI 4
> +#define CLK_MDP_APB_BUS 5
> +#define CLK_MDP_APB_BUS_MML 6
> +#define CLK_MDP_MDP_RDMA0 7
> +#define CLK_MDP_MDP_RDMA0_MML 8
> +#define CLK_MDP_MDP_RDMA1 9
> +#define CLK_MDP_MDP_RDMA1_MML 10
> +#define CLK_MDP_MDP_RDMA2 11
> +#define CLK_MDP_MDP_RDMA2_MML 12
> +#define CLK_MDP_MDP_BIRSZ0 13
> +#define CLK_MDP_MDP_BIRSZ0_MML 14
> +#define CLK_MDP_MDP_HDR0 15
> +#define CLK_MDP_MDP_HDR0_MML 16
> +#define CLK_MDP_MDP_AAL0 17
> +#define CLK_MDP_MDP_AAL0_MML 18
> +#define CLK_MDP_MDP_RSZ0 19
> +#define CLK_MDP_MDP_RSZ0_MML 20
> +#define CLK_MDP_MDP_RSZ2 21
> +#define CLK_MDP_MDP_RSZ2_MML 22
> +#define CLK_MDP_MDP_TDSHP0 23
> +#define CLK_MDP_MDP_TDSHP0_MML 24
> +#define CLK_MDP_MDP_COLOR0 25
> +#define CLK_MDP_MDP_COLOR0_MML 26
> +#define CLK_MDP_MDP_WROT0 27
> +#define CLK_MDP_MDP_WROT0_MML 28
> +#define CLK_MDP_MDP_WROT1 29
> +#define CLK_MDP_MDP_WROT1_MML 30
> +#define CLK_MDP_MDP_WROT2 31
> +#define CLK_MDP_MDP_WROT2_MML 32
> +#define CLK_MDP_MDP_FAKE_ENG0 33
> +#define CLK_MDP_MDP_FAKE_ENG0_MML 34
> +#define CLK_MDP_APB_DB 35
> +#define CLK_MDP_APB_DB_MML 36
> +#define CLK_MDP_MDP_DLI_ASYNC0 37
> +#define CLK_MDP_MDP_DLI_ASYNC0_MML 38
> +#define CLK_MDP_MDP_DLI_ASYNC1 39
> +#define CLK_MDP_MDP_DLI_ASYNC1_MML 40
> +#define CLK_MDP_MDP_DLO_ASYNC0 41
> +#define CLK_MDP_MDP_DLO_ASYNC0_MML 42
> +#define CLK_MDP_MDP_DLO_ASYNC1 43
> +#define CLK_MDP_MDP_DLO_ASYNC1_MML 44
> +#define CLK_MDP_MDP_DLI_ASYNC2 45
> +#define CLK_MDP_MDP_DLI_ASYNC2_MML 46
> +#define CLK_MDP_MDP_DLO_ASYNC2 47
> +#define CLK_MDP_MDP_DLO_ASYNC2_MML 48
> +#define CLK_MDP_MDP_DLO_ASYNC3 49
> +#define CLK_MDP_MDP_DLO_ASYNC3_MML 50
> +#define CLK_MDP_IMG_DL_ASYNC0 51
> +#define CLK_MDP_IMG_DL_ASYNC0_MML 52
> +#define CLK_MDP_MDP_RROT0 53
> +#define CLK_MDP_MDP_RROT0_MML 54
> +#define CLK_MDP_MDP_MERGE0 55
> +#define CLK_MDP_MDP_MERGE0_MML 56
> +#define CLK_MDP_MDP_C3D0 57
> +#define CLK_MDP_MDP_C3D0_MML 58
> +#define CLK_MDP_MDP_FG0 59
> +#define CLK_MDP_MDP_FG0_MML 60
> +#define CLK_MDP_MDP_CLA2 61
> +#define CLK_MDP_MDP_CLA2_MML 62
> +#define CLK_MDP_MDP_DLO_ASYNC4 63
> +#define CLK_MDP_MDP_DLO_ASYNC4_MML 64
> +#define CLK_MDP_VPP_RSZ0 65
> +#define CLK_MDP_VPP_RSZ0_MML 66
> +#define CLK_MDP_VPP_RSZ1 67
> +#define CLK_MDP_VPP_RSZ1_MML 68
> +#define CLK_MDP_MDP_DLO_ASYNC5 69
> +#define CLK_MDP_MDP_DLO_ASYNC5_MML 70
> +#define CLK_MDP_IMG0 71
> +#define CLK_MDP_IMG0_MML 72
> +#define CLK_MDP_F26M 73
> +#define CLK_MDP_F26M_MML 74
> +#define CLK_MDP_IMG_DL_RELAY0 75
> +#define CLK_MDP_IMG_DL_RELAY0_MML 76
> +#define CLK_MDP_IMG_DL_RELAY1 77
> +#define CLK_MDP_IMG_DL_RELAY1_MML 78
> +#define CLK_MDP_NR_CLK 79
> +
> +/* MDPSYS1_CONFIG */
> +#define CLK_MDP1_MDP_MUTEX0 0
> +#define CLK_MDP1_MDP_MUTEX0_MML 1
> +#define CLK_MDP1_SMI0 2
> +#define CLK_MDP1_SMI0_SMI 3
> +#define CLK_MDP1_APB_BUS 4
> +#define CLK_MDP1_APB_BUS_MML 5
> +#define CLK_MDP1_MDP_RDMA0 6
> +#define CLK_MDP1_MDP_RDMA0_MML 7
> +#define CLK_MDP1_MDP_RDMA1 8
> +#define CLK_MDP1_MDP_RDMA1_MML 9
> +#define CLK_MDP1_MDP_RDMA2 10
> +#define CLK_MDP1_MDP_RDMA2_MML 11
> +#define CLK_MDP1_MDP_BIRSZ0 12
> +#define CLK_MDP1_MDP_BIRSZ0_MML 13
> +#define CLK_MDP1_MDP_HDR0 14
> +#define CLK_MDP1_MDP_HDR0_MML 15
> +#define CLK_MDP1_MDP_AAL0 16
> +#define CLK_MDP1_MDP_AAL0_MML 17
> +#define CLK_MDP1_MDP_RSZ0 18
> +#define CLK_MDP1_MDP_RSZ0_MML 19
> +#define CLK_MDP1_MDP_RSZ2 20
> +#define CLK_MDP1_MDP_RSZ2_MML 21
> +#define CLK_MDP1_MDP_TDSHP0 22
> +#define CLK_MDP1_MDP_TDSHP0_MML 23
> +#define CLK_MDP1_MDP_COLOR0 24
> +#define CLK_MDP1_MDP_COLOR0_MML 25
> +#define CLK_MDP1_MDP_WROT0 26
> +#define CLK_MDP1_MDP_WROT0_MML 27
> +#define CLK_MDP1_MDP_WROT1 28
> +#define CLK_MDP1_MDP_WROT1_MML 29
> +#define CLK_MDP1_MDP_WROT2 30
> +#define CLK_MDP1_MDP_WROT2_MML 31
> +#define CLK_MDP1_MDP_FAKE_ENG0 32
> +#define CLK_MDP1_MDP_FAKE_ENG0_MML 33
> +#define CLK_MDP1_APB_DB 34
> +#define CLK_MDP1_APB_DB_MML 35
> +#define CLK_MDP1_MDP_DLI_ASYNC0 36
> +#define CLK_MDP1_MDP_DLI_ASYNC0_MML 37
> +#define CLK_MDP1_MDP_DLI_ASYNC1 38
> +#define CLK_MDP1_MDP_DLI_ASYNC1_MML 39
> +#define CLK_MDP1_MDP_DLO_ASYNC0 40
> +#define CLK_MDP1_MDP_DLO_ASYNC0_MML 41
> +#define CLK_MDP1_MDP_DLO_ASYNC1 42
> +#define CLK_MDP1_MDP_DLO_ASYNC1_MML 43
> +#define CLK_MDP1_MDP_DLI_ASYNC2 44
> +#define CLK_MDP1_MDP_DLI_ASYNC2_MML 45
> +#define CLK_MDP1_MDP_DLO_ASYNC2 46
> +#define CLK_MDP1_MDP_DLO_ASYNC2_MML 47
> +#define CLK_MDP1_MDP_DLO_ASYNC3 48
> +#define CLK_MDP1_MDP_DLO_ASYNC3_MML 49
> +#define CLK_MDP1_IMG_DL_ASYNC0 50
> +#define CLK_MDP1_IMG_DL_ASYNC0_MML 51
> +#define CLK_MDP1_MDP_RROT0 52
> +#define CLK_MDP1_MDP_RROT0_MML 53
> +#define CLK_MDP1_MDP_MERGE0 54
> +#define CLK_MDP1_MDP_MERGE0_MML 55
> +#define CLK_MDP1_MDP_C3D0 56
> +#define CLK_MDP1_MDP_C3D0_MML 57
> +#define CLK_MDP1_MDP_FG0 58
> +#define CLK_MDP1_MDP_FG0_MML 59
> +#define CLK_MDP1_MDP_CLA2 60
> +#define CLK_MDP1_MDP_CLA2_MML 61
> +#define CLK_MDP1_MDP_DLO_ASYNC4 62
> +#define CLK_MDP1_MDP_DLO_ASYNC4_MML 63
> +#define CLK_MDP1_VPP_RSZ0 64
> +#define CLK_MDP1_VPP_RSZ0_MML 65
> +#define CLK_MDP1_VPP_RSZ1 66
> +#define CLK_MDP1_VPP_RSZ1_MML 67
> +#define CLK_MDP1_MDP_DLO_ASYNC5 68
> +#define CLK_MDP1_MDP_DLO_ASYNC5_MML 69
> +#define CLK_MDP1_IMG0 70
> +#define CLK_MDP1_IMG0_MML 71
> +#define CLK_MDP1_F26M 72
> +#define CLK_MDP1_F26M_MML 73
> +#define CLK_MDP1_IMG_DL_RELAY0 74
> +#define CLK_MDP1_IMG_DL_RELAY0_MML 75
> +#define CLK_MDP1_IMG_DL_RELAY1 76
> +#define CLK_MDP1_IMG_DL_RELAY1_MML 77
> +#define CLK_MDP1_NR_CLK 78
> +
> +/* DISP_VDISP_AO_CONFIG */
> +#define CLK_MM_V_DISP_VDISP_AO_CONFIG 0
> +#define CLK_MM_V_DISP_VDISP_AO_CONFIG_DISP 1
> +#define CLK_MM_V_DISP_DPC 2
> +#define CLK_MM_V_DISP_DPC_DISP 3
> +#define CLK_MM_V_SMI_SUB_SOMM0 4
> +#define CLK_MM_V_SMI_SUB_SOMM0_SMI 5
> +#define CLK_MM_V_NR_CLK 6
> +
> +/* MFGPLL_PLL_CTRL */
> +#define CLK_MFG_AO_MFGPLL 0
> +#define CLK_MFG_AO_NR_CLK 1
> +
> +/* MFGPLL_SC0_PLL_CTRL */
> +#define CLK_MFGSC0_AO_MFGPLL_SC0 0
> +#define CLK_MFGSC0_AO_NR_CLK 1
> +
> +/* MFGPLL_SC1_PLL_CTRL */
> +#define CLK_MFGSC1_AO_MFGPLL_SC1 0
> +#define CLK_MFGSC1_AO_NR_CLK 1
> +
> +/* CCIPLL_PLL_CTRL */
> +#define CLK_CCIPLL 0
> +#define CLK_CCI_NR_CLK 1
> +
> +/* ARMPLL_LL_PLL_CTRL */
> +#define CLK_CPLL_ARMPLL_LL 0
> +#define CLK_CPU_LL_NR_CLK 1
> +
> +/* ARMPLL_BL_PLL_CTRL */
> +#define CLK_CPBL_ARMPLL_BL 0
> +#define CLK_CPU_BL_NR_CLK 1
> +
> +/* ARMPLL_B_PLL_CTRL */
> +#define CLK_CPB_ARMPLL_B 0
> +#define CLK_CPU_B_NR_CLK 1
> +
> +/* PTPPLL_PLL_CTRL */
> +#define CLK_PTPPLL 0
> +#define CLK_PTP_NR_CLK 1
> +
> +#endif /* _DT_BINDINGS_CLK_MT8196_H */
> --
> 2.45.2
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2025-04-16 9:20 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz follow: Atom feed
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2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
2025-03-07 3:26 ` [PATCH 01/26] clk: mediatek: Add defines for vote Guangjie Song
2025-03-07 3:26 ` [PATCH 02/26] clk: mediatek: Support voting for pll Guangjie Song
2025-03-07 3:26 ` [PATCH 03/26] clk: mediatek: Support voting for mux Guangjie Song
2025-03-10 14:12 ` AngeloGioacchino Del Regno
2025-03-07 3:27 ` [PATCH 04/26] clk: mediatek: Support voting for gate Guangjie Song
2025-03-07 3:27 ` [PATCH 05/26] clk: mediatek: Add gate ops without disable Guangjie Song
2025-03-07 3:27 ` [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock Guangjie Song
2025-03-07 4:16 ` Rob Herring (Arm)
2025-03-07 7:29 ` Krzysztof Kozlowski
2025-04-16 9:20 ` Chen-Yu Tsai
2025-03-07 3:27 ` [PATCH 07/26] clk: mediatek: Add MT8196 apmixedsys clock support Guangjie Song
2025-03-11 17:05 ` Jeff Johnson
2025-03-07 3:27 ` [PATCH 08/26] clk: mediatek: Add MT8196 apmixedsys_gp2 " Guangjie Song
2025-03-07 3:27 ` [PATCH 09/26] clk: mediatek: Add MT8196 topckgen " Guangjie Song
2025-04-16 9:04 ` Chen-Yu Tsai
2025-03-07 3:27 ` [PATCH 10/26] clk: mediatek: Add MT8196 topckgen2 " Guangjie Song
2025-03-07 3:27 ` [PATCH 11/26] clk: mediatek: Add MT8196 vlpckgen " Guangjie Song
2025-03-07 3:27 ` [PATCH 12/26] clk: mediatek: Add MT8196 peripheral " Guangjie Song
2025-03-07 3:27 ` [PATCH 13/26] clk: mediatek: Add MT8196 adsp " Guangjie Song
2025-03-07 3:27 ` [PATCH 14/26] clk: mediatek: Add MT8196 i2c " Guangjie Song
2025-03-07 3:27 ` [PATCH 15/26] clk: mediatek: Add MT8196 mcu " Guangjie Song
2025-03-07 3:27 ` [PATCH 16/26] clk: mediatek: Add MT8196 mdpsys " Guangjie Song
2025-03-07 3:27 ` [PATCH 17/26] clk: mediatek: Add MT8196 mfg " Guangjie Song
2025-03-07 3:27 ` [PATCH 18/26] clk: mediatek: Add MT8196 disp0 " Guangjie Song
2025-03-07 3:27 ` [PATCH 19/26] clk: mediatek: Add MT8196 disp1 " Guangjie Song
2025-03-07 3:27 ` [PATCH 20/26] clk: mediatek: Add MT8196 disp-ao " Guangjie Song
2025-03-07 3:27 ` [PATCH 21/26] clk: mediatek: Add MT8196 ovl0 " Guangjie Song
2025-03-07 7:29 ` Krzysztof Kozlowski
2025-03-07 3:27 ` [PATCH 22/26] clk: mediatek: Add MT8196 ovl1 " Guangjie Song
2025-03-07 3:27 ` [PATCH 23/26] clk: mediatek: Add MT8196 pextpsys " Guangjie Song
2025-03-07 3:27 ` [PATCH 24/26] clk: mediatek: Add MT8196 ufssys " Guangjie Song
2025-03-07 3:27 ` [PATCH 25/26] clk: mediatek: Add MT8196 vdecsys " Guangjie Song
2025-03-07 3:27 ` [PATCH 26/26] clk: mediatek: Add MT8196 vencsys " Guangjie Song
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