Re: [PATCH RFC net-next 2/5] ptp: marvell: add core support for Marvell PTP v2.1

[Kory Maincent <kory.maincent@bootlin.com>]

On Fri, 11 Apr 2025 22:26:37 +0100
Russell King <rmk+kernel@armlinux.org.uk> wrote:

> Provide core support for the Marvell PTP v2.1 implementations, which
> consist of a TAI (time application interface) and timestamping blocks.
> This hardware can be found in Marvell 88E151x PHYs, Armada 38x and
> Armada 37xx (mvneta), as well as Marvell DSA devices.
> 
> Support for both arrival timestamps is supported, we use arrival 1 for
> PTP peer delay messages, and arrival 0 for all other messages.
> 
> External event capture is also supported.
> 
> PPS output and trigger generation is not supported.
> 
> This core takes inspiration from the existing Marvell 88E6xxx DSA PTP
> code and DP83640 drivers. Like the original 88E6xxx DSA code, we
> use a delayed work to keep the cycle counter updated, and a separate
> delayed work for event capture.
> 
> We expose the ptp clock aux work to allow users to support single and
> multi-port designs - where there is one Marvell TAI instance and a
> number of Marvell TS instances.

...

> +#define MV_PTP_MSGTYPE_DELAY_RESP	9
> +
> +/* This defines which incoming or outgoing PTP frames are timestampped */
> +#define MV_PTP_MSD_ID_TS_EN	(BIT(PTP_MSGTYPE_SYNC) | \
> +				 BIT(PTP_MSGTYPE_DELAY_REQ) | \
> +				 BIT(MV_PTP_MSGTYPE_DELAY_RESP))
> +/* Direct Sync messages to Arr0 and delay messages to Arr1 */
> +#define MV_PTP_TS_ARR_PTR	(BIT(PTP_MSGTYPE_DELAY_REQ) | \
> +				 BIT(MV_PTP_MSGTYPE_DELAY_RESP))

Why did you have chosen to use two queues with two separate behavior?
I have tried using only one queue and the PTP as master behaves correctly
without all these overrun. It is way better with one queue.
Maybe it was not the best approach if you want to use the two queues.  

Regards,
-- 
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com