From: Grzegorz Nitka <grzegorz.nitka@intel.com>
To: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org,
poros@redhat.com, richardcochran@gmail.com,
andrew+netdev@lunn.ch, przemyslaw.kitszel@intel.com,
anthony.l.nguyen@intel.com, Prathosh.Satish@microchip.com,
ivecera@redhat.com, jiri@resnulli.us,
arkadiusz.kubalewski@intel.com, vadim.fedorenko@linux.dev,
donald.hunter@gmail.com, horms@kernel.org, pabeni@redhat.com,
kuba@kernel.org, davem@davemloft.net, edumazet@google.com,
Grzegorz Nitka <grzegorz.nitka@intel.com>,
Jiri Pirko <jiri@nvidia.com>,
Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Subject: [PATCH v8 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL
Date: Tue, 12 May 2026 01:31:53 +0200 [thread overview]
Message-ID: <20260511233159.2558165-3-grzegorz.nitka@intel.com> (raw)
In-Reply-To: <20260511233159.2558165-1-grzegorz.nitka@intel.com>
Relax the (module, clock_id) equality requirement when registering a
pin identified by firmware (pin->fwnode). Some platforms associate a
FW-described pin with a DPLL instance that differs from the pin's
(module, clock_id) tuple. For such pins, permit registration without
requiring the strict match. Non-FW pins still require equality.
Keep netlink pin module reporting/filtering safe for this relaxed
registration model by caching the module name in the pin object at
allocation time and using the cached string in netlink paths.
This avoids dereferencing pin->module after provider module teardown.
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
---
drivers/dpll/dpll_core.c | 20 ++++++++++++++++----
drivers/dpll/dpll_core.h | 1 +
drivers/dpll/dpll_netlink.c | 6 +++---
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c
index cbb635db4321..3f5a822e44fb 100644
--- a/drivers/dpll/dpll_core.c
+++ b/drivers/dpll/dpll_core.c
@@ -11,6 +11,7 @@
#include <linux/device.h>
#include <linux/err.h>
#include <linux/idr.h>
+#include <linux/module.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/string.h>
@@ -652,6 +653,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module,
pin->pin_idx = pin_idx;
pin->clock_id = clock_id;
pin->module = module;
+ strscpy(pin->module_name, module_name(module));
if (WARN_ON(prop->type < DPLL_PIN_TYPE_MUX ||
prop->type > DPLL_PIN_TYPE_MAX)) {
ret = -EINVAL;
@@ -883,11 +885,21 @@ dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
return -EINVAL;
mutex_lock(&dpll_lock);
- if (WARN_ON(!(dpll->module == pin->module &&
- dpll->clock_id == pin->clock_id)))
+
+ /*
+ * For pins identified via firmware (pin->fwnode), allow registration
+ * even if the pin's (module, clock_id) differs from the target DPLL.
+ * For non-fwnode pins, require a strict (module, clock_id) match.
+ */
+ if (!pin->fwnode &&
+ WARN_ON_ONCE(dpll->module != pin->module ||
+ dpll->clock_id != pin->clock_id)) {
ret = -EINVAL;
- else
- ret = __dpll_pin_register(dpll, pin, ops, priv, NULL);
+ goto out_unlock;
+ }
+
+ ret = __dpll_pin_register(dpll, pin, ops, priv, NULL);
+out_unlock:
mutex_unlock(&dpll_lock);
return ret;
diff --git a/drivers/dpll/dpll_core.h b/drivers/dpll/dpll_core.h
index 71ac88ef2017..5b7db39a2dd0 100644
--- a/drivers/dpll/dpll_core.h
+++ b/drivers/dpll/dpll_core.h
@@ -59,6 +59,7 @@ struct dpll_pin {
u32 pin_idx;
u64 clock_id;
struct module *module;
+ char module_name[MODULE_NAME_LEN];
struct fwnode_handle *fwnode;
struct xarray dpll_refs;
struct xarray parent_refs;
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index ea6360263786..0af6b0cf3965 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -713,7 +713,7 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
if (ret)
return ret;
if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME,
- module_name(pin->module)))
+ pin->module_name))
return -EMSGSIZE;
if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id),
&pin->clock_id, DPLL_A_PIN_PAD))
@@ -1650,9 +1650,9 @@ dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr,
xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) {
prop = &pin->prop;
cid_match = clock_id ? pin->clock_id == clock_id : true;
- mod_match = mod_name_attr && module_name(pin->module) ?
+ mod_match = mod_name_attr && pin->module_name[0] ?
!nla_strcmp(mod_name_attr,
- module_name(pin->module)) : true;
+ pin->module_name) : true;
type_match = type ? prop->type == type : true;
board_match = board_label ? (prop->board_label ?
!nla_strcmp(board_label, prop->board_label) : false) :
--
2.39.3
next prev parent reply other threads:[~2026-05-11 23:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 23:31 [PATCH v8 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 1/8] dpll: add generic DPLL type Grzegorz Nitka
2026-05-11 23:31 ` Grzegorz Nitka [this message]
2026-05-11 23:31 ` [PATCH v8 net-next 3/8] dpll: extend pin notifier with notification source ID Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 4/8] dpll: allow fwnode pins to attempt state change without capability bit Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
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