From: Grzegorz Nitka <grzegorz.nitka@intel.com>
To: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org,
poros@redhat.com, richardcochran@gmail.com,
andrew+netdev@lunn.ch, przemyslaw.kitszel@intel.com,
anthony.l.nguyen@intel.com, Prathosh.Satish@microchip.com,
ivecera@redhat.com, jiri@resnulli.us,
arkadiusz.kubalewski@intel.com, vadim.fedorenko@linux.dev,
donald.hunter@gmail.com, horms@kernel.org, pabeni@redhat.com,
kuba@kernel.org, davem@davemloft.net, edumazet@google.com,
Grzegorz Nitka <grzegorz.nitka@intel.com>
Subject: [PATCH v8 net-next 4/8] dpll: allow fwnode pins to attempt state change without capability bit
Date: Tue, 12 May 2026 01:31:55 +0200 [thread overview]
Message-ID: <20260511233159.2558165-5-grzegorz.nitka@intel.com> (raw)
In-Reply-To: <20260511233159.2558165-1-grzegorz.nitka@intel.com>
Pins registered with an fwnode may have .state_on_dpll_set implemented
without advertising DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE upfront.
Requiring the bit for fwnode pins ties firmware description to driver
implementation details unnecessarily.
Relax the capability check in dpll_pin_state_set() and
dpll_pin_on_pin_state_set(): when a pin has an associated fwnode, bypass
the capability gate and let the ops layer decide, returning -EOPNOTSUPP
if .state_on_dpll_set is absent. Non-fwnode pins retain the original
strict behavior.
This is used later in the series by the SyncE_Ref output pin, which
relies on the fwnode path for state control.
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
---
drivers/dpll/dpll_netlink.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index b2c099990017..4f461d39ecf9 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -1325,8 +1325,11 @@ dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx,
unsigned long i;
int ret;
+ /* fwnode pins may not set the capability bit upfront; let the ops
+ * layer return -EOPNOTSUPP if the operation is unsupported.
+ */
if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE &
- pin->prop.capabilities)) {
+ pin->prop.capabilities) && !pin->fwnode) {
NL_SET_ERR_MSG(extack, "state changing is not allowed");
return -EOPNOTSUPP;
}
@@ -1361,8 +1364,11 @@ dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin,
struct dpll_pin_ref *ref;
int ret;
+ /* fwnode pins may not set the capability bit upfront; let the ops
+ * layer return -EOPNOTSUPP if the operation is unsupported.
+ */
if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE &
- pin->prop.capabilities)) {
+ pin->prop.capabilities) && !pin->fwnode) {
NL_SET_ERR_MSG(extack, "state changing is not allowed");
return -EOPNOTSUPP;
}
--
2.39.3
next prev parent reply other threads:[~2026-05-11 23:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 23:31 [PATCH v8 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 1/8] dpll: add generic DPLL type Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 3/8] dpll: extend pin notifier with notification source ID Grzegorz Nitka
2026-05-11 23:31 ` Grzegorz Nitka [this message]
2026-05-11 23:31 ` [PATCH v8 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-05-11 23:31 ` [PATCH v8 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
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