From: Grzegorz Nitka <grzegorz.nitka@intel.com>
To: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org,
poros@redhat.com, richardcochran@gmail.com,
andrew+netdev@lunn.ch, przemyslaw.kitszel@intel.com,
anthony.l.nguyen@intel.com, Prathosh.Satish@microchip.com,
ivecera@redhat.com, jiri@resnulli.us,
arkadiusz.kubalewski@intel.com, vadim.fedorenko@linux.dev,
donald.hunter@gmail.com, horms@kernel.org, pabeni@redhat.com,
kuba@kernel.org, davem@davemloft.net, edumazet@google.com,
Grzegorz Nitka <grzegorz.nitka@intel.com>,
Aleksandr Loktionov <aleksandr.loktionov@intel.com>,
Jiri Pirko <jiri@nvidia.com>
Subject: [PATCH v14 net-next 01/13] dpll: add generic DPLL type
Date: Sun, 7 Jun 2026 20:30:33 +0200 [thread overview]
Message-ID: <20260607183045.1213735-2-grzegorz.nitka@intel.com> (raw)
In-Reply-To: <20260607183045.1213735-1-grzegorz.nitka@intel.com>
Add DPLL_TYPE_GENERIC to represent DPLL devices which do not fit the
existing PPS or EEC classes.
The UAPI type is intentionally generic. During netdev discussion,
maintainers pointed out that introducing identifiers tied to a specific
placement or single design does not scale across ASICs and vendors.
The role of a DPLL is already inferable from the spawning driver,
bus device, and pin topology, without encoding additional
purpose-specific taxonomy in the type name.
Using a generic type keeps the UAPI extensible and avoids premature
naming that may become incorrect as new hardware topologies are
exposed through the DPLL subsystem.
Expose the new type through UAPI and netlink specification as "generic".
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
---
Documentation/netlink/specs/dpll.yaml | 3 +++
drivers/dpll/dpll_nl.c | 2 +-
include/uapi/linux/dpll.h | 2 ++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index 91a172617b3a..2bf83f6732ab 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -138,6 +138,9 @@ definitions:
-
name: eec
doc: dpll drives the Ethernet Equipment Clock
+ -
+ name: generic
+ doc: generic dpll type for devices outside PPS/EEC classes
render-max: true
-
type: enum
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index b1d9182c7802..ed3bbe9841ea 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -37,7 +37,7 @@ const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1] = {
static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + 1] = {
[DPLL_A_MODULE_NAME] = { .type = NLA_NUL_STRING, },
[DPLL_A_CLOCK_ID] = { .type = NLA_U64, },
- [DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
+ [DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
};
/* DPLL_CMD_DEVICE_GET - do */
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index cb363cccf2e2..55eaa82f5f98 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -109,10 +109,12 @@ enum dpll_clock_quality_level {
* enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
* @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
* @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
+ * @DPLL_TYPE_GENERIC: generic dpll type for devices outside PPS/EEC classes
*/
enum dpll_type {
DPLL_TYPE_PPS = 1,
DPLL_TYPE_EEC,
+ DPLL_TYPE_GENERIC,
/* private: */
__DPLL_TYPE_MAX,
--
2.39.3
next prev parent reply other threads:[~2026-06-07 18:35 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-07 18:30 [PATCH v14 net-next 00/13] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-06-07 18:30 ` Grzegorz Nitka [this message]
2026-06-07 18:30 ` [PATCH v14 net-next 02/13] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 03/13] dpll: fix stale iteration in dpll_pin_on_pin_unregister() Grzegorz Nitka
2026-06-08 16:51 ` Kubalewski, Arkadiusz
2026-06-09 6:50 ` Nitka, Grzegorz
2026-06-11 8:50 ` Paolo Abeni
2026-06-11 10:01 ` Nitka, Grzegorz
2026-06-11 14:41 ` Paolo Abeni
2026-06-11 17:41 ` Jakub Kicinski
2026-06-11 18:36 ` Nitka, Grzegorz
2026-06-07 18:30 ` [PATCH v14 net-next 04/13] dpll: send delete notification before unregister in on-pin rollback Grzegorz Nitka
2026-06-08 16:45 ` Kubalewski, Arkadiusz
2026-06-09 7:09 ` Nitka, Grzegorz
2026-06-10 19:42 ` Nitka, Grzegorz
2026-06-10 21:27 ` Nitka, Grzegorz
2026-06-07 18:30 ` [PATCH v14 net-next 05/13] dpll: emit per-dpll delete notifications in dpll_pin_on_pin_unregister() Grzegorz Nitka
2026-06-08 16:40 ` Kubalewski, Arkadiusz
2026-06-07 18:30 ` [PATCH v14 net-next 06/13] dpll: guard sync-pair removal on full pin unregister Grzegorz Nitka
2026-06-08 16:38 ` Kubalewski, Arkadiusz
2026-06-07 18:30 ` [PATCH v14 net-next 07/13] dpll: balance create/delete notifications in __dpll_pin_(un)register Grzegorz Nitka
2026-06-08 16:35 ` Kubalewski, Arkadiusz
2026-06-07 18:30 ` [PATCH v14 net-next 08/13] dpll: extend pin notifier with notification source ID Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 09/13] dpll: allow fwnode pins to attempt state change without capability bit Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 10/13] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 11/13] ice: implement CPI support for E825C Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 12/13] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 13/13] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
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