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From: Grzegorz Nitka <grzegorz.nitka@intel.com>
To: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org,
	poros@redhat.com, richardcochran@gmail.com,
	andrew+netdev@lunn.ch, przemyslaw.kitszel@intel.com,
	anthony.l.nguyen@intel.com, Prathosh.Satish@microchip.com,
	ivecera@redhat.com, jiri@resnulli.us,
	arkadiusz.kubalewski@intel.com, vadim.fedorenko@linux.dev,
	donald.hunter@gmail.com, horms@kernel.org, pabeni@redhat.com,
	kuba@kernel.org, davem@davemloft.net, edumazet@google.com,
	Grzegorz Nitka <grzegorz.nitka@intel.com>,
	Jiri Pirko <jiri@nvidia.com>,
	Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Subject: [PATCH v14 net-next 02/13] dpll: allow registering FW-identified pin with a different DPLL
Date: Sun,  7 Jun 2026 20:30:34 +0200	[thread overview]
Message-ID: <20260607183045.1213735-3-grzegorz.nitka@intel.com> (raw)
In-Reply-To: <20260607183045.1213735-1-grzegorz.nitka@intel.com>

Relax the (module, clock_id) equality requirement when registering a
pin identified by firmware (pin->fwnode). Some platforms associate a
FW-described pin with a DPLL instance that differs from the pin's
(module, clock_id) tuple. For such pins, permit registration without
requiring the strict match. Non-FW pins still require equality.

Keep netlink pin module reporting/filtering safe for this relaxed
registration model by caching the module name in the pin object at
allocation time and using the cached string in netlink paths.
This avoids dereferencing pin->module after provider module teardown.

Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
---
 drivers/dpll/dpll_core.c    | 20 ++++++++++++++++----
 drivers/dpll/dpll_core.h    |  2 ++
 drivers/dpll/dpll_netlink.c |  6 +++---
 3 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c
index 20a54728549c..6dc7e93ece75 100644
--- a/drivers/dpll/dpll_core.c
+++ b/drivers/dpll/dpll_core.c
@@ -11,6 +11,7 @@
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/idr.h>
+#include <linux/module.h>
 #include <linux/property.h>
 #include <linux/slab.h>
 #include <linux/string.h>
@@ -652,6 +653,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module,
 	pin->pin_idx = pin_idx;
 	pin->clock_id = clock_id;
 	pin->module = module;
+	strscpy(pin->module_name, module_name(module));
 	if (WARN_ON(prop->type < DPLL_PIN_TYPE_MUX ||
 		    prop->type > DPLL_PIN_TYPE_MAX)) {
 		ret = -EINVAL;
@@ -884,11 +886,21 @@ dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
 		return -EINVAL;
 
 	mutex_lock(&dpll_lock);
-	if (WARN_ON(!(dpll->module == pin->module &&
-		      dpll->clock_id == pin->clock_id)))
+
+	/*
+	 * For pins identified via firmware (pin->fwnode), allow registration
+	 * even if the pin's (module, clock_id) differs from the target DPLL.
+	 * For non-fwnode pins, require a strict (module, clock_id) match.
+	 */
+	if (!pin->fwnode &&
+	    WARN_ON_ONCE(dpll->module != pin->module ||
+			 dpll->clock_id != pin->clock_id)) {
 		ret = -EINVAL;
-	else
-		ret = __dpll_pin_register(dpll, pin, ops, priv, NULL);
+		goto out_unlock;
+	}
+
+	ret = __dpll_pin_register(dpll, pin, ops, priv, NULL);
+out_unlock:
 	mutex_unlock(&dpll_lock);
 
 	return ret;
diff --git a/drivers/dpll/dpll_core.h b/drivers/dpll/dpll_core.h
index 71ac88ef2017..26d1537ada82 100644
--- a/drivers/dpll/dpll_core.h
+++ b/drivers/dpll/dpll_core.h
@@ -45,6 +45,7 @@ struct dpll_device {
  * @pin_idx:		index of a pin given by dev driver
  * @clock_id:		clock_id of creator
  * @module:		module of creator
+ * @module_name:	module name of creator
  * @fwnode:		optional reference to firmware node
  * @dpll_refs:		hold referencees to dplls pin was registered with
  * @parent_refs:	hold references to parent pins pin was registered with
@@ -59,6 +60,7 @@ struct dpll_pin {
 	u32 pin_idx;
 	u64 clock_id;
 	struct module *module;
+	char module_name[MODULE_NAME_LEN];
 	struct fwnode_handle *fwnode;
 	struct xarray dpll_refs;
 	struct xarray parent_refs;
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index d62350b18107..6a23298244cc 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -703,7 +703,7 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
 	if (ret)
 		return ret;
 	if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME,
-			   module_name(pin->module)))
+			   pin->module_name))
 		return -EMSGSIZE;
 	if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id),
 			  &pin->clock_id, DPLL_A_PIN_PAD))
@@ -1650,9 +1650,9 @@ dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr,
 	xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) {
 		prop = &pin->prop;
 		cid_match = clock_id ? pin->clock_id == clock_id : true;
-		mod_match = mod_name_attr && module_name(pin->module) ?
+		mod_match = mod_name_attr && pin->module_name[0] ?
 			!nla_strcmp(mod_name_attr,
-				    module_name(pin->module)) : true;
+				    pin->module_name) : true;
 		type_match = type ? prop->type == type : true;
 		board_match = board_label ? (prop->board_label ?
 			!nla_strcmp(board_label, prop->board_label) : false) :
-- 
2.39.3


  parent reply	other threads:[~2026-06-07 18:35 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-07 18:30 [PATCH v14 net-next 00/13] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 01/13] dpll: add generic DPLL type Grzegorz Nitka
2026-06-07 18:30 ` Grzegorz Nitka [this message]
2026-06-07 18:30 ` [PATCH v14 net-next 03/13] dpll: fix stale iteration in dpll_pin_on_pin_unregister() Grzegorz Nitka
2026-06-08 16:51   ` Kubalewski, Arkadiusz
2026-06-09  6:50     ` Nitka, Grzegorz
2026-06-11  8:50   ` Paolo Abeni
2026-06-11 10:01     ` Nitka, Grzegorz
2026-06-11 14:41       ` Paolo Abeni
2026-06-11 17:41         ` Jakub Kicinski
2026-06-11 18:36           ` Nitka, Grzegorz
2026-06-07 18:30 ` [PATCH v14 net-next 04/13] dpll: send delete notification before unregister in on-pin rollback Grzegorz Nitka
2026-06-08 16:45   ` Kubalewski, Arkadiusz
2026-06-09  7:09     ` Nitka, Grzegorz
2026-06-10 19:42       ` Nitka, Grzegorz
2026-06-10 21:27         ` Nitka, Grzegorz
2026-06-07 18:30 ` [PATCH v14 net-next 05/13] dpll: emit per-dpll delete notifications in dpll_pin_on_pin_unregister() Grzegorz Nitka
2026-06-08 16:40   ` Kubalewski, Arkadiusz
2026-06-07 18:30 ` [PATCH v14 net-next 06/13] dpll: guard sync-pair removal on full pin unregister Grzegorz Nitka
2026-06-08 16:38   ` Kubalewski, Arkadiusz
2026-06-07 18:30 ` [PATCH v14 net-next 07/13] dpll: balance create/delete notifications in __dpll_pin_(un)register Grzegorz Nitka
2026-06-08 16:35   ` Kubalewski, Arkadiusz
2026-06-07 18:30 ` [PATCH v14 net-next 08/13] dpll: extend pin notifier with notification source ID Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 09/13] dpll: allow fwnode pins to attempt state change without capability bit Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 10/13] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 11/13] ice: implement CPI support for E825C Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 12/13] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-06-07 18:30 ` [PATCH v14 net-next 13/13] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka

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