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From: Jakub Kicinski <kuba@kernel.org>
To: Potnuri Bharat Teja <bharat@chelsio.com>
Cc: netdev@vger.kernel.org, davem@davemloft.net, edumazet@google.com,
	pabeni@redhat.com, andrew+netdev@lunn.ch
Subject: Re: [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support
Date: Tue, 9 Jun 2026 15:36:14 -0700	[thread overview]
Message-ID: <20260609153614.20d8bb0d@kernel.org> (raw)
In-Reply-To: <aifv8SR/ANbxBAUM@chelsio.com>

On Tue, 9 Jun 2026 16:20:25 +0530 Potnuri Bharat Teja wrote:
> You are right, and I apologize. We have had some difficult internal 
> circumstances recently that pulled us away, but I know that doesn't excuse 
> neglecting our upstream responsibilities to the community.
> 
> I am taking ownership of this moving forward. I went through the netdev 
> backlog, Shall reply if they are still relevant. 

I have no doubt that you are genuinely willing to improve things going
forward. I'd prefer to iron out the process issues before we accept any
more code. Specifically I think the process issue is that Chelsio does
not have a (competent) engineer assigned to participating upstream, and
explicitly given some amount of time a day to read the ML and review
other people's code. There may be no cxgb4 patches on the ML right now
but there's plenty of submissions for other drivers. Please start
reading the list, engaging, reviewing, asking questions which indicate
your understanding of the code and the process.. And if things are
going well, in a month or so we can revisit this rejection.

      reply	other threads:[~2026-06-09 22:36 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-07  3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures Potnuri Bharat Teja
2026-06-07  7:02   ` Andrew Lunn
2026-06-07  3:52 ` [PATCH net-next v1 02/10] cxgb4: Add T7 chip type identification and HW constants Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 03/10] cxgb4: Add T7 CPL messages, FW constants, and PCI IDs Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 04/10] cxgb4: Add versioned structures and scratch buffs Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 05/10] cxgb4: Add T7 indirect regs and update library Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 06/10] cxgb4: Move PCI initialization logic to cxgb4_pci.c Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 07/10] cxgb4: Extend hardware abstraction layer for T7 logs Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 08/10] cxgb4: Update driver lifecycle and peripherals for T7 Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 09/10] cxgb4: Update debugfs interface for T7 versioned structures Potnuri Bharat Teja
2026-06-07  3:52 ` [PATCH net-next v1 10/10] cxgb4: Update SGE path and filtering logic for T7 Potnuri Bharat Teja
2026-06-08 21:13 ` [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Jakub Kicinski
2026-06-09 10:50   ` Potnuri Bharat Teja
2026-06-09 22:36     ` Jakub Kicinski [this message]

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