[PATCH net v2] octeontx2-af: Block VFs from clobbering special CGX PKIND state

[PATCH net v2] octeontx2-af: Block VFs from clobbering special CGX PKIND state

[Ratheesh Kannoth]

From: Hariprasad Kelam <hkelam@marvell.com>

PF and VF NIX LFs that share a CGX LMAC reuse the same hardware PKIND
programming. When HiGig2 or EDSA parsing is enabled, a VF NIX LF alloc must
not reset the LMAC RX PKIND or default TX parse config over the PF setup.

Add cgx_get_pkind() and rvu_cgx_is_pkind_config_permitted() so VFs skip
cgx_set_pkind(), rvu_npc_set_pkind(), and NIX_AF_LFX_TX_PARSE_CFG updates
when the LMAC is using NPC_RX_HIGIG_PKIND or NPC_RX_EDSA_PKIND.

Fixes: 94d942c5fb97 ("octeontx2-af: Config pkind for CGX mapped PFs")
Cc: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>

---
v1 -> v2: Addressed simon comments
	https://lore.kernel.org/netdev/20260619041002.1773822-1-rkannoth@marvell.com/
---
 .../net/ethernet/marvell/octeontx2/af/cgx.c   | 12 +++++++
 .../net/ethernet/marvell/octeontx2/af/cgx.h   |  1 +
 .../net/ethernet/marvell/octeontx2/af/rvu.h   |  1 +
 .../ethernet/marvell/octeontx2/af/rvu_cgx.c   | 32 +++++++++++++++++++
 .../ethernet/marvell/octeontx2/af/rvu_nix.c   | 28 +++++++++++++---
 5 files changed, 70 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
index 2e94d5105016..f5fd6138c352 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
@@ -518,6 +518,18 @@ int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
 	return 0;
 }
 
+int cgx_get_pkind(void *cgxd, u8 lmac_id, int *pkind)
+{
+	struct cgx *cgx = cgxd;
+
+	if (!is_lmac_valid(cgx, lmac_id))
+		return -ENODEV;
+
+	*pkind = cgx_read(cgx, lmac_id, cgx->mac_ops->rxid_map_offset);
+	*pkind = *pkind & 0x3F;
+	return 0;
+}
+
 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id)
 {
 	struct cgx *cgx = cgxd;
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
index 92ccf343dfe0..8411a75dd723 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
@@ -141,6 +141,7 @@ int cgx_get_cgxid(void *cgxd);
 int cgx_get_lmac_cnt(void *cgxd);
 void *cgx_get_pdata(int cgx_id);
 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
+int cgx_get_pkind(void *cgxd, u8 lmac_id, int *pkind);
 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 7f3505ae6860..bb671e2150aa 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -1115,6 +1115,7 @@ void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 			 u8 *intf, u8 *ena);
 int npc_config_cntr_default_entries(struct rvu *rvu, bool enable);
 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
+bool rvu_cgx_is_pkind_config_permitted(struct rvu *rvu, u16 pcifunc);
 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
 u32  rvu_cgx_get_fifolen(struct rvu *rvu);
 void *rvu_first_cgx_pdata(struct rvu *rvu);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
index 4ff3935ed3fe..2be1da3476ac 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
@@ -1355,3 +1355,35 @@ void rvu_mac_reset(struct rvu *rvu, u16 pcifunc)
 	if (mac_ops->mac_reset(cgxd, lmac, !is_vf(pcifunc)))
 		dev_err(rvu->dev, "Failed to reset MAC\n");
 }
+
+/* Do not allow CGX-mapped VFs to overwrite PKIND when special parse kinds
+ * (HiGig, EDSA, etc.) are in use on the shared LMAC.
+ */
+bool rvu_cgx_is_pkind_config_permitted(struct rvu *rvu, u16 pcifunc)
+{
+	int pf, err, rxpkind;
+	u8 cgx_id, lmac_id;
+	void *cgxd;
+
+	pf = rvu_get_pf(rvu->pdev, pcifunc);
+
+	if (!(pcifunc & RVU_PFVF_FUNC_MASK))
+		return true;
+
+	if (!is_pf_cgxmapped(rvu, pf))
+		return true;
+
+	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
+	cgxd = rvu_cgx_pdata(cgx_id, rvu);
+	err = cgx_get_pkind(cgxd, lmac_id, &rxpkind);
+	if (err)
+		return false;
+
+	switch (rxpkind) {
+	case NPC_RX_HIGIG_PKIND:
+	case NPC_RX_EDSA_PKIND:
+		return false;
+	default:
+		return true;
+	}
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index d8989395e875..40f5b25eafb1 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -338,6 +338,7 @@ static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf,
 	struct sdp_node_info *sdp_info;
 	int pkind, pf, vf, lbkid, vfid;
 	u8 cgx_id, lmac_id;
+	struct cgx *cgxd;
 	bool from_vf;
 	int err;
 
@@ -363,8 +364,15 @@ static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf,
 		pfvf->tx_chan_cnt = 1;
 		rsp->tx_link = cgx_id * hw->lmac_per_cgx + lmac_id;
 
-		cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind);
-		rvu_npc_set_pkind(rvu, pkind, pfvf);
+		cgxd = rvu_cgx_pdata(cgx_id, rvu);
+
+		mutex_lock(&cgxd->lock);
+		if (rvu_cgx_is_pkind_config_permitted(rvu, pcifunc)) {
+			cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
+				      pkind);
+			rvu_npc_set_pkind(rvu, pkind, pfvf);
+		}
+		mutex_unlock(&cgxd->lock);
 		break;
 	case NIX_INTF_TYPE_LBK:
 		vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
@@ -1508,7 +1516,10 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
 	struct rvu_block *block;
 	struct rvu_pfvf *pfvf;
 	u64 cfg, ctx_cfg;
+	struct cgx *cgxd;
 	int blkaddr;
+	u8 cgx;
+	int pf;
 
 	if (!req->rq_cnt || !req->sq_cnt || !req->cq_cnt)
 		return NIX_AF_ERR_PARAM;
@@ -1680,8 +1691,17 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg);
 
 	/* Configure pkind for TX parse config */
-	cfg = NPC_TX_DEF_PKIND;
-	rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg);
+	if (is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))) {
+		pf = rvu_get_pf(rvu->pdev, pcifunc);
+		cgxd = rvu_cgx_pdata(cgx, rvu);
+
+		mutex_lock(&cgxd->lock);
+		if (rvu_cgx_is_pkind_config_permitted(rvu, pcifunc)) {
+			cfg = NPC_TX_DEF_PKIND;
+			rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg);
+		}
+		mutex_unlock(&cgxd->lock);
+	}
 
 	if (is_rep_dev(rvu, pcifunc)) {
 		pfvf->tx_chan_base = RVU_SWITCH_LBK_CHAN;
-- 
2.43.0

Re: [PATCH net v2] octeontx2-af: Block VFs from clobbering special CGX PKIND state

[Ratheesh Kannoth]

On 2026-06-25 at 10:16:21, Ratheesh Kannoth (rkannoth@marvell.com) wrote:
> From: Hariprasad Kelam <hkelam@marvell.com>
>
> PF and VF NIX LFs that share a CGX LMAC reuse the same hardware PKIND
> programming. When HiGig2 or EDSA parsing is enabled, a VF NIX LF alloc must
> not reset the LMAC RX PKIND or default TX parse config over the PF setup.
>
> Add cgx_get_pkind() and rvu_cgx_is_pkind_config_permitted() so VFs skip
> cgx_set_pkind(), rvu_npc_set_pkind(), and NIX_AF_LFX_TX_PARSE_CFG updates
> when the LMAC is using NPC_RX_HIGIG_PKIND or NPC_RX_EDSA_PKIND.
>
> Fixes: 94d942c5fb97 ("octeontx2-af: Config pkind for CGX mapped PFs")
> Cc: Geetha sowjanya <gakula@marvell.com>
> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
> Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
>
> ---
> v1 -> v2: Addressed simon comments
> 	https://lore.kernel.org/netdev/20260619041002.1773822-1-rkannoth@marvell.com/
> ---

Apologies for the inconvenience — it appears I submitted an incorrect patch.
I will abandon it and post a revised one later. Thanks.

pw-bot: changes-requested

Re: [PATCH net v2] octeontx2-af: Block VFs from clobbering special CGX PKIND state

[kernel test robot]

Hi Ratheesh,

kernel test robot noticed the following build warnings:

[auto build test WARNING on net/main]
[also build test WARNING on linus/master v7.1 next-20260623]
[cannot apply to linux-review/Ratheesh-Kannoth/octeontx2-af-Block-VFs-from-clobbering-special-CGX-PKIND-state/20260622-133621 horms-ipvs/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ratheesh-Kannoth/octeontx2-af-Block-VFs-from-clobbering-special-CGX-PKIND-state/20260625-124846
base:   net/main
patch link:    https://lore.kernel.org/r/20260625044621.2841831-1-rkannoth%40marvell.com
patch subject: [PATCH net v2] octeontx2-af: Block VFs from clobbering special CGX PKIND state
config: s390-allmodconfig (https://download.01.org/0day-ci/archive/20260625/202606251954.vsXupLpQ-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 6cc609bb250b21b47fc7d394b4019101e9983597)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260625/202606251954.vsXupLpQ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202606251954.vsXupLpQ-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c:1522:6: warning: variable 'pf' set but not used [-Wunused-but-set-variable]
    1522 |         int pf;
         |             ^
>> drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c:1696:24: warning: variable 'cgx' is uninitialized when used here [-Wuninitialized]
    1696 |                 cgxd = rvu_cgx_pdata(cgx, rvu);
         |                                      ^~~
   drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c:1521:8: note: initialize the variable 'cgx' to silence this warning
    1521 |         u8 cgx;
         |               ^
         |                = '\0'
   2 warnings generated.


vim +/pf +1522 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

  1506	
  1507	int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
  1508					  struct nix_lf_alloc_req *req,
  1509					  struct nix_lf_alloc_rsp *rsp)
  1510	{
  1511		int nixlf, qints, hwctx_size, intf, rc = 0;
  1512		u16 bcast, mcast, promisc, ucast;
  1513		struct rvu_hwinfo *hw = rvu->hw;
  1514		u16 pcifunc = req->hdr.pcifunc;
  1515		bool rules_created = false;
  1516		struct rvu_block *block;
  1517		struct rvu_pfvf *pfvf;
  1518		u64 cfg, ctx_cfg;
  1519		struct cgx *cgxd;
  1520		int blkaddr;
  1521		u8 cgx;
> 1522		int pf;
  1523	
  1524		if (!req->rq_cnt || !req->sq_cnt || !req->cq_cnt)
  1525			return NIX_AF_ERR_PARAM;
  1526	
  1527		if (req->way_mask)
  1528			req->way_mask &= 0xFFFF;
  1529	
  1530		pfvf = rvu_get_pfvf(rvu, pcifunc);
  1531		blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
  1532		if (!pfvf->nixlf || blkaddr < 0)
  1533			return NIX_AF_ERR_AF_LF_INVALID;
  1534	
  1535		block = &hw->block[blkaddr];
  1536		nixlf = rvu_get_lf(rvu, block, pcifunc, 0);
  1537		if (nixlf < 0)
  1538			return NIX_AF_ERR_AF_LF_INVALID;
  1539	
  1540		/* Check if requested 'NIXLF <=> NPALF' mapping is valid */
  1541		if (req->npa_func) {
  1542			/* If default, use 'this' NIXLF's PFFUNC */
  1543			if (req->npa_func == RVU_DEFAULT_PF_FUNC)
  1544				req->npa_func = pcifunc;
  1545			if (!is_pffunc_map_valid(rvu, req->npa_func, BLKTYPE_NPA))
  1546				return NIX_AF_INVAL_NPA_PF_FUNC;
  1547		}
  1548	
  1549		/* Check if requested 'NIXLF <=> SSOLF' mapping is valid */
  1550		if (req->sso_func) {
  1551			/* If default, use 'this' NIXLF's PFFUNC */
  1552			if (req->sso_func == RVU_DEFAULT_PF_FUNC)
  1553				req->sso_func = pcifunc;
  1554			if (!is_pffunc_map_valid(rvu, req->sso_func, BLKTYPE_SSO))
  1555				return NIX_AF_INVAL_SSO_PF_FUNC;
  1556		}
  1557	
  1558		/* If RSS is being enabled, check if requested config is valid.
  1559		 * RSS table size should be power of two, otherwise
  1560		 * RSS_GRP::OFFSET + adder might go beyond that group or
  1561		 * won't be able to use entire table.
  1562		 */
  1563		if (req->rss_sz && (req->rss_sz > MAX_RSS_INDIR_TBL_SIZE ||
  1564				    !is_power_of_2(req->rss_sz)))
  1565			return NIX_AF_ERR_RSS_SIZE_INVALID;
  1566	
  1567		if (req->rss_sz &&
  1568		    (!req->rss_grps || req->rss_grps > MAX_RSS_GROUPS))
  1569			return NIX_AF_ERR_RSS_GRPS_INVALID;
  1570	
  1571		/* Reset this NIX LF */
  1572		rc = rvu_lf_reset(rvu, block, nixlf);
  1573		if (rc) {
  1574			dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n",
  1575				block->addr - BLKADDR_NIX0, nixlf);
  1576			return NIX_AF_ERR_LF_RESET;
  1577		}
  1578	
  1579		ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3);
  1580	
  1581		/* Alloc NIX RQ HW context memory and config the base */
  1582		hwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF);
  1583		rc = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size);
  1584		if (rc)
  1585			goto free_mem;
  1586	
  1587		pfvf->rq_bmap = kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL);
  1588		if (!pfvf->rq_bmap) {
  1589			rc = -ENOMEM;
  1590			goto free_mem;
  1591		}
  1592	
  1593		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf),
  1594			    (u64)pfvf->rq_ctx->iova);
  1595	
  1596		/* Set caching and queue count in HW */
  1597		cfg = BIT_ULL(36) | (req->rq_cnt - 1) | req->way_mask << 20;
  1598		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_CFG(nixlf), cfg);
  1599	
  1600		/* Alloc NIX SQ HW context memory and config the base */
  1601		hwctx_size = 1UL << (ctx_cfg & 0xF);
  1602		rc = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size);
  1603		if (rc)
  1604			goto free_mem;
  1605	
  1606		pfvf->sq_bmap = kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL);
  1607		if (!pfvf->sq_bmap) {
  1608			rc = -ENOMEM;
  1609			goto free_mem;
  1610		}
  1611	
  1612		rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf),
  1613			    (u64)pfvf->sq_ctx->iova);
  1614	
  1615		cfg = BIT_ULL(36) | (req->sq_cnt - 1) | req->way_mask << 20;
  1616		rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_CFG(nixlf), cfg);
  1617	
  1618		/* Alloc NIX CQ HW context memory and config the base */
  1619		hwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF);
  1620		rc = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size);
  1621		if (rc)
  1622			goto free_mem;
  1623	
  1624		pfvf->cq_bmap = kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL);
  1625		if (!pfvf->cq_bmap) {
  1626			rc = -ENOMEM;
  1627			goto free_mem;
  1628		}
  1629	
  1630		rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf),
  1631			    (u64)pfvf->cq_ctx->iova);
  1632	
  1633		cfg = BIT_ULL(36) | (req->cq_cnt - 1) | req->way_mask << 20;
  1634		rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_CFG(nixlf), cfg);
  1635	
  1636		/* Initialize receive side scaling (RSS) */
  1637		hwctx_size = 1UL << ((ctx_cfg >> 12) & 0xF);
  1638		rc = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz,
  1639					req->rss_grps, hwctx_size, req->way_mask,
  1640					!!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER));
  1641		if (rc)
  1642			goto free_mem;
  1643	
  1644		/* Alloc memory for CQINT's HW contexts */
  1645		cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
  1646		qints = (cfg >> 24) & 0xFFF;
  1647		hwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF);
  1648		rc = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size);
  1649		if (rc)
  1650			goto free_mem;
  1651	
  1652		rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf),
  1653			    (u64)pfvf->cq_ints_ctx->iova);
  1654	
  1655		rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_CFG(nixlf),
  1656			    BIT_ULL(36) | req->way_mask << 20);
  1657	
  1658		/* Alloc memory for QINT's HW contexts */
  1659		cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
  1660		qints = (cfg >> 12) & 0xFFF;
  1661		hwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF);
  1662		rc = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size);
  1663		if (rc)
  1664			goto free_mem;
  1665	
  1666		rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf),
  1667			    (u64)pfvf->nix_qints_ctx->iova);
  1668		rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_CFG(nixlf),
  1669			    BIT_ULL(36) | req->way_mask << 20);
  1670	
  1671		/* Setup VLANX TPID's.
  1672		 * Use VLAN1 for 802.1Q
  1673		 * and VLAN0 for 802.1AD.
  1674		 */
  1675		cfg = (0x8100ULL << 16) | 0x88A8ULL;
  1676		rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg);
  1677	
  1678		/* Enable LMTST for this NIX LF */
  1679		rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0));
  1680	
  1681		/* Set CQE/WQE size, NPA_PF_FUNC for SQBs and also SSO_PF_FUNC */
  1682		if (req->npa_func)
  1683			cfg = req->npa_func;
  1684		if (req->sso_func)
  1685			cfg |= (u64)req->sso_func << 16;
  1686	
  1687		cfg |= (u64)req->xqe_sz << 33;
  1688		rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), cfg);
  1689	
  1690		/* Config Rx pkt length, csum checks and apad  enable / disable */
  1691		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg);
  1692	
  1693		/* Configure pkind for TX parse config */
  1694		if (is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))) {
  1695			pf = rvu_get_pf(rvu->pdev, pcifunc);
> 1696			cgxd = rvu_cgx_pdata(cgx, rvu);
  1697	
  1698			mutex_lock(&cgxd->lock);
  1699			if (rvu_cgx_is_pkind_config_permitted(rvu, pcifunc)) {
  1700				cfg = NPC_TX_DEF_PKIND;
  1701				rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg);
  1702			}
  1703			mutex_unlock(&cgxd->lock);
  1704		}
  1705	
  1706		if (is_rep_dev(rvu, pcifunc)) {
  1707			pfvf->tx_chan_base = RVU_SWITCH_LBK_CHAN;
  1708			pfvf->tx_chan_cnt = 1;
  1709			goto exit;
  1710		}
  1711	
  1712		intf = is_lbk_vf(rvu, pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
  1713		if (is_sdp_pfvf(rvu, pcifunc))
  1714			intf = NIX_INTF_TYPE_SDP;
  1715	
  1716		if (is_cn20k(rvu->pdev)) {
  1717			rc = npc_cn20k_dft_rules_idx_get(rvu, pcifunc, &bcast, &mcast,
  1718							 &promisc, &ucast);
  1719			if (rc) {
  1720				rc = npc_cn20k_dft_rules_alloc(rvu, pcifunc);
  1721				if (rc)
  1722					goto free_mem;
  1723	
  1724				rules_created = true;
  1725			}
  1726		}
  1727	
  1728		rc = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp,
  1729					!!(req->flags & NIX_LF_LBK_BLK_SEL));
  1730		if (rc)
  1731			goto free_dft;
  1732	
  1733		/* Disable NPC entries as NIXLF's contexts are not initialized yet */
  1734		rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
  1735	
  1736		/* Configure RX VTAG Type 7 (strip) for vf vlan */
  1737		rvu_write64(rvu, blkaddr,
  1738			    NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, NIX_AF_LFX_RX_VTAG_TYPE7),
  1739			    VTAGSIZE_T4 | VTAG_STRIP);
  1740	
  1741		goto exit;
  1742	
  1743	free_dft:
  1744		if (is_cn20k(rvu->pdev) && rules_created)
  1745			npc_cn20k_dft_rules_free(rvu, pcifunc);
  1746	
  1747	free_mem:
  1748		nix_ctx_free(rvu, pfvf);
  1749	
  1750	exit:
  1751		/* Set macaddr of this PF/VF */
  1752		ether_addr_copy(rsp->mac_addr, pfvf->mac_addr);
  1753	
  1754		/* set SQB size info */
  1755		cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST);
  1756		rsp->sqb_size = (cfg >> 34) & 0xFFFF;
  1757		rsp->rx_chan_base = pfvf->rx_chan_base;
  1758		rsp->tx_chan_base = pfvf->tx_chan_base;
  1759		rsp->rx_chan_cnt = pfvf->rx_chan_cnt;
  1760		rsp->tx_chan_cnt = pfvf->tx_chan_cnt;
  1761		rsp->lso_tsov4_idx = NIX_LSO_FORMAT_IDX_TSOV4;
  1762		rsp->lso_tsov6_idx = NIX_LSO_FORMAT_IDX_TSOV6;
  1763		/* Get HW supported stat count */
  1764		cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
  1765		rsp->lf_rx_stats = ((cfg >> 32) & 0xFF);
  1766		rsp->lf_tx_stats = ((cfg >> 24) & 0xFF);
  1767		/* Get count of CQ IRQs and error IRQs supported per LF */
  1768		cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
  1769		rsp->qints = ((cfg >> 12) & 0xFFF);
  1770		rsp->cints = ((cfg >> 24) & 0xFFF);
  1771		rsp->cgx_links = hw->cgx_links;
  1772		rsp->lbk_links = hw->lbk_links;
  1773		rsp->sdp_links = hw->sdp_links;
  1774	
  1775		return rc;
  1776	}
  1777	

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki