From: <alejandro.lucero-palau@amd.com>
To: <netdev@vger.kernel.org>, <kuba@kernel.org>,
<davem@davemloft.net>, <edumazet@google.com>, <pabeni@redhat.com>,
<horms@kernel.org>, <dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ben Cheatham <benjamin.cheatham@amd.com>,
Edward Cree <ecree.xilinx@gmail.com>
Subject: [PATCH net 4/7] sfc: Map cxl regs
Date: Wed, 1 Jul 2026 12:38:02 +0100 [thread overview]
Message-ID: <20260701113805.14072-5-alejandro.lucero-palau@amd.com> (raw)
In-Reply-To: <20260701113805.14072-1-alejandro.lucero-palau@amd.com>
From: Alejandro Lucero <alucerop@amd.com>
Use cxl core functions for discovering and mapping CXL device registers.
Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
Link: https://patch.msgid.link/20260630151346.31201-3-alejandro.lucero-palau@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/net/ethernet/sfc/efx_cxl.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
index be252af972ab..704b0ebae937 100644
--- a/drivers/net/ethernet/sfc/efx_cxl.c
+++ b/drivers/net/ethernet/sfc/efx_cxl.c
@@ -7,6 +7,8 @@
#include <linux/pci.h>
+#include <cxl/cxl.h>
+#include <cxl/pci.h>
#include "net_driver.h"
#include "efx_cxl.h"
@@ -18,6 +20,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
struct pci_dev *pci_dev = efx->pci_dev;
struct efx_cxl *cxl;
u16 dvsec;
+ int rc;
/* Is the device configured with and using CXL? */
if (!pcie_is_cxl(pci_dev))
@@ -42,6 +45,29 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
if (!cxl)
return -ENOMEM;
+ rc = cxl_pci_setup_regs(pci_dev, CXL_REGLOC_RBI_COMPONENT,
+ &cxl->cxlds.reg_map);
+ if (rc) {
+ pci_err(pci_dev, "No component registers\n");
+ return rc;
+ }
+
+ if (!cxl->cxlds.reg_map.component_map.hdm_decoder.valid) {
+ pci_err(pci_dev, "Expected HDM component register not found\n");
+ return -ENODEV;
+ }
+
+ if (!cxl->cxlds.reg_map.component_map.ras.valid) {
+ pci_err(pci_dev, "Expected RAS component register not found\n");
+ return -ENODEV;
+ }
+
+ /* Set media ready explicitly as there are neither mailbox for checking
+ * this state nor the CXL register involved, both not mandatory for
+ * type2.
+ */
+ cxl->cxlds.media_ready = true;
+
probe_data->cxl = cxl;
return 0;
--
2.34.1
next prev parent reply other threads:[~2026-07-01 10:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 11:37 [PATCH net 0/7] pull request: sfc 2026-07-01 alejandro.lucero-palau
2026-07-01 11:37 ` [PATCH net 1/7] cxl: Support Type2 cxl regs mapping alejandro.lucero-palau
2026-07-01 11:38 ` [PATCH net 2/7] cxl: Support dpa without a mailbox alejandro.lucero-palau
2026-07-01 11:38 ` [PATCH net 3/7] sfc: add cxl support alejandro.lucero-palau
2026-07-01 11:38 ` alejandro.lucero-palau [this message]
2026-07-01 11:38 ` [PATCH net 5/7] sfc: Initialize cxl dpa alejandro.lucero-palau
2026-07-01 11:38 ` [PATCH net 6/7] sfc: obtain and map cxl range using devm_cxl_probe_mem alejandro.lucero-palau
2026-07-01 11:38 ` [PATCH net 7/7] sfc: support pio mapping based on cxl alejandro.lucero-palau
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