From: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
To: Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Richard Cochran <richardcochran@gmail.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Biao Huang <biao.huang@mediatek.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: maxime.chevallier@bootlin.com, rmk+kernel@armlinux.org.uk,
kernel@collabora.com, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com,
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Subject: [PATCH net-next 3/6] net: stmmac: mediatek: rename MT2712 and MT8195 variant methods
Date: Tue, 07 Jul 2026 10:21:21 +0200 [thread overview]
Message-ID: <20260707-dwmac-mediatek-mt8189-v1-3-17f345eaaca3@collabora.com> (raw)
In-Reply-To: <20260707-dwmac-mediatek-mt8189-v1-0-17f345eaaca3@collabora.com>
In preparation of newer SoC support, rename MT2712 and MT8195 variant
methods and sub functions to more generic names.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 32 +++++++++++-----------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index 0cabab4fd89a..28e87990b0a1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
@@ -110,7 +110,7 @@ static const char * const mt8195_dwmac_clk_l[] = {
"axi", "apb", "mac_cg", "mac_main", "ptp_ref"
};
-static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,
+static int set_phy_interface_v1(struct mediatek_dwmac_plat_data *plat,
u8 phy_intf_sel)
{
u32 intf_val = phy_intf_sel;
@@ -127,7 +127,7 @@ static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,
return 0;
}
-static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
+static void delay_ps2stage_v1(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -152,7 +152,7 @@ static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
}
}
-static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
+static void delay_stage2ps_v1(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -177,12 +177,12 @@ static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
}
}
-static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
+static int set_delay_v1(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
u32 delay_val = 0, fine_val = 0;
- mt2712_delay_ps2stage(plat);
+ delay_ps2stage_v1(plat);
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
@@ -261,14 +261,14 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
- mt2712_delay_stage2ps(plat);
+ delay_stage2ps_v1(plat);
return 0;
}
static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
- .dwmac_set_phy_interface = mt2712_set_interface,
- .dwmac_set_delay = mt2712_set_delay,
+ .dwmac_set_phy_interface = set_phy_interface_v1,
+ .dwmac_set_delay = set_delay_v1,
.clk_list = mt2712_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
.rx_delay_max = 17600,
@@ -276,7 +276,7 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
.dma_bit_mask = 33,
};
-static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
+static int set_phy_interface_v2(struct mediatek_dwmac_plat_data *plat,
u8 phy_intf_sel)
{
u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel);
@@ -299,7 +299,7 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
return 0;
}
-static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
+static void delay_ps2stage_v2(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -308,7 +308,7 @@ static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
mac_delay->rx_delay /= 290;
}
-static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
+static void delay_stage2ps_v2(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -317,13 +317,13 @@ static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
mac_delay->rx_delay *= 290;
}
-static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
+static int set_delay_v2(struct mediatek_dwmac_plat_data *plat)
{
u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0;
struct mac_delay_struct *mac_delay = &plat->mac_delay;
u32 reg_offset = plat->variant->peri_eth_ctrl_offset;
- mt8195_delay_ps2stage(plat);
+ delay_ps2stage_v2(plat);
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
@@ -419,14 +419,14 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
reg_offset + MT8195_PERI_ETH_CTRL2,
rmii_delay_val);
- mt8195_delay_stage2ps(plat);
+ delay_stage2ps_v2(plat);
return 0;
}
static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
- .dwmac_set_phy_interface = mt8195_set_interface,
- .dwmac_set_delay = mt8195_set_delay,
+ .dwmac_set_phy_interface = set_phy_interface_v2,
+ .dwmac_set_delay = set_delay_v2,
.clk_list = mt8195_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
.rx_delay_max = 9280,
--
2.55.0
next prev parent reply other threads:[~2026-07-07 8:21 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-07 8:21 [PATCH net-next 0/6] net/stmmac: Add Mediatek MT8189 support Louis-Alexis Eyraud
2026-07-07 8:21 ` [PATCH net-next 1/6] dt-bindings: net: mediatek-dwmac: add support for MT8189 SoC Louis-Alexis Eyraud
2026-07-07 12:42 ` Andrew Lunn
2026-07-07 8:21 ` [PATCH net-next 2/6] net: stmmac: mediatek: add PERI_ETH_CTRLx register offset in platform data Louis-Alexis Eyraud
2026-07-07 8:55 ` Maxime Chevallier
2026-07-07 12:45 ` Andrew Lunn
2026-07-07 8:21 ` Louis-Alexis Eyraud [this message]
2026-07-07 9:05 ` [PATCH net-next 3/6] net: stmmac: mediatek: rename MT2712 and MT8195 variant methods Maxime Chevallier
2026-07-07 8:21 ` [PATCH net-next 4/6] net: stmmac: mediatek: add support for TX clock output enable feature Louis-Alexis Eyraud
2026-07-07 8:21 ` [PATCH net-next 5/6] net: stmmac: mediatek: add support for TX deallocation adjustment feature Louis-Alexis Eyraud
2026-07-07 9:11 ` Maxime Chevallier
2026-07-07 8:21 ` [PATCH net-next 6/6] net: stmmac: mediatek: add support for MT8189 SoC Louis-Alexis Eyraud
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