From: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
To: intel-wired-lan@lists.osuosl.org
Cc: netdev@vger.kernel.org
Subject: [PATCH iwl-next v1 4/4] ice: dpll: Rework the SMA control logic to match the requirements
Date: Thu, 16 Jul 2026 09:49:11 +0000 [thread overview]
Message-ID: <20260716094912.1210865-5-sergey.temerkhanov@intel.com> (raw)
In-Reply-To: <20260716094912.1210865-1-sergey.temerkhanov@intel.com>
Make the SMA control logic match the requirements:
Setting SMA1 as Rx automatically enables U.FL1 as Tx if U.FL1 is
disconnected.
Setting SMA1 as Tx automatically changes U.FL1 state to disconnected.
Setting SMA2 as Tx automatically enables U.FL2 as Rx if U.FL2 is
disconnected.
Setting SMA2 as Rx automatically changes U.FL2 state to disconnected.
Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Reviewed-by: Przemyslaw Korba <przemyslaw.korba@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 88 ++++++++++++++++++++---
1 file changed, 78 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index cb14621b3aef..f11d90ed80f2 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -698,10 +698,10 @@ ice_dpll_sw_pins_update(struct ice_pf *pf)
p = &d->sma[ICE_DPLL_PIN_SW_2_IDX];
p->active = true;
p->direction = DPLL_PIN_DIRECTION_INPUT;
+ if (data & ICE_SMA2_DIR_EN)
+ p->direction = DPLL_PIN_DIRECTION_OUTPUT;
if ((data & ICE_SMA2_INACTIVE_MASK) == ICE_SMA2_INACTIVE_MASK)
p->active = false;
- else if (data & ICE_SMA2_DIR_EN)
- p->direction = DPLL_PIN_DIRECTION_OUTPUT;
p = &d->ufl[ICE_DPLL_PIN_SW_1_IDX];
if (!(data & (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)))
@@ -1224,17 +1224,21 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p,
switch (p->idx) {
case ICE_DPLL_PIN_SW_1_IDX:
- data &= ~ICE_SMA1_MASK;
- if (direction == DPLL_PIN_DIRECTION_OUTPUT)
+ if (direction == DPLL_PIN_DIRECTION_OUTPUT) {
+ data &= ~ICE_SMA1_TX_EN;
data |= ICE_SMA1_DIR_EN;
+ } else {
+ data &= ~ICE_SMA1_DIR_EN;
+ data &= ~ICE_SMA1_TX_EN;
+ }
break;
case ICE_DPLL_PIN_SW_2_IDX:
if (direction == DPLL_PIN_DIRECTION_INPUT) {
data &= ~ICE_SMA2_DIR_EN;
- data |= ICE_SMA2_UFL2_RX_DIS;
} else {
- data &= ~(ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS);
data |= ICE_SMA2_DIR_EN;
+ data &= ~ICE_SMA2_UFL2_RX_DIS;
+ data &= ~ICE_SMA2_TX_EN;
}
break;
default:
@@ -1505,6 +1509,7 @@ ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv,
struct ice_dpll *d = dpll_priv;
struct ice_pf *pf = sma->pf;
enum ice_dpll_pin_type type;
+ u8 old_data = 0;
bool enable;
int ret;
@@ -1556,13 +1561,76 @@ ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv,
goto unlock;
}
- if (enable)
+ if (enable) {
+ u8 data;
+
+ ret = ice_read_sma_ctrl(&pf->hw, &data);
+ if (ret)
+ goto unlock;
+ old_data = data;
+ if (sma->idx == ICE_DPLL_PIN_SW_1_IDX) {
+ data &= ~ICE_SMA1_TX_EN;
+ } else if (sma->idx == ICE_DPLL_PIN_SW_2_IDX) {
+ data &= ~ICE_SMA2_UFL2_RX_DIS;
+ data &= ~ICE_SMA2_TX_EN;
+ }
+ ret = ice_write_sma_ctrl(&pf->hw, data);
+ if (ret)
+ goto unlock;
+ ret = ice_dpll_sw_pins_update(pf);
+ if (ret)
+ goto restore_sma_ctrl;
+
ret = ice_dpll_pin_enable(&pf->hw, target, d->dpll_idx, type,
extack);
- else
- ret = ice_dpll_pin_disable(&pf->hw, target, type, extack);
- if (!ret)
+ if (ret)
+ goto restore_sma_ctrl;
+ /* refresh target state first so a peer-side error cannot leave it stale */
ret = ice_dpll_pin_state_update(pf, target, type, extack);
+ if (ret)
+ goto restore_sma_ctrl;
+
+ if (sma->muxed->active) {
+ struct ice_dpll_pin *peer = sma->muxed;
+ struct ice_dpll_pin *peer_target;
+ enum ice_dpll_pin_type peer_type;
+
+ if (peer->direction == DPLL_PIN_DIRECTION_OUTPUT) {
+ peer_target = peer->output;
+ peer_type = ICE_DPLL_PIN_TYPE_OUTPUT;
+ } else {
+ peer_target = peer->input;
+ peer_type = ICE_DPLL_PIN_TYPE_INPUT;
+ }
+ ret = ice_dpll_pin_enable(&pf->hw, peer_target,
+ d->dpll_idx,
+ peer_type, extack);
+ if (!ret)
+ ret = ice_dpll_pin_state_update(pf, peer_target,
+ peer_type, extack);
+ if (ret)
+ goto restore_sma_ctrl;
+ }
+ } else {
+ ret = ice_dpll_pin_disable(&pf->hw, target, type, extack);
+ if (!ret)
+ ret = ice_dpll_pin_state_update(pf, target, type,
+ extack);
+ }
+ goto unlock;
+
+restore_sma_ctrl:
+ {
+ int restore_ret;
+
+ restore_ret = ice_write_sma_ctrl(&pf->hw, old_data);
+ if (!restore_ret)
+ restore_ret = ice_dpll_sw_pins_update(pf);
+ if (restore_ret)
+ dev_warn(ice_pf_to_dev(pf),
+ "Failed to restore SMA control after pin state error %d, restore err %d\n",
+ ret, restore_ret);
+ }
unlock:
mutex_unlock(&pf->dplls.lock);
--
2.53.0
prev parent reply other threads:[~2026-07-16 9:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-16 9:49 [PATCH iwl-next v1 0/4] Rework and fix ice dpll pin control Sergey Temerkhanov
2026-07-16 9:49 ` [PATCH iwl-next v1 1/4] ice: dpll: Rework multiplexed pin notifications Sergey Temerkhanov
2026-07-16 9:49 ` [PATCH iwl-next v1 2/4] ice: dpll: Use switch statements to handle pin states Sergey Temerkhanov
2026-07-16 9:49 ` [PATCH iwl-next v1 3/4] ice: dpll: Rework U.FL muxed pin (SMA) control Sergey Temerkhanov
2026-07-16 9:49 ` Sergey Temerkhanov [this message]
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