Re: [PATCH net-next v7 3/3] dpll: add SiTime SiT9531x DPLL clock driver

[Ali Rouhi <arouhi@sitime.com>]

On 19/08/2026 22:16, Vadim Fedorenko wrote:
> as the new version is need, could you please think of how it can be
> split. reviewing if 5.6k lines of code in one go is quite tough

Agreed. v8 will be a series.

The order follows the first zl3073x series that Ivan pointed at, which
we took as the model: the mechanical foundation first, then one
capability per patch.

   1  basic SiT9531x support - Kconfig, Makefile, MAINTAINERS, regmap
      with the page selector, variant detection, probe
   2  read DPLL types and pin properties from system firmware
   3  register the DPLL devices and their pins
   4  lock status, device mode, and the periodic state monitor,
      including the optional INTRB interrupt
   5  input pin state on a DPLL
   6  input pin priority get and set
   7  pin frequency get and set
   8  output phase adjustment
   9  embedded sync control on outputs
  10  phase offset measurement through the TDC
  11  fractional frequency offset of the selected reference
  12  the INTSYNC source and destination pin pair
  13  optional device-tree overrides, per-PLL Fvco and the
      output-to-PLL map

preceded by the two dt-bindings patches, which are unchanged from v7
apart from moving a VCO example value inside a supported band.

Property parsing comes before registration because both device and pin
registration read from it. Sizes run from roughly 250 to 900 lines,
largest at the front.

Two ground rules: every patch builds and works on its own so the series
stays bisectable, and the end state is byte-identical to what v7 would
have been, so nothing you find is an artefact of the split. checkpatch
--strict, W=1 C=1 with sparse, and a 32-bit build on every patch
individually, then git am of the whole series onto clean net-next and
dt_binding_check.

If you would rather see it split differently, say so now and I will
restructure before posting.

Thanks,
Ali