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From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: Manivannan Sadhasivam <mani@kernel.org>,
	Jeff Hugo <jeff.hugo@oss.qualcomm.com>,
	Richard Cochran <richardcochran@gmail.com>
Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
	Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Subject: [PATCH v3 5/6] bus: mhi: host: Export mhi_read_reg
Date: Thu, 17 Sep 2026 12:38:06 +0530	[thread overview]
Message-ID: <20260917-tsc_timesync-v3-5-6826d5d2d527@oss.qualcomm.com> (raw)
In-Reply-To: <20260917-tsc_timesync-v3-0-6826d5d2d527@oss.qualcomm.com>

Export mhi_read_reg() so it can be called from other MHI bus modules
that are built separately from mhi.ko.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 drivers/bus/mhi/host/main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c
index bfeb5cf53448..1ca9f781bbdb 100644
--- a/drivers/bus/mhi/host/main.c
+++ b/drivers/bus/mhi/host/main.c
@@ -22,6 +22,7 @@ int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
 {
 	return mhi_cntrl->read_reg(mhi_cntrl, base + offset, out);
 }
+EXPORT_SYMBOL_GPL(mhi_read_reg);
 
 int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,
 				    void __iomem *base, u32 offset,

-- 
2.34.1


  parent reply	other threads:[~2026-09-17  7:08 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-17  7:08 [PATCH v3 0/6] bus: mhi: host: mhi_phc: Add support for PHC over MHI Krishna Chaitanya Chundru
2026-09-17  7:08 ` [PATCH v3 1/6] bus: mhi: host: Add support to read MHI capabilities Krishna Chaitanya Chundru
2026-09-17  7:08 ` [PATCH v3 2/6] bus: mhi: host: mhi_phc: Add support for PHC over MHI Krishna Chaitanya Chundru
2026-09-17  7:08 ` [PATCH v3 3/6] bus: mhi: host: Add support for 64bit register reads and writes Krishna Chaitanya Chundru
2026-09-17  7:08 ` [PATCH v3 4/6] bus: mhi: pci_generic: Add support for 64 bit register read & write Krishna Chaitanya Chundru
2026-09-17  7:08 ` Krishna Chaitanya Chundru [this message]
2026-09-17  7:08 ` [PATCH v3 6/6] bus: mhi: host: mhi_phc: Update the Time sync logic to read 64 bit register value Krishna Chaitanya Chundru
2026-09-17 14:48 ` [PATCH v3 0/6] bus: mhi: host: mhi_phc: Add support for PHC over MHI Jakub Kicinski
2026-09-18 10:52   ` Krishna Chaitanya Chundru
2026-09-21 21:14     ` Jakub Kicinski

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