* [PATCH net-next v4] Add config phase for dp83td510e phy
@ 2026-09-18 13:37 Julien Blanc
2026-09-23 2:13 ` Jakub Kicinski
0 siblings, 1 reply; 2+ messages in thread
From: Julien Blanc @ 2026-09-18 13:37 UTC (permalink / raw)
To: netdev@vger.kernel.org
Cc: o.rempel@pengutronix.de, hkallweit1@gmail.com, kuba@kernel.org,
andrew@lunn.ch
Add a config phase for the Texas Instruments DP83TD510E ethenet PHY
The config phase currently sets the following properties from the
device tree:
* RMII / RGMII mode (note : RMII master / slave can only be set
by straps and cannot be changed at runtime)
* RGMII delays. These delays can be enabled on the phy side, only
as a boolean. Delays are enabled if phy-mode is rgmii-id, or
rgmii-[rx|tx]id which enables only the corresponding delay.
* In case another mode is encountered, do nothing and return
success (keep old behavior)
Signed-off-by: Julien Blanc <julien.blanc@sprinte.eu>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v4:
- fixes formatting and comment style issues
Changes in v3:
- fix returning an uninitialized value if mode was not rgmii[-xx]
or rmii (mii is a valid mode for this phy as well). Return
success in that case to keep the old driver behavior.
- updated commit description accordingly
Changes in v2:
- remove the usage of phy_get_internal_delay
- use booleans to make it clear that thy phy supports only a
fixed delay activation, no configurable delay
drivers/net/phy/dp83td510.c | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
index 9e9a41bf6457..aa61220dbce3 100644
--- a/drivers/net/phy/dp83td510.c
+++ b/drivers/net/phy/dp83td510.c
@@ -30,6 +30,12 @@
#define DP83TD510E_INT1_LINK BIT(13)
#define DP83TD510E_INT1_LINK_EN BIT(5)
+#define DP83TD510E_RCSR 0x17
+#define DP83TD510E_RMII_MODE_EN BIT(5)
+#define DP83TD510E_RGMII_MODE_EN BIT(9)
+#define DP83TD510E_TX_CLK_SHIFT BIT(11)
+#define DP83TD510E_RX_CLK_SHIFT BIT(12)
+
#define DP83TD510E_CTRL 0x1f
#define DP83TD510E_CTRL_HW_RESET BIT(15)
#define DP83TD510E_CTRL_SW_RESET BIT(14)
@@ -649,6 +655,68 @@ static int dp83td510_config_aneg(struct phy_device *phydev)
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
+static bool dp83td510_config_rgmii_rx_delay(struct phy_device *phydev)
+{
+ return phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID;
+}
+
+static bool dp83td510_config_rgmii_tx_delay(struct phy_device *phydev)
+{
+ return phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+static int dp83td510_config_init(struct phy_device *phydev)
+{
+ int rgmii_delay = 0;
+ bool rx_int_delay;
+ bool tx_int_delay;
+ int ret;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ rx_int_delay = dp83td510_config_rgmii_rx_delay(phydev);
+ if (rx_int_delay)
+ rgmii_delay |= DP83TD510E_RX_CLK_SHIFT;
+
+ tx_int_delay = dp83td510_config_rgmii_tx_delay(phydev);
+
+ if (tx_int_delay)
+ rgmii_delay |= DP83TD510E_TX_CLK_SHIFT;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_RCSR,
+ DP83TD510E_RX_CLK_SHIFT |
+ DP83TD510E_TX_CLK_SHIFT,
+ rgmii_delay);
+ if (ret)
+ return ret;
+
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
+ DP83TD510E_RCSR,
DP83TD510E_RGMII_MODE_EN);
+
+ if (ret)
+ return ret;
+
+ } else if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
+ /* set RMII_MODE_EN, clear RGMII_MODE_EN (exclusive) */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_RCSR,
+ DP83TD510E_RMII_MODE_EN |
+ DP83TD510E_RGMII_MODE_EN,
+ DP83TD510E_RMII_MODE_EN);
+ if (ret)
+ return ret;
+ } else {
+ /* may be MII, which is supported, or something else. Just
+ * return success to keep the old behavior and not break
+ * anything. Configuration may have been done by straps so
+ * it's better to not touch it.
+ */
+ ret = 0;
+ }
+
+ return ret;
+}
+
static int dp83td510_get_sqi(struct phy_device *phydev)
{
int sqi, ret;
@@ -942,6 +1010,7 @@ static struct phy_driver dp83td510_driver[] = {
.name = "TI DP83TD510E",
.flags = PHY_POLL_CABLE_TEST,
+ .config_init = dp83td510_config_init,
.probe = dp83td510_probe,
.config_aneg = dp83td510_config_aneg,
.read_status = dp83td510_read_status,
--
2.47.3
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH net-next v4] Add config phase for dp83td510e phy
2026-09-18 13:37 [PATCH net-next v4] Add config phase for dp83td510e phy Julien Blanc
@ 2026-09-23 2:13 ` Jakub Kicinski
0 siblings, 0 replies; 2+ messages in thread
From: Jakub Kicinski @ 2026-09-23 2:13 UTC (permalink / raw)
To: Julien Blanc
Cc: netdev@vger.kernel.org, o.rempel@pengutronix.de,
hkallweit1@gmail.com, andrew@lunn.ch
On Fri, 18 Sep 2026 13:37:18 +0000 Julien Blanc wrote:
> + ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
> + DP83TD510E_RCSR,
> DP83TD510E_RGMII_MODE_EN);
Looks like the diff got mangled this time, pls repost
--
pw-bot: cr
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