* PHY ports: combo port with a MAC-side GPIO mux on a DSA switch?
@ 2026-09-23 22:59 Aleksei Sviridkin
2026-09-24 7:06 ` Maxime Chevallier
0 siblings, 1 reply; 2+ messages in thread
From: Aleksei Sviridkin @ 2026-09-23 22:59 UTC (permalink / raw)
To: Maxime Chevallier
Cc: Aleksei Sviridkin, netdev, Russell King, Andrew Lunn,
Heiner Kallweit, Vladimir Oltean
Hi Maxime,
I have a board where one switch port can use either an SFP cage or a
separate copper PHY, picked by a GPIO mux. I would like to know whether
the PHY ports work is meant to cover it, and how to describe such a
port in devicetree until then.
The board is a Keenetic KN-1012 (MT7981B) with an MT7531 switch. Port 5
is a DSA user port, lan4, in 2500base-x. Its SerDes goes through a mux
on GPIO 27 either to an SFP cage or to an Airoha EN8811H 2.5G copper
PHY, one at a time. SFP presence is on GPIO 23.
OpenWrt handles it downstream with two devicetree overlays. The copper
one gives port 5 a phy-handle to the EN8811H. The SFP one gives it
sfp = <&sfp1> and managed = "in-band-status". The mux is set by an
OpenWrt-only gpio-export node, and a chainloaded U-Boot reads the SFP
presence pin at each boot and picks the overlay. Changing media needs a
reboot.
The PHY ports code in net-next covers an SFP that the PHY drives itself,
with marvell10g as the user. Here the choice sits between the SerDes on
the MAC side and two separate media, a cage and a separate PHY. So my
questions:
1. Is a MAC-side mux like this in scope for the PHY ports work?
2. If it is, what devicetree shape should a board use today so it does
not have to change later?
3. If it is not, is describing a single medium the accepted way for now?
I can test patches on this board. Writing the framework part is beyond
what I can take on myself.
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: PHY ports: combo port with a MAC-side GPIO mux on a DSA switch?
2026-09-23 22:59 PHY ports: combo port with a MAC-side GPIO mux on a DSA switch? Aleksei Sviridkin
@ 2026-09-24 7:06 ` Maxime Chevallier
0 siblings, 0 replies; 2+ messages in thread
From: Maxime Chevallier @ 2026-09-24 7:06 UTC (permalink / raw)
To: Aleksei Sviridkin
Cc: netdev, Russell King, Andrew Lunn, Heiner Kallweit,
Vladimir Oltean
Hi,
On 9/24/26 00:59, Aleksei Sviridkin wrote:
> Hi Maxime,
>
> I have a board where one switch port can use either an SFP cage or a
> separate copper PHY, picked by a GPIO mux. I would like to know whether
> the PHY ports work is meant to cover it, and how to describe such a
> port in devicetree until then.
>
> The board is a Keenetic KN-1012 (MT7981B) with an MT7531 switch. Port 5
> is a DSA user port, lan4, in 2500base-x. Its SerDes goes through a mux
> on GPIO 27 either to an SFP cage or to an Airoha EN8811H 2.5G copper
> PHY, one at a time. SFP presence is on GPIO 23.
>
> OpenWrt handles it downstream with two devicetree overlays. The copper
> one gives port 5 a phy-handle to the EN8811H. The SFP one gives it
> sfp = <&sfp1> and managed = "in-band-status". The mux is set by an
> OpenWrt-only gpio-export node, and a chainloaded U-Boot reads the SFP
> presence pin at each boot and picks the overlay. Changing media needs a
> reboot.
>
> The PHY ports code in net-next covers an SFP that the PHY drives itself,
> with marvell10g as the user. Here the choice sits between the SerDes on
> the MAC side and two separate media, a cage and a separate PHY. So my
> questions:
>
> 1. Is a MAC-side mux like this in scope for the PHY ports work?
> 2. If it is, what devicetree shape should a board use today so it does
> not have to change later?
> 3. If it is not, is describing a single medium the accepted way for now?
>
> I can test patches on this board. Writing the framework part is beyond
> what I can take on myself.
There's ongoing work for that, hopefully that'll work soon :)
https://lore.kernel.org/netdev/20260910170103.1029108-1-maxime.chevallier@bootlin.com/
This is bringing the SFP representation as a "phy_port" that we can see from
userspace, so that we can later switch dynamically between the interfaces
of a combo port.
The next step is mux, including GPIO driven ones :) Any review and testing
is welcome for the above series, I'll CC you on the next iterations,
Maxime
^ permalink raw reply [flat|nested] 2+ messages in thread
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