* [PATCH net-next v3 01/12] cxgb4: add T7 hardware definitions and firmware interfaces
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 02/12] cxgb4: rework the interrupt handling framework Potnuri Bharat Teja
` (10 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Add the initial T7-specific hardware definitions required by the cxgb4
driver. This patch updates chip identification, PCI device IDs,
register definitions, TCB layout definitions, firmware API interfaces,
firmware version information, message formats, and related constants to
provide the foundational infrastructure for upcoming T7 support.
No functional changes are introduced by this patch. It only extends the
existing hardware and firmware definition headers for T7-specific
driver functionality.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/t4_chip_type.h | 10 +
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h | 109 +-
.../ethernet/chelsio/cxgb4/t4_pci_id_tbl.h | 21 +
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 7284 ++++++++++++++---
drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h | 16 +
.../net/ethernet/chelsio/cxgb4/t4_values.h | 11 +
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 83 +-
.../net/ethernet/chelsio/cxgb4/t4fw_version.h | 9 +
8 files changed, 6401 insertions(+), 1142 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h b/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
index 721c77577ec5..444675436b01 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
@@ -39,6 +39,7 @@
#define CHELSIO_T4 0x4
#define CHELSIO_T5 0x5
#define CHELSIO_T6 0x6
+#define CHELSIO_T7 0x7
/* We code the Chelsio T4 Family "Chip Code" as a tuple:
*
@@ -67,6 +68,11 @@ enum chip_type {
T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
T6_FIRST_REV = T6_A0,
T6_LAST_REV = T6_A0,
+
+ T7_A0 = CHELSIO_CHIP_CODE(CHELSIO_T7, 0),
+ T7_B0 = CHELSIO_CHIP_CODE(CHELSIO_T7, 1),
+ T7_FIRST_REV = T7_A0,
+ T7_LAST_REV = T7_B0,
};
static inline int is_t4(enum chip_type chip)
@@ -84,4 +90,8 @@ static inline int is_t6(enum chip_type chip)
return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
}
+static inline int is_t7(enum chip_type chip)
+{
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T7);
+}
#endif /* __T4_CHIP_TYPE_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
index fed5f93bf620..66a55ddf0c24 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
@@ -88,6 +88,7 @@ enum {
CPL_RDMA_READ_REQ = 0x60,
+ CPL_SET_LE_REQ = 0x80,
CPL_PASS_OPEN_REQ6 = 0x81,
CPL_ACT_OPEN_REQ6 = 0x83,
@@ -544,6 +545,26 @@ struct cpl_t6_act_open_req {
__be32 opt3;
};
+struct cpl_t7_act_open_req {
+ WR_HDR;
+ union opcode_tid ot;
+ __be16 local_port;
+ __be16 peer_port;
+ __be32 local_ip;
+ __be32 peer_ip;
+ __be64 opt0;
+ __be32 iss;
+ __be32 opt2;
+ __be64 params;
+ __be32 rsvd2;
+ __be32 opt3;
+};
+
+#define T7_FILTER_TUPLE_S 1
+#define T7_FILTER_TUPLE_M 0x7FFFFFFFFFFFFFFFULL
+#define T7_FILTER_TUPLE_V(x) ((x) << T7_FILTER_TUPLE_S)
+#define T7_FILTER_TUPLE_G(x) (((x) >> T7_FILTER_TUPLE_S) & T7_FILTER_TUPLE_M)
+
struct cpl_act_open_req6 {
WR_HDR;
union opcode_tid ot;
@@ -590,6 +611,23 @@ struct cpl_t6_act_open_req6 {
__be32 opt3;
};
+struct cpl_t7_act_open_req6 {
+ WR_HDR;
+ union opcode_tid ot;
+ __be16 local_port;
+ __be16 peer_port;
+ __be64 local_ip_hi;
+ __be64 local_ip_lo;
+ __be64 peer_ip_hi;
+ __be64 peer_ip_lo;
+ __be64 opt0;
+ __be32 iss;
+ __be32 opt2;
+ __be64 params;
+ __be32 rsvd2;
+ __be32 opt3;
+};
+
struct cpl_act_open_rpl {
union opcode_tid ot;
__be32 atid_status;
@@ -682,10 +720,20 @@ struct cpl_get_tcb {
#define QUEUENO_S 0
#define QUEUENO_V(x) ((x) << QUEUENO_S)
+#define T7_QUEUENO_S 0
+#define T7_QUEUENO_M 0xFFF
+#define T7_QUEUENO_V(x) ((x) << T7_QUEUENO_S)
+#define T7_QUEUENO_G(x) (((x) >> T7_QUEUENO_S) & T7_QUEUENO_M)
+
#define REPLY_CHAN_S 14
#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
#define REPLY_CHAN_F REPLY_CHAN_V(1U)
+#define T7_REPLY_CHAN_S 12
+#define T7_REPLY_CHAN_M 0x7
+#define T7_REPLY_CHAN_V(x) ((x) << T7_REPLY_CHAN_S)
+#define T7_REPLY_CHAN_G(x) (((x) >> T7_REPLY_CHAN_S) & T7_REPLY_CHAN_M)
+
#define NO_REPLY_S 15
#define NO_REPLY_V(x) ((x) << NO_REPLY_S)
#define NO_REPLY_F NO_REPLY_V(1U)
@@ -1363,6 +1411,53 @@ struct cpl_smt_write_rpl {
#define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S)
#define SMTW_NORPL_F SMTW_NORPL_V(1U)
+struct cpl_set_le_req {
+ WR_HDR;
+ union opcode_tid ot;
+ __be16 reply_ctrl;
+ __be16 params;
+ __be64 mask_hi;
+ __be64 mask_lo;
+ __be64 val_hi;
+ __be64 val_lo;
+};
+
+/* cpl_set_le_req.reply_ctrl additional fields */
+#define LE_REQ_RXCHANNEL_S 14
+#define LE_REQ_RXCHANNEL_M 0x1
+#define LE_REQ_RXCHANNEL_V(x) ((x) << LE_REQ_RXCHANNEL_S)
+#define LE_REQ_RXCHANNEL_G(x) (((x) >> LE_REQ_RXCHANNEL_S) & LE_REQ_RXCHANNEL_M)
+#define LE_REQ_RXCHANNEL_F LE_REQ_RXCHANNEL_V(1U)
+
+#define LE_REQ_IP6_S 13
+#define LE_REQ_IP6_V(x) ((x) << LE_REQ_IP6_S)
+#define LE_REQ_IP6_F LE_REQ_IP6_V(1U)
+
+/* cpl_set_le_req.params fields */
+#define LE_CHAN_S 0
+#define LE_CHAN_M 0x3
+#define LE_CHAN_V(x) ((x) << LE_CHAN_S)
+#define LE_CHAN_G(x) (((x) >> LE_CHAN_S) & LE_CHAN_M)
+
+#define LE_OFFSET_S 5
+#define LE_OFFSET_M 0x7
+#define LE_OFFSET_V(x) ((x) << LE_OFFSET_S)
+#define LE_OFFSET_G(x) (((x) >> LE_OFFSET_S) & LE_OFFSET_M)
+
+#define LE_MORE_S 8
+#define LE_MORE_V(x) ((x) << LE_MORE_S)
+#define LE_MORE_F LE_MORE_V(1U)
+
+#define LE_REQSIZE_S 9
+#define LE_REQSIZE_M 0x7
+#define LE_REQSIZE_V(x) ((x) << LE_REQSIZE_S)
+#define LE_REQSIZE_G(x) (((x) >> LE_REQSIZE_S) & LE_REQSIZE_M)
+
+#define LE_REQCMD_S 12
+#define LE_REQCMD_M 0xF
+#define LE_REQCMD_V(x) ((x) << LE_REQCMD_S)
+#define LE_REQCMD_G(x) (((x) >> LE_REQCMD_S) & LE_REQCMD_M)
+
struct cpl_rdma_terminate {
union opcode_tid ot;
__be16 rsvd;
@@ -1631,10 +1726,10 @@ struct cpl_tx_tnl_lso {
(((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M)
#define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U)
-#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
-#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
-#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
-#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
+#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
+#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
+#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
+#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
(((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M)
#define CPL_TX_TNL_LSO_IPHDRLEN_S 4
@@ -1719,12 +1814,6 @@ struct cpl_tx_tnl_lso {
#define CPL_TX_TNL_LSO_TNLTYPE_G(x) \
(((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M)
-#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
-#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
-#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
-#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
- (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
-
#define CPL_TX_TNL_LSO_TNLHDRLEN_S 0
#define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff
#define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h b/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h
index 0b1b5f9c67d4..d0921b76049d 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h
@@ -220,6 +220,27 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
CH_PCI_ID_TABLE_FENTRY(0x608a), /* Custom T62100-CR */
CH_PCI_ID_TABLE_FENTRY(0x608b), /* Custom T6225-CR */
CH_PCI_ID_TABLE_FENTRY(0x6092), /* Custom T62100-CR-LOM */
+
+ /* T7 adapter */
+ CH_PCI_ID_TABLE_FENTRY(0x7000), /* T7-DBG */
+ CH_PCI_ID_TABLE_FENTRY(0x7001), /* T7250 */
+ CH_PCI_ID_TABLE_FENTRY(0x7002), /* S7250 */
+ CH_PCI_ID_TABLE_FENTRY(0x7003), /* T7450 */
+ CH_PCI_ID_TABLE_FENTRY(0x7004), /* S7450 */
+ CH_PCI_ID_TABLE_FENTRY(0x7005), /* T72200 */
+ CH_PCI_ID_TABLE_FENTRY(0x7006), /* S72200 */
+ CH_PCI_ID_TABLE_FENTRY(0x7007), /* T72200-FH */
+ CH_PCI_ID_TABLE_FENTRY(0x7008), /* T71400 */
+ CH_PCI_ID_TABLE_FENTRY(0x7009), /* S7210-BT */
+ CH_PCI_ID_TABLE_FENTRY(0x700a), /* T7450-RC */
+ CH_PCI_ID_TABLE_FENTRY(0x700b), /* T72200-RC */
+ CH_PCI_ID_TABLE_FENTRY(0x700c), /* T72200-FH-RC */
+ CH_PCI_ID_TABLE_FENTRY(0x700d), /* S72200-OCP3 */
+ CH_PCI_ID_TABLE_FENTRY(0x700e), /* S7450-OCP3 */
+ CH_PCI_ID_TABLE_FENTRY(0x700f), /* S7410-BT-OCP3 */
+ CH_PCI_ID_TABLE_FENTRY(0x7010), /* S7210-BT-A */
+ CH_PCI_ID_TABLE_FENTRY(0x7011), /* T7_MAYRA_7 */
+ CH_PCI_ID_TABLE_FENTRY(0x7012), /* T7-iNIC */
CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
#endif /* __T4_PCI_ID_TBL_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 695916ba0405..5ac262ec389f 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -66,6 +66,8 @@
#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define T7_PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+
#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
@@ -172,6 +174,7 @@
#define SGE_CTXT_DATA0_A 0x1200
#define SGE_CTXT_DATA5_A 0x1214
+#define SGE_CTXT_DATA6_A 0x1218
#define GLOBALENABLE_S 0
#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
@@ -229,8 +232,204 @@
#define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
#define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
+#define SGE_INT_ENABLE1_A 0x1028
#define SGE_INT_CAUSE1_A 0x1024
+
+#define PERR_FLM_CREDITFIFO_S 30
+#define PERR_FLM_CREDITFIFO_V(x) ((x) << PERR_FLM_CREDITFIFO_S)
+#define PERR_FLM_CREDITFIFO_F PERR_FLM_CREDITFIFO_V(1U)
+
+#define PERR_IMSG_HINT_FIFO_S 29
+#define PERR_IMSG_HINT_FIFO_V(x) ((x) << PERR_IMSG_HINT_FIFO_S)
+#define PERR_IMSG_HINT_FIFO_F PERR_IMSG_HINT_FIFO_V(1U)
+
+#define PERR_DMARBT_S 17
+#define PERR_DMARBT_V(x) ((x) << PERR_DMARBT_S)
+#define PERR_DMARBT_F PERR_DMARBT_V(1U)
+
+#define PERR_FLM_DBPFIFO_S 16
+#define PERR_FLM_DBPFIFO_V(x) ((x) << PERR_FLM_DBPFIFO_S)
+#define PERR_FLM_DBPFIFO_F PERR_FLM_DBPFIFO_V(1U)
+
+#define PERR_FLM_MCREQ_FIFO_S 15
+#define PERR_FLM_MCREQ_FIFO_V(x) ((x) << PERR_FLM_MCREQ_FIFO_S)
+#define PERR_FLM_MCREQ_FIFO_F PERR_FLM_MCREQ_FIFO_V(1U)
+
+#define PERR_FLM_HINTFIFO_S 14
+#define PERR_FLM_HINTFIFO_V(x) ((x) << PERR_FLM_HINTFIFO_S)
+#define PERR_FLM_HINTFIFO_F PERR_FLM_HINTFIFO_V(1U)
+
+#define PERR_ING_CTXT_MIFRSP_S 1
+#define PERR_ING_CTXT_MIFRSP_V(x) ((x) << PERR_ING_CTXT_MIFRSP_S)
+#define PERR_ING_CTXT_MIFRSP_F PERR_ING_CTXT_MIFRSP_V(1U)
+
+#define PERR_EGR_CTXT_MIFRSP_S 0
+#define PERR_EGR_CTXT_MIFRSP_V(x) ((x) << PERR_EGR_CTXT_MIFRSP_S)
+#define PERR_EGR_CTXT_MIFRSP_F PERR_EGR_CTXT_MIFRSP_V(1U)
+
+#define PERR_PC_RSP_S 23
+#define PERR_PC_RSP_V(x) ((x) << PERR_PC_RSP_S)
+#define PERR_PC_RSP_F PERR_PC_RSP_V(1U)
+
+#define PERR_PC_REQ_S 22
+#define PERR_PC_REQ_V(x) ((x) << PERR_PC_REQ_S)
+#define PERR_PC_REQ_F PERR_PC_REQ_V(1U)
+
+#define PERR_HEADERSPLIT_FIFO3_S 28
+#define PERR_HEADERSPLIT_FIFO3_V(x) ((x) << PERR_HEADERSPLIT_FIFO3_S)
+#define PERR_HEADERSPLIT_FIFO3_F PERR_HEADERSPLIT_FIFO3_V(1U)
+
+#define PERR_HEADERSPLIT_FIFO2_S 27
+#define PERR_HEADERSPLIT_FIFO2_V(x) ((x) << PERR_HEADERSPLIT_FIFO2_S)
+#define PERR_HEADERSPLIT_FIFO2_F PERR_HEADERSPLIT_FIFO2_V(1U)
+
+#define PERR_PAYLOAD_FIFO3_S 26
+#define PERR_PAYLOAD_FIFO3_V(x) ((x) << PERR_PAYLOAD_FIFO3_S)
+#define PERR_PAYLOAD_FIFO3_F PERR_PAYLOAD_FIFO3_V(1U)
+
+#define PERR_PAYLOAD_FIFO2_S 25
+#define PERR_PAYLOAD_FIFO2_V(x) ((x) << PERR_PAYLOAD_FIFO2_S)
+#define PERR_PAYLOAD_FIFO2_F PERR_PAYLOAD_FIFO2_V(1U)
+
+#define SGE_INT_ENABLE2_A 0x1034
#define SGE_INT_CAUSE2_A 0x1030
+
+#define PERR_HINT_DELAY_FIFO1_S 30
+#define PERR_HINT_DELAY_FIFO1_V(x) ((x) << PERR_HINT_DELAY_FIFO1_S)
+#define PERR_HINT_DELAY_FIFO1_F PERR_HINT_DELAY_FIFO1_V(1U)
+
+#define PERR_HINT_DELAY_FIFO0_S 29
+#define PERR_HINT_DELAY_FIFO0_V(x) ((x) << PERR_HINT_DELAY_FIFO0_S)
+#define PERR_HINT_DELAY_FIFO0_F PERR_HINT_DELAY_FIFO0_V(1U)
+
+#define PERR_IMSG_PD_FIFO_S 28
+#define PERR_IMSG_PD_FIFO_V(x) ((x) << PERR_IMSG_PD_FIFO_S)
+#define PERR_IMSG_PD_FIFO_F PERR_IMSG_PD_FIFO_V(1U)
+
+#define PERR_ULPTX_FIFO1_S 27
+#define PERR_ULPTX_FIFO1_V(x) ((x) << PERR_ULPTX_FIFO1_S)
+#define PERR_ULPTX_FIFO1_F PERR_ULPTX_FIFO1_V(1U)
+
+#define PERR_ULPTX_FIFO0_S 26
+#define PERR_ULPTX_FIFO0_V(x) ((x) << PERR_ULPTX_FIFO0_S)
+#define PERR_ULPTX_FIFO0_F PERR_ULPTX_FIFO0_V(1U)
+
+#define PERR_IDMA2IMSG_FIFO1_S 25
+#define PERR_IDMA2IMSG_FIFO1_V(x) ((x) << PERR_IDMA2IMSG_FIFO1_S)
+#define PERR_IDMA2IMSG_FIFO1_F PERR_IDMA2IMSG_FIFO1_V(1U)
+
+#define PERR_IDMA2IMSG_FIFO0_S 24
+#define PERR_IDMA2IMSG_FIFO0_V(x) ((x) << PERR_IDMA2IMSG_FIFO0_S)
+#define PERR_IDMA2IMSG_FIFO0_F PERR_IDMA2IMSG_FIFO0_V(1U)
+
+#define PERR_HEADERSPLIT_FIFO1_S 23
+#define PERR_HEADERSPLIT_FIFO1_V(x) ((x) << PERR_HEADERSPLIT_FIFO1_S)
+#define PERR_HEADERSPLIT_FIFO1_F PERR_HEADERSPLIT_FIFO1_V(1U)
+
+#define PERR_HEADERSPLIT_FIFO0_S 22
+#define PERR_HEADERSPLIT_FIFO0_V(x) ((x) << PERR_HEADERSPLIT_FIFO0_S)
+#define PERR_HEADERSPLIT_FIFO0_F PERR_HEADERSPLIT_FIFO0_V(1U)
+
+#define PERR_CONM_SRAM_S 14
+#define PERR_CONM_SRAM_V(x) ((x) << PERR_CONM_SRAM_S)
+#define PERR_CONM_SRAM_F PERR_CONM_SRAM_V(1U)
+
+#define PERR_ISW_IDMA0_FIFO_S 12
+#define PERR_ISW_IDMA0_FIFO_V(x) ((x) << PERR_ISW_IDMA0_FIFO_S)
+#define PERR_ISW_IDMA0_FIFO_F PERR_ISW_IDMA0_FIFO_V(1U)
+
+#define PERR_ISW_IDMA1_FIFO_S 11
+#define PERR_ISW_IDMA1_FIFO_V(x) ((x) << PERR_ISW_IDMA1_FIFO_S)
+#define PERR_ISW_IDMA1_FIFO_F PERR_ISW_IDMA1_FIFO_V(1U)
+
+#define PERR_ISW_DBP_FIFO_S 10
+#define PERR_ISW_DBP_FIFO_V(x) ((x) << PERR_ISW_DBP_FIFO_S)
+#define PERR_ISW_DBP_FIFO_F PERR_ISW_DBP_FIFO_V(1U)
+
+#define PERR_ISW_GTS_FIFO_S 9
+#define PERR_ISW_GTS_FIFO_V(x) ((x) << PERR_ISW_GTS_FIFO_S)
+#define PERR_ISW_GTS_FIFO_F PERR_ISW_GTS_FIFO_V(1U)
+
+#define PERR_ITP_EVR_S 8
+#define PERR_ITP_EVR_V(x) ((x) << PERR_ITP_EVR_S)
+#define PERR_ITP_EVR_F PERR_ITP_EVR_V(1U)
+
+#define PERR_FLM_CNTXMEM_S 7
+#define PERR_FLM_CNTXMEM_V(x) ((x) << PERR_FLM_CNTXMEM_S)
+#define PERR_FLM_CNTXMEM_F PERR_FLM_CNTXMEM_V(1U)
+
+#define PERR_FLM_L1CACHE_S 6
+#define PERR_FLM_L1CACHE_V(x) ((x) << PERR_FLM_L1CACHE_S)
+#define PERR_FLM_L1CACHE_F PERR_FLM_L1CACHE_V(1U)
+
+#define PERR_DBP_HINT_FIFO_S 5
+#define PERR_DBP_HINT_FIFO_V(x) ((x) << PERR_DBP_HINT_FIFO_S)
+#define PERR_DBP_HINT_FIFO_F PERR_DBP_HINT_FIFO_V(1U)
+
+#define PERR_DBP_HP_FIFO_S 4
+#define PERR_DBP_HP_FIFO_V(x) ((x) << PERR_DBP_HP_FIFO_S)
+#define PERR_DBP_HP_FIFO_F PERR_DBP_HP_FIFO_V(1U)
+
+#define PERR_ING_CTXT_CACHE_S 2
+#define PERR_ING_CTXT_CACHE_V(x) ((x) << PERR_ING_CTXT_CACHE_S)
+#define PERR_ING_CTXT_CACHE_F PERR_ING_CTXT_CACHE_V(1U)
+
+#define PERR_EGR_CTXT_CACHE_S 1
+#define PERR_EGR_CTXT_CACHE_V(x) ((x) << PERR_EGR_CTXT_CACHE_S)
+#define PERR_EGR_CTXT_CACHE_F PERR_EGR_CTXT_CACHE_V(1U)
+
+#define PERR_BASE_SIZE_S 0
+#define PERR_BASE_SIZE_V(x) ((x) << PERR_BASE_SIZE_S)
+#define PERR_BASE_SIZE_F PERR_BASE_SIZE_V(1U)
+
+#define PERR_DBP_HINT_FL_FIFO_S 24
+#define PERR_DBP_HINT_FL_FIFO_V(x) ((x) << PERR_DBP_HINT_FL_FIFO_S)
+#define PERR_DBP_HINT_FL_FIFO_F PERR_DBP_HINT_FL_FIFO_V(1U)
+
+#define PERR_EGR_DBP_TX_COAL_S 23
+#define PERR_EGR_DBP_TX_COAL_V(x) ((x) << PERR_EGR_DBP_TX_COAL_S)
+#define PERR_EGR_DBP_TX_COAL_F PERR_EGR_DBP_TX_COAL_V(1U)
+
+#define PERR_DBP_FL_FIFO_S 22
+#define PERR_DBP_FL_FIFO_V(x) ((x) << PERR_DBP_FL_FIFO_S)
+#define PERR_DBP_FL_FIFO_F PERR_DBP_FL_FIFO_V(1U)
+
+#define DEQ_LL_PERR_S 21
+#define DEQ_LL_PERR_V(x) ((x) << DEQ_LL_PERR_S)
+#define DEQ_LL_PERR_F DEQ_LL_PERR_V(1U)
+
+#define ENQ_PERR_S 20
+#define ENQ_PERR_V(x) ((x) << ENQ_PERR_S)
+#define ENQ_PERR_F ENQ_PERR_V(1U)
+
+#define DEQ_OUT_PERR_S 19
+#define DEQ_OUT_PERR_V(x) ((x) << DEQ_OUT_PERR_S)
+#define DEQ_OUT_PERR_F DEQ_OUT_PERR_V(1U)
+
+#define BUF_PERR_S 18
+#define BUF_PERR_V(x) ((x) << BUF_PERR_S)
+#define BUF_PERR_F BUF_PERR_V(1U)
+
+#define PERR_DB_FIFO_S 3
+#define PERR_DB_FIFO_V(x) ((x) << PERR_DB_FIFO_S)
+#define PERR_DB_FIFO_F PERR_DB_FIFO_V(1U)
+
+#define TF_FIFO_PERR_S 24
+#define TF_FIFO_PERR_V(x) ((x) << TF_FIFO_PERR_S)
+#define TF_FIFO_PERR_F TF_FIFO_PERR_V(1U)
+
+#define PERR_ISW_IDMA3_FIFO_S 15
+#define PERR_ISW_IDMA3_FIFO_V(x) ((x) << PERR_ISW_IDMA3_FIFO_S)
+#define PERR_ISW_IDMA3_FIFO_F PERR_ISW_IDMA3_FIFO_V(1U)
+
+#define PERR_ISW_IDMA2_FIFO_S 13
+#define PERR_ISW_IDMA2_FIFO_V(x) ((x) << PERR_ISW_IDMA2_FIFO_S)
+#define PERR_ISW_IDMA2_FIFO_F PERR_ISW_IDMA2_FIFO_V(1U)
+
+#define SGE_IPP_FIFO_PERR_S 5
+#define SGE_IPP_FIFO_PERR_V(x) ((x) << SGE_IPP_FIFO_PERR_S)
+#define SGE_IPP_FIFO_PERR_F SGE_IPP_FIFO_PERR_V(1U)
+
#define SGE_INT_CAUSE3_A 0x103c
#define ERR_FLM_DBP_S 31
@@ -329,6 +528,505 @@
#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)
+#define SGE_INT_ENABLE4_A 0x10e0
+#define SGE_INT_CAUSE4_A 0x10dc
+
+#define ERR_BAD_UPFL_INC_CREDIT3_S 8
+#define ERR_BAD_UPFL_INC_CREDIT3_V(x) ((x) << ERR_BAD_UPFL_INC_CREDIT3_S)
+#define ERR_BAD_UPFL_INC_CREDIT3_F ERR_BAD_UPFL_INC_CREDIT3_V(1U)
+
+#define ERR_BAD_UPFL_INC_CREDIT2_S 7
+#define ERR_BAD_UPFL_INC_CREDIT2_V(x) ((x) << ERR_BAD_UPFL_INC_CREDIT2_S)
+#define ERR_BAD_UPFL_INC_CREDIT2_F ERR_BAD_UPFL_INC_CREDIT2_V(1U)
+
+#define ERR_BAD_UPFL_INC_CREDIT1_S 6
+#define ERR_BAD_UPFL_INC_CREDIT1_V(x) ((x) << ERR_BAD_UPFL_INC_CREDIT1_S)
+#define ERR_BAD_UPFL_INC_CREDIT1_F ERR_BAD_UPFL_INC_CREDIT1_V(1U)
+
+#define ERR_BAD_UPFL_INC_CREDIT0_S 5
+#define ERR_BAD_UPFL_INC_CREDIT0_V(x) ((x) << ERR_BAD_UPFL_INC_CREDIT0_S)
+#define ERR_BAD_UPFL_INC_CREDIT0_F ERR_BAD_UPFL_INC_CREDIT0_V(1U)
+
+#define ERR_PHYSADDR_LEN0_IDMA1_S 4
+#define ERR_PHYSADDR_LEN0_IDMA1_V(x) ((x) << ERR_PHYSADDR_LEN0_IDMA1_S)
+#define ERR_PHYSADDR_LEN0_IDMA1_F ERR_PHYSADDR_LEN0_IDMA1_V(1U)
+
+#define ERR_PHYSADDR_LEN0_IDMA0_S 3
+#define ERR_PHYSADDR_LEN0_IDMA0_V(x) ((x) << ERR_PHYSADDR_LEN0_IDMA0_S)
+#define ERR_PHYSADDR_LEN0_IDMA0_F ERR_PHYSADDR_LEN0_IDMA0_V(1U)
+
+#define ERR_FLM_INVALID_PKT_DROP1_S 2
+#define ERR_FLM_INVALID_PKT_DROP1_V(x) ((x) << ERR_FLM_INVALID_PKT_DROP1_S)
+#define ERR_FLM_INVALID_PKT_DROP1_F ERR_FLM_INVALID_PKT_DROP1_V(1U)
+
+#define ERR_FLM_INVALID_PKT_DROP0_S 1
+#define ERR_FLM_INVALID_PKT_DROP0_V(x) ((x) << ERR_FLM_INVALID_PKT_DROP0_S)
+#define ERR_FLM_INVALID_PKT_DROP0_F ERR_FLM_INVALID_PKT_DROP0_V(1U)
+
+#define ERR_UNEXPECTED_TIMER_S 0
+#define ERR_UNEXPECTED_TIMER_V(x) ((x) << ERR_UNEXPECTED_TIMER_S)
+#define ERR_UNEXPECTED_TIMER_F ERR_UNEXPECTED_TIMER_V(1U)
+
+#define BAR2_EGRESS_LEN_OR_ADDR_ERR_S 29
+#define BAR2_EGRESS_LEN_OR_ADDR_ERR_V(x) ((x) << BAR2_EGRESS_LEN_OR_ADDR_ERR_S)
+#define BAR2_EGRESS_LEN_OR_ADDR_ERR_F BAR2_EGRESS_LEN_OR_ADDR_ERR_V(1U)
+
+#define ERR_CPL_EXCEED_MAX_IQE_SIZE1_S 28
+#define ERR_CPL_EXCEED_MAX_IQE_SIZE1_V(x) ((x) << ERR_CPL_EXCEED_MAX_IQE_SIZE1_S)
+#define ERR_CPL_EXCEED_MAX_IQE_SIZE1_F ERR_CPL_EXCEED_MAX_IQE_SIZE1_V(1U)
+
+#define ERR_CPL_EXCEED_MAX_IQE_SIZE0_S 27
+#define ERR_CPL_EXCEED_MAX_IQE_SIZE0_V(x) ((x) << ERR_CPL_EXCEED_MAX_IQE_SIZE0_S)
+#define ERR_CPL_EXCEED_MAX_IQE_SIZE0_F ERR_CPL_EXCEED_MAX_IQE_SIZE0_V(1U)
+
+#define ERR_WR_LEN_TOO_LARGE3_S 26
+#define ERR_WR_LEN_TOO_LARGE3_V(x) ((x) << ERR_WR_LEN_TOO_LARGE3_S)
+#define ERR_WR_LEN_TOO_LARGE3_F ERR_WR_LEN_TOO_LARGE3_V(1U)
+
+#define ERR_WR_LEN_TOO_LARGE2_S 25
+#define ERR_WR_LEN_TOO_LARGE2_V(x) ((x) << ERR_WR_LEN_TOO_LARGE2_S)
+#define ERR_WR_LEN_TOO_LARGE2_F ERR_WR_LEN_TOO_LARGE2_V(1U)
+
+#define ERR_WR_LEN_TOO_LARGE1_S 24
+#define ERR_WR_LEN_TOO_LARGE1_V(x) ((x) << ERR_WR_LEN_TOO_LARGE1_S)
+#define ERR_WR_LEN_TOO_LARGE1_F ERR_WR_LEN_TOO_LARGE1_V(1U)
+
+#define ERR_WR_LEN_TOO_LARGE0_S 23
+#define ERR_WR_LEN_TOO_LARGE0_V(x) ((x) << ERR_WR_LEN_TOO_LARGE0_S)
+#define ERR_WR_LEN_TOO_LARGE0_F ERR_WR_LEN_TOO_LARGE0_V(1U)
+
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL3_S 22
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL3_V(x) ((x) << ERR_LARGE_MINFETCH_WITH_TXCOAL3_S)
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL3_F ERR_LARGE_MINFETCH_WITH_TXCOAL3_V(1U)
+
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL2_S 21
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL2_V(x) ((x) << ERR_LARGE_MINFETCH_WITH_TXCOAL2_S)
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL2_F ERR_LARGE_MINFETCH_WITH_TXCOAL2_V(1U)
+
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL1_S 20
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL1_V(x) ((x) << ERR_LARGE_MINFETCH_WITH_TXCOAL1_S)
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL1_F ERR_LARGE_MINFETCH_WITH_TXCOAL1_V(1U)
+
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL0_S 19
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL0_V(x) ((x) << ERR_LARGE_MINFETCH_WITH_TXCOAL0_S)
+#define ERR_LARGE_MINFETCH_WITH_TXCOAL0_F ERR_LARGE_MINFETCH_WITH_TXCOAL0_V(1U)
+
+#define COAL_WITH_HP_DISABLE_ERR_S 18
+#define COAL_WITH_HP_DISABLE_ERR_V(x) ((x) << COAL_WITH_HP_DISABLE_ERR_S)
+#define COAL_WITH_HP_DISABLE_ERR_F COAL_WITH_HP_DISABLE_ERR_V(1U)
+
+#define BAR2_EGRESS_COAL0_ERR_S 17
+#define BAR2_EGRESS_COAL0_ERR_V(x) ((x) << BAR2_EGRESS_COAL0_ERR_S)
+#define BAR2_EGRESS_COAL0_ERR_F BAR2_EGRESS_COAL0_ERR_V(1U)
+
+#define BAR2_EGRESS_SIZE_ERR_S 16
+#define BAR2_EGRESS_SIZE_ERR_V(x) ((x) << BAR2_EGRESS_SIZE_ERR_S)
+#define BAR2_EGRESS_SIZE_ERR_F BAR2_EGRESS_SIZE_ERR_V(1U)
+
+#define FLM_PC_RSP_ERR_S 15
+#define FLM_PC_RSP_ERR_V(x) ((x) << FLM_PC_RSP_ERR_S)
+#define FLM_PC_RSP_ERR_F FLM_PC_RSP_ERR_V(1U)
+
+#define ERR_RX_CPL_PACKET_SIZE1_S 10
+#define ERR_RX_CPL_PACKET_SIZE1_V(x) ((x) << ERR_RX_CPL_PACKET_SIZE1_S)
+#define ERR_RX_CPL_PACKET_SIZE1_F ERR_RX_CPL_PACKET_SIZE1_V(1U)
+
+#define ERR_RX_CPL_PACKET_SIZE0_S 9
+#define ERR_RX_CPL_PACKET_SIZE0_V(x) ((x) << ERR_RX_CPL_PACKET_SIZE0_S)
+#define ERR_RX_CPL_PACKET_SIZE0_F ERR_RX_CPL_PACKET_SIZE0_V(1U)
+
+#define ERR_ISHIFT_UR1_S 31
+#define ERR_ISHIFT_UR1_V(x) ((x) << ERR_ISHIFT_UR1_S)
+#define ERR_ISHIFT_UR1_F ERR_ISHIFT_UR1_V(1U)
+
+#define ERR_ISHIFT_UR0_S 30
+#define ERR_ISHIFT_UR0_V(x) ((x) << ERR_ISHIFT_UR0_S)
+#define ERR_ISHIFT_UR0_F ERR_ISHIFT_UR0_V(1U)
+
+#define ERR_TH3_MAX_FETCH_S 14
+#define ERR_TH3_MAX_FETCH_V(x) ((x) << ERR_TH3_MAX_FETCH_S)
+#define ERR_TH3_MAX_FETCH_F ERR_TH3_MAX_FETCH_V(1U)
+
+#define ERR_TH2_MAX_FETCH_S 13
+#define ERR_TH2_MAX_FETCH_V(x) ((x) << ERR_TH2_MAX_FETCH_S)
+#define ERR_TH2_MAX_FETCH_F ERR_TH2_MAX_FETCH_V(1U)
+
+#define ERR_TH1_MAX_FETCH_S 12
+#define ERR_TH1_MAX_FETCH_V(x) ((x) << ERR_TH1_MAX_FETCH_S)
+#define ERR_TH1_MAX_FETCH_F ERR_TH1_MAX_FETCH_V(1U)
+
+#define ERR_TH0_MAX_FETCH_S 11
+#define ERR_TH0_MAX_FETCH_V(x) ((x) << ERR_TH0_MAX_FETCH_S)
+#define ERR_TH0_MAX_FETCH_F ERR_TH0_MAX_FETCH_V(1U)
+
+#define SGE_INT_ENABLE5_A 0x1110
+#define SGE_INT_CAUSE5_A 0x110c
+
+#define ERR_T_RXCRC_S 31
+#define ERR_T_RXCRC_V(x) ((x) << ERR_T_RXCRC_S)
+#define ERR_T_RXCRC_F ERR_T_RXCRC_V(1U)
+
+#define PERR_MC_RSPDATA_S 30
+#define PERR_MC_RSPDATA_V(x) ((x) << PERR_MC_RSPDATA_S)
+#define PERR_MC_RSPDATA_F PERR_MC_RSPDATA_V(1U)
+
+#define PERR_PC_RSPDATA_S 29
+#define PERR_PC_RSPDATA_V(x) ((x) << PERR_PC_RSPDATA_S)
+#define PERR_PC_RSPDATA_F PERR_PC_RSPDATA_V(1U)
+
+#define PERR_PD_RDRSPDATA_S 28
+#define PERR_PD_RDRSPDATA_V(x) ((x) << PERR_PD_RDRSPDATA_S)
+#define PERR_PD_RDRSPDATA_F PERR_PD_RDRSPDATA_V(1U)
+
+#define PERR_U_RXDATA_S 27
+#define PERR_U_RXDATA_V(x) ((x) << PERR_U_RXDATA_S)
+#define PERR_U_RXDATA_F PERR_U_RXDATA_V(1U)
+
+#define PERR_UD_RXDATA_S 26
+#define PERR_UD_RXDATA_V(x) ((x) << PERR_UD_RXDATA_S)
+#define PERR_UD_RXDATA_F PERR_UD_RXDATA_V(1U)
+
+#define PERR_UP_DATA_S 25
+#define PERR_UP_DATA_V(x) ((x) << PERR_UP_DATA_S)
+#define PERR_UP_DATA_F PERR_UP_DATA_V(1U)
+
+#define PERR_CIM2SGE_RXDATA_S 24
+#define PERR_CIM2SGE_RXDATA_V(x) ((x) << PERR_CIM2SGE_RXDATA_S)
+#define PERR_CIM2SGE_RXDATA_F PERR_CIM2SGE_RXDATA_V(1U)
+
+#define PERR_POINTER_DATA_FIFO0_S 16
+#define PERR_POINTER_DATA_FIFO0_V(x) ((x) << PERR_POINTER_DATA_FIFO0_S)
+#define PERR_POINTER_DATA_FIFO0_F PERR_POINTER_DATA_FIFO0_V(1U)
+
+#define PERR_POINTER_DATA_FIFO1_S 15
+#define PERR_POINTER_DATA_FIFO1_V(x) ((x) << PERR_POINTER_DATA_FIFO1_S)
+#define PERR_POINTER_DATA_FIFO1_F PERR_POINTER_DATA_FIFO1_V(1U)
+
+#define PERR_POINTER_HDR_FIFO0_S 14
+#define PERR_POINTER_HDR_FIFO0_V(x) ((x) << PERR_POINTER_HDR_FIFO0_S)
+#define PERR_POINTER_HDR_FIFO0_F PERR_POINTER_HDR_FIFO0_V(1U)
+
+#define PERR_POINTER_HDR_FIFO1_S 13
+#define PERR_POINTER_HDR_FIFO1_V(x) ((x) << PERR_POINTER_HDR_FIFO1_S)
+#define PERR_POINTER_HDR_FIFO1_F PERR_POINTER_HDR_FIFO1_V(1U)
+
+#define PERR_PAYLOAD_FIFO0_S 12
+#define PERR_PAYLOAD_FIFO0_V(x) ((x) << PERR_PAYLOAD_FIFO0_S)
+#define PERR_PAYLOAD_FIFO0_F PERR_PAYLOAD_FIFO0_V(1U)
+
+#define PERR_PAYLOAD_FIFO1_S 11
+#define PERR_PAYLOAD_FIFO1_V(x) ((x) << PERR_PAYLOAD_FIFO1_S)
+#define PERR_PAYLOAD_FIFO1_F PERR_PAYLOAD_FIFO1_V(1U)
+
+#define PERR_EDMA_INPUT_FIFO3_S 10
+#define PERR_EDMA_INPUT_FIFO3_V(x) ((x) << PERR_EDMA_INPUT_FIFO3_S)
+#define PERR_EDMA_INPUT_FIFO3_F PERR_EDMA_INPUT_FIFO3_V(1U)
+
+#define PERR_EDMA_INPUT_FIFO2_S 9
+#define PERR_EDMA_INPUT_FIFO2_V(x) ((x) << PERR_EDMA_INPUT_FIFO2_S)
+#define PERR_EDMA_INPUT_FIFO2_F PERR_EDMA_INPUT_FIFO2_V(1U)
+
+#define PERR_EDMA_INPUT_FIFO1_S 8
+#define PERR_EDMA_INPUT_FIFO1_V(x) ((x) << PERR_EDMA_INPUT_FIFO1_S)
+#define PERR_EDMA_INPUT_FIFO1_F PERR_EDMA_INPUT_FIFO1_V(1U)
+
+#define PERR_EDMA_INPUT_FIFO0_S 7
+#define PERR_EDMA_INPUT_FIFO0_V(x) ((x) << PERR_EDMA_INPUT_FIFO0_S)
+#define PERR_EDMA_INPUT_FIFO0_F PERR_EDMA_INPUT_FIFO0_V(1U)
+
+#define PERR_MGT_BAR2_FIFO_S 6
+#define PERR_MGT_BAR2_FIFO_V(x) ((x) << PERR_MGT_BAR2_FIFO_S)
+#define PERR_MGT_BAR2_FIFO_F PERR_MGT_BAR2_FIFO_V(1U)
+
+#define PERR_CIM_FIFO1_S 3
+#define PERR_CIM_FIFO1_V(x) ((x) << PERR_CIM_FIFO1_S)
+#define PERR_CIM_FIFO1_F PERR_CIM_FIFO1_V(1U)
+
+#define PERR_CIM_FIFO0_S 2
+#define PERR_CIM_FIFO0_V(x) ((x) << PERR_CIM_FIFO0_S)
+#define PERR_CIM_FIFO0_F PERR_CIM_FIFO0_V(1U)
+
+#define PERR_IDMA_SWITCH_OUTPUT_FIFO1_S 1
+#define PERR_IDMA_SWITCH_OUTPUT_FIFO1_V(x) ((x) << PERR_IDMA_SWITCH_OUTPUT_FIFO1_S)
+#define PERR_IDMA_SWITCH_OUTPUT_FIFO1_F PERR_IDMA_SWITCH_OUTPUT_FIFO1_V(1U)
+
+#define PERR_IDMA_SWITCH_OUTPUT_FIFO0_S 0
+#define PERR_IDMA_SWITCH_OUTPUT_FIFO0_V(x) ((x) << PERR_IDMA_SWITCH_OUTPUT_FIFO0_S)
+#define PERR_IDMA_SWITCH_OUTPUT_FIFO0_F PERR_IDMA_SWITCH_OUTPUT_FIFO0_V(1U)
+
+#define PERR_POINTER_HDR_FIFO3_S 10
+#define PERR_POINTER_HDR_FIFO3_V(x) ((x) << PERR_POINTER_HDR_FIFO3_S)
+#define PERR_POINTER_HDR_FIFO3_F PERR_POINTER_HDR_FIFO3_V(1U)
+
+#define PERR_POINTER_HDR_FIFO2_S 9
+#define PERR_POINTER_HDR_FIFO2_V(x) ((x) << PERR_POINTER_HDR_FIFO2_S)
+#define PERR_POINTER_HDR_FIFO2_F PERR_POINTER_HDR_FIFO2_V(1U)
+
+#define PERR_POINTER_DATA_FIFO3_S 8
+#define PERR_POINTER_DATA_FIFO3_V(x) ((x) << PERR_POINTER_DATA_FIFO3_S)
+#define PERR_POINTER_DATA_FIFO3_F PERR_POINTER_DATA_FIFO3_V(1U)
+
+#define PERR_POINTER_DATA_FIFO2_S 7
+#define PERR_POINTER_DATA_FIFO2_V(x) ((x) << PERR_POINTER_DATA_FIFO2_S)
+#define PERR_POINTER_DATA_FIFO2_F PERR_POINTER_DATA_FIFO2_V(1U)
+
+#define PERR_IDMA2IMSG_FIFO3_S 3
+#define PERR_IDMA2IMSG_FIFO3_V(x) ((x) << PERR_IDMA2IMSG_FIFO3_S)
+#define PERR_IDMA2IMSG_FIFO3_F PERR_IDMA2IMSG_FIFO3_V(1U)
+
+#define PERR_IDMA2IMSG_FIFO2_S 2
+#define PERR_IDMA2IMSG_FIFO2_V(x) ((x) << PERR_IDMA2IMSG_FIFO2_S)
+#define PERR_IDMA2IMSG_FIFO2_F PERR_IDMA2IMSG_FIFO2_V(1U)
+
+#define PERR_HINT_DELAY_FIFO_S 0
+#define PERR_HINT_DELAY_FIFO_V(x) ((x) << PERR_HINT_DELAY_FIFO_S)
+#define PERR_HINT_DELAY_FIFO_F PERR_HINT_DELAY_FIFO_V(1U)
+
+#define SGE_INT_ENABLE6_A 0x112c
+#define SGE_INT_CAUSE6_A 0x1128
+
+#define FATAL_TAG_MISMATCH_S 13
+#define FATAL_TAG_MISMATCH_V(x) ((x) << FATAL_TAG_MISMATCH_S)
+#define FATAL_TAG_MISMATCH_F FATAL_TAG_MISMATCH_V(1U)
+
+#define FATAL_ENQ_CTL_RDY_S 12
+#define FATAL_ENQ_CTL_RDY_V(x) ((x) << FATAL_ENQ_CTL_RDY_S)
+#define FATAL_ENQ_CTL_RDY_F FATAL_ENQ_CTL_RDY_V(1U)
+
+#define ERR_DB_SYNC_S 21
+#define ERR_DB_SYNC_V(x) ((x) << ERR_DB_SYNC_S)
+#define ERR_DB_SYNC_F ERR_DB_SYNC_V(1U)
+
+#define ERR_GTS_SYNC_S 20
+#define ERR_GTS_SYNC_V(x) ((x) << ERR_GTS_SYNC_S)
+#define ERR_GTS_SYNC_F ERR_GTS_SYNC_V(1U)
+
+#define FATAL_LARGE_COAL_S 19
+#define FATAL_LARGE_COAL_V(x) ((x) << FATAL_LARGE_COAL_S)
+#define FATAL_LARGE_COAL_F FATAL_LARGE_COAL_V(1U)
+
+#define PL_BAR2_FRM_ERR_S 18
+#define PL_BAR2_FRM_ERR_V(x) ((x) << PL_BAR2_FRM_ERR_S)
+#define PL_BAR2_FRM_ERR_F PL_BAR2_FRM_ERR_V(1U)
+
+#define SILENT_DROP_TX_COAL_S 17
+#define SILENT_DROP_TX_COAL_V(x) ((x) << SILENT_DROP_TX_COAL_S)
+#define SILENT_DROP_TX_COAL_F SILENT_DROP_TX_COAL_V(1U)
+
+#define ERR_INV_CTXT4_S 16
+#define ERR_INV_CTXT4_V(x) ((x) << ERR_INV_CTXT4_S)
+#define ERR_INV_CTXT4_F ERR_INV_CTXT4_V(1U)
+
+#define ERR_BAD_DB_PIDX4_S 15
+#define ERR_BAD_DB_PIDX4_V(x) ((x) << ERR_BAD_DB_PIDX4_S)
+#define ERR_BAD_DB_PIDX4_F ERR_BAD_DB_PIDX4_V(1U)
+
+#define ERR_BAD_UPFL_INC_CREDIT4_S 14
+#define ERR_BAD_UPFL_INC_CREDIT4_V(x) ((x) << ERR_BAD_UPFL_INC_CREDIT4_S)
+#define ERR_BAD_UPFL_INC_CREDIT4_F ERR_BAD_UPFL_INC_CREDIT4_V(1U)
+
+#define ERR_PC_RSP_LEN3_S 11
+#define ERR_PC_RSP_LEN3_V(x) ((x) << ERR_PC_RSP_LEN3_S)
+#define ERR_PC_RSP_LEN3_F ERR_PC_RSP_LEN3_V(1U)
+
+#define ERR_PC_RSP_LEN2_S 10
+#define ERR_PC_RSP_LEN2_V(x) ((x) << ERR_PC_RSP_LEN2_S)
+#define ERR_PC_RSP_LEN2_F ERR_PC_RSP_LEN2_V(1U)
+
+#define ERR_PC_RSP_LEN1_S 9
+#define ERR_PC_RSP_LEN1_V(x) ((x) << ERR_PC_RSP_LEN1_S)
+#define ERR_PC_RSP_LEN1_F ERR_PC_RSP_LEN1_V(1U)
+
+#define ERR_PC_RSP_LEN0_S 8
+#define ERR_PC_RSP_LEN0_V(x) ((x) << ERR_PC_RSP_LEN0_S)
+#define ERR_PC_RSP_LEN0_F ERR_PC_RSP_LEN0_V(1U)
+
+#define FATAL_ENQ2LL_VLD_S 7
+#define FATAL_ENQ2LL_VLD_V(x) ((x) << FATAL_ENQ2LL_VLD_S)
+#define FATAL_ENQ2LL_VLD_F FATAL_ENQ2LL_VLD_V(1U)
+
+#define FATAL_LL_EMPTY_S 6
+#define FATAL_LL_EMPTY_V(x) ((x) << FATAL_LL_EMPTY_S)
+#define FATAL_LL_EMPTY_F FATAL_LL_EMPTY_V(1U)
+
+#define FATAL_OFF_WDENQ_S 5
+#define FATAL_OFF_WDENQ_V(x) ((x) << FATAL_OFF_WDENQ_S)
+#define FATAL_OFF_WDENQ_F FATAL_OFF_WDENQ_V(1U)
+
+#define FATAL_DEQ_S 0
+#define FATAL_DEQ_V(x) ((x) << FATAL_DEQ_S)
+#define FATAL_DEQ_F FATAL_DEQ_V(1U)
+
+#define IMSG_DBG3_STUCK_S 25
+#define IMSG_DBG3_STUCK_V(x) ((x) << IMSG_DBG3_STUCK_S)
+#define IMSG_DBG3_STUCK_F IMSG_DBG3_STUCK_V(1U)
+
+#define IMSG_DBG2_STUCK_S 24
+#define IMSG_DBG2_STUCK_V(x) ((x) << IMSG_DBG2_STUCK_S)
+#define IMSG_DBG2_STUCK_F IMSG_DBG2_STUCK_V(1U)
+
+#define IMSG_DBG1_STUCK_S 23
+#define IMSG_DBG1_STUCK_V(x) ((x) << IMSG_DBG1_STUCK_S)
+#define IMSG_DBG1_STUCK_F IMSG_DBG1_STUCK_V(1U)
+
+#define IMSG_DBG0_STUCK_S 22
+#define IMSG_DBG0_STUCK_V(x) ((x) << IMSG_DBG0_STUCK_S)
+#define IMSG_DBG0_STUCK_F IMSG_DBG0_STUCK_V(1U)
+
+#define SGE_INT_ENABLE7_A 0x1364
+#define SGE_INT_CAUSE7_A 0x1360
+
+#define HINT_FIFO_FULL_S 25
+#define HINT_FIFO_FULL_V(x) ((x) << HINT_FIFO_FULL_S)
+#define HINT_FIFO_FULL_F HINT_FIFO_FULL_V(1U)
+
+#define CERR_HINT_DELAY_FIFO_S 24
+#define CERR_HINT_DELAY_FIFO_V(x) ((x) << CERR_HINT_DELAY_FIFO_S)
+#define CERR_HINT_DELAY_FIFO_F CERR_HINT_DELAY_FIFO_V(1U)
+
+#define COAL_TIMER_FIFO_PERR_S 23
+#define COAL_TIMER_FIFO_PERR_V(x) ((x) << COAL_TIMER_FIFO_PERR_S)
+#define COAL_TIMER_FIFO_PERR_F COAL_TIMER_FIFO_PERR_V(1U)
+
+#define CMP_FIFO_PERR_S 22
+#define CMP_FIFO_PERR_V(x) ((x) << CMP_FIFO_PERR_S)
+#define CMP_FIFO_PERR_F CMP_FIFO_PERR_V(1U)
+
+#define SGE_IPP_FIFO_CERR_S 21
+#define SGE_IPP_FIFO_CERR_V(x) ((x) << SGE_IPP_FIFO_CERR_S)
+#define SGE_IPP_FIFO_CERR_F SGE_IPP_FIFO_CERR_V(1U)
+
+#define CERR_ING_CTXT_CACHE_S 20
+#define CERR_ING_CTXT_CACHE_V(x) ((x) << CERR_ING_CTXT_CACHE_S)
+#define CERR_ING_CTXT_CACHE_F CERR_ING_CTXT_CACHE_V(1U)
+
+#define IMSG_CNTX_PERR_S 19
+#define IMSG_CNTX_PERR_V(x) ((x) << IMSG_CNTX_PERR_S)
+#define IMSG_CNTX_PERR_F IMSG_CNTX_PERR_V(1U)
+
+#define PD_FIFO_PERR_S 18
+#define PD_FIFO_PERR_V(x) ((x) << PD_FIFO_PERR_S)
+#define PD_FIFO_PERR_F PD_FIFO_PERR_V(1U)
+
+#define IMSG_512_FIFO_PERR_S 17
+#define IMSG_512_FIFO_PERR_V(x) ((x) << IMSG_512_FIFO_PERR_S)
+#define IMSG_512_FIFO_PERR_F IMSG_512_FIFO_PERR_V(1U)
+
+#define CPLSW_FIFO_PERR_S 16
+#define CPLSW_FIFO_PERR_V(x) ((x) << CPLSW_FIFO_PERR_S)
+#define CPLSW_FIFO_PERR_F CPLSW_FIFO_PERR_V(1U)
+
+#define IMSG_FIFO_PERR_S 15
+#define IMSG_FIFO_PERR_V(x) ((x) << IMSG_FIFO_PERR_S)
+#define IMSG_FIFO_PERR_F IMSG_FIFO_PERR_V(1U)
+
+#define CERR_ITP_EVR_S 14
+#define CERR_ITP_EVR_V(x) ((x) << CERR_ITP_EVR_S)
+#define CERR_ITP_EVR_F CERR_ITP_EVR_V(1U)
+
+#define CERR_CONM_SRAM_S 13
+#define CERR_CONM_SRAM_V(x) ((x) << CERR_CONM_SRAM_S)
+#define CERR_CONM_SRAM_F CERR_CONM_SRAM_V(1U)
+
+#define CERR_EGR_CTXT_CACHE_S 12
+#define CERR_EGR_CTXT_CACHE_V(x) ((x) << CERR_EGR_CTXT_CACHE_S)
+#define CERR_EGR_CTXT_CACHE_F CERR_EGR_CTXT_CACHE_V(1U)
+
+#define CERR_FLM_CNTXMEM_S 11
+#define CERR_FLM_CNTXMEM_V(x) ((x) << CERR_FLM_CNTXMEM_S)
+#define CERR_FLM_CNTXMEM_F CERR_FLM_CNTXMEM_V(1U)
+
+#define CERR_FUNC_QBASE_S 10
+#define CERR_FUNC_QBASE_V(x) ((x) << CERR_FUNC_QBASE_S)
+#define CERR_FUNC_QBASE_F CERR_FUNC_QBASE_V(1U)
+
+#define IMSG_CNTX_CERR_S 9
+#define IMSG_CNTX_CERR_V(x) ((x) << IMSG_CNTX_CERR_S)
+#define IMSG_CNTX_CERR_F IMSG_CNTX_CERR_V(1U)
+
+#define PD_FIFO_CERR_S 8
+#define PD_FIFO_CERR_V(x) ((x) << PD_FIFO_CERR_S)
+#define PD_FIFO_CERR_F PD_FIFO_CERR_V(1U)
+
+#define IMSG_512_FIFO_CERR_S 7
+#define IMSG_512_FIFO_CERR_V(x) ((x) << IMSG_512_FIFO_CERR_S)
+#define IMSG_512_FIFO_CERR_F IMSG_512_FIFO_CERR_V(1U)
+
+#define CPLSW_FIFO_CERR_S 6
+#define CPLSW_FIFO_CERR_V(x) ((x) << CPLSW_FIFO_CERR_S)
+#define CPLSW_FIFO_CERR_F CPLSW_FIFO_CERR_V(1U)
+
+#define IMSG_FIFO_CERR_S 5
+#define IMSG_FIFO_CERR_V(x) ((x) << IMSG_FIFO_CERR_S)
+#define IMSG_FIFO_CERR_F IMSG_FIFO_CERR_V(1U)
+
+#define CERR_FLM_L1CACHE_S 0
+#define CERR_FLM_L1CACHE_V(x) ((x) << CERR_FLM_L1CACHE_S)
+#define CERR_FLM_L1CACHE_F CERR_FLM_L1CACHE_V(1U)
+
+#define SGE_INT_ENABLE8_A 0x11cc
+#define SGE_INT_CAUSE8_A 0x11c8
+
+#define TRACE_RXPERR_S 8
+#define TRACE_RXPERR_V(x) ((x) << TRACE_RXPERR_S)
+#define TRACE_RXPERR_F TRACE_RXPERR_V(1U)
+
+#define U3_RXPERR_S 7
+#define U3_RXPERR_V(x) ((x) << U3_RXPERR_S)
+#define U3_RXPERR_F U3_RXPERR_V(1U)
+
+#define U2_RXPERR_S 6
+#define U2_RXPERR_V(x) ((x) << U2_RXPERR_S)
+#define U2_RXPERR_F U2_RXPERR_V(1U)
+
+#define U1_RXPERR_S 5
+#define U1_RXPERR_V(x) ((x) << U1_RXPERR_S)
+#define U1_RXPERR_F U1_RXPERR_V(1U)
+
+#define U0_RXPERR_S 4
+#define U0_RXPERR_V(x) ((x) << U0_RXPERR_S)
+#define U0_RXPERR_F U0_RXPERR_V(1U)
+
+#define T3_RXPERR_S 3
+#define T3_RXPERR_V(x) ((x) << T3_RXPERR_S)
+#define T3_RXPERR_F T3_RXPERR_V(1U)
+
+#define T2_RXPERR_S 2
+#define T2_RXPERR_V(x) ((x) << T2_RXPERR_S)
+#define T2_RXPERR_F T2_RXPERR_V(1U)
+
+#define T1_RXPERR_S 1
+#define T1_RXPERR_V(x) ((x) << T1_RXPERR_S)
+#define T1_RXPERR_F T1_RXPERR_V(1U)
+
+#define T0_RXPERR_S 0
+#define T0_RXPERR_V(x) ((x) << T0_RXPERR_S)
+#define T0_RXPERR_F T0_RXPERR_V(1U)
+
+#define ERR_TIMER_ABOVE_MAX_QID_S 23
+#define ERR_TIMER_ABOVE_MAX_QID_V(x) ((x) << ERR_TIMER_ABOVE_MAX_QID_S)
+#define ERR_TIMER_ABOVE_MAX_QID_F ERR_TIMER_ABOVE_MAX_QID_V(1U)
+
+#define ERR_ITP_TIME_PAUSED_S 20
+#define ERR_ITP_TIME_PAUSED_V(x) ((x) << ERR_ITP_TIME_PAUSED_S)
+#define ERR_ITP_TIME_PAUSED_F ERR_ITP_TIME_PAUSED_V(1U)
+
+#define ERR_ING_PCIE_CHAN_S 11
+#define ERR_ING_PCIE_CHAN_V(x) ((x) << ERR_ING_PCIE_CHAN_S)
+#define ERR_ING_PCIE_CHAN_F ERR_ING_PCIE_CHAN_V(1U)
+
+#define REG_ADDRESS_ERR_S 6
+#define REG_ADDRESS_ERR_V(x) ((x) << REG_ADDRESS_ERR_S)
+#define REG_ADDRESS_ERR_F REG_ADDRESS_ERR_V(1U)
+
+#define DBP_TBUF_FULL_S 8
+#define DBP_TBUF_FULL_V(x) ((x) << DBP_TBUF_FULL_S)
+#define DBP_TBUF_FULL_F DBP_TBUF_FULL_V(1U)
+
+#define FATAL_WRE_LEN_S 7
+#define FATAL_WRE_LEN_V(x) ((x) << FATAL_WRE_LEN_S)
+#define FATAL_WRE_LEN_F FATAL_WRE_LEN_V(1U)
+
#define SGE_INT_ENABLE3_A 0x1040
#define SGE_FL_BUFFER_SIZE0_A 0x1044
#define SGE_FL_BUFFER_SIZE1_A 0x1048
@@ -344,10 +1042,6 @@
#define SGE_FLM_CACHE_BADDR_A 0x108c
#define SGE_FLM_CFG_A 0x1090
-#define NOHDR_S 18
-#define NOHDR_V(x) ((x) << NOHDR_S)
-#define NOHDR_F NOHDR_V(1U)
-
#define HDRSTARTFLQ_S 11
#define HDRSTARTFLQ_M 0x7U
#define HDRSTARTFLQ_G(x) (((x) >> HDRSTARTFLQ_S) & HDRSTARTFLQ_M)
@@ -378,12 +1072,10 @@
#define EGRTHRESHOLD_S 8
#define EGRTHRESHOLD_M 0x3fU
-#define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
#define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
#define EGRTHRESHOLDPACKING_S 14
#define EGRTHRESHOLDPACKING_M 0x3fU
-#define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
#define EGRTHRESHOLDPACKING_G(x) \
(((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
@@ -395,37 +1087,12 @@
#define SGE_TIMESTAMP_LO_A 0x1098
#define SGE_TIMESTAMP_HI_A 0x109c
-#define TSOP_S 28
-#define TSOP_M 0x3U
-#define TSOP_V(x) ((x) << TSOP_S)
-#define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
-
#define TSVAL_S 0
#define TSVAL_M 0xfffffffU
-#define TSVAL_V(x) ((x) << TSVAL_S)
#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
#define SGE_DBFIFO_STATUS_A 0x10a4
#define SGE_DBVFIFO_SIZE_A 0x113c
-
-#define HP_INT_THRESH_S 28
-#define HP_INT_THRESH_M 0xfU
-#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
-
-#define LP_INT_THRESH_S 12
-#define LP_INT_THRESH_M 0xfU
-#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
-
-#define SGE_DOORBELL_CONTROL_A 0x10a8
-
-#define NOCOALESCE_S 26
-#define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
-#define NOCOALESCE_F NOCOALESCE_V(1U)
-
-#define ENABLE_DROP_S 13
-#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
-#define ENABLE_DROP_F ENABLE_DROP_V(1U)
-
#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
#define TIMERVALUE0_S 16
@@ -487,24 +1154,10 @@
#define ERROR_QID_M 0x1ffffU
#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
-#define SGE_INT_CAUSE5_A 0x110c
-
-#define ERR_T_RXCRC_S 31
-#define ERR_T_RXCRC_V(x) ((x) << ERR_T_RXCRC_S)
-#define ERR_T_RXCRC_F ERR_T_RXCRC_V(1U)
-
-#define HP_INT_THRESH_S 28
-#define HP_INT_THRESH_M 0xfU
-#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
-
#define HP_COUNT_S 16
#define HP_COUNT_M 0x7ffU
#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
-#define LP_INT_THRESH_S 12
-#define LP_INT_THRESH_M 0xfU
-#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
-
#define LP_COUNT_S 0
#define LP_COUNT_M 0x7ffU
#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
@@ -537,7 +1190,6 @@
#define SGE_DBFIFO_STATUS2_A 0x1118
#define HP_INT_THRESH_T5_S 10
-#define HP_INT_THRESH_T5_M 0xfU
#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
#define HP_COUNT_T5_S 0
@@ -552,7 +1204,6 @@
#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
#define DROPPED_DB_F DROPPED_DB_V(1U)
-#define SGE_CTXT_CMD_A 0x11fc
#define SGE_DBQ_CTXT_BADDR_A 0x1084
/* registers for module PCIE */
@@ -569,8 +1220,13 @@
#define OFFSET_M 0x3fffU
#define OFFSET_G(x) (((x) >> OFFSET_S) & OFFSET_M)
+#define PCIE_INT_ENABLE_A 0x3000
#define PCIE_INT_CAUSE_A 0x3004
+#define NONFATALERR_S 30
+#define NONFATALERR_V(x) ((x) << NONFATALERR_S)
+#define NONFATALERR_F NONFATALERR_V(1U)
+
#define UNXSPLCPLERR_S 29
#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
@@ -691,6 +1347,10 @@
#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
#define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
+#define IPGRPPERR_S 31
+#define IPGRPPERR_V(x) ((x) << IPGRPPERR_S)
+#define IPGRPPERR_F IPGRPPERR_V(1U)
+
#define READRSPERR_S 29
#define READRSPERR_V(x) ((x) << READRSPERR_S)
#define READRSPERR_F READRSPERR_V(1U)
@@ -715,6 +1375,10 @@
#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
+#define PIOTAGQPERR_S 23
+#define PIOTAGQPERR_V(x) ((x) << PIOTAGQPERR_S)
+#define PIOTAGQPERR_F PIOTAGQPERR_V(1U)
+
#define MAGRPPERR_S 22
#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
#define MAGRPPERR_F MAGRPPERR_V(1U)
@@ -723,10 +1387,18 @@
#define VFIDPERR_V(x) ((x) << VFIDPERR_S)
#define VFIDPERR_F VFIDPERR_V(1U)
+#define HREQRDPERR_S 17
+#define HREQRDPERR_V(x) ((x) << HREQRDPERR_S)
+#define HREQRDPERR_F HREQRDPERR_V(1U)
+
#define HREQWRPERR_S 16
#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
#define HREQWRPERR_F HREQWRPERR_V(1U)
+#define DREQRDPERR_S 14
+#define DREQRDPERR_V(x) ((x) << DREQRDPERR_S)
+#define DREQRDPERR_F DREQRDPERR_V(1U)
+
#define DREQWRPERR_S 13
#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
#define DREQWRPERR_F DREQWRPERR_V(1U)
@@ -739,6 +1411,10 @@
#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
#define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
+#define TGTTAGQPERR_S 9
+#define TGTTAGQPERR_V(x) ((x) << TGTTAGQPERR_S)
+#define TGTTAGQPERR_F TGTTAGQPERR_V(1U)
+
#define PIOREQGRPPERR_S 8
#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
@@ -759,8 +1435,154 @@
#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
#define MSTGRPPERR_F MSTGRPPERR_V(1U)
-#define PCIE_NONFAT_ERR_A 0x3010
+#define PCIE_INT_ENABLE_EXT_A 0x3030
+#define PCIE_INT_ENABLE_X8_A 0x3034
+#define PCIE_INT_CAUSE_EXT_A 0x3038
+
+#define IPFORMQPERR_S 30
+#define IPFORMQPERR_V(x) ((x) << IPFORMQPERR_S)
+#define IPFORMQPERR_F IPFORMQPERR_V(1U)
+
+#define IPFORMQCERR_S 29
+#define IPFORMQCERR_V(x) ((x) << IPFORMQCERR_S)
+#define IPFORMQCERR_F IPFORMQCERR_V(1U)
+
+#define TRGT1GRPCERR_S 28
+#define TRGT1GRPCERR_V(x) ((x) << TRGT1GRPCERR_S)
+#define TRGT1GRPCERR_F TRGT1GRPCERR_V(1U)
+
+#define IPSOTCERR_S 27
+#define IPSOTCERR_V(x) ((x) << IPSOTCERR_S)
+#define IPSOTCERR_F IPSOTCERR_V(1U)
+
+#define IPRETRYCERR_S 26
+#define IPRETRYCERR_V(x) ((x) << IPRETRYCERR_S)
+#define IPRETRYCERR_F IPRETRYCERR_V(1U)
+
+#define IPRXDATAGRPCERR_S 25
+#define IPRXDATAGRPCERR_V(x) ((x) << IPRXDATAGRPCERR_S)
+#define IPRXDATAGRPCERR_F IPRXDATAGRPCERR_V(1U)
+
+#define IPRXHDRGRPCERR_S 24
+#define IPRXHDRGRPCERR_V(x) ((x) << IPRXHDRGRPCERR_S)
+#define IPRXHDRGRPCERR_F IPRXHDRGRPCERR_V(1U)
+
+#define A0ARBRSPORDFIFOPERR_S 19
+#define A0ARBRSPORDFIFOPERR_V(x) ((x) << A0ARBRSPORDFIFOPERR_S)
+#define A0ARBRSPORDFIFOPERR_F A0ARBRSPORDFIFOPERR_V(1U)
+
+#define HRSPCERR_S 18
+#define HRSPCERR_V(x) ((x) << HRSPCERR_S)
+#define HRSPCERR_F HRSPCERR_V(1U)
+
+#define HREQRDCERR_S 17
+#define HREQRDCERR_V(x) ((x) << HREQRDCERR_S)
+#define HREQRDCERR_F HREQRDCERR_V(1U)
+
+#define HREQWRCERR_S 16
+#define HREQWRCERR_V(x) ((x) << HREQWRCERR_S)
+#define HREQWRCERR_F HREQWRCERR_V(1U)
+
+#define DRSPCERR_S 15
+#define DRSPCERR_V(x) ((x) << DRSPCERR_S)
+#define DRSPCERR_F DRSPCERR_V(1U)
+
+#define DREQRDCERR_S 14
+#define DREQRDCERR_V(x) ((x) << DREQRDCERR_S)
+#define DREQRDCERR_F DREQRDCERR_V(1U)
+
+#define DREQWRCERR_S 13
+#define DREQWRCERR_V(x) ((x) << DREQWRCERR_S)
+#define DREQWRCERR_F DREQWRCERR_V(1U)
+
+#define CRSPCERR_S 12
+#define CRSPCERR_V(x) ((x) << CRSPCERR_S)
+#define CRSPCERR_F CRSPCERR_V(1U)
+
+#define ARSPPERR_S 11
+#define ARSPPERR_V(x) ((x) << ARSPPERR_S)
+#define ARSPPERR_F ARSPPERR_V(1U)
+
+#define AREQRDPERR_S 10
+#define AREQRDPERR_V(x) ((x) << AREQRDPERR_S)
+#define AREQRDPERR_F AREQRDPERR_V(1U)
+
+#define AREQWRPERR_S 9
+#define AREQWRPERR_V(x) ((x) << AREQWRPERR_S)
+#define AREQWRPERR_F AREQWRPERR_V(1U)
+
+#define PIOREQGRPCERR_S 8
+#define PIOREQGRPCERR_V(x) ((x) << PIOREQGRPCERR_S)
+#define PIOREQGRPCERR_F PIOREQGRPCERR_V(1U)
+
+#define ARSPCERR_S 7
+#define ARSPCERR_V(x) ((x) << ARSPCERR_S)
+#define ARSPCERR_F ARSPCERR_V(1U)
+
+#define AREQRDCERR_S 6
+#define AREQRDCERR_V(x) ((x) << AREQRDCERR_S)
+#define AREQRDCERR_F AREQRDCERR_V(1U)
+
+#define AREQWRCERR_S 5
+#define AREQWRCERR_V(x) ((x) << AREQWRCERR_S)
+#define AREQWRCERR_F AREQWRCERR_V(1U)
+
+#define MARSPPERR_S 4
+#define MARSPPERR_V(x) ((x) << MARSPPERR_S)
+#define MARSPPERR_F MARSPPERR_V(1U)
+
+#define INICMAWDATAORDPERR_S 3
+#define INICMAWDATAORDPERR_V(x) ((x) << INICMAWDATAORDPERR_S)
+#define INICMAWDATAORDPERR_F INICMAWDATAORDPERR_V(1U)
+
+#define EMUPERR_S 2
+#define EMUPERR_V(x) ((x) << EMUPERR_S)
+#define EMUPERR_F EMUPERR_V(1U)
+
+#define ERRSPPERR_S 1
+#define ERRSPPERR_V(x) ((x) << ERRSPPERR_S)
+#define ERRSPPERR_F ERRSPPERR_V(1U)
+
+#define MSTGRPCERR_S 0
+#define MSTGRPCERR_V(x) ((x) << MSTGRPCERR_S)
+#define MSTGRPCERR_F MSTGRPCERR_V(1U)
+
+#define PCIE_INT_CAUSE_X8_A 0x303c
+
+#define X8TGTGRPPERR_S 23
+#define X8TGTGRPPERR_V(x) ((x) << X8TGTGRPPERR_S)
+#define X8TGTGRPPERR_F X8TGTGRPPERR_V(1U)
+
+#define X8IPSOTPERR_S 22
+#define X8IPSOTPERR_V(x) ((x) << X8IPSOTPERR_S)
+#define X8IPSOTPERR_F X8IPSOTPERR_V(1U)
+
+#define X8IPRETRYPERR_S 21
+#define X8IPRETRYPERR_V(x) ((x) << X8IPRETRYPERR_S)
+#define X8IPRETRYPERR_F X8IPRETRYPERR_V(1U)
+
+#define X8IPRXDATAGRPPERR_S 20
+#define X8IPRXDATAGRPPERR_V(x) ((x) << X8IPRXDATAGRPPERR_S)
+#define X8IPRXDATAGRPPERR_F X8IPRXDATAGRPPERR_V(1U)
+
+#define X8IPRXHDRGRPPERR_S 19
+#define X8IPRXHDRGRPPERR_V(x) ((x) << X8IPRXHDRGRPPERR_S)
+#define X8IPRXHDRGRPPERR_F X8IPRXHDRGRPPERR_V(1U)
+
+#define X8IPCORECERR_S 3
+#define X8IPCORECERR_V(x) ((x) << X8IPCORECERR_S)
+#define X8IPCORECERR_F X8IPCORECERR_V(1U)
+
+#define X8MSTGRPPERR_S 2
+#define X8MSTGRPPERR_V(x) ((x) << X8MSTGRPPERR_S)
+#define X8MSTGRPPERR_F X8MSTGRPPERR_V(1U)
+
+#define X8MSTGRPCERR_S 1
+#define X8MSTGRPCERR_V(x) ((x) << X8MSTGRPCERR_S)
+#define X8MSTGRPCERR_F X8MSTGRPCERR_V(1U)
+
#define PCIE_CFG_SPACE_REQ_A 0x3060
+
#define PCIE_CFG_SPACE_DATA_A 0x3064
#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
@@ -769,9 +1591,7 @@
#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
#define BIR_S 8
-#define BIR_M 0x3U
#define BIR_V(x) ((x) << BIR_S)
-#define BIR_G(x) (((x) >> BIR_S) & BIR_M)
#define WINDOW_S 0
#define WINDOW_M 0xffU
@@ -826,11 +1646,9 @@
#define RFTP_V(x) ((x) << RFTP_S)
#define RFTP_F RFTP_V(1U)
-#define PTRP_S 20
-#define PTRP_V(x) ((x) << PTRP_S)
-#define PTRP_F PTRP_V(1U)
-
+#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE_A 0x5910
#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
+#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE_A 0x59ac
#define TPCP_S 30
#define TPCP_V(x) ((x) << TPCP_S)
@@ -856,34 +1674,21 @@
#define RCAP_V(x) ((x) << RCAP_S)
#define RCAP_F RCAP_V(1U)
-#define PLUP_S 23
-#define PLUP_V(x) ((x) << PLUP_S)
-#define PLUP_F PLUP_V(1U)
-
-#define PLDN_S 22
-#define PLDN_V(x) ((x) << PLDN_S)
-#define PLDN_F PLDN_V(1U)
-
#define OTDD_S 21
#define OTDD_V(x) ((x) << OTDD_S)
#define OTDD_F OTDD_V(1U)
-#define GTRP_S 20
-#define GTRP_V(x) ((x) << GTRP_S)
-#define GTRP_F GTRP_V(1U)
-
#define RDPE_S 18
#define RDPE_V(x) ((x) << RDPE_S)
#define RDPE_F RDPE_V(1U)
-#define TDCE_S 17
-#define TDCE_V(x) ((x) << TDCE_S)
-#define TDCE_F TDCE_V(1U)
-
#define TDUE_S 16
#define TDUE_V(x) ((x) << TDUE_S)
#define TDUE_F TDUE_V(1U)
+#define PCIE_MEM_ACCESS_OFFSET0_A 0x3708
+#define T7_PCIE_MEM_ACCESS_BASE_WIN_A 0x3700
+
/* SPARE2 register contains 32-bit value at offset 0x6 in Serial INIT
* Configuration flashed on EEPROM. This value corresponds to 32-bit
* Serial Configuration Version information.
@@ -891,11 +1696,33 @@
#define PCIE_STATIC_SPARE2_A 0x5bfc
/* registers for module MC */
-#define MC_INT_CAUSE_A 0x7518
-#define MC_P_INT_CAUSE_A 0x41318
+#define MC_PAR_ENABLE_A 0x750c
+#define MC_PAR_CAUSE_A 0x7510
-#define ECC_UE_INT_CAUSE_S 2
-#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
+#define ECC_UE_PAR_CAUSE_S 3
+#define ECC_UE_PAR_CAUSE_V(x) ((x) << ECC_UE_PAR_CAUSE_S)
+#define ECC_UE_PAR_CAUSE_F ECC_UE_PAR_CAUSE_V(1U)
+
+#define ECC_CE_PAR_CAUSE_S 2
+#define ECC_CE_PAR_CAUSE_V(x) ((x) << ECC_CE_PAR_CAUSE_S)
+#define ECC_CE_PAR_CAUSE_F ECC_CE_PAR_CAUSE_V(1U)
+
+#define FIFOR_PAR_CAUSE_S 1
+#define FIFOR_PAR_CAUSE_V(x) ((x) << FIFOR_PAR_CAUSE_S)
+#define FIFOR_PAR_CAUSE_F FIFOR_PAR_CAUSE_V(1U)
+
+#define RDATA_FIFOR_PAR_CAUSE_S 0
+#define RDATA_FIFOR_PAR_CAUSE_V(x) ((x) << RDATA_FIFOR_PAR_CAUSE_S)
+#define RDATA_FIFOR_PAR_CAUSE_F RDATA_FIFOR_PAR_CAUSE_V(1U)
+
+#define MC_INT_ENABLE_A 0x7514
+#define MC_INT_CAUSE_A 0x7518
+
+#define MC_P_INT_ENABLE_A 0x41314
+#define MC_P_INT_CAUSE_A 0x41318
+
+#define ECC_UE_INT_CAUSE_S 2
+#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
#define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U)
#define ECC_CE_INT_CAUSE_S 1
@@ -912,7 +1739,6 @@
#define SIGNAL_DET_S 14
#define SIGNAL_DET_V(x) ((x) << SIGNAL_DET_S)
-#define SIGNAL_DET_F SIGNAL_DET_V(1U)
#define MC_ECC_STATUS_A 0x751c
#define MC_P_ECC_STATUS_A 0x4131c
@@ -924,11 +1750,8 @@
#define ECC_UECNT_S 0
#define ECC_UECNT_M 0xffffU
-#define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
#define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
-#define MC_BIST_CMD_A 0x7600
-
#define START_BIST_S 31
#define START_BIST_V(x) ((x) << START_BIST_S)
#define START_BIST_F START_BIST_V(1U)
@@ -939,10 +1762,6 @@
#define BIST_OPCODE_S 0
#define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
-#define MC_BIST_CMD_ADDR_A 0x7604
-#define MC_BIST_CMD_LEN_A 0x7608
-#define MC_BIST_DATA_PATTERN_A 0x760c
-
#define MC_BIST_STATUS_RDATA_A 0x7688
/* registers for module MA */
@@ -954,9 +1773,12 @@
#define EDRAM0_SIZE_S 0
#define EDRAM0_SIZE_M 0xfffU
-#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
#define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
+#define T7_EDRAM0_SIZE_S 0
+#define T7_EDRAM0_SIZE_M 0xffffU
+#define T7_EDRAM0_SIZE_G(x) (((x) >> T7_EDRAM0_SIZE_S) & T7_EDRAM0_SIZE_M)
+
#define MA_EDRAM1_BAR_A 0x77c4
#define EDRAM1_BASE_S 16
@@ -965,19 +1787,20 @@
#define EDRAM1_SIZE_S 0
#define EDRAM1_SIZE_M 0xfffU
-#define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
#define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
+#define T7_EDRAM1_SIZE_S 0
+#define T7_EDRAM1_SIZE_M 0xffffU
+#define T7_EDRAM1_SIZE_G(x) (((x) >> T7_EDRAM1_SIZE_S) & T7_EDRAM1_SIZE_M)
+
#define MA_EXT_MEMORY_BAR_A 0x77c8
#define EXT_MEM_BASE_S 16
#define EXT_MEM_BASE_M 0xfffU
-#define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S)
#define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M)
#define EXT_MEM_SIZE_S 0
#define EXT_MEM_SIZE_M 0xfffU
-#define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
#define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
#define MA_EXT_MEMORY1_BAR_A 0x7808
@@ -992,20 +1815,40 @@
#define EXT_MEM1_SIZE_S 0
#define EXT_MEM1_SIZE_M 0xfffU
-#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
-#define MA_EXT_MEMORY0_BAR_A 0x77c8
+#define T7_EXT_MEM1_SIZE_S 0
+#define T7_EXT_MEM1_SIZE_M 0xffffU
+#define T7_EXT_MEM1_SIZE_G(x) (((x) >> T7_EXT_MEM1_SIZE_S) & T7_EXT_MEM1_SIZE_M)
+
+#define T7_EXT_MEM1_BASE_S 16
+#define T7_EXT_MEM1_BASE_M 0xffffU
+#define T7_EXT_MEM1_BASE_G(x) (((x) >> T7_EXT_MEM1_BASE_S) & T7_EXT_MEM1_BASE_M)
-#define EXT_MEM0_BASE_S 16
-#define EXT_MEM0_BASE_M 0xfffU
-#define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M)
+#define MA_HOST_MEMORY_BAR_A 0x77cc
+
+#define HMATARGETBASE_S 16
+#define HMATARGETBASE_M 0xffffU
+#define HMATARGETBASE_G(x) (((x) >> HMATARGETBASE_S) & HMATARGETBASE_M)
+
+#define T7_HMA_SIZE_S 0
+#define T7_HMA_SIZE_M 0xffffU
+#define T7_HMA_SIZE_G(x) (((x) >> T7_HMA_SIZE_S) & T7_HMA_SIZE_M)
+
+#define MA_EXT_MEMORY0_BAR_A 0x77c8
#define EXT_MEM0_SIZE_S 0
#define EXT_MEM0_SIZE_M 0xfffU
-#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
+#define T7_EXT_MEM0_SIZE_S 0
+#define T7_EXT_MEM0_SIZE_M 0xffffU
+#define T7_EXT_MEM0_SIZE_G(x) (((x) >> T7_EXT_MEM0_SIZE_S) & T7_EXT_MEM0_SIZE_M)
+
+#define T7_EXT_MEM0_BASE_S 16
+#define T7_EXT_MEM0_BASE_M 0xffffU
+#define T7_EXT_MEM0_BASE_G(x) (((x) >> T7_EXT_MEM0_BASE_S) & T7_EXT_MEM0_BASE_M)
+
#define MA_TARGET_MEM_ENABLE_A 0x77d8
#define EXT_MEM_ENABLE_S 2
@@ -1028,6 +1871,11 @@
#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
+#define MC_SPLIT_S 6
+#define MC_SPLIT_V(x) ((x) << MC_SPLIT_S)
+#define MC_SPLIT_F MC_SPLIT_V(1U)
+
+#define MA_INT_ENABLE_A 0x77dc
#define MA_INT_CAUSE_A 0x77e0
#define MEM_PERR_INT_CAUSE_S 1
@@ -1038,6 +1886,10 @@
#define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
#define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U)
+#define MEM_TO_INT_CAUSE_S 2
+#define MEM_TO_INT_CAUSE_V(x) ((x) << MEM_TO_INT_CAUSE_S)
+#define MEM_TO_INT_CAUSE_F MEM_TO_INT_CAUSE_V(1U)
+
#define MA_INT_WRAP_STATUS_A 0x77e4
#define MEM_WRAP_ADDRESS_S 4
@@ -1049,36 +1901,57 @@
#define MEM_WRAP_CLIENT_NUM_G(x) \
(((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
+#define T7_TP_DMARBT_PAR_ERROR_S 1
+#define T7_TP_DMARBT_PAR_ERROR_V(x) ((x) << T7_TP_DMARBT_PAR_ERROR_S)
+#define T7_TP_DMARBT_PAR_ERROR_F T7_TP_DMARBT_PAR_ERROR_V(1U)
+
+#define T7_LOGIC_FIFO_PAR_ERROR_S 0
+#define T7_LOGIC_FIFO_PAR_ERROR_V(x) ((x) << T7_LOGIC_FIFO_PAR_ERROR_S)
+#define T7_LOGIC_FIFO_PAR_ERROR_F T7_LOGIC_FIFO_PAR_ERROR_V(1U)
+
#define MA_PARITY_ERROR_STATUS_A 0x77f4
#define MA_PARITY_ERROR_STATUS1_A 0x77f4
#define MA_PARITY_ERROR_STATUS2_A 0x7804
+#define MA_PARITY_ERROR_STATUS3_A 0x7888
+#define MA_PARITY_ERROR_ENABLE1_A 0x77f0
+#define MA_PARITY_ERROR_ENABLE2_A 0x7800
+#define MA_PARITY_ERROR_ENABLE3_A 0x7884
-/* registers for module EDC_0 */
-#define EDC_0_BASE_ADDR 0x7900
+#define TP_DMARBT_PAR_ERROR_S 31
+#define TP_DMARBT_PAR_ERROR_V(x) ((x) << TP_DMARBT_PAR_ERROR_S)
+#define TP_DMARBT_PAR_ERROR_F TP_DMARBT_PAR_ERROR_V(1U)
-#define EDC_BIST_CMD_A 0x7904
-#define EDC_BIST_CMD_ADDR_A 0x7908
-#define EDC_BIST_CMD_LEN_A 0x790c
-#define EDC_BIST_DATA_PATTERN_A 0x7910
-#define EDC_BIST_STATUS_RDATA_A 0x7928
-#define EDC_INT_CAUSE_A 0x7978
+#define LOGIC_FIFO_PAR_ERROR_S 30
+#define LOGIC_FIFO_PAR_ERROR_V(x) ((x) << LOGIC_FIFO_PAR_ERROR_S)
+#define LOGIC_FIFO_PAR_ERROR_F LOGIC_FIFO_PAR_ERROR_V(1U)
+
+#define ARB4_PAR_WRQUEUE_ERROR_S 1
+#define ARB4_PAR_WRQUEUE_ERROR_V(x) ((x) << ARB4_PAR_WRQUEUE_ERROR_S)
+#define ARB4_PAR_WRQUEUE_ERROR_F ARB4_PAR_WRQUEUE_ERROR_V(1U)
+
+#define ARB4_PAR_RDQUEUE_ERROR_S 0
+#define ARB4_PAR_RDQUEUE_ERROR_V(x) ((x) << ARB4_PAR_RDQUEUE_ERROR_S)
+#define ARB4_PAR_RDQUEUE_ERROR_F ARB4_PAR_RDQUEUE_ERROR_V(1U)
+
+#define MA_LOCAL_DEBUG_CFG_A 0x78f8
+#define MA_LOCAL_DEBUG_PERF_CFG_A 0x7914
-#define ECC_UE_PAR_S 5
-#define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
-#define ECC_UE_PAR_F ECC_UE_PAR_V(1U)
+#define MA_WRITE_TIMEOUT_ERROR_ENABLE_A 0x78d4
+#define MA_WRITE_TIMEOUT_ERROR_STATUS_A 0x78d8
+#define MA_READ_TIMEOUT_ERROR_ENABLE_A 0x78dc
+#define MA_READ_TIMEOUT_ERROR_STATUS_A 0x78e0
-#define ECC_CE_PAR_S 4
-#define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
-#define ECC_CE_PAR_F ECC_CE_PAR_V(1U)
+/* registers for module EDC_0 */
+#define EDC_0_BASE_ADDR 0x7900
-#define PERR_PAR_CAUSE_S 3
-#define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
-#define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U)
+#define EDC_BIST_STATUS_RDATA_A 0x7928
+#define EDC_INT_ENABLE_A 0x7974
+#define EDC_INT_CAUSE_A 0x7978
#define EDC_ECC_STATUS_A 0x797c
/* registers for module EDC_1 */
-#define EDC_1_BASE_ADDR 0x7980
+#define EDC_1_BASE_ADDR 0x7980
/* registers for module CIM */
#define CIM_BOOT_CFG_A 0x7b00
@@ -1088,8 +1961,6 @@
#define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
#define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
-#define BOOTADDR_M 0xffffff00U
-
#define UPCRST_S 0
#define UPCRST_V(x) ((x) << UPCRST_S)
#define UPCRST_F UPCRST_V(1U)
@@ -1097,6 +1968,125 @@
#define CIM_PF_MAILBOX_DATA_A 0x240
#define CIM_PF_MAILBOX_CTRL_A 0x280
+#define CIM_PERR_ENABLE_A 0x7c24
+#define CIM_PERR_CAUSE_A 0x7b0c
+
+#define T7_MA_CIM_INTFPERR_S 31
+#define T7_MA_CIM_INTFPERR_V(x) ((x) << T7_MA_CIM_INTFPERR_S)
+#define T7_MA_CIM_INTFPERR_F T7_MA_CIM_INTFPERR_V(1U)
+
+#define T7_MBHOSTPARERR_S 30
+#define T7_MBHOSTPARERR_V(x) ((x) << T7_MBHOSTPARERR_S)
+#define T7_MBHOSTPARERR_F T7_MBHOSTPARERR_V(1U)
+
+#define MAARBINVRSPTAG_S 29
+#define MAARBINVRSPTAG_V(x) ((x) << MAARBINVRSPTAG_S)
+#define MAARBINVRSPTAG_F MAARBINVRSPTAG_V(1U)
+
+#define MAARBFIFOPARERR_S 28
+#define MAARBFIFOPARERR_V(x) ((x) << MAARBFIFOPARERR_S)
+#define MAARBFIFOPARERR_F MAARBFIFOPARERR_V(1U)
+
+#define SEMSRAMPARERR_S 27
+#define SEMSRAMPARERR_V(x) ((x) << SEMSRAMPARERR_S)
+#define SEMSRAMPARERR_F SEMSRAMPARERR_V(1U)
+
+#define RSACPARERR_S 26
+#define RSACPARERR_V(x) ((x) << RSACPARERR_S)
+#define RSACPARERR_F RSACPARERR_V(1U)
+
+#define RSADPARERR_S 25
+#define RSADPARERR_V(x) ((x) << RSADPARERR_S)
+#define RSADPARERR_F RSADPARERR_V(1U)
+
+#define T7_PLCIM_MSTRSPDATAPARERR_S 24
+#define T7_PLCIM_MSTRSPDATAPARERR_V(x) ((x) << T7_PLCIM_MSTRSPDATAPARERR_S)
+#define T7_PLCIM_MSTRSPDATAPARERR_F T7_PLCIM_MSTRSPDATAPARERR_V(1U)
+
+#define T7_PCIE2CIMINTFPARERR_S 23
+#define T7_PCIE2CIMINTFPARERR_V(x) ((x) << T7_PCIE2CIMINTFPARERR_S)
+#define T7_PCIE2CIMINTFPARERR_F T7_PCIE2CIMINTFPARERR_V(1U)
+
+#define T7_NCSI2CIMINTFPARERR_S 22
+#define T7_NCSI2CIMINTFPARERR_V(x) ((x) << T7_NCSI2CIMINTFPARERR_S)
+#define T7_NCSI2CIMINTFPARERR_F T7_NCSI2CIMINTFPARERR_V(1U)
+
+#define T7_SGE2CIMINTFPARERR_S 21
+#define T7_SGE2CIMINTFPARERR_V(x) ((x) << T7_SGE2CIMINTFPARERR_S)
+#define T7_SGE2CIMINTFPARERR_F T7_SGE2CIMINTFPARERR_V(1U)
+
+#define T7_ULP2CIMINTFPARERR_S 20
+#define T7_ULP2CIMINTFPARERR_V(x) ((x) << T7_ULP2CIMINTFPARERR_S)
+#define T7_ULP2CIMINTFPARERR_F T7_ULP2CIMINTFPARERR_V(1U)
+
+#define T7_TP2CIMINTFPARERR_S 19
+#define T7_TP2CIMINTFPARERR_V(x) ((x) << T7_TP2CIMINTFPARERR_S)
+#define T7_TP2CIMINTFPARERR_F T7_TP2CIMINTFPARERR_V(1U)
+
+#define CORE7PARERR_S 18
+#define CORE7PARERR_V(x) ((x) << CORE7PARERR_S)
+#define CORE7PARERR_F CORE7PARERR_V(1U)
+
+#define CORE6PARERR_S 17
+#define CORE6PARERR_V(x) ((x) << CORE6PARERR_S)
+#define CORE6PARERR_F CORE6PARERR_V(1U)
+
+#define CORE5PARERR_S 16
+#define CORE5PARERR_V(x) ((x) << CORE5PARERR_S)
+#define CORE5PARERR_F CORE5PARERR_V(1U)
+
+#define CORE4PARERR_S 15
+#define CORE4PARERR_V(x) ((x) << CORE4PARERR_S)
+#define CORE4PARERR_F CORE4PARERR_V(1U)
+
+#define CORE3PARERR_S 14
+#define CORE3PARERR_V(x) ((x) << CORE3PARERR_S)
+#define CORE3PARERR_F CORE3PARERR_V(1U)
+
+#define CORE2PARERR_S 13
+#define CORE2PARERR_V(x) ((x) << CORE2PARERR_S)
+#define CORE2PARERR_F CORE2PARERR_V(1U)
+
+#define CORE1PARERR_S 12
+#define CORE1PARERR_V(x) ((x) << CORE1PARERR_S)
+#define CORE1PARERR_F CORE1PARERR_V(1U)
+
+#define GFTPARERR_S 10
+#define GFTPARERR_V(x) ((x) << GFTPARERR_S)
+#define GFTPARERR_F GFTPARERR_V(1U)
+
+#define MPSRSPDATAPARERR_S 9
+#define MPSRSPDATAPARERR_V(x) ((x) << MPSRSPDATAPARERR_S)
+#define MPSRSPDATAPARERR_F MPSRSPDATAPARERR_V(1U)
+
+#define ER_RSPDATAPARERR_S 8
+#define ER_RSPDATAPARERR_V(x) ((x) << ER_RSPDATAPARERR_S)
+#define ER_RSPDATAPARERR_F ER_RSPDATAPARERR_V(1U)
+
+#define FLOWFIFOPARERR_S 7
+#define FLOWFIFOPARERR_V(x) ((x) << FLOWFIFOPARERR_S)
+#define FLOWFIFOPARERR_F FLOWFIFOPARERR_V(1U)
+
+#define OBQSRAMPARERR_S 6
+#define OBQSRAMPARERR_V(x) ((x) << OBQSRAMPARERR_S)
+#define OBQSRAMPARERR_F OBQSRAMPARERR_V(1U)
+
+#define TIEQOUTPARERR_S 3
+#define TIEQOUTPARERR_V(x) ((x) << TIEQOUTPARERR_S)
+#define TIEQOUTPARERR_F TIEQOUTPARERR_V(1U)
+
+#define TIEQINPARERR_S 2
+#define TIEQINPARERR_V(x) ((x) << TIEQINPARERR_S)
+#define TIEQINPARERR_F TIEQINPARERR_V(1U)
+
+#define PIFRSPPARERR_S 1
+#define PIFRSPPARERR_V(x) ((x) << PIFRSPPARERR_S)
+#define PIFRSPPARERR_F PIFRSPPARERR_V(1U)
+
+#define PIFREQPARERR_S 0
+#define PIFREQPARERR_V(x) ((x) << PIFREQPARERR_S)
+#define PIFREQPARERR_F PIFREQPARERR_V(1U)
+
#define MBMSGVALID_S 3
#define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
#define MBMSGVALID_F MBMSGVALID_V(1U)
@@ -1122,6 +2112,7 @@
#define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
#define MBMSGRDYINT_F MBMSGRDYINT_V(1U)
+#define CIM_HOST_INT_ENABLE_A 0x7b28
#define CIM_HOST_INT_CAUSE_A 0x7b2c
#define TIEQOUTPARERRINT_S 20
@@ -1132,18 +2123,6 @@
#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
-#define TIMER0INT_S 2
-#define TIMER0INT_V(x) ((x) << TIMER0INT_S)
-#define TIMER0INT_F TIMER0INT_V(1U)
-
-#define PREFDROPINT_S 1
-#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
-#define PREFDROPINT_F PREFDROPINT_V(1U)
-
-#define UPACCNONZERO_S 0
-#define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
-#define UPACCNONZERO_F UPACCNONZERO_V(1U)
-
#define MBHOSTPARERR_S 18
#define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
#define MBHOSTPARERR_F MBHOSTPARERR_V(1U)
@@ -1200,6 +2179,87 @@
#define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
#define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U)
+#define TIMER1INT_S 3
+#define TIMER1INT_V(x) ((x) << TIMER1INT_S)
+#define TIMER1INT_F TIMER1INT_V(1U)
+
+#define TIMER0INT_S 2
+#define TIMER0INT_V(x) ((x) << TIMER0INT_S)
+#define TIMER0INT_F TIMER0INT_V(1U)
+
+#define PREFDROPINT_S 1
+#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
+#define PREFDROPINT_F PREFDROPINT_V(1U)
+
+#define MA_CIM_INTFPERR_S 28
+#define MA_CIM_INTFPERR_V(x) ((x) << MA_CIM_INTFPERR_S)
+#define MA_CIM_INTFPERR_F MA_CIM_INTFPERR_V(1U)
+
+#define PLCIM_MSTRSPDATAPARERR_S 27
+#define PLCIM_MSTRSPDATAPARERR_V(x) ((x) << PLCIM_MSTRSPDATAPARERR_S)
+#define PLCIM_MSTRSPDATAPARERR_F PLCIM_MSTRSPDATAPARERR_V(1U)
+
+#define NCSI2CIMINTFPARERR_S 26
+#define NCSI2CIMINTFPARERR_V(x) ((x) << NCSI2CIMINTFPARERR_S)
+#define NCSI2CIMINTFPARERR_F NCSI2CIMINTFPARERR_V(1U)
+
+#define SGE2CIMINTFPARERR_S 25
+#define SGE2CIMINTFPARERR_V(x) ((x) << SGE2CIMINTFPARERR_S)
+#define SGE2CIMINTFPARERR_F SGE2CIMINTFPARERR_V(1U)
+
+#define ULP2CIMINTFPARERR_S 24
+#define ULP2CIMINTFPARERR_V(x) ((x) << ULP2CIMINTFPARERR_S)
+#define ULP2CIMINTFPARERR_F ULP2CIMINTFPARERR_V(1U)
+
+#define TP2CIMINTFPARERR_S 23
+#define TP2CIMINTFPARERR_V(x) ((x) << TP2CIMINTFPARERR_S)
+#define TP2CIMINTFPARERR_F TP2CIMINTFPARERR_V(1U)
+
+#define OBQSGERX1PARERR_S 22
+#define OBQSGERX1PARERR_V(x) ((x) << OBQSGERX1PARERR_S)
+#define OBQSGERX1PARERR_F OBQSGERX1PARERR_V(1U)
+
+#define OBQSGERX0PARERR_S 21
+#define OBQSGERX0PARERR_V(x) ((x) << OBQSGERX0PARERR_S)
+#define OBQSGERX0PARERR_F OBQSGERX0PARERR_V(1U)
+
+#define PCIE2CIMINTFPARERR_S 29
+#define PCIE2CIMINTFPARERR_V(x) ((x) << PCIE2CIMINTFPARERR_S)
+#define PCIE2CIMINTFPARERR_F PCIE2CIMINTFPARERR_V(1U)
+
+#define IBQPCIEPARERR_S 12
+#define IBQPCIEPARERR_V(x) ((x) << IBQPCIEPARERR_S)
+#define IBQPCIEPARERR_F IBQPCIEPARERR_V(1U)
+
+#define CORE7ACCINT_S 22
+#define CORE7ACCINT_V(x) ((x) << CORE7ACCINT_S)
+#define CORE7ACCINT_F CORE7ACCINT_V(1U)
+
+#define CORE6ACCINT_S 21
+#define CORE6ACCINT_V(x) ((x) << CORE6ACCINT_S)
+#define CORE6ACCINT_F CORE6ACCINT_V(1U)
+
+#define CORE5ACCINT_S 20
+#define CORE5ACCINT_V(x) ((x) << CORE5ACCINT_S)
+#define CORE5ACCINT_F CORE5ACCINT_V(1U)
+
+#define CORE4ACCINT_S 19
+#define CORE4ACCINT_V(x) ((x) << CORE4ACCINT_S)
+#define CORE4ACCINT_F CORE4ACCINT_V(1U)
+
+#define CORE3ACCINT_S 18
+#define CORE3ACCINT_V(x) ((x) << CORE3ACCINT_S)
+#define CORE3ACCINT_F CORE3ACCINT_V(1U)
+
+#define CORE2ACCINT_S 17
+#define CORE2ACCINT_V(x) ((x) << CORE2ACCINT_S)
+#define CORE2ACCINT_F CORE2ACCINT_V(1U)
+
+#define CORE1ACCINT_S 16
+#define CORE1ACCINT_V(x) ((x) << CORE1ACCINT_S)
+#define CORE1ACCINT_F CORE1ACCINT_V(1U)
+
+#define CIM_HOST_UPACC_INT_ENABLE_A 0x7b30
#define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
#define EEPROMWRINT_S 30
@@ -1326,6 +2386,10 @@
#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
#define RSVDSPACEINT_F RSVDSPACEINT_V(1U)
+#define CONWRERRINT_S 31
+#define CONWRERRINT_V(x) ((x) << CONWRERRINT_S)
+#define CONWRERRINT_F CONWRERRINT_V(1U)
+
/* registers for module TP */
#define DBGLAWHLF_S 23
#define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)
@@ -1352,6 +2416,532 @@
#define TP_OUT_CONFIG_A 0x7d04
#define TP_GLOBAL_CONFIG_A 0x7d08
+#define TP_C_PERR_ENABLE_A 0x7f30
+#define TP_C_PERR_CAUSE_A 0x7f34
+
+#define DMXFIFOOVFL_S 26
+#define DMXFIFOOVFL_V(x) ((x) << DMXFIFOOVFL_S)
+#define DMXFIFOOVFL_F DMXFIFOOVFL_V(1U)
+
+#define URX2TPCDDPINTF_S 25
+#define URX2TPCDDPINTF_V(x) ((x) << URX2TPCDDPINTF_S)
+#define URX2TPCDDPINTF_F URX2TPCDDPINTF_V(1U)
+
+#define TPCDISPTOKENFIFO_S 24
+#define TPCDISPTOKENFIFO_V(x) ((x) << TPCDISPTOKENFIFO_S)
+#define TPCDISPTOKENFIFO_F TPCDISPTOKENFIFO_V(1U)
+
+#define TPCDISPCPLFIFO3_S 23
+#define TPCDISPCPLFIFO3_V(x) ((x) << TPCDISPCPLFIFO3_S)
+#define TPCDISPCPLFIFO3_F TPCDISPCPLFIFO3_V(1U)
+
+#define TPCDISPCPLFIFO2_S 22
+#define TPCDISPCPLFIFO2_V(x) ((x) << TPCDISPCPLFIFO2_S)
+#define TPCDISPCPLFIFO2_F TPCDISPCPLFIFO2_V(1U)
+
+#define TPCDISPCPLFIFO1_S 21
+#define TPCDISPCPLFIFO1_V(x) ((x) << TPCDISPCPLFIFO1_S)
+#define TPCDISPCPLFIFO1_F TPCDISPCPLFIFO1_V(1U)
+
+#define TPCDISPCPLFIFO0_S 20
+#define TPCDISPCPLFIFO0_V(x) ((x) << TPCDISPCPLFIFO0_S)
+#define TPCDISPCPLFIFO0_F TPCDISPCPLFIFO0_V(1U)
+
+#define URXPLDINTFCRC3_S 19
+#define URXPLDINTFCRC3_V(x) ((x) << URXPLDINTFCRC3_S)
+#define URXPLDINTFCRC3_F URXPLDINTFCRC3_V(1U)
+
+#define URXPLDINTFCRC2_S 18
+#define URXPLDINTFCRC2_V(x) ((x) << URXPLDINTFCRC2_S)
+#define URXPLDINTFCRC2_F URXPLDINTFCRC2_V(1U)
+
+#define URXPLDINTFCRC1_S 17
+#define URXPLDINTFCRC1_V(x) ((x) << URXPLDINTFCRC1_S)
+#define URXPLDINTFCRC1_F URXPLDINTFCRC1_V(1U)
+
+#define URXPLDINTFCRC0_S 16
+#define URXPLDINTFCRC0_V(x) ((x) << URXPLDINTFCRC0_S)
+#define URXPLDINTFCRC0_F URXPLDINTFCRC0_V(1U)
+
+#define DMXDBFIFO_S 15
+#define DMXDBFIFO_V(x) ((x) << DMXDBFIFO_S)
+#define DMXDBFIFO_F DMXDBFIFO_V(1U)
+
+#define DMXDBSRAM_S 14
+#define DMXDBSRAM_V(x) ((x) << DMXDBSRAM_S)
+#define DMXDBSRAM_F DMXDBSRAM_V(1U)
+
+#define DMXCPLFIFO_S 13
+#define DMXCPLFIFO_V(x) ((x) << DMXCPLFIFO_S)
+#define DMXCPLFIFO_F DMXCPLFIFO_V(1U)
+
+#define DMXCPLSRAM_S 12
+#define DMXCPLSRAM_V(x) ((x) << DMXCPLSRAM_S)
+#define DMXCPLSRAM_F DMXCPLSRAM_V(1U)
+
+#define DMXCSUMFIFO_S 11
+#define DMXCSUMFIFO_V(x) ((x) << DMXCSUMFIFO_S)
+#define DMXCSUMFIFO_F DMXCSUMFIFO_V(1U)
+
+#define DMXLENFIFO_S 10
+#define DMXLENFIFO_V(x) ((x) << DMXLENFIFO_S)
+#define DMXLENFIFO_F DMXLENFIFO_V(1U)
+
+#define DMXCHECKFIFO_S 9
+#define DMXCHECKFIFO_V(x) ((x) << DMXCHECKFIFO_S)
+#define DMXCHECKFIFO_F DMXCHECKFIFO_V(1U)
+
+#define DMXWINFIFO_S 8
+#define DMXWINFIFO_V(x) ((x) << DMXWINFIFO_S)
+#define DMXWINFIFO_F DMXWINFIFO_V(1U)
+
+#define EGTOKENFIFO_S 7
+#define EGTOKENFIFO_V(x) ((x) << EGTOKENFIFO_S)
+#define EGTOKENFIFO_F EGTOKENFIFO_V(1U)
+
+#define EGDATAFIFO_S 6
+#define EGDATAFIFO_V(x) ((x) << EGDATAFIFO_S)
+#define EGDATAFIFO_F EGDATAFIFO_V(1U)
+
+#define UTX2TPCINTF3_S 5
+#define UTX2TPCINTF3_V(x) ((x) << UTX2TPCINTF3_S)
+#define UTX2TPCINTF3_F UTX2TPCINTF3_V(1U)
+
+#define UTX2TPCINTF2_S 4
+#define UTX2TPCINTF2_V(x) ((x) << UTX2TPCINTF2_S)
+#define UTX2TPCINTF2_F UTX2TPCINTF2_V(1U)
+
+#define UTX2TPCINTF1_S 3
+#define UTX2TPCINTF1_V(x) ((x) << UTX2TPCINTF1_S)
+#define UTX2TPCINTF1_F UTX2TPCINTF1_V(1U)
+
+#define UTX2TPCINTF0_S 2
+#define UTX2TPCINTF0_V(x) ((x) << UTX2TPCINTF0_S)
+#define UTX2TPCINTF0_F UTX2TPCINTF0_V(1U)
+
+#define LBKTOKENFIFO_S 1
+#define LBKTOKENFIFO_V(x) ((x) << LBKTOKENFIFO_S)
+#define LBKTOKENFIFO_F LBKTOKENFIFO_V(1U)
+
+#define LBKDATAFIFO_S 0
+#define LBKDATAFIFO_V(x) ((x) << LBKDATAFIFO_S)
+#define LBKDATAFIFO_F LBKDATAFIFO_V(1U)
+
+#define TP_E_EG_PERR_ENABLE_A 0x7f38
+#define TP_E_EG_PERR_CAUSE_A 0x7f3c
+
+#define MPSLPBKTOKENFIFO_S 25
+#define MPSLPBKTOKENFIFO_V(x) ((x) << MPSLPBKTOKENFIFO_S)
+#define MPSLPBKTOKENFIFO_F MPSLPBKTOKENFIFO_V(1U)
+
+#define MPSMACTOKENFIFO_S 24
+#define MPSMACTOKENFIFO_V(x) ((x) << MPSMACTOKENFIFO_S)
+#define MPSMACTOKENFIFO_F MPSMACTOKENFIFO_V(1U)
+
+#define DISPIPSECFIFO3_S 23
+#define DISPIPSECFIFO3_V(x) ((x) << DISPIPSECFIFO3_S)
+#define DISPIPSECFIFO3_F DISPIPSECFIFO3_V(1U)
+
+#define DISPTCPFIFO3_S 22
+#define DISPTCPFIFO3_V(x) ((x) << DISPTCPFIFO3_S)
+#define DISPTCPFIFO3_F DISPTCPFIFO3_V(1U)
+
+#define DISPIPFIFO3_S 21
+#define DISPIPFIFO3_V(x) ((x) << DISPIPFIFO3_S)
+#define DISPIPFIFO3_F DISPIPFIFO3_V(1U)
+
+#define DISPETHFIFO3_S 20
+#define DISPETHFIFO3_V(x) ((x) << DISPETHFIFO3_S)
+#define DISPETHFIFO3_F DISPETHFIFO3_V(1U)
+
+#define DISPGREFIFO3_S 19
+#define DISPGREFIFO3_V(x) ((x) << DISPGREFIFO3_S)
+#define DISPGREFIFO3_F DISPGREFIFO3_V(1U)
+
+#define DISPCPL5FIFO3_S 18
+#define DISPCPL5FIFO3_V(x) ((x) << DISPCPL5FIFO3_S)
+#define DISPCPL5FIFO3_F DISPCPL5FIFO3_V(1U)
+
+#define DISPIPSECFIFO2_S 17
+#define DISPIPSECFIFO2_V(x) ((x) << DISPIPSECFIFO2_S)
+#define DISPIPSECFIFO2_F DISPIPSECFIFO2_V(1U)
+
+#define DISPTCPFIFO2_S 16
+#define DISPTCPFIFO2_V(x) ((x) << DISPTCPFIFO2_S)
+#define DISPTCPFIFO2_F DISPTCPFIFO2_V(1U)
+
+#define DISPIPFIFO2_S 15
+#define DISPIPFIFO2_V(x) ((x) << DISPIPFIFO2_S)
+#define DISPIPFIFO2_F DISPIPFIFO2_V(1U)
+
+#define DISPETHFIFO2_S 14
+#define DISPETHFIFO2_V(x) ((x) << DISPETHFIFO2_S)
+#define DISPETHFIFO2_F DISPETHFIFO2_V(1U)
+
+#define DISPGREFIFO2_S 13
+#define DISPGREFIFO2_V(x) ((x) << DISPGREFIFO2_S)
+#define DISPGREFIFO2_F DISPGREFIFO2_V(1U)
+
+#define DISPCPL5FIFO2_S 12
+#define DISPCPL5FIFO2_V(x) ((x) << DISPCPL5FIFO2_S)
+#define DISPCPL5FIFO2_F DISPCPL5FIFO2_V(1U)
+
+#define DISPIPSECFIFO1_S 11
+#define DISPIPSECFIFO1_V(x) ((x) << DISPIPSECFIFO1_S)
+#define DISPIPSECFIFO1_F DISPIPSECFIFO1_V(1U)
+
+#define DISPTCPFIFO1_S 10
+#define DISPTCPFIFO1_V(x) ((x) << DISPTCPFIFO1_S)
+#define DISPTCPFIFO1_F DISPTCPFIFO1_V(1U)
+
+#define DISPIPFIFO1_S 9
+#define DISPIPFIFO1_V(x) ((x) << DISPIPFIFO1_S)
+#define DISPIPFIFO1_F DISPIPFIFO1_V(1U)
+
+#define DISPETHFIFO1_S 8
+#define DISPETHFIFO1_V(x) ((x) << DISPETHFIFO1_S)
+#define DISPETHFIFO1_F DISPETHFIFO1_V(1U)
+
+#define DISPGREFIFO1_S 7
+#define DISPGREFIFO1_V(x) ((x) << DISPGREFIFO1_S)
+#define DISPGREFIFO1_F DISPGREFIFO1_V(1U)
+
+#define DISPCPL5FIFO1_S 6
+#define DISPCPL5FIFO1_V(x) ((x) << DISPCPL5FIFO1_S)
+#define DISPCPL5FIFO1_F DISPCPL5FIFO1_V(1U)
+
+#define DISPIPSECFIFO0_S 5
+#define DISPIPSECFIFO0_V(x) ((x) << DISPIPSECFIFO0_S)
+#define DISPIPSECFIFO0_F DISPIPSECFIFO0_V(1U)
+
+#define DISPTCPFIFO0_S 4
+#define DISPTCPFIFO0_V(x) ((x) << DISPTCPFIFO0_S)
+#define DISPTCPFIFO0_F DISPTCPFIFO0_V(1U)
+
+#define DISPIPFIFO0_S 3
+#define DISPIPFIFO0_V(x) ((x) << DISPIPFIFO0_S)
+#define DISPIPFIFO0_F DISPIPFIFO0_V(1U)
+
+#define DISPETHFIFO0_S 2
+#define DISPETHFIFO0_V(x) ((x) << DISPETHFIFO0_S)
+#define DISPETHFIFO0_F DISPETHFIFO0_V(1U)
+
+#define DISPGREFIFO0_S 1
+#define DISPGREFIFO0_V(x) ((x) << DISPGREFIFO0_S)
+#define DISPGREFIFO0_F DISPGREFIFO0_V(1U)
+
+#define DISPCPL5FIFO0_S 0
+#define DISPCPL5FIFO0_V(x) ((x) << DISPCPL5FIFO0_S)
+#define DISPCPL5FIFO0_F DISPCPL5FIFO0_V(1U)
+
+#define TP_E_IN0_PERR_ENABLE_A 0x7f40
+#define TP_E_IN0_PERR_CAUSE_A 0x7f44
+
+#define DMXISSFIFO_S 30
+#define DMXISSFIFO_V(x) ((x) << DMXISSFIFO_S)
+#define DMXISSFIFO_F DMXISSFIFO_V(1U)
+
+#define DMXERRFIFO_S 29
+#define DMXERRFIFO_V(x) ((x) << DMXERRFIFO_S)
+#define DMXERRFIFO_F DMXERRFIFO_V(1U)
+
+#define DMXATTFIFO_S 28
+#define DMXATTFIFO_V(x) ((x) << DMXATTFIFO_S)
+#define DMXATTFIFO_F DMXATTFIFO_V(1U)
+
+#define DMXTCPFIFO_S 27
+#define DMXTCPFIFO_V(x) ((x) << DMXTCPFIFO_S)
+#define DMXTCPFIFO_F DMXTCPFIFO_V(1U)
+
+#define DMXMPAFIFO_S 26
+#define DMXMPAFIFO_V(x) ((x) << DMXMPAFIFO_S)
+#define DMXMPAFIFO_F DMXMPAFIFO_V(1U)
+
+#define DMXOPTFIFO_S 25
+#define DMXOPTFIFO_V(x) ((x) << DMXOPTFIFO_S)
+#define DMXOPTFIFO_F DMXOPTFIFO_V(1U)
+
+#define INGTOKENFIFO_S 24
+#define INGTOKENFIFO_V(x) ((x) << INGTOKENFIFO_S)
+#define INGTOKENFIFO_F INGTOKENFIFO_V(1U)
+
+#define DMXPLDCHKOVFL1_S 21
+#define DMXPLDCHKOVFL1_V(x) ((x) << DMXPLDCHKOVFL1_S)
+#define DMXPLDCHKOVFL1_F DMXPLDCHKOVFL1_V(1U)
+
+#define DMXPLDCHKFIFO1_S 20
+#define DMXPLDCHKFIFO1_V(x) ((x) << DMXPLDCHKFIFO1_S)
+#define DMXPLDCHKFIFO1_F DMXPLDCHKFIFO1_V(1U)
+
+#define DMXOPTFIFO1_S 19
+#define DMXOPTFIFO1_V(x) ((x) << DMXOPTFIFO1_S)
+#define DMXOPTFIFO1_F DMXOPTFIFO1_V(1U)
+
+#define DMXMPAFIFO1_S 18
+#define DMXMPAFIFO1_V(x) ((x) << DMXMPAFIFO1_S)
+#define DMXMPAFIFO1_F DMXMPAFIFO1_V(1U)
+
+#define DMXDBFIFO1_S 17
+#define DMXDBFIFO1_V(x) ((x) << DMXDBFIFO1_S)
+#define DMXDBFIFO1_F DMXDBFIFO1_V(1U)
+
+#define DMXATTFIFO1_S 16
+#define DMXATTFIFO1_V(x) ((x) << DMXATTFIFO1_S)
+#define DMXATTFIFO1_F DMXATTFIFO1_V(1U)
+
+#define DMXISSFIFO1_S 15
+#define DMXISSFIFO1_V(x) ((x) << DMXISSFIFO1_S)
+#define DMXISSFIFO1_F DMXISSFIFO1_V(1U)
+
+#define DMXTCPFIFO1_S 14
+#define DMXTCPFIFO1_V(x) ((x) << DMXTCPFIFO1_S)
+#define DMXTCPFIFO1_F DMXTCPFIFO1_V(1U)
+
+#define DMXERRFIFO1_S 13
+#define DMXERRFIFO1_V(x) ((x) << DMXERRFIFO1_S)
+#define DMXERRFIFO1_F DMXERRFIFO1_V(1U)
+
+#define MPS2TPINTF1_S 12
+#define MPS2TPINTF1_V(x) ((x) << MPS2TPINTF1_S)
+#define MPS2TPINTF1_F MPS2TPINTF1_V(1U)
+
+#define DMXPLDCHKOVFL0_S 9
+#define DMXPLDCHKOVFL0_V(x) ((x) << DMXPLDCHKOVFL0_S)
+#define DMXPLDCHKOVFL0_F DMXPLDCHKOVFL0_V(1U)
+
+#define DMXPLDCHKFIFO0_S 8
+#define DMXPLDCHKFIFO0_V(x) ((x) << DMXPLDCHKFIFO0_S)
+#define DMXPLDCHKFIFO0_F DMXPLDCHKFIFO0_V(1U)
+
+#define DMXOPTFIFO0_S 7
+#define DMXOPTFIFO0_V(x) ((x) << DMXOPTFIFO0_S)
+#define DMXOPTFIFO0_F DMXOPTFIFO0_V(1U)
+
+#define DMXMPAFIFO0_S 6
+#define DMXMPAFIFO0_V(x) ((x) << DMXMPAFIFO0_S)
+#define DMXMPAFIFO0_F DMXMPAFIFO0_V(1U)
+
+#define DMXDBFIFO0_S 5
+#define DMXDBFIFO0_V(x) ((x) << DMXDBFIFO0_S)
+#define DMXDBFIFO0_F DMXDBFIFO0_V(1U)
+
+#define DMXATTFIFO0_S 4
+#define DMXATTFIFO0_V(x) ((x) << DMXATTFIFO0_S)
+#define DMXATTFIFO0_F DMXATTFIFO0_V(1U)
+
+#define DMXISSFIFO0_S 3
+#define DMXISSFIFO0_V(x) ((x) << DMXISSFIFO0_S)
+#define DMXISSFIFO0_F DMXISSFIFO0_V(1U)
+
+#define DMXTCPFIFO0_S 2
+#define DMXTCPFIFO0_V(x) ((x) << DMXTCPFIFO0_S)
+#define DMXTCPFIFO0_F DMXTCPFIFO0_V(1U)
+
+#define DMXERRFIFO0_S 1
+#define DMXERRFIFO0_V(x) ((x) << DMXERRFIFO0_S)
+#define DMXERRFIFO0_F DMXERRFIFO0_V(1U)
+
+#define MPS2TPINTF0_S 0
+#define MPS2TPINTF0_V(x) ((x) << MPS2TPINTF0_S)
+#define MPS2TPINTF0_F MPS2TPINTF0_V(1U)
+
+#define TP_E_IN1_PERR_ENABLE_A 0x7f48
+#define TP_E_IN1_PERR_CAUSE_A 0x7f4c
+
+#define DMXPLDCHKOVFL3_S 21
+#define DMXPLDCHKOVFL3_V(x) ((x) << DMXPLDCHKOVFL3_S)
+#define DMXPLDCHKOVFL3_F DMXPLDCHKOVFL3_V(1U)
+
+#define DMXPLDCHKFIFO3_S 20
+#define DMXPLDCHKFIFO3_V(x) ((x) << DMXPLDCHKFIFO3_S)
+#define DMXPLDCHKFIFO3_F DMXPLDCHKFIFO3_V(1U)
+
+#define DMXOPTFIFO3_S 19
+#define DMXOPTFIFO3_V(x) ((x) << DMXOPTFIFO3_S)
+#define DMXOPTFIFO3_F DMXOPTFIFO3_V(1U)
+
+#define DMXMPAFIFO3_S 18
+#define DMXMPAFIFO3_V(x) ((x) << DMXMPAFIFO3_S)
+#define DMXMPAFIFO3_F DMXMPAFIFO3_V(1U)
+
+#define DMXDBFIFO3_S 17
+#define DMXDBFIFO3_V(x) ((x) << DMXDBFIFO3_S)
+#define DMXDBFIFO3_F DMXDBFIFO3_V(1U)
+
+#define DMXATTFIFO3_S 16
+#define DMXATTFIFO3_V(x) ((x) << DMXATTFIFO3_S)
+#define DMXATTFIFO3_F DMXATTFIFO3_V(1U)
+
+#define DMXISSFIFO3_S 15
+#define DMXISSFIFO3_V(x) ((x) << DMXISSFIFO3_S)
+#define DMXISSFIFO3_F DMXISSFIFO3_V(1U)
+
+#define DMXTCPFIFO3_S 14
+#define DMXTCPFIFO3_V(x) ((x) << DMXTCPFIFO3_S)
+#define DMXTCPFIFO3_F DMXTCPFIFO3_V(1U)
+
+#define DMXERRFIFO3_S 13
+#define DMXERRFIFO3_V(x) ((x) << DMXERRFIFO3_S)
+#define DMXERRFIFO3_F DMXERRFIFO3_V(1U)
+
+#define MPS2TPINTF3_S 12
+#define MPS2TPINTF3_V(x) ((x) << MPS2TPINTF3_S)
+#define MPS2TPINTF3_F MPS2TPINTF3_V(1U)
+
+#define DMXPLDCHKOVFL2_S 9
+#define DMXPLDCHKOVFL2_V(x) ((x) << DMXPLDCHKOVFL2_S)
+#define DMXPLDCHKOVFL2_F DMXPLDCHKOVFL2_V(1U)
+
+#define DMXPLDCHKFIFO2_S 8
+#define DMXPLDCHKFIFO2_V(x) ((x) << DMXPLDCHKFIFO2_S)
+#define DMXPLDCHKFIFO2_F DMXPLDCHKFIFO2_V(1U)
+
+#define DMXOPTFIFO2_S 7
+#define DMXOPTFIFO2_V(x) ((x) << DMXOPTFIFO2_S)
+#define DMXOPTFIFO2_F DMXOPTFIFO2_V(1U)
+
+#define DMXMPAFIFO2_S 6
+#define DMXMPAFIFO2_V(x) ((x) << DMXMPAFIFO2_S)
+#define DMXMPAFIFO2_F DMXMPAFIFO2_V(1U)
+
+#define DMXDBFIFO2_S 5
+#define DMXDBFIFO2_V(x) ((x) << DMXDBFIFO2_S)
+#define DMXDBFIFO2_F DMXDBFIFO2_V(1U)
+
+#define DMXATTFIFO2_S 4
+#define DMXATTFIFO2_V(x) ((x) << DMXATTFIFO2_S)
+#define DMXATTFIFO2_F DMXATTFIFO2_V(1U)
+
+#define DMXISSFIFO2_S 3
+#define DMXISSFIFO2_V(x) ((x) << DMXISSFIFO2_S)
+#define DMXISSFIFO2_F DMXISSFIFO2_V(1U)
+
+#define DMXTCPFIFO2_S 2
+#define DMXTCPFIFO2_V(x) ((x) << DMXTCPFIFO2_S)
+#define DMXTCPFIFO2_F DMXTCPFIFO2_V(1U)
+
+#define DMXERRFIFO2_S 1
+#define DMXERRFIFO2_V(x) ((x) << DMXERRFIFO2_S)
+#define DMXERRFIFO2_F DMXERRFIFO2_V(1U)
+
+#define MPS2TPINTF2_S 0
+#define MPS2TPINTF2_V(x) ((x) << MPS2TPINTF2_S)
+#define MPS2TPINTF2_F MPS2TPINTF2_V(1U)
+
+#define TP_O_PERR_ENABLE_A 0x7f50
+#define TP_O_PERR_CAUSE_A 0x7f54
+
+#define DMARBTPERR_S 31
+#define DMARBTPERR_V(x) ((x) << DMARBTPERR_S)
+#define DMARBTPERR_F DMARBTPERR_V(1U)
+
+#define MMGRCACHEDATASRAM_S 24
+#define MMGRCACHEDATASRAM_V(x) ((x) << MMGRCACHEDATASRAM_S)
+#define MMGRCACHEDATASRAM_F MMGRCACHEDATASRAM_V(1U)
+
+#define MMGRCACHETAGFIFO_S 23
+#define MMGRCACHETAGFIFO_V(x) ((x) << MMGRCACHETAGFIFO_S)
+#define MMGRCACHETAGFIFO_F MMGRCACHETAGFIFO_V(1U)
+
+#define DBL2TLUTPERR_S 22
+#define DBL2TLUTPERR_V(x) ((x) << DBL2TLUTPERR_S)
+#define DBL2TLUTPERR_F DBL2TLUTPERR_V(1U)
+
+#define DBTXTIDPERR_S 21
+#define DBTXTIDPERR_V(x) ((x) << DBTXTIDPERR_S)
+#define DBTXTIDPERR_F DBTXTIDPERR_V(1U)
+
+#define DBEXTPERR_S 20
+#define DBEXTPERR_V(x) ((x) << DBEXTPERR_S)
+#define DBEXTPERR_F DBEXTPERR_V(1U)
+
+#define DBOPPERR_S 19
+#define DBOPPERR_V(x) ((x) << DBOPPERR_S)
+#define DBOPPERR_F DBOPPERR_V(1U)
+
+#define TMCACHEPERR_S 18
+#define TMCACHEPERR_V(x) ((x) << TMCACHEPERR_S)
+#define TMCACHEPERR_F TMCACHEPERR_V(1U)
+
+#define TPPROTOSRAM_S 16
+#define TPPROTOSRAM_V(x) ((x) << TPPROTOSRAM_S)
+#define TPPROTOSRAM_F TPPROTOSRAM_V(1U)
+
+#define HSPSRAM_S 15
+#define HSPSRAM_V(x) ((x) << HSPSRAM_S)
+#define HSPSRAM_F HSPSRAM_V(1U)
+
+#define RATEGRPSRAM_S 14
+#define RATEGRPSRAM_V(x) ((x) << RATEGRPSRAM_S)
+#define RATEGRPSRAM_F RATEGRPSRAM_V(1U)
+
+#define TXFBSEQFIFO_S 13
+#define TXFBSEQFIFO_V(x) ((x) << TXFBSEQFIFO_S)
+#define TXFBSEQFIFO_F TXFBSEQFIFO_V(1U)
+
+#define CMDATASRAM_S 12
+#define CMDATASRAM_V(x) ((x) << CMDATASRAM_S)
+#define CMDATASRAM_F CMDATASRAM_V(1U)
+
+#define CMTAGFIFO_S 11
+#define CMTAGFIFO_V(x) ((x) << CMTAGFIFO_S)
+#define CMTAGFIFO_F CMTAGFIFO_V(1U)
+
+#define RFCOPFIFO_S 10
+#define RFCOPFIFO_V(x) ((x) << RFCOPFIFO_S)
+#define RFCOPFIFO_F RFCOPFIFO_V(1U)
+
+#define DELINVFIFO_S 9
+#define DELINVFIFO_V(x) ((x) << DELINVFIFO_S)
+#define DELINVFIFO_F DELINVFIFO_V(1U)
+
+#define RSSCFGSRAM_S 8
+#define RSSCFGSRAM_V(x) ((x) << RSSCFGSRAM_S)
+#define RSSCFGSRAM_F RSSCFGSRAM_V(1U)
+
+#define RSSKEYSRAM_S 7
+#define RSSKEYSRAM_V(x) ((x) << RSSKEYSRAM_S)
+#define RSSKEYSRAM_F RSSKEYSRAM_V(1U)
+
+#define RSSLKPSRAM_S 6
+#define RSSLKPSRAM_V(x) ((x) << RSSLKPSRAM_S)
+#define RSSLKPSRAM_F RSSLKPSRAM_V(1U)
+
+#define SRQSRAM_S 5
+#define SRQSRAM_V(x) ((x) << SRQSRAM_S)
+#define SRQSRAM_F SRQSRAM_V(1U)
+
+#define ARPDASRAM_S 4
+#define ARPDASRAM_V(x) ((x) << ARPDASRAM_S)
+#define ARPDASRAM_F ARPDASRAM_V(1U)
+
+#define ARPSASRAM_S 3
+#define ARPSASRAM_V(x) ((x) << ARPSASRAM_S)
+#define ARPSASRAM_F ARPSASRAM_V(1U)
+
+#define ARPGRESRAM_S 2
+#define ARPGRESRAM_V(x) ((x) << ARPGRESRAM_S)
+#define ARPGRESRAM_F ARPGRESRAM_V(1U)
+
+#define ARPIPSECSRAM1_S 1
+#define ARPIPSECSRAM1_V(x) ((x) << ARPIPSECSRAM1_S)
+#define ARPIPSECSRAM1_F ARPIPSECSRAM1_V(1U)
+
+#define ARPIPSECSRAM0_S 0
+#define ARPIPSECSRAM0_V(x) ((x) << ARPIPSECSRAM0_S)
+#define ARPIPSECSRAM0_F ARPIPSECSRAM0_V(1U)
+
+#define TP_CERR_ENABLE_A 0x7f58
+#define TP_CERR_CAUSE_A 0x7f5c
+
+#define TPCEGDATAFIFO_S 8
+#define TPCEGDATAFIFO_V(x) ((x) << TPCEGDATAFIFO_S)
+#define TPCEGDATAFIFO_F TPCEGDATAFIFO_V(1U)
+
+#define TPCLBKDATAFIFO_S 7
+#define TPCLBKDATAFIFO_V(x) ((x) << TPCLBKDATAFIFO_S)
+#define TPCLBKDATAFIFO_F TPCLBKDATAFIFO_V(1U)
+
#define ACTIVEFILTERCOUNTS_S 22
#define ACTIVEFILTERCOUNTS_V(x) ((x) << ACTIVEFILTERCOUNTS_S)
#define ACTIVEFILTERCOUNTS_F ACTIVEFILTERCOUNTS_V(1U)
@@ -1387,11 +2977,6 @@
#define DBGLAMODE_M 0x3U
#define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M)
-#define FIVETUPLELOOKUP_S 17
-#define FIVETUPLELOOKUP_M 0x3U
-#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
-#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
-
#define TP_PARA_REG2_A 0x7d68
#define MAXRXDATA_S 16
@@ -1429,47 +3014,6 @@
#define INITSRTT_M 0xffffU
#define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
-#define PERSMAX_S 0
-#define PERSMAX_M 0x3fffffffU
-#define PERSMAX_V(x) ((x) << PERSMAX_S)
-#define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
-
-#define SYNSHIFTMAX_S 24
-#define SYNSHIFTMAX_M 0xffU
-#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
-#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
-
-#define RXTSHIFTMAXR1_S 20
-#define RXTSHIFTMAXR1_M 0xfU
-#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
-#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
-
-#define RXTSHIFTMAXR2_S 16
-#define RXTSHIFTMAXR2_M 0xfU
-#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
-#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
-
-#define PERSHIFTBACKOFFMAX_S 12
-#define PERSHIFTBACKOFFMAX_M 0xfU
-#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
-#define PERSHIFTBACKOFFMAX_G(x) \
- (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
-
-#define PERSHIFTMAX_S 8
-#define PERSHIFTMAX_M 0xfU
-#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
-#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
-
-#define KEEPALIVEMAXR1_S 4
-#define KEEPALIVEMAXR1_M 0xfU
-#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
-#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
-
-#define KEEPALIVEMAXR2_S 0
-#define KEEPALIVEMAXR2_M 0xfU
-#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
-#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
-
#define ROWINDEX_S 16
#define ROWINDEX_V(x) ((x) << ROWINDEX_S)
@@ -1522,8 +3066,34 @@
#define TP_PIO_DATA_A 0x7e44
#define TP_MIB_INDEX_A 0x7e50
#define TP_MIB_DATA_A 0x7e54
+
+#define TP_INT_ENABLE_A 0x7e70
#define TP_INT_CAUSE_A 0x7e74
+#define TPCERR_S 5
+#define TPCERR_V(x) ((x) << TPCERR_S)
+#define TPCERR_F TPCERR_V(1U)
+
+#define OTHERPERR_S 4
+#define OTHERPERR_V(x) ((x) << OTHERPERR_S)
+#define OTHERPERR_F OTHERPERR_V(1U)
+
+#define TPEING1PERR_S 3
+#define TPEING1PERR_V(x) ((x) << TPEING1PERR_S)
+#define TPEING1PERR_F TPEING1PERR_V(1U)
+
+#define TPEING0PERR_S 2
+#define TPEING0PERR_V(x) ((x) << TPEING0PERR_S)
+#define TPEING0PERR_F TPEING0PERR_V(1U)
+
+#define TPEEGPERR_S 1
+#define TPEEGPERR_V(x) ((x) << TPEEGPERR_S)
+#define TPEEGPERR_F TPEEGPERR_V(1U)
+
+#define TPCPERR_S 0
+#define TPCPERR_V(x) ((x) << TPCPERR_S)
+#define TPCPERR_F TPCPERR_V(1U)
+
#define TP_FLM_FREE_PS_CNT_A 0x7e80
#define TP_FLM_FREE_RX_CNT_A 0x7e84
@@ -1533,14 +3103,12 @@
#define FREERXPAGECOUNT_S 0
#define FREERXPAGECOUNT_M 0x1fffffU
-#define FREERXPAGECOUNT_V(x) ((x) << FREERXPAGECOUNT_S)
#define FREERXPAGECOUNT_G(x) (((x) >> FREERXPAGECOUNT_S) & FREERXPAGECOUNT_M)
#define TP_FLM_FREE_TX_CNT_A 0x7e88
#define FREETXPAGECOUNT_S 0
#define FREETXPAGECOUNT_M 0x1fffffU
-#define FREETXPAGECOUNT_V(x) ((x) << FREETXPAGECOUNT_S)
#define FREETXPAGECOUNT_G(x) (((x) >> FREETXPAGECOUNT_S) & FREETXPAGECOUNT_M)
#define FLMTXFLSTEMPTY_S 30
@@ -1625,13 +3193,57 @@
#define FCOE_V(x) ((x) << FCOE_S)
#define FCOE_F FCOE_V(1U)
-#define FILTERMODE_S 15
-#define FILTERMODE_V(x) ((x) << FILTERMODE_S)
-#define FILTERMODE_F FILTERMODE_V(1U)
+#define TCPFLAGS_S 13
+#define TCPFLAGS_V(x) ((x) << TCPFLAGS_S)
+#define TCPFLAGS_F TCPFLAGS_V(1U)
+
+#define SYNONLY_S 12
+#define SYNONLY_V(x) ((x) << SYNONLY_S)
+#define SYNONLY_F SYNONLY_V(1U)
+
+#define T7_FRAGMENTATION_S 10
+#define T7_FRAGMENTATION_V(x) ((x) << T7_FRAGMENTATION_S)
+#define T7_FRAGMENTATION_F T7_FRAGMENTATION_V(1U)
+
+#define T7_MPSHITTYPE_S 9
+#define T7_MPSHITTYPE_V(x) ((x) << T7_MPSHITTYPE_S)
+#define T7_MPSHITTYPE_F T7_MPSHITTYPE_V(1U)
+
+#define T7_MACMATCH_S 8
+#define T7_MACMATCH_V(x) ((x) << T7_MACMATCH_S)
+#define T7_MACMATCH_F T7_MACMATCH_V(1U)
-#define FCOEMASK_S 14
-#define FCOEMASK_V(x) ((x) << FCOEMASK_S)
-#define FCOEMASK_F FCOEMASK_V(1U)
+#define T7_ETHERTYPE_S 7
+#define T7_ETHERTYPE_V(x) ((x) << T7_ETHERTYPE_S)
+#define T7_ETHERTYPE_F T7_ETHERTYPE_V(1U)
+
+#define T7_PROTOCOL_S 6
+#define T7_PROTOCOL_V(x) ((x) << T7_PROTOCOL_S)
+#define T7_PROTOCOL_F T7_PROTOCOL_V(1U)
+
+#define T7_TOS_S 5
+#define T7_TOS_V(x) ((x) << T7_TOS_S)
+#define T7_TOS_F T7_TOS_V(1U)
+
+#define T7_VLAN_S 4
+#define T7_VLAN_V(x) ((x) << T7_VLAN_S)
+#define T7_VLAN_F T7_VLAN_V(1U)
+
+#define T7_VNIC_ID_S 3
+#define T7_VNIC_ID_V(x) ((x) << T7_VNIC_ID_S)
+#define T7_VNIC_ID_F T7_VNIC_ID_V(1U)
+
+#define T7_PORT_S 2
+#define T7_PORT_V(x) ((x) << T7_PORT_S)
+#define T7_PORT_F T7_PORT_V(1U)
+
+#define T7_FCOE_S 1
+#define T7_FCOE_V(x) ((x) << T7_FCOE_S)
+#define T7_FCOE_F T7_FCOE_V(1U)
+
+#define IPSECIDX_S 0
+#define IPSECIDX_V(x) ((x) << IPSECIDX_S)
+#define IPSECIDX_F IPSECIDX_V(1U)
#define TP_INGRESS_CONFIG_A 0x141
@@ -1670,14 +3282,150 @@
#define TP_MIB_FCOE_BYTE_0_HI_A 0x50
#define TP_MIB_OFD_VLN_DROP_0_A 0x58
#define TP_MIB_USM_PKTS_A 0x5c
-#define TP_MIB_RQE_DFR_PKT_A 0x64
+#define TP_CHANNEL_MAP_A 0x27
+#define T7_LB_MODE_S 30
+#define T7_LB_MODE_M 0x3U
+#define T7_LB_MODE_G(x) (((x) >> T7_LB_MODE_S) & T7_LB_MODE_M)
+
+#define TP_MIB_RQE_DFR_PKT_A 0x64
+
+#define ULP_TX_INT_ENABLE_2_A 0x8e7c
+#define ULP_TX_INT_CAUSE_2_A 0x8e80
+
+#define FSO_HDR_SRAM_PERR_SET3_S 7
+#define FSO_HDR_SRAM_PERR_SET3_V(x) ((x) << FSO_HDR_SRAM_PERR_SET3_S)
+#define FSO_HDR_SRAM_PERR_SET3_F FSO_HDR_SRAM_PERR_SET3_V(1U)
+
+#define FSO_HDR_SRAM_PERR_SET2_S 6
+#define FSO_HDR_SRAM_PERR_SET2_V(x) ((x) << FSO_HDR_SRAM_PERR_SET2_S)
+#define FSO_HDR_SRAM_PERR_SET2_F FSO_HDR_SRAM_PERR_SET2_V(1U)
+
+#define FSO_HDR_SRAM_PERR_SET1_S 5
+#define FSO_HDR_SRAM_PERR_SET1_V(x) ((x) << FSO_HDR_SRAM_PERR_SET1_S)
+#define FSO_HDR_SRAM_PERR_SET1_F FSO_HDR_SRAM_PERR_SET1_V(1U)
+
+#define FSO_HDR_SRAM_PERR_SET0_S 4
+#define FSO_HDR_SRAM_PERR_SET0_V(x) ((x) << FSO_HDR_SRAM_PERR_SET0_S)
+#define FSO_HDR_SRAM_PERR_SET0_F FSO_HDR_SRAM_PERR_SET0_V(1U)
+
+#define T10_PI_SRAM_PERR_SET3_S 3
+#define T10_PI_SRAM_PERR_SET3_V(x) ((x) << T10_PI_SRAM_PERR_SET3_S)
+#define T10_PI_SRAM_PERR_SET3_F T10_PI_SRAM_PERR_SET3_V(1U)
+
+#define T10_PI_SRAM_PERR_SET2_S 2
+#define T10_PI_SRAM_PERR_SET2_V(x) ((x) << T10_PI_SRAM_PERR_SET2_S)
+#define T10_PI_SRAM_PERR_SET2_F T10_PI_SRAM_PERR_SET2_V(1U)
+
+#define T10_PI_SRAM_PERR_SET1_S 1
+#define T10_PI_SRAM_PERR_SET1_V(x) ((x) << T10_PI_SRAM_PERR_SET1_S)
+#define T10_PI_SRAM_PERR_SET1_F T10_PI_SRAM_PERR_SET1_V(1U)
+
+#define T10_PI_SRAM_PERR_SET0_S 0
+#define T10_PI_SRAM_PERR_SET0_V(x) ((x) << T10_PI_SRAM_PERR_SET0_S)
+#define T10_PI_SRAM_PERR_SET0_F T10_PI_SRAM_PERR_SET0_V(1U)
+
+#define EDMA_IN_FIFO_PERR_SET3_S 31
+#define EDMA_IN_FIFO_PERR_SET3_V(x) ((x) << EDMA_IN_FIFO_PERR_SET3_S)
+#define EDMA_IN_FIFO_PERR_SET3_F EDMA_IN_FIFO_PERR_SET3_V(1U)
+
+#define EDMA_IN_FIFO_PERR_SET2_S 30
+#define EDMA_IN_FIFO_PERR_SET2_V(x) ((x) << EDMA_IN_FIFO_PERR_SET2_S)
+#define EDMA_IN_FIFO_PERR_SET2_F EDMA_IN_FIFO_PERR_SET2_V(1U)
+
+#define EDMA_IN_FIFO_PERR_SET1_S 29
+#define EDMA_IN_FIFO_PERR_SET1_V(x) ((x) << EDMA_IN_FIFO_PERR_SET1_S)
+#define EDMA_IN_FIFO_PERR_SET1_F EDMA_IN_FIFO_PERR_SET1_V(1U)
+
+#define EDMA_IN_FIFO_PERR_SET0_S 28
+#define EDMA_IN_FIFO_PERR_SET0_V(x) ((x) << EDMA_IN_FIFO_PERR_SET0_S)
+#define EDMA_IN_FIFO_PERR_SET0_F EDMA_IN_FIFO_PERR_SET0_V(1U)
+
+#define ALIGN_CTL_FIFO_PERR_SET3_S 27
+#define ALIGN_CTL_FIFO_PERR_SET3_V(x) ((x) << ALIGN_CTL_FIFO_PERR_SET3_S)
+#define ALIGN_CTL_FIFO_PERR_SET3_F ALIGN_CTL_FIFO_PERR_SET3_V(1U)
+
+#define ALIGN_CTL_FIFO_PERR_SET2_S 26
+#define ALIGN_CTL_FIFO_PERR_SET2_V(x) ((x) << ALIGN_CTL_FIFO_PERR_SET2_S)
+#define ALIGN_CTL_FIFO_PERR_SET2_F ALIGN_CTL_FIFO_PERR_SET2_V(1U)
+
+#define ALIGN_CTL_FIFO_PERR_SET1_S 25
+#define ALIGN_CTL_FIFO_PERR_SET1_V(x) ((x) << ALIGN_CTL_FIFO_PERR_SET1_S)
+#define ALIGN_CTL_FIFO_PERR_SET1_F ALIGN_CTL_FIFO_PERR_SET1_V(1U)
+
+#define ALIGN_CTL_FIFO_PERR_SET0_S 24
+#define ALIGN_CTL_FIFO_PERR_SET0_V(x) ((x) << ALIGN_CTL_FIFO_PERR_SET0_S)
+#define ALIGN_CTL_FIFO_PERR_SET0_F ALIGN_CTL_FIFO_PERR_SET0_V(1U)
+
+#define SGE_FIFO_PERR_SET3_S 23
+#define SGE_FIFO_PERR_SET3_V(x) ((x) << SGE_FIFO_PERR_SET3_S)
+#define SGE_FIFO_PERR_SET3_F SGE_FIFO_PERR_SET3_V(1U)
+
+#define SGE_FIFO_PERR_SET2_S 22
+#define SGE_FIFO_PERR_SET2_V(x) ((x) << SGE_FIFO_PERR_SET2_S)
+#define SGE_FIFO_PERR_SET2_F SGE_FIFO_PERR_SET2_V(1U)
+
+#define SGE_FIFO_PERR_SET1_S 21
+#define SGE_FIFO_PERR_SET1_V(x) ((x) << SGE_FIFO_PERR_SET1_S)
+#define SGE_FIFO_PERR_SET1_F SGE_FIFO_PERR_SET1_V(1U)
+
+#define SGE_FIFO_PERR_SET0_S 20
+#define SGE_FIFO_PERR_SET0_V(x) ((x) << SGE_FIFO_PERR_SET0_S)
+#define SGE_FIFO_PERR_SET0_F SGE_FIFO_PERR_SET0_V(1U)
+
+#define STAG_FIFO_PERR_SET3_S 19
+#define STAG_FIFO_PERR_SET3_V(x) ((x) << STAG_FIFO_PERR_SET3_S)
+#define STAG_FIFO_PERR_SET3_F STAG_FIFO_PERR_SET3_V(1U)
+
+#define STAG_FIFO_PERR_SET2_S 18
+#define STAG_FIFO_PERR_SET2_V(x) ((x) << STAG_FIFO_PERR_SET2_S)
+#define STAG_FIFO_PERR_SET2_F STAG_FIFO_PERR_SET2_V(1U)
+
+#define STAG_FIFO_PERR_SET1_S 17
+#define STAG_FIFO_PERR_SET1_V(x) ((x) << STAG_FIFO_PERR_SET1_S)
+#define STAG_FIFO_PERR_SET1_F STAG_FIFO_PERR_SET1_V(1U)
+
+#define STAG_FIFO_PERR_SET0_S 16
+#define STAG_FIFO_PERR_SET0_V(x) ((x) << STAG_FIFO_PERR_SET0_S)
+#define STAG_FIFO_PERR_SET0_F STAG_FIFO_PERR_SET0_V(1U)
+
+#define MAP_FIFO_PERR_SET3_S 15
+#define MAP_FIFO_PERR_SET3_V(x) ((x) << MAP_FIFO_PERR_SET3_S)
+#define MAP_FIFO_PERR_SET3_F MAP_FIFO_PERR_SET3_V(1U)
+
+#define MAP_FIFO_PERR_SET2_S 14
+#define MAP_FIFO_PERR_SET2_V(x) ((x) << MAP_FIFO_PERR_SET2_S)
+#define MAP_FIFO_PERR_SET2_F MAP_FIFO_PERR_SET2_V(1U)
+
+#define MAP_FIFO_PERR_SET1_S 13
+#define MAP_FIFO_PERR_SET1_V(x) ((x) << MAP_FIFO_PERR_SET1_S)
+#define MAP_FIFO_PERR_SET1_F MAP_FIFO_PERR_SET1_V(1U)
+
+#define MAP_FIFO_PERR_SET0_S 12
+#define MAP_FIFO_PERR_SET0_V(x) ((x) << MAP_FIFO_PERR_SET0_S)
+#define MAP_FIFO_PERR_SET0_F MAP_FIFO_PERR_SET0_V(1U)
+
+#define DMA_FIFO_PERR_SET3_S 11
+#define DMA_FIFO_PERR_SET3_V(x) ((x) << DMA_FIFO_PERR_SET3_S)
+#define DMA_FIFO_PERR_SET3_F DMA_FIFO_PERR_SET3_V(1U)
+
+#define DMA_FIFO_PERR_SET2_S 10
+#define DMA_FIFO_PERR_SET2_V(x) ((x) << DMA_FIFO_PERR_SET2_S)
+#define DMA_FIFO_PERR_SET2_F DMA_FIFO_PERR_SET2_V(1U)
+
+#define DMA_FIFO_PERR_SET1_S 9
+#define DMA_FIFO_PERR_SET1_V(x) ((x) << DMA_FIFO_PERR_SET1_S)
+#define DMA_FIFO_PERR_SET1_F DMA_FIFO_PERR_SET1_V(1U)
+
+#define DMA_FIFO_PERR_SET0_S 8
+#define DMA_FIFO_PERR_SET0_V(x) ((x) << DMA_FIFO_PERR_SET0_S)
+#define DMA_FIFO_PERR_SET0_F DMA_FIFO_PERR_SET0_V(1U)
+
+#define ULP_TX_INT_ENABLE_3_A 0x8e88
+#define ULP_TX_INT_CAUSE_3_A 0x8e8c
+
+#define ULP_TX_INT_ENABLE_A 0x8dc8
#define ULP_TX_INT_CAUSE_A 0x8dcc
-#define ULP_TX_TPT_LLIMIT_A 0x8dd4
-#define ULP_TX_TPT_ULIMIT_A 0x8dd8
-#define ULP_TX_PBL_LLIMIT_A 0x8ddc
-#define ULP_TX_PBL_ULIMIT_A 0x8de0
-#define ULP_TX_ERR_TABLE_BASE_A 0x8e04
#define PBL_BOUND_ERR_CH3_S 31
#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
@@ -1695,1146 +3443,3330 @@
#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
-#define PM_RX_INT_CAUSE_A 0x8fdc
-#define PM_RX_STAT_CONFIG_A 0x8fc8
-#define PM_RX_STAT_COUNT_A 0x8fcc
-#define PM_RX_STAT_LSB_A 0x8fd0
-#define PM_RX_DBG_CTRL_A 0x8fd0
-#define PM_RX_DBG_DATA_A 0x8fd4
-#define PM_RX_DBG_STAT_MSB_A 0x10013
+#define SGE2ULP_FIFO_PERR_SET3_S 27
+#define SGE2ULP_FIFO_PERR_SET3_V(x) ((x) << SGE2ULP_FIFO_PERR_SET3_S)
+#define SGE2ULP_FIFO_PERR_SET3_F SGE2ULP_FIFO_PERR_SET3_V(1U)
-#define PMRX_FRAMING_ERROR_F 0x003ffff0U
+#define SGE2ULP_FIFO_PERR_SET2_S 26
+#define SGE2ULP_FIFO_PERR_SET2_V(x) ((x) << SGE2ULP_FIFO_PERR_SET2_S)
+#define SGE2ULP_FIFO_PERR_SET2_F SGE2ULP_FIFO_PERR_SET2_V(1U)
-#define ZERO_E_CMD_ERROR_S 22
-#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
-#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
+#define SGE2ULP_FIFO_PERR_SET1_S 25
+#define SGE2ULP_FIFO_PERR_SET1_V(x) ((x) << SGE2ULP_FIFO_PERR_SET1_S)
+#define SGE2ULP_FIFO_PERR_SET1_F SGE2ULP_FIFO_PERR_SET1_V(1U)
-#define OCSPI_PAR_ERROR_S 3
-#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
-#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
+#define SGE2ULP_FIFO_PERR_SET0_S 24
+#define SGE2ULP_FIFO_PERR_SET0_V(x) ((x) << SGE2ULP_FIFO_PERR_SET0_S)
+#define SGE2ULP_FIFO_PERR_SET0_F SGE2ULP_FIFO_PERR_SET0_V(1U)
-#define DB_OPTIONS_PAR_ERROR_S 2
-#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
-#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
+#define CIM2ULP_FIFO_PERR_SET3_S 23
+#define CIM2ULP_FIFO_PERR_SET3_V(x) ((x) << CIM2ULP_FIFO_PERR_SET3_S)
+#define CIM2ULP_FIFO_PERR_SET3_F CIM2ULP_FIFO_PERR_SET3_V(1U)
-#define IESPI_PAR_ERROR_S 1
-#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
-#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
+#define CIM2ULP_FIFO_PERR_SET2_S 22
+#define CIM2ULP_FIFO_PERR_SET2_V(x) ((x) << CIM2ULP_FIFO_PERR_SET2_S)
+#define CIM2ULP_FIFO_PERR_SET2_F CIM2ULP_FIFO_PERR_SET2_V(1U)
-#define ULP_TX_LA_RDPTR_0_A 0x8ec0
-#define ULP_TX_LA_RDDATA_0_A 0x8ec4
-#define ULP_TX_LA_WRPTR_0_A 0x8ec8
-#define ULP_TX_ASIC_DEBUG_CTRL_A 0x8f70
+#define CIM2ULP_FIFO_PERR_SET1_S 21
+#define CIM2ULP_FIFO_PERR_SET1_V(x) ((x) << CIM2ULP_FIFO_PERR_SET1_S)
+#define CIM2ULP_FIFO_PERR_SET1_F CIM2ULP_FIFO_PERR_SET1_V(1U)
-#define ULP_TX_ASIC_DEBUG_0_A 0x8f74
-#define ULP_TX_ASIC_DEBUG_1_A 0x8f78
-#define ULP_TX_ASIC_DEBUG_2_A 0x8f7c
-#define ULP_TX_ASIC_DEBUG_3_A 0x8f80
-#define ULP_TX_ASIC_DEBUG_4_A 0x8f84
+#define CIM2ULP_FIFO_PERR_SET0_S 20
+#define CIM2ULP_FIFO_PERR_SET0_V(x) ((x) << CIM2ULP_FIFO_PERR_SET0_S)
+#define CIM2ULP_FIFO_PERR_SET0_F CIM2ULP_FIFO_PERR_SET0_V(1U)
-/* registers for module PM_RX */
-#define PM_RX_BASE_ADDR 0x8fc0
+#define CQE_FIFO_PERR_SET3_S 19
+#define CQE_FIFO_PERR_SET3_V(x) ((x) << CQE_FIFO_PERR_SET3_S)
+#define CQE_FIFO_PERR_SET3_F CQE_FIFO_PERR_SET3_V(1U)
-#define PMRX_E_PCMD_PAR_ERROR_S 0
-#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
-#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
+#define CQE_FIFO_PERR_SET2_S 18
+#define CQE_FIFO_PERR_SET2_V(x) ((x) << CQE_FIFO_PERR_SET2_S)
+#define CQE_FIFO_PERR_SET2_F CQE_FIFO_PERR_SET2_V(1U)
-#define PM_TX_INT_CAUSE_A 0x8ffc
-#define PM_TX_STAT_CONFIG_A 0x8fe8
-#define PM_TX_STAT_COUNT_A 0x8fec
-#define PM_TX_STAT_LSB_A 0x8ff0
-#define PM_TX_DBG_CTRL_A 0x8ff0
-#define PM_TX_DBG_DATA_A 0x8ff4
-#define PM_TX_DBG_STAT_MSB_A 0x1001a
+#define CQE_FIFO_PERR_SET1_S 17
+#define CQE_FIFO_PERR_SET1_V(x) ((x) << CQE_FIFO_PERR_SET1_S)
+#define CQE_FIFO_PERR_SET1_F CQE_FIFO_PERR_SET1_V(1U)
-#define PCMD_LEN_OVFL0_S 31
-#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
-#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
+#define CQE_FIFO_PERR_SET0_S 16
+#define CQE_FIFO_PERR_SET0_V(x) ((x) << CQE_FIFO_PERR_SET0_S)
+#define CQE_FIFO_PERR_SET0_F CQE_FIFO_PERR_SET0_V(1U)
-#define PCMD_LEN_OVFL1_S 30
-#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
-#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
+#define PBL_FIFO_PERR_SET3_S 15
+#define PBL_FIFO_PERR_SET3_V(x) ((x) << PBL_FIFO_PERR_SET3_S)
+#define PBL_FIFO_PERR_SET3_F PBL_FIFO_PERR_SET3_V(1U)
-#define PCMD_LEN_OVFL2_S 29
-#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
-#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
+#define PBL_FIFO_PERR_SET2_S 14
+#define PBL_FIFO_PERR_SET2_V(x) ((x) << PBL_FIFO_PERR_SET2_S)
+#define PBL_FIFO_PERR_SET2_F PBL_FIFO_PERR_SET2_V(1U)
-#define ZERO_C_CMD_ERROR_S 28
-#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
-#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
+#define PBL_FIFO_PERR_SET1_S 13
+#define PBL_FIFO_PERR_SET1_V(x) ((x) << PBL_FIFO_PERR_SET1_S)
+#define PBL_FIFO_PERR_SET1_F PBL_FIFO_PERR_SET1_V(1U)
-#define PMTX_FRAMING_ERROR_F 0x0ffffff0U
+#define PBL_FIFO_PERR_SET0_S 12
+#define PBL_FIFO_PERR_SET0_V(x) ((x) << PBL_FIFO_PERR_SET0_S)
+#define PBL_FIFO_PERR_SET0_F PBL_FIFO_PERR_SET0_V(1U)
-#define OESPI_PAR_ERROR_S 3
-#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
-#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
+#define CMD_FIFO_PERR_SET3_S 11
+#define CMD_FIFO_PERR_SET3_V(x) ((x) << CMD_FIFO_PERR_SET3_S)
+#define CMD_FIFO_PERR_SET3_F CMD_FIFO_PERR_SET3_V(1U)
-#define ICSPI_PAR_ERROR_S 1
-#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
-#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
+#define CMD_FIFO_PERR_SET2_S 10
+#define CMD_FIFO_PERR_SET2_V(x) ((x) << CMD_FIFO_PERR_SET2_S)
+#define CMD_FIFO_PERR_SET2_F CMD_FIFO_PERR_SET2_V(1U)
-#define PMTX_C_PCMD_PAR_ERROR_S 0
-#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
-#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
+#define CMD_FIFO_PERR_SET1_S 9
+#define CMD_FIFO_PERR_SET1_V(x) ((x) << CMD_FIFO_PERR_SET1_S)
+#define CMD_FIFO_PERR_SET1_F CMD_FIFO_PERR_SET1_V(1U)
-#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
-#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
-#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
-#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
-#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
-#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
-#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
-#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
-#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
-#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
-#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
-#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
-#define MPS_PORT_STAT_TX_PORT_64B_L 0x430
-#define MPS_PORT_STAT_TX_PORT_64B_H 0x434
-#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
-#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
-#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
-#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
-#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
-#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
-#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
-#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
-#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
-#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
-#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
-#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
-#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
-#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
-#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
-#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
-#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
-#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
-#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
-#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
-#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
-#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
-#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
-#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
-#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
-#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
-#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
-#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
-#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
-#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
-#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
-#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
-#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
-#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
-#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
-#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
-#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
-#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
-#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
-#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
-#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
-#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
-#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
-#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
-#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
-#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
-#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
-#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
-#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
-#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
-#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
-#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
-#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
-#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
-#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
-#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
-#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
-#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
-#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
-#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
-#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
-#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
-#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
-#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
-#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
-#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
-#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
-#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
-#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
-#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
-#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
-#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
-#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
-#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
-#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
-#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
-#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
-#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
-#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
-#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
-#define MPS_PORT_STAT_RX_PORT_64B_L 0x590
-#define MPS_PORT_STAT_RX_PORT_64B_H 0x594
-#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
-#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
-#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
-#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
-#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
-#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
-#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
-#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
-#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
-#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
-#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
-#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
-#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
-#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
-#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
-#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
-#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
-#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
-#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
-#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
-#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
-#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
-#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
-#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
-#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
-#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
-#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
-#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
-#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
-#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
-#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
-#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
-#define MAC_PORT_MAGIC_MACID_LO 0x824
-#define MAC_PORT_MAGIC_MACID_HI 0x828
-#define MAC_PORT_TX_TS_VAL_LO 0x928
-#define MAC_PORT_TX_TS_VAL_HI 0x92c
+#define CMD_FIFO_PERR_SET0_S 8
+#define CMD_FIFO_PERR_SET0_V(x) ((x) << CMD_FIFO_PERR_SET0_S)
+#define CMD_FIFO_PERR_SET0_F CMD_FIFO_PERR_SET0_V(1U)
-#define MAC_PORT_EPIO_DATA0_A 0x8c0
-#define MAC_PORT_EPIO_DATA1_A 0x8c4
-#define MAC_PORT_EPIO_DATA2_A 0x8c8
-#define MAC_PORT_EPIO_DATA3_A 0x8cc
-#define MAC_PORT_EPIO_OP_A 0x8d0
+#define LSO_HDR_SRAM_PERR_SET3_S 7
+#define LSO_HDR_SRAM_PERR_SET3_V(x) ((x) << LSO_HDR_SRAM_PERR_SET3_S)
+#define LSO_HDR_SRAM_PERR_SET3_F LSO_HDR_SRAM_PERR_SET3_V(1U)
-#define MAC_PORT_CFG2_A 0x818
+#define LSO_HDR_SRAM_PERR_SET2_S 6
+#define LSO_HDR_SRAM_PERR_SET2_V(x) ((x) << LSO_HDR_SRAM_PERR_SET2_S)
+#define LSO_HDR_SRAM_PERR_SET2_F LSO_HDR_SRAM_PERR_SET2_V(1U)
-#define MAC_PORT_PTP_SUM_LO_A 0x990
-#define MAC_PORT_PTP_SUM_HI_A 0x994
+#define LSO_HDR_SRAM_PERR_SET1_S 5
+#define LSO_HDR_SRAM_PERR_SET1_V(x) ((x) << LSO_HDR_SRAM_PERR_SET1_S)
+#define LSO_HDR_SRAM_PERR_SET1_F LSO_HDR_SRAM_PERR_SET1_V(1U)
-#define MPS_CMN_CTL_A 0x9000
+#define LSO_HDR_SRAM_PERR_SET0_S 4
+#define LSO_HDR_SRAM_PERR_SET0_V(x) ((x) << LSO_HDR_SRAM_PERR_SET0_S)
+#define LSO_HDR_SRAM_PERR_SET0_F LSO_HDR_SRAM_PERR_SET0_V(1U)
-#define COUNTPAUSEMCRX_S 5
-#define COUNTPAUSEMCRX_V(x) ((x) << COUNTPAUSEMCRX_S)
-#define COUNTPAUSEMCRX_F COUNTPAUSEMCRX_V(1U)
+#define ULP_TX_INT_ENABLE_1_A 0x8dc8
+#define ULP_TX_INT_CAUSE_1_A 0x8dcc
-#define COUNTPAUSESTATRX_S 4
-#define COUNTPAUSESTATRX_V(x) ((x) << COUNTPAUSESTATRX_S)
-#define COUNTPAUSESTATRX_F COUNTPAUSESTATRX_V(1U)
+#define TLS_DSGL_PARERR3_S 3
+#define TLS_DSGL_PARERR3_V(x) ((x) << TLS_DSGL_PARERR3_S)
+#define TLS_DSGL_PARERR3_F TLS_DSGL_PARERR3_V(1U)
-#define COUNTPAUSEMCTX_S 3
-#define COUNTPAUSEMCTX_V(x) ((x) << COUNTPAUSEMCTX_S)
-#define COUNTPAUSEMCTX_F COUNTPAUSEMCTX_V(1U)
+#define TLS_DSGL_PARERR2_S 2
+#define TLS_DSGL_PARERR2_V(x) ((x) << TLS_DSGL_PARERR2_S)
+#define TLS_DSGL_PARERR2_F TLS_DSGL_PARERR2_V(1U)
-#define COUNTPAUSESTATTX_S 2
-#define COUNTPAUSESTATTX_V(x) ((x) << COUNTPAUSESTATTX_S)
+#define TLS_DSGL_PARERR1_S 1
+#define TLS_DSGL_PARERR1_V(x) ((x) << TLS_DSGL_PARERR1_S)
+#define TLS_DSGL_PARERR1_F TLS_DSGL_PARERR1_V(1U)
+
+#define TLS_DSGL_PARERR0_S 0
+#define TLS_DSGL_PARERR0_V(x) ((x) << TLS_DSGL_PARERR0_S)
+#define TLS_DSGL_PARERR0_F TLS_DSGL_PARERR0_V(1U)
+
+#define ULP_TX_TPT_LLIMIT_A 0x8dd4
+#define ULP_TX_TPT_ULIMIT_A 0x8dd8
+#define ULP_TX_PBL_LLIMIT_A 0x8ddc
+#define ULP_TX_PBL_ULIMIT_A 0x8de0
+#define ULP_TX_ERR_TABLE_BASE_A 0x8e04
+
+#define GF_SGE_FIFO_PARERR3_S 31
+#define GF_SGE_FIFO_PARERR3_V(x) ((x) << GF_SGE_FIFO_PARERR3_S)
+#define GF_SGE_FIFO_PARERR3_F GF_SGE_FIFO_PARERR3_V(1U)
+
+#define GF_SGE_FIFO_PARERR2_S 30
+#define GF_SGE_FIFO_PARERR2_V(x) ((x) << GF_SGE_FIFO_PARERR2_S)
+#define GF_SGE_FIFO_PARERR2_F GF_SGE_FIFO_PARERR2_V(1U)
+
+#define GF_SGE_FIFO_PARERR1_S 29
+#define GF_SGE_FIFO_PARERR1_V(x) ((x) << GF_SGE_FIFO_PARERR1_S)
+#define GF_SGE_FIFO_PARERR1_F GF_SGE_FIFO_PARERR1_V(1U)
+
+#define GF_SGE_FIFO_PARERR0_S 28
+#define GF_SGE_FIFO_PARERR0_V(x) ((x) << GF_SGE_FIFO_PARERR0_S)
+#define GF_SGE_FIFO_PARERR0_F GF_SGE_FIFO_PARERR0_V(1U)
+
+#define DEDUPE_SGE_FIFO_PARERR3_S 27
+#define DEDUPE_SGE_FIFO_PARERR3_V(x) ((x) << DEDUPE_SGE_FIFO_PARERR3_S)
+#define DEDUPE_SGE_FIFO_PARERR3_F DEDUPE_SGE_FIFO_PARERR3_V(1U)
+
+#define DEDUPE_SGE_FIFO_PARERR2_S 26
+#define DEDUPE_SGE_FIFO_PARERR2_V(x) ((x) << DEDUPE_SGE_FIFO_PARERR2_S)
+#define DEDUPE_SGE_FIFO_PARERR2_F DEDUPE_SGE_FIFO_PARERR2_V(1U)
+
+#define DEDUPE_SGE_FIFO_PARERR1_S 25
+#define DEDUPE_SGE_FIFO_PARERR1_V(x) ((x) << DEDUPE_SGE_FIFO_PARERR1_S)
+#define DEDUPE_SGE_FIFO_PARERR1_F DEDUPE_SGE_FIFO_PARERR1_V(1U)
+
+#define DEDUPE_SGE_FIFO_PARERR0_S 24
+#define DEDUPE_SGE_FIFO_PARERR0_V(x) ((x) << DEDUPE_SGE_FIFO_PARERR0_S)
+#define DEDUPE_SGE_FIFO_PARERR0_F DEDUPE_SGE_FIFO_PARERR0_V(1U)
+
+#define GF3_DSGL_FIFO_PARERR_S 23
+#define GF3_DSGL_FIFO_PARERR_V(x) ((x) << GF3_DSGL_FIFO_PARERR_S)
+#define GF3_DSGL_FIFO_PARERR_F GF3_DSGL_FIFO_PARERR_V(1U)
+
+#define GF2_DSGL_FIFO_PARERR_S 22
+#define GF2_DSGL_FIFO_PARERR_V(x) ((x) << GF2_DSGL_FIFO_PARERR_S)
+#define GF2_DSGL_FIFO_PARERR_F GF2_DSGL_FIFO_PARERR_V(1U)
+
+#define GF1_DSGL_FIFO_PARERR_S 21
+#define GF1_DSGL_FIFO_PARERR_V(x) ((x) << GF1_DSGL_FIFO_PARERR_S)
+#define GF1_DSGL_FIFO_PARERR_F GF1_DSGL_FIFO_PARERR_V(1U)
+
+#define GF0_DSGL_FIFO_PARERR_S 20
+#define GF0_DSGL_FIFO_PARERR_V(x) ((x) << GF0_DSGL_FIFO_PARERR_S)
+#define GF0_DSGL_FIFO_PARERR_F GF0_DSGL_FIFO_PARERR_V(1U)
+
+#define DEDUPE3_DSGL_FIFO_PARERR_S 19
+#define DEDUPE3_DSGL_FIFO_PARERR_V(x) ((x) << DEDUPE3_DSGL_FIFO_PARERR_S)
+#define DEDUPE3_DSGL_FIFO_PARERR_F DEDUPE3_DSGL_FIFO_PARERR_V(1U)
+
+#define DEDUPE2_DSGL_FIFO_PARERR_S 18
+#define DEDUPE2_DSGL_FIFO_PARERR_V(x) ((x) << DEDUPE2_DSGL_FIFO_PARERR_S)
+#define DEDUPE2_DSGL_FIFO_PARERR_F DEDUPE2_DSGL_FIFO_PARERR_V(1U)
+
+#define DEDUPE1_DSGL_FIFO_PARERR_S 17
+#define DEDUPE1_DSGL_FIFO_PARERR_V(x) ((x) << DEDUPE1_DSGL_FIFO_PARERR_S)
+#define DEDUPE1_DSGL_FIFO_PARERR_F DEDUPE1_DSGL_FIFO_PARERR_V(1U)
+
+#define DEDUPE0_DSGL_FIFO_PARERR_S 16
+#define DEDUPE0_DSGL_FIFO_PARERR_V(x) ((x) << DEDUPE0_DSGL_FIFO_PARERR_S)
+#define DEDUPE0_DSGL_FIFO_PARERR_F DEDUPE0_DSGL_FIFO_PARERR_V(1U)
+
+#define XP10_SGE_FIFO_PARERR_S 15
+#define XP10_SGE_FIFO_PARERR_V(x) ((x) << XP10_SGE_FIFO_PARERR_S)
+#define XP10_SGE_FIFO_PARERR_F XP10_SGE_FIFO_PARERR_V(1U)
+
+#define DSGL_PAR_ERR_S 14
+#define DSGL_PAR_ERR_V(x) ((x) << DSGL_PAR_ERR_S)
+#define DSGL_PAR_ERR_F DSGL_PAR_ERR_V(1U)
+
+#define CDDIP_INT_S 13
+#define CDDIP_INT_V(x) ((x) << CDDIP_INT_S)
+#define CDDIP_INT_F CDDIP_INT_V(1U)
+
+#define CCEIP_INT_S 12
+#define CCEIP_INT_V(x) ((x) << CCEIP_INT_S)
+#define CCEIP_INT_F CCEIP_INT_V(1U)
+
+#define TLS_SGE_FIFO_PARERR3_S 11
+#define TLS_SGE_FIFO_PARERR3_V(x) ((x) << TLS_SGE_FIFO_PARERR3_S)
+#define TLS_SGE_FIFO_PARERR3_F TLS_SGE_FIFO_PARERR3_V(1U)
+
+#define TLS_SGE_FIFO_PARERR2_S 10
+#define TLS_SGE_FIFO_PARERR2_V(x) ((x) << TLS_SGE_FIFO_PARERR2_S)
+#define TLS_SGE_FIFO_PARERR2_F TLS_SGE_FIFO_PARERR2_V(1U)
+
+#define TLS_SGE_FIFO_PARERR1_S 9
+#define TLS_SGE_FIFO_PARERR1_V(x) ((x) << TLS_SGE_FIFO_PARERR1_S)
+#define TLS_SGE_FIFO_PARERR1_F TLS_SGE_FIFO_PARERR1_V(1U)
+
+#define TLS_SGE_FIFO_PARERR0_S 8
+#define TLS_SGE_FIFO_PARERR0_V(x) ((x) << TLS_SGE_FIFO_PARERR0_S)
+#define TLS_SGE_FIFO_PARERR0_F TLS_SGE_FIFO_PARERR0_V(1U)
+
+#define ULP2SMARBT_RSP_PERR_S 6
+#define ULP2SMARBT_RSP_PERR_V(x) ((x) << ULP2SMARBT_RSP_PERR_S)
+#define ULP2SMARBT_RSP_PERR_F ULP2SMARBT_RSP_PERR_V(1U)
+
+#define ULPTX2MA_RSP_PERR_S 5
+#define ULPTX2MA_RSP_PERR_V(x) ((x) << ULPTX2MA_RSP_PERR_S)
+#define ULPTX2MA_RSP_PERR_F ULPTX2MA_RSP_PERR_V(1U)
+
+#define PCIE2ULP_PERR3_S 4
+#define PCIE2ULP_PERR3_V(x) ((x) << PCIE2ULP_PERR3_S)
+#define PCIE2ULP_PERR3_F PCIE2ULP_PERR3_V(1U)
+
+#define PCIE2ULP_PERR2_S 3
+#define PCIE2ULP_PERR2_V(x) ((x) << PCIE2ULP_PERR2_S)
+#define PCIE2ULP_PERR2_F PCIE2ULP_PERR2_V(1U)
+
+#define PCIE2ULP_PERR1_S 2
+#define PCIE2ULP_PERR1_V(x) ((x) << PCIE2ULP_PERR1_S)
+#define PCIE2ULP_PERR1_F PCIE2ULP_PERR1_V(1U)
+
+#define PCIE2ULP_PERR0_S 1
+#define PCIE2ULP_PERR0_V(x) ((x) << PCIE2ULP_PERR0_S)
+#define PCIE2ULP_PERR0_F PCIE2ULP_PERR0_V(1U)
+
+#define CIM2ULP_PERR_S 0
+#define CIM2ULP_PERR_V(x) ((x) << CIM2ULP_PERR_S)
+#define CIM2ULP_PERR_F CIM2ULP_PERR_V(1U)
+
+#define ULP_TX_INT_ENABLE_4_A 0x8e94
+#define ULP_TX_INT_CAUSE_4_A 0x8e98
+
+#define XP10_2_ULP_PERR_S 7
+#define XP10_2_ULP_PERR_V(x) ((x) << XP10_2_ULP_PERR_S)
+#define XP10_2_ULP_PERR_F XP10_2_ULP_PERR_V(1U)
+
+#define ULP_2_XP10_PERR_S 6
+#define ULP_2_XP10_PERR_V(x) ((x) << ULP_2_XP10_PERR_S)
+#define ULP_2_XP10_PERR_F ULP_2_XP10_PERR_V(1U)
+
+#define CMD_FIFO_LB1_S 5
+#define CMD_FIFO_LB1_V(x) ((x) << CMD_FIFO_LB1_S)
+#define CMD_FIFO_LB1_F CMD_FIFO_LB1_V(1U)
+
+#define CMD_FIFO_LB0_S 4
+#define CMD_FIFO_LB0_V(x) ((x) << CMD_FIFO_LB0_S)
+#define CMD_FIFO_LB0_F CMD_FIFO_LB0_V(1U)
+
+#define TF_TP_PERR_S 3
+#define TF_TP_PERR_V(x) ((x) << TF_TP_PERR_S)
+#define TF_TP_PERR_F TF_TP_PERR_V(1U)
+
+#define TF_SGE_PERR_S 2
+#define TF_SGE_PERR_V(x) ((x) << TF_SGE_PERR_S)
+#define TF_SGE_PERR_F TF_SGE_PERR_V(1U)
+
+#define TF_MEM_PERR_S 1
+#define TF_MEM_PERR_V(x) ((x) << TF_MEM_PERR_S)
+#define TF_MEM_PERR_F TF_MEM_PERR_V(1U)
+
+#define TF_MP_PERR_S 0
+#define TF_MP_PERR_V(x) ((x) << TF_MP_PERR_S)
+#define TF_MP_PERR_F TF_MP_PERR_V(1U)
+
+#define ULP_TX_INT_ENABLE_5_A 0x8ec4
+#define ULP_TX_INT_CAUSE_5_A 0x8ec8
+
+#define DEDUPE_PERR3_S 23
+#define DEDUPE_PERR3_V(x) ((x) << DEDUPE_PERR3_S)
+#define DEDUPE_PERR3_F DEDUPE_PERR3_V(1U)
+
+#define DEDUPE_PERR2_S 22
+#define DEDUPE_PERR2_V(x) ((x) << DEDUPE_PERR2_S)
+#define DEDUPE_PERR2_F DEDUPE_PERR2_V(1U)
+
+#define DEDUPE_PERR1_S 21
+#define DEDUPE_PERR1_V(x) ((x) << DEDUPE_PERR1_S)
+#define DEDUPE_PERR1_F DEDUPE_PERR1_V(1U)
+
+#define DEDUPE_PERR0_S 20
+#define DEDUPE_PERR0_V(x) ((x) << DEDUPE_PERR0_S)
+#define DEDUPE_PERR0_F DEDUPE_PERR0_V(1U)
+
+#define GF_PERR3_S 19
+#define GF_PERR3_V(x) ((x) << GF_PERR3_S)
+#define GF_PERR3_F GF_PERR3_V(1U)
+
+#define GF_PERR2_S 18
+#define GF_PERR2_V(x) ((x) << GF_PERR2_S)
+#define GF_PERR2_F GF_PERR2_V(1U)
+
+#define GF_PERR1_S 17
+#define GF_PERR1_V(x) ((x) << GF_PERR1_S)
+#define GF_PERR1_F GF_PERR1_V(1U)
+
+#define GF_PERR0_S 16
+#define GF_PERR0_V(x) ((x) << GF_PERR0_S)
+#define GF_PERR0_F GF_PERR0_V(1U)
+
+#define SGE2ULP_INV_PERR_S 13
+#define SGE2ULP_INV_PERR_V(x) ((x) << SGE2ULP_INV_PERR_S)
+#define SGE2ULP_INV_PERR_F SGE2ULP_INV_PERR_V(1U)
+
+#define T7_PL_BUSPERR_S 12
+#define T7_PL_BUSPERR_V(x) ((x) << T7_PL_BUSPERR_S)
+#define T7_PL_BUSPERR_F T7_PL_BUSPERR_V(1U)
+
+#define TLSTX2ULPTX_PERR3_S 11
+#define TLSTX2ULPTX_PERR3_V(x) ((x) << TLSTX2ULPTX_PERR3_S)
+#define TLSTX2ULPTX_PERR3_F TLSTX2ULPTX_PERR3_V(1U)
+
+#define TLSTX2ULPTX_PERR2_S 10
+#define TLSTX2ULPTX_PERR2_V(x) ((x) << TLSTX2ULPTX_PERR2_S)
+#define TLSTX2ULPTX_PERR2_F TLSTX2ULPTX_PERR2_V(1U)
+
+#define TLSTX2ULPTX_PERR1_S 9
+#define TLSTX2ULPTX_PERR1_V(x) ((x) << TLSTX2ULPTX_PERR1_S)
+#define TLSTX2ULPTX_PERR1_F TLSTX2ULPTX_PERR1_V(1U)
+
+#define TLSTX2ULPTX_PERR0_S 8
+#define TLSTX2ULPTX_PERR0_V(x) ((x) << TLSTX2ULPTX_PERR0_S)
+#define TLSTX2ULPTX_PERR0_F TLSTX2ULPTX_PERR0_V(1U)
+
+#define XP10_2_ULP_PL_PERR_S 1
+#define XP10_2_ULP_PL_PERR_V(x) ((x) << XP10_2_ULP_PL_PERR_S)
+#define XP10_2_ULP_PL_PERR_F XP10_2_ULP_PL_PERR_V(1U)
+
+#define ULP_2_XP10_PL_PERR_S 0
+#define ULP_2_XP10_PL_PERR_V(x) ((x) << ULP_2_XP10_PL_PERR_S)
+#define ULP_2_XP10_PL_PERR_F ULP_2_XP10_PL_PERR_V(1U)
+
+#define ULP_TX_INT_CAUSE_6_A 0x8ed0
+#define ULP_TX_INT_ENABLE_6_A 0x8ed4
+
+#define DDR_HDR_FIFO_PERR_SET3_S 12
+#define DDR_HDR_FIFO_PERR_SET3_V(x) ((x) << DDR_HDR_FIFO_PERR_SET3_S)
+#define DDR_HDR_FIFO_PERR_SET3_F DDR_HDR_FIFO_PERR_SET3_V(1U)
+
+#define DDR_HDR_FIFO_PERR_SET2_S 11
+#define DDR_HDR_FIFO_PERR_SET2_V(x) ((x) << DDR_HDR_FIFO_PERR_SET2_S)
+#define DDR_HDR_FIFO_PERR_SET2_F DDR_HDR_FIFO_PERR_SET2_V(1U)
+
+#define DDR_HDR_FIFO_PERR_SET1_S 10
+#define DDR_HDR_FIFO_PERR_SET1_V(x) ((x) << DDR_HDR_FIFO_PERR_SET1_S)
+#define DDR_HDR_FIFO_PERR_SET1_F DDR_HDR_FIFO_PERR_SET1_V(1U)
+
+#define DDR_HDR_FIFO_PERR_SET0_S 9
+#define DDR_HDR_FIFO_PERR_SET0_V(x) ((x) << DDR_HDR_FIFO_PERR_SET0_S)
+#define DDR_HDR_FIFO_PERR_SET0_F DDR_HDR_FIFO_PERR_SET0_V(1U)
+
+#define PRE_MP_RSP_PERR_SET3_S 8
+#define PRE_MP_RSP_PERR_SET3_V(x) ((x) << PRE_MP_RSP_PERR_SET3_S)
+#define PRE_MP_RSP_PERR_SET3_F PRE_MP_RSP_PERR_SET3_V(1U)
+
+#define PRE_MP_RSP_PERR_SET2_S 7
+#define PRE_MP_RSP_PERR_SET2_V(x) ((x) << PRE_MP_RSP_PERR_SET2_S)
+#define PRE_MP_RSP_PERR_SET2_F PRE_MP_RSP_PERR_SET2_V(1U)
+
+#define PRE_MP_RSP_PERR_SET1_S 6
+#define PRE_MP_RSP_PERR_SET1_V(x) ((x) << PRE_MP_RSP_PERR_SET1_S)
+#define PRE_MP_RSP_PERR_SET1_F PRE_MP_RSP_PERR_SET1_V(1U)
+
+#define PRE_MP_RSP_PERR_SET0_S 5
+#define PRE_MP_RSP_PERR_SET0_V(x) ((x) << PRE_MP_RSP_PERR_SET0_S)
+#define PRE_MP_RSP_PERR_SET0_F PRE_MP_RSP_PERR_SET0_V(1U)
+
+#define PRE_CQE_FIFO_PERR_SET3_S 4
+#define PRE_CQE_FIFO_PERR_SET3_V(x) ((x) << PRE_CQE_FIFO_PERR_SET3_S)
+#define PRE_CQE_FIFO_PERR_SET3_F PRE_CQE_FIFO_PERR_SET3_V(1U)
+
+#define PRE_CQE_FIFO_PERR_SET2_S 3
+#define PRE_CQE_FIFO_PERR_SET2_V(x) ((x) << PRE_CQE_FIFO_PERR_SET2_S)
+#define PRE_CQE_FIFO_PERR_SET2_F PRE_CQE_FIFO_PERR_SET2_V(1U)
+
+#define PRE_CQE_FIFO_PERR_SET1_S 2
+#define PRE_CQE_FIFO_PERR_SET1_V(x) ((x) << PRE_CQE_FIFO_PERR_SET1_S)
+#define PRE_CQE_FIFO_PERR_SET1_F PRE_CQE_FIFO_PERR_SET1_V(1U)
+
+#define PRE_CQE_FIFO_PERR_SET0_S 1
+#define PRE_CQE_FIFO_PERR_SET0_V(x) ((x) << PRE_CQE_FIFO_PERR_SET0_S)
+#define PRE_CQE_FIFO_PERR_SET0_F PRE_CQE_FIFO_PERR_SET0_V(1U)
+
+#define RSP_FIFO_PERR_SET_S 0
+#define RSP_FIFO_PERR_SET_V(x) ((x) << RSP_FIFO_PERR_SET_S)
+#define RSP_FIFO_PERR_SET_F RSP_FIFO_PERR_SET_V(1U)
+
+#define ULP_TX_INT_CAUSE_7_A 0x8edc
+#define ULP_TX_INT_ENABLE_7_A 0x8ee0
+
+#define TLS_SGE_FIFO_CORERR3_S 23
+#define TLS_SGE_FIFO_CORERR3_V(x) ((x) << TLS_SGE_FIFO_CORERR3_S)
+#define TLS_SGE_FIFO_CORERR3_F TLS_SGE_FIFO_CORERR3_V(1U)
+
+#define TLS_SGE_FIFO_CORERR2_S 22
+#define TLS_SGE_FIFO_CORERR2_V(x) ((x) << TLS_SGE_FIFO_CORERR2_S)
+#define TLS_SGE_FIFO_CORERR2_F TLS_SGE_FIFO_CORERR2_V(1U)
+
+#define TLS_SGE_FIFO_CORERR1_S 21
+#define TLS_SGE_FIFO_CORERR1_V(x) ((x) << TLS_SGE_FIFO_CORERR1_S)
+#define TLS_SGE_FIFO_CORERR1_F TLS_SGE_FIFO_CORERR1_V(1U)
+
+#define TLS_SGE_FIFO_CORERR0_S 20
+#define TLS_SGE_FIFO_CORERR0_V(x) ((x) << TLS_SGE_FIFO_CORERR0_S)
+#define TLS_SGE_FIFO_CORERR0_F TLS_SGE_FIFO_CORERR0_V(1U)
+
+#define LSO_HDR_SRAM_CERR_SET3_S 19
+#define LSO_HDR_SRAM_CERR_SET3_V(x) ((x) << LSO_HDR_SRAM_CERR_SET3_S)
+#define LSO_HDR_SRAM_CERR_SET3_F LSO_HDR_SRAM_CERR_SET3_V(1U)
+
+#define LSO_HDR_SRAM_CERR_SET2_S 18
+#define LSO_HDR_SRAM_CERR_SET2_V(x) ((x) << LSO_HDR_SRAM_CERR_SET2_S)
+#define LSO_HDR_SRAM_CERR_SET2_F LSO_HDR_SRAM_CERR_SET2_V(1U)
+
+#define LSO_HDR_SRAM_CERR_SET1_S 17
+#define LSO_HDR_SRAM_CERR_SET1_V(x) ((x) << LSO_HDR_SRAM_CERR_SET1_S)
+#define LSO_HDR_SRAM_CERR_SET1_F LSO_HDR_SRAM_CERR_SET1_V(1U)
+
+#define LSO_HDR_SRAM_CERR_SET0_S 16
+#define LSO_HDR_SRAM_CERR_SET0_V(x) ((x) << LSO_HDR_SRAM_CERR_SET0_S)
+#define LSO_HDR_SRAM_CERR_SET0_F LSO_HDR_SRAM_CERR_SET0_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH3_LB1_S 15
+#define CORE_CMD_FIFO_CERR_SET_CH3_LB1_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH3_LB1_S)
+#define CORE_CMD_FIFO_CERR_SET_CH3_LB1_F CORE_CMD_FIFO_CERR_SET_CH3_LB1_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH2_LB1_S 14
+#define CORE_CMD_FIFO_CERR_SET_CH2_LB1_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH2_LB1_S)
+#define CORE_CMD_FIFO_CERR_SET_CH2_LB1_F CORE_CMD_FIFO_CERR_SET_CH2_LB1_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH1_LB1_S 13
+#define CORE_CMD_FIFO_CERR_SET_CH1_LB1_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH1_LB1_S)
+#define CORE_CMD_FIFO_CERR_SET_CH1_LB1_F CORE_CMD_FIFO_CERR_SET_CH1_LB1_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH0_LB1_S 12
+#define CORE_CMD_FIFO_CERR_SET_CH0_LB1_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH0_LB1_S)
+#define CORE_CMD_FIFO_CERR_SET_CH0_LB1_F CORE_CMD_FIFO_CERR_SET_CH0_LB1_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH3_LB0_S 11
+#define CORE_CMD_FIFO_CERR_SET_CH3_LB0_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH3_LB0_S)
+#define CORE_CMD_FIFO_CERR_SET_CH3_LB0_F CORE_CMD_FIFO_CERR_SET_CH3_LB0_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH2_LB0_S 10
+#define CORE_CMD_FIFO_CERR_SET_CH2_LB0_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH2_LB0_S)
+#define CORE_CMD_FIFO_CERR_SET_CH2_LB0_F CORE_CMD_FIFO_CERR_SET_CH2_LB0_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH1_LB0_S 9
+#define CORE_CMD_FIFO_CERR_SET_CH1_LB0_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH1_LB0_S)
+#define CORE_CMD_FIFO_CERR_SET_CH1_LB0_F CORE_CMD_FIFO_CERR_SET_CH1_LB0_V(1U)
+
+#define CORE_CMD_FIFO_CERR_SET_CH0_LB0_S 8
+#define CORE_CMD_FIFO_CERR_SET_CH0_LB0_V(x) ((x) << CORE_CMD_FIFO_CERR_SET_CH0_LB0_S)
+#define CORE_CMD_FIFO_CERR_SET_CH0_LB0_F CORE_CMD_FIFO_CERR_SET_CH0_LB0_V(1U)
+
+#define CQE_FIFO_CERR_SET3_S 7
+#define CQE_FIFO_CERR_SET3_V(x) ((x) << CQE_FIFO_CERR_SET3_S)
+#define CQE_FIFO_CERR_SET3_F CQE_FIFO_CERR_SET3_V(1U)
+
+#define CQE_FIFO_CERR_SET2_S 6
+#define CQE_FIFO_CERR_SET2_V(x) ((x) << CQE_FIFO_CERR_SET2_S)
+#define CQE_FIFO_CERR_SET2_F CQE_FIFO_CERR_SET2_V(1U)
+
+#define CQE_FIFO_CERR_SET1_S 5
+#define CQE_FIFO_CERR_SET1_V(x) ((x) << CQE_FIFO_CERR_SET1_S)
+#define CQE_FIFO_CERR_SET1_F CQE_FIFO_CERR_SET1_V(1U)
+
+#define CQE_FIFO_CERR_SET0_S 4
+#define CQE_FIFO_CERR_SET0_V(x) ((x) << CQE_FIFO_CERR_SET0_S)
+#define CQE_FIFO_CERR_SET0_F CQE_FIFO_CERR_SET0_V(1U)
+
+#define PRE_CQE_FIFO_CERR_SET3_S 3
+#define PRE_CQE_FIFO_CERR_SET3_V(x) ((x) << PRE_CQE_FIFO_CERR_SET3_S)
+#define PRE_CQE_FIFO_CERR_SET3_F PRE_CQE_FIFO_CERR_SET3_V(1U)
+
+#define PRE_CQE_FIFO_CERR_SET2_S 2
+#define PRE_CQE_FIFO_CERR_SET2_V(x) ((x) << PRE_CQE_FIFO_CERR_SET2_S)
+#define PRE_CQE_FIFO_CERR_SET2_F PRE_CQE_FIFO_CERR_SET2_V(1U)
+
+#define PRE_CQE_FIFO_CERR_SET1_S 1
+#define PRE_CQE_FIFO_CERR_SET1_V(x) ((x) << PRE_CQE_FIFO_CERR_SET1_S)
+#define PRE_CQE_FIFO_CERR_SET1_F PRE_CQE_FIFO_CERR_SET1_V(1U)
+
+#define PRE_CQE_FIFO_CERR_SET0_S 0
+#define PRE_CQE_FIFO_CERR_SET0_V(x) ((x) << PRE_CQE_FIFO_CERR_SET0_S)
+#define PRE_CQE_FIFO_CERR_SET0_F PRE_CQE_FIFO_CERR_SET0_V(1U)
+
+#define ULP_TX_INT_CAUSE_8_A 0x8ee4
+#define ULP_TX_INT_ENABLE_8_A 0x8ee8
+
+#define MEM_RSP_FIFO_CERR_SET3_S 28
+#define MEM_RSP_FIFO_CERR_SET3_V(x) ((x) << MEM_RSP_FIFO_CERR_SET3_S)
+#define MEM_RSP_FIFO_CERR_SET3_F MEM_RSP_FIFO_CERR_SET3_V(1U)
+
+#define MEM_RSP_FIFO_CERR_SET2_S 27
+#define MEM_RSP_FIFO_CERR_SET2_V(x) ((x) << MEM_RSP_FIFO_CERR_SET2_S)
+#define MEM_RSP_FIFO_CERR_SET2_F MEM_RSP_FIFO_CERR_SET2_V(1U)
+
+#define MEM_RSP_FIFO_CERR_SET1_S 26
+#define MEM_RSP_FIFO_CERR_SET1_V(x) ((x) << MEM_RSP_FIFO_CERR_SET1_S)
+#define MEM_RSP_FIFO_CERR_SET1_F MEM_RSP_FIFO_CERR_SET1_V(1U)
+
+#define MEM_RSP_FIFO_CERR_SET0_S 25
+#define MEM_RSP_FIFO_CERR_SET0_V(x) ((x) << MEM_RSP_FIFO_CERR_SET0_S)
+#define MEM_RSP_FIFO_CERR_SET0_F MEM_RSP_FIFO_CERR_SET0_V(1U)
+
+#define PI_SRAM_CERR_SET3_S 24
+#define PI_SRAM_CERR_SET3_V(x) ((x) << PI_SRAM_CERR_SET3_S)
+#define PI_SRAM_CERR_SET3_F PI_SRAM_CERR_SET3_V(1U)
+
+#define PI_SRAM_CERR_SET2_S 23
+#define PI_SRAM_CERR_SET2_V(x) ((x) << PI_SRAM_CERR_SET2_S)
+#define PI_SRAM_CERR_SET2_F PI_SRAM_CERR_SET2_V(1U)
+
+#define PI_SRAM_CERR_SET1_S 22
+#define PI_SRAM_CERR_SET1_V(x) ((x) << PI_SRAM_CERR_SET1_S)
+#define PI_SRAM_CERR_SET1_F PI_SRAM_CERR_SET1_V(1U)
+
+#define PI_SRAM_CERR_SET0_S 21
+#define PI_SRAM_CERR_SET0_V(x) ((x) << PI_SRAM_CERR_SET0_S)
+#define PI_SRAM_CERR_SET0_F PI_SRAM_CERR_SET0_V(1U)
+
+#define PRE_MP_RSP_CERR_SET3_S 20
+#define PRE_MP_RSP_CERR_SET3_V(x) ((x) << PRE_MP_RSP_CERR_SET3_S)
+#define PRE_MP_RSP_CERR_SET3_F PRE_MP_RSP_CERR_SET3_V(1U)
+
+#define PRE_MP_RSP_CERR_SET2_S 19
+#define PRE_MP_RSP_CERR_SET2_V(x) ((x) << PRE_MP_RSP_CERR_SET2_S)
+#define PRE_MP_RSP_CERR_SET2_F PRE_MP_RSP_CERR_SET2_V(1U)
+
+#define PRE_MP_RSP_CERR_SET1_S 18
+#define PRE_MP_RSP_CERR_SET1_V(x) ((x) << PRE_MP_RSP_CERR_SET1_S)
+#define PRE_MP_RSP_CERR_SET1_F PRE_MP_RSP_CERR_SET1_V(1U)
+
+#define PRE_MP_RSP_CERR_SET0_S 17
+#define PRE_MP_RSP_CERR_SET0_V(x) ((x) << PRE_MP_RSP_CERR_SET0_S)
+#define PRE_MP_RSP_CERR_SET0_F PRE_MP_RSP_CERR_SET0_V(1U)
+
+#define DDR_HDR_FIFO_CERR_SET3_S 16
+#define DDR_HDR_FIFO_CERR_SET3_V(x) ((x) << DDR_HDR_FIFO_CERR_SET3_S)
+#define DDR_HDR_FIFO_CERR_SET3_F DDR_HDR_FIFO_CERR_SET3_V(1U)
+
+#define DDR_HDR_FIFO_CERR_SET2_S 15
+#define DDR_HDR_FIFO_CERR_SET2_V(x) ((x) << DDR_HDR_FIFO_CERR_SET2_S)
+#define DDR_HDR_FIFO_CERR_SET2_F DDR_HDR_FIFO_CERR_SET2_V(1U)
+
+#define DDR_HDR_FIFO_CERR_SET1_S 14
+#define DDR_HDR_FIFO_CERR_SET1_V(x) ((x) << DDR_HDR_FIFO_CERR_SET1_S)
+#define DDR_HDR_FIFO_CERR_SET1_F DDR_HDR_FIFO_CERR_SET1_V(1U)
+
+#define DDR_HDR_FIFO_CERR_SET0_S 13
+#define DDR_HDR_FIFO_CERR_SET0_V(x) ((x) << DDR_HDR_FIFO_CERR_SET0_S)
+#define DDR_HDR_FIFO_CERR_SET0_F DDR_HDR_FIFO_CERR_SET0_V(1U)
+
+#define CMD_FIFO_CERR_SET3_S 12
+#define CMD_FIFO_CERR_SET3_V(x) ((x) << CMD_FIFO_CERR_SET3_S)
+#define CMD_FIFO_CERR_SET3_F CMD_FIFO_CERR_SET3_V(1U)
+
+#define CMD_FIFO_CERR_SET2_S 11
+#define CMD_FIFO_CERR_SET2_V(x) ((x) << CMD_FIFO_CERR_SET2_S)
+#define CMD_FIFO_CERR_SET2_F CMD_FIFO_CERR_SET2_V(1U)
+
+#define CMD_FIFO_CERR_SET1_S 10
+#define CMD_FIFO_CERR_SET1_V(x) ((x) << CMD_FIFO_CERR_SET1_S)
+#define CMD_FIFO_CERR_SET1_F CMD_FIFO_CERR_SET1_V(1U)
+
+#define CMD_FIFO_CERR_SET0_S 9
+#define CMD_FIFO_CERR_SET0_V(x) ((x) << CMD_FIFO_CERR_SET0_S)
+#define CMD_FIFO_CERR_SET0_F CMD_FIFO_CERR_SET0_V(1U)
+
+#define GF_SGE_FIFO_CORERR3_S 8
+#define GF_SGE_FIFO_CORERR3_V(x) ((x) << GF_SGE_FIFO_CORERR3_S)
+#define GF_SGE_FIFO_CORERR3_F GF_SGE_FIFO_CORERR3_V(1U)
+
+#define GF_SGE_FIFO_CORERR2_S 7
+#define GF_SGE_FIFO_CORERR2_V(x) ((x) << GF_SGE_FIFO_CORERR2_S)
+#define GF_SGE_FIFO_CORERR2_F GF_SGE_FIFO_CORERR2_V(1U)
+
+#define GF_SGE_FIFO_CORERR1_S 6
+#define GF_SGE_FIFO_CORERR1_V(x) ((x) << GF_SGE_FIFO_CORERR1_S)
+#define GF_SGE_FIFO_CORERR1_F GF_SGE_FIFO_CORERR1_V(1U)
+
+#define GF_SGE_FIFO_CORERR0_S 5
+#define GF_SGE_FIFO_CORERR0_V(x) ((x) << GF_SGE_FIFO_CORERR0_S)
+#define GF_SGE_FIFO_CORERR0_F GF_SGE_FIFO_CORERR0_V(1U)
+
+#define DEDUPE_SGE_FIFO_CORERR3_S 4
+#define DEDUPE_SGE_FIFO_CORERR3_V(x) ((x) << DEDUPE_SGE_FIFO_CORERR3_S)
+#define DEDUPE_SGE_FIFO_CORERR3_F DEDUPE_SGE_FIFO_CORERR3_V(1U)
+
+#define DEDUPE_SGE_FIFO_CORERR2_S 3
+#define DEDUPE_SGE_FIFO_CORERR2_V(x) ((x) << DEDUPE_SGE_FIFO_CORERR2_S)
+#define DEDUPE_SGE_FIFO_CORERR2_F DEDUPE_SGE_FIFO_CORERR2_V(1U)
+
+#define DEDUPE_SGE_FIFO_CORERR1_S 2
+#define DEDUPE_SGE_FIFO_CORERR1_V(x) ((x) << DEDUPE_SGE_FIFO_CORERR1_S)
+#define DEDUPE_SGE_FIFO_CORERR1_F DEDUPE_SGE_FIFO_CORERR1_V(1U)
+
+#define DEDUPE_SGE_FIFO_CORERR0_S 1
+#define DEDUPE_SGE_FIFO_CORERR0_V(x) ((x) << DEDUPE_SGE_FIFO_CORERR0_S)
+#define DEDUPE_SGE_FIFO_CORERR0_F DEDUPE_SGE_FIFO_CORERR0_V(1U)
+
+#define RSP_FIFO_CERR_SET_S 0
+#define RSP_FIFO_CERR_SET_V(x) ((x) << RSP_FIFO_CERR_SET_S)
+#define RSP_FIFO_CERR_SET_F RSP_FIFO_CERR_SET_V(1U)
+
+#define PM_RX_INT_ENABLE_2_A 0x10060
+#define PM_RX_INT_CAUSE_2_A 0x10061
+
+#define CACHE_SRAM_ODD_CERR_S 12
+#define CACHE_SRAM_ODD_CERR_V(x) ((x) << CACHE_SRAM_ODD_CERR_S)
+#define CACHE_SRAM_ODD_CERR_F CACHE_SRAM_ODD_CERR_V(1U)
+
+#define CACHE_SRAM_EVEN_CERR_S 11
+#define CACHE_SRAM_EVEN_CERR_V(x) ((x) << CACHE_SRAM_EVEN_CERR_S)
+#define CACHE_SRAM_EVEN_CERR_F CACHE_SRAM_EVEN_CERR_V(1U)
+
+#define CACHE_LRU_LEFT_CERR_S 10
+#define CACHE_LRU_LEFT_CERR_V(x) ((x) << CACHE_LRU_LEFT_CERR_S)
+#define CACHE_LRU_LEFT_CERR_F CACHE_LRU_LEFT_CERR_V(1U)
+
+#define CACHE_LRU_RIGHT_CERR_S 9
+#define CACHE_LRU_RIGHT_CERR_V(x) ((x) << CACHE_LRU_RIGHT_CERR_S)
+#define CACHE_LRU_RIGHT_CERR_F CACHE_LRU_RIGHT_CERR_V(1U)
+
+#define CACHE_ISLAND_CERR_S 8
+#define CACHE_ISLAND_CERR_V(x) ((x) << CACHE_ISLAND_CERR_S)
+#define CACHE_ISLAND_CERR_F CACHE_ISLAND_CERR_V(1U)
+
+#define OCSPI_CERR_S 7
+#define OCSPI_CERR_V(x) ((x) << OCSPI_CERR_S)
+#define OCSPI_CERR_F OCSPI_CERR_V(1U)
+
+#define IESPI_CERR_S 6
+#define IESPI_CERR_V(x) ((x) << IESPI_CERR_S)
+#define IESPI_CERR_F IESPI_CERR_V(1U)
+
+#define OCSPI2_RX_FRAMING_ERROR_S 5
+#define OCSPI2_RX_FRAMING_ERROR_V(x) ((x) << OCSPI2_RX_FRAMING_ERROR_S)
+#define OCSPI2_RX_FRAMING_ERROR_F OCSPI2_RX_FRAMING_ERROR_V(1U)
+
+#define OCSPI3_RX_FRAMING_ERROR_S 4
+#define OCSPI3_RX_FRAMING_ERROR_V(x) ((x) << OCSPI3_RX_FRAMING_ERROR_S)
+#define OCSPI3_RX_FRAMING_ERROR_F OCSPI3_RX_FRAMING_ERROR_V(1U)
+
+#define OCSPI2_TX_FRAMING_ERROR_S 3
+#define OCSPI2_TX_FRAMING_ERROR_V(x) ((x) << OCSPI2_TX_FRAMING_ERROR_S)
+#define OCSPI2_TX_FRAMING_ERROR_F OCSPI2_TX_FRAMING_ERROR_V(1U)
+
+#define OCSPI3_TX_FRAMING_ERROR_S 2
+#define OCSPI3_TX_FRAMING_ERROR_V(x) ((x) << OCSPI3_TX_FRAMING_ERROR_S)
+#define OCSPI3_TX_FRAMING_ERROR_F OCSPI3_TX_FRAMING_ERROR_V(1U)
+
+#define OCSPI2_OFIFO2X_TX_FRAMING_ERROR_S 1
+#define OCSPI2_OFIFO2X_TX_FRAMING_ERROR_V(x) ((x) << OCSPI2_OFIFO2X_TX_FRAMING_ERROR_S)
+#define OCSPI2_OFIFO2X_TX_FRAMING_ERROR_F OCSPI2_OFIFO2X_TX_FRAMING_ERROR_V(1U)
+
+#define OCSPI3_OFIFO2X_TX_FRAMING_ERROR_S 0
+#define OCSPI3_OFIFO2X_TX_FRAMING_ERROR_V(x) ((x) << OCSPI3_OFIFO2X_TX_FRAMING_ERROR_S)
+#define OCSPI3_OFIFO2X_TX_FRAMING_ERROR_F OCSPI3_OFIFO2X_TX_FRAMING_ERROR_V(1U)
+
+#define PM_RX_PERR_ENABLE_A 0x10062
+#define PM_RX_PERR_CAUSE_A 0x10063
+
+#define T7_SDC_ERR_S 31
+#define T7_SDC_ERR_V(x) ((x) << T7_SDC_ERR_S)
+#define T7_SDC_ERR_F T7_SDC_ERR_V(1U)
+
+#define T7_MA_INTF_SDC_ERR_S 30
+#define T7_MA_INTF_SDC_ERR_V(x) ((x) << T7_MA_INTF_SDC_ERR_S)
+#define T7_MA_INTF_SDC_ERR_F T7_MA_INTF_SDC_ERR_V(1U)
+
+#define E_PCMD_PERR_S 21
+#define E_PCMD_PERR_V(x) ((x) << E_PCMD_PERR_S)
+#define E_PCMD_PERR_F E_PCMD_PERR_V(1U)
+
+#define CACHE_RSP_DFIFO_PERR_S 20
+#define CACHE_RSP_DFIFO_PERR_V(x) ((x) << CACHE_RSP_DFIFO_PERR_S)
+#define CACHE_RSP_DFIFO_PERR_F CACHE_RSP_DFIFO_PERR_V(1U)
+
+#define CACHE_SRAM_ODD_PERR_S 19
+#define CACHE_SRAM_ODD_PERR_V(x) ((x) << CACHE_SRAM_ODD_PERR_S)
+#define CACHE_SRAM_ODD_PERR_F CACHE_SRAM_ODD_PERR_V(1U)
+
+#define CACHE_SRAM_EVEN_PERR_S 18
+#define CACHE_SRAM_EVEN_PERR_V(x) ((x) << CACHE_SRAM_EVEN_PERR_S)
+#define CACHE_SRAM_EVEN_PERR_F CACHE_SRAM_EVEN_PERR_V(1U)
+
+#define CACHE_RSVD_PERR_S 17
+#define CACHE_RSVD_PERR_V(x) ((x) << CACHE_RSVD_PERR_S)
+#define CACHE_RSVD_PERR_F CACHE_RSVD_PERR_V(1U)
+
+#define CACHE_LRU_LEFT_PERR_S 16
+#define CACHE_LRU_LEFT_PERR_V(x) ((x) << CACHE_LRU_LEFT_PERR_S)
+#define CACHE_LRU_LEFT_PERR_F CACHE_LRU_LEFT_PERR_V(1U)
+
+#define CACHE_LRU_RIGHT_PERR_S 15
+#define CACHE_LRU_RIGHT_PERR_V(x) ((x) << CACHE_LRU_RIGHT_PERR_S)
+#define CACHE_LRU_RIGHT_PERR_F CACHE_LRU_RIGHT_PERR_V(1U)
+
+#define CACHE_RSP_CMD_PERR_S 14
+#define CACHE_RSP_CMD_PERR_V(x) ((x) << CACHE_RSP_CMD_PERR_S)
+#define CACHE_RSP_CMD_PERR_F CACHE_RSP_CMD_PERR_V(1U)
+
+#define CACHE_SRAM_CMD_PERR_S 13
+#define CACHE_SRAM_CMD_PERR_V(x) ((x) << CACHE_SRAM_CMD_PERR_S)
+#define CACHE_SRAM_CMD_PERR_F CACHE_SRAM_CMD_PERR_V(1U)
+
+#define CACHE_MA_CMD_PERR_S 12
+#define CACHE_MA_CMD_PERR_V(x) ((x) << CACHE_MA_CMD_PERR_S)
+#define CACHE_MA_CMD_PERR_F CACHE_MA_CMD_PERR_V(1U)
+
+#define CACHE_TCAM_PERR_S 11
+#define CACHE_TCAM_PERR_V(x) ((x) << CACHE_TCAM_PERR_S)
+#define CACHE_TCAM_PERR_F CACHE_TCAM_PERR_V(1U)
+
+#define CACHE_ISLAND_PERR_S 10
+#define CACHE_ISLAND_PERR_V(x) ((x) << CACHE_ISLAND_PERR_S)
+#define CACHE_ISLAND_PERR_F CACHE_ISLAND_PERR_V(1U)
+
+#define MC_WCNT_FIFO_PERR_S 9
+#define MC_WCNT_FIFO_PERR_V(x) ((x) << MC_WCNT_FIFO_PERR_S)
+#define MC_WCNT_FIFO_PERR_F MC_WCNT_FIFO_PERR_V(1U)
+
+#define MC_WDATA_FIFO_PERR_S 8
+#define MC_WDATA_FIFO_PERR_V(x) ((x) << MC_WDATA_FIFO_PERR_S)
+#define MC_WDATA_FIFO_PERR_F MC_WDATA_FIFO_PERR_V(1U)
+
+#define MC_RCNT_FIFO_PERR_S 7
+#define MC_RCNT_FIFO_PERR_V(x) ((x) << MC_RCNT_FIFO_PERR_S)
+#define MC_RCNT_FIFO_PERR_F MC_RCNT_FIFO_PERR_V(1U)
+
+#define MC_RDATA_FIFO_PERR_S 6
+#define MC_RDATA_FIFO_PERR_V(x) ((x) << MC_RDATA_FIFO_PERR_S)
+#define MC_RDATA_FIFO_PERR_F MC_RDATA_FIFO_PERR_V(1U)
+
+#define TOKEN_FIFO_PERR_S 5
+#define TOKEN_FIFO_PERR_V(x) ((x) << TOKEN_FIFO_PERR_S)
+#define TOKEN_FIFO_PERR_F TOKEN_FIFO_PERR_V(1U)
+
+#define T7_BUNDLE_LEN_PARERR_S 4
+#define T7_BUNDLE_LEN_PARERR_V(x) ((x) << T7_BUNDLE_LEN_PARERR_S)
+#define T7_BUNDLE_LEN_PARERR_F T7_BUNDLE_LEN_PARERR_V(1U)
+
+#define PM_TX_DBG_STAT0_A 0x1002c
+
+#define PM_TX_INT_ENABLE_A 0x8ff8
+#define PM_TX_INT_CAUSE_A 0x8ffc
+
+#define PCMD_LEN_OVFL0_S 31
+#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
+#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
+
+#define PCMD_LEN_OVFL1_S 30
+#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
+#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
+
+#define PCMD_LEN_OVFL2_S 29
+#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
+#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
+
+#define OESPI_PAR_ERROR_S 3
+#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
+#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
+
+#define ICSPI_PAR_ERROR_S 1
+#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
+#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
+
+#define C_PCMD_PAR_ERROR_S 0
+#define C_PCMD_PAR_ERROR_V(x) ((x) << C_PCMD_PAR_ERROR_S)
+#define C_PCMD_PAR_ERROR_F C_PCMD_PAR_ERROR_V(1U)
+
+#define T7_ZERO_C_CMD_ERROR_S 30
+#define T7_ZERO_C_CMD_ERROR_V(x) ((x) << T7_ZERO_C_CMD_ERROR_S)
+#define T7_ZERO_C_CMD_ERROR_F T7_ZERO_C_CMD_ERROR_V(1U)
+
+#define OESPI_COR_ERR_S 29
+#define OESPI_COR_ERR_V(x) ((x) << OESPI_COR_ERR_S)
+#define OESPI_COR_ERR_F OESPI_COR_ERR_V(1U)
+
+#define ICSPI_COR_ERR_S 28
+#define ICSPI_COR_ERR_V(x) ((x) << ICSPI_COR_ERR_S)
+#define ICSPI_COR_ERR_F ICSPI_COR_ERR_V(1U)
+
+#define ICSPI_OVFL_S 24
+#define ICSPI_OVFL_V(x) ((x) << ICSPI_OVFL_S)
+#define ICSPI_OVFL_F ICSPI_OVFL_V(1U)
+
+#define PCMD_LEN_OVFL3_S 23
+#define PCMD_LEN_OVFL3_V(x) ((x) << PCMD_LEN_OVFL3_S)
+#define PCMD_LEN_OVFL3_F PCMD_LEN_OVFL3_V(1U)
+
+#define T7_PCMD_LEN_OVFL2_S 22
+#define T7_PCMD_LEN_OVFL2_V(x) ((x) << T7_PCMD_LEN_OVFL2_S)
+#define T7_PCMD_LEN_OVFL2_F T7_PCMD_LEN_OVFL2_V(1U)
+
+#define T7_PCMD_LEN_OVFL1_S 21
+#define T7_PCMD_LEN_OVFL1_V(x) ((x) << T7_PCMD_LEN_OVFL1_S)
+#define T7_PCMD_LEN_OVFL1_F T7_PCMD_LEN_OVFL1_V(1U)
+
+#define T7_PCMD_LEN_OVFL0_S 20
+#define T7_PCMD_LEN_OVFL0_V(x) ((x) << T7_PCMD_LEN_OVFL0_S)
+#define T7_PCMD_LEN_OVFL0_F T7_PCMD_LEN_OVFL0_V(1U)
+
+#define PM_TX_PERR_ENABLE_A 0x10028
+#define PM_TX_PERR_CAUSE_A 0x10029
+
+#define OSPI_OVERFLOW3_TX_S 23
+#define OSPI_OVERFLOW3_TX_V(x) ((x) << OSPI_OVERFLOW3_TX_S)
+#define OSPI_OVERFLOW3_TX_F OSPI_OVERFLOW3_TX_V(1U)
+
+#define OSPI_OVERFLOW2_TX_S 22
+#define OSPI_OVERFLOW2_TX_V(x) ((x) << OSPI_OVERFLOW2_TX_S)
+#define OSPI_OVERFLOW2_TX_F OSPI_OVERFLOW2_TX_V(1U)
+
+#define OSPI_OVERFLOW1_TX_S 21
+#define OSPI_OVERFLOW1_TX_V(x) ((x) << OSPI_OVERFLOW1_TX_S)
+#define OSPI_OVERFLOW1_TX_F OSPI_OVERFLOW1_TX_V(1U)
+
+#define OSPI_OVERFLOW0_TX_S 20
+#define OSPI_OVERFLOW0_TX_V(x) ((x) << OSPI_OVERFLOW0_TX_S)
+#define OSPI_OVERFLOW0_TX_F OSPI_OVERFLOW0_TX_V(1U)
+
+#define T7_BUNDLE_LEN_OVFL_EN_S 18
+#define T7_BUNDLE_LEN_OVFL_EN_V(x) ((x) << T7_BUNDLE_LEN_OVFL_EN_S)
+#define T7_BUNDLE_LEN_OVFL_EN_F T7_BUNDLE_LEN_OVFL_EN_V(1U)
+
+#define T7_M_INTFPERREN_S 17
+#define T7_M_INTFPERREN_V(x) ((x) << T7_M_INTFPERREN_S)
+#define T7_M_INTFPERREN_F T7_M_INTFPERREN_V(1U)
+
+#define T7_1_SDC_ERR_S 16
+#define T7_1_SDC_ERR_V(x) ((x) << T7_1_SDC_ERR_S)
+#define T7_1_SDC_ERR_F T7_1_SDC_ERR_V(1U)
+
+#define TOKEN_PAR_ERROR_S 5
+#define TOKEN_PAR_ERROR_V(x) ((x) << TOKEN_PAR_ERROR_S)
+#define TOKEN_PAR_ERROR_F TOKEN_PAR_ERROR_V(1U)
+
+#define BUNDLE_LEN_PAR_ERROR_S 4
+#define BUNDLE_LEN_PAR_ERROR_V(x) ((x) << BUNDLE_LEN_PAR_ERROR_S)
+#define BUNDLE_LEN_PAR_ERROR_F BUNDLE_LEN_PAR_ERROR_V(1U)
+
+#define C_PCMD_TOKEN_PAR_ERROR_S 0
+#define C_PCMD_TOKEN_PAR_ERROR_V(x) ((x) << C_PCMD_TOKEN_PAR_ERROR_S)
+#define C_PCMD_TOKEN_PAR_ERROR_F C_PCMD_TOKEN_PAR_ERROR_V(1U)
+
+#define PM_RX_INT_ENABLE_A 0x8fd8
+#define PM_RX_INT_CAUSE_A 0x8fdc
+#define PM_RX_STAT_CONFIG_A 0x8fc8
+#define PM_RX_STAT_COUNT_A 0x8fcc
+#define PM_RX_STAT_LSB_A 0x8fd0
+#define PM_RX_DBG_CTRL_A 0x8fd0
+#define PM_RX_DBG_DATA_A 0x8fd4
+#define PM_RX_DBG_STAT_MSB_A 0x10013
+
+#define PMRX_FRAMING_ERROR_F 0x003ffff0U
+
+#define ZERO_E_CMD_ERROR_S 22
+#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
+#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
+
+#define OCSPI_PAR_ERROR_S 3
+#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
+#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
+
+#define DB_OPTIONS_PAR_ERROR_S 2
+#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
+#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
+
+#define IESPI_PAR_ERROR_S 1
+#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
+#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
+
+#define E_PCMD_PAR_ERROR_S 0
+#define E_PCMD_PAR_ERROR_V(x) ((x) << E_PCMD_PAR_ERROR_S)
+#define E_PCMD_PAR_ERROR_F E_PCMD_PAR_ERROR_V(1U)
+
+#define MA_INTF_SDC_ERR_S 26
+#define MA_INTF_SDC_ERR_V(x) ((x) << MA_INTF_SDC_ERR_S)
+#define MA_INTF_SDC_ERR_F MA_INTF_SDC_ERR_V(1U)
+
+#define BUNDLE_LEN_PARERR_S 25
+#define BUNDLE_LEN_PARERR_V(x) ((x) << BUNDLE_LEN_PARERR_S)
+#define BUNDLE_LEN_PARERR_F BUNDLE_LEN_PARERR_V(1U)
+
+#define BUNDLE_LEN_OVFL_S 24
+#define BUNDLE_LEN_OVFL_V(x) ((x) << BUNDLE_LEN_OVFL_S)
+#define BUNDLE_LEN_OVFL_F BUNDLE_LEN_OVFL_V(1U)
+
+#define SDC_ERR_S 23
+#define SDC_ERR_V(x) ((x) << SDC_ERR_S)
+#define SDC_ERR_F SDC_ERR_V(1U)
+
+#define MASTER_PERR_S 31
+#define MASTER_PERR_V(x) ((x) << MASTER_PERR_S)
+#define MASTER_PERR_F MASTER_PERR_V(1U)
+
+#define ULP_TX_LA_RDPTR_0_A 0x8ec0
+#define ULP_TX_LA_RDDATA_0_A 0x8ec4
+#define ULP_TX_LA_WRPTR_0_A 0x8ec8
+#define ULP_TX_ASIC_DEBUG_CTRL_A 0x8f70
+
+#define ULP_TX_ASIC_DEBUG_0_A 0x8f74
+#define ULP_TX_ASIC_DEBUG_1_A 0x8f78
+#define ULP_TX_ASIC_DEBUG_2_A 0x8f7c
+#define ULP_TX_ASIC_DEBUG_3_A 0x8f80
+#define ULP_TX_ASIC_DEBUG_4_A 0x8f84
+
+/* registers for module PM_RX */
+#define PM_RX_BASE_ADDR 0x8fc0
+
+#define PMRX_E_PCMD_PAR_ERROR_S 0
+#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
+#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
+
+#define PM_TX_STAT_CONFIG_A 0x8fe8
+#define PM_TX_STAT_COUNT_A 0x8fec
+#define PM_TX_STAT_LSB_A 0x8ff0
+#define PM_TX_DBG_CTRL_A 0x8ff0
+#define PM_TX_DBG_DATA_A 0x8ff4
+#define T7_PM_TX_DBG_STAT_MSB_A 0x10000
+#define PM_TX_DBG_STAT_MSB_A 0x1001a
+
+#define ZERO_C_CMD_ERROR_S 28
+#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
+#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
+
+#define PMTX_FRAMING_ERROR_F 0x0ffffff0U
+
+#define PMTX_C_PCMD_PAR_ERROR_S 0
+#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
+#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
+
+#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
+#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
+#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
+#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
+#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
+#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
+#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
+#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
+#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
+#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
+#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
+#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
+#define MPS_PORT_STAT_TX_PORT_64B_L 0x430
+#define MPS_PORT_STAT_TX_PORT_64B_H 0x434
+#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
+#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
+#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
+#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
+#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
+#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
+#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
+#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
+#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
+#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
+#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
+#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
+#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
+#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
+#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
+#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
+#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
+#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
+#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
+#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
+#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
+#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
+#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
+#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
+#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
+#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
+#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
+#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
+#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
+#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
+#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
+#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
+#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
+#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
+#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
+#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
+#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
+#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
+#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
+#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
+#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
+#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
+#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
+#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
+#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
+#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
+#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
+#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
+#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
+#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
+#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
+#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
+#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
+#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
+#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
+#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
+#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
+#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
+#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
+#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
+#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
+#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
+#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
+#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
+#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
+#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
+#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
+#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
+#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
+#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
+#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
+#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
+#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
+#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
+#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
+#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
+#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
+#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
+#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
+#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
+#define MPS_PORT_STAT_RX_PORT_64B_L 0x590
+#define MPS_PORT_STAT_RX_PORT_64B_H 0x594
+#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
+#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
+#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
+#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
+#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
+#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
+#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
+#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
+#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
+#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
+#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
+#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
+#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
+#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
+#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
+#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
+#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
+#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
+#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
+#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
+#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
+#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
+#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
+#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
+#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
+#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
+#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
+#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
+#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
+#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
+#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
+#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
+#define MAC_PORT_MAGIC_MACID_LO 0x824
+#define MAC_PORT_MAGIC_MACID_HI 0x828
+#define T7_MAC_PORT_TX_TS_VAL_LO 0x88c
+#define MAC_PORT_TX_TS_VAL_LO 0x928
+#define MAC_PORT_TX_TS_VAL_HI 0x92c
+
+#define MAC_PORT_EPIO_DATA0_A 0x8c0
+#define MAC_PORT_EPIO_DATA1_A 0x8c4
+#define MAC_PORT_EPIO_DATA2_A 0x8c8
+#define MAC_PORT_EPIO_DATA3_A 0x8cc
+#define MAC_PORT_EPIO_OP_A 0x8d0
+
+#define MAC_PORT_CFG2_A 0x818
+
+#define MAC_PORT_PTP_SUM_LO_A 0x990
+#define MAC_PORT_PTP_SUM_HI_A 0x994
+
+#define MAC_INT_EN_CMN_A 0x380c8
+#define MAC_INT_CAUSE_CMN_A 0x380cc
+
+#define FLOCK_ASSERTED_S 5
+#define FLOCK_ASSERTED_V(x) ((x) << FLOCK_ASSERTED_S)
+#define FLOCK_ASSERTED_F FLOCK_ASSERTED_V(1U)
+
+#define FLOCK_LOST_S 4
+#define FLOCK_LOST_V(x) ((x) << FLOCK_LOST_S)
+#define FLOCK_LOST_F FLOCK_LOST_V(1U)
+
+#define PHASE_LOCK_ASSERTED_S 3
+#define PHASE_LOCK_ASSERTED_V(x) ((x) << PHASE_LOCK_ASSERTED_S)
+#define PHASE_LOCK_ASSERTED_F PHASE_LOCK_ASSERTED_V(1U)
+
+#define PHASE_LOCK_LOST_S 2
+#define PHASE_LOCK_LOST_V(x) ((x) << PHASE_LOCK_LOST_S)
+#define PHASE_LOCK_LOST_F PHASE_LOCK_LOST_V(1U)
+
+#define LOCK_ASSERTED_S 1
+#define LOCK_ASSERTED_V(x) ((x) << LOCK_ASSERTED_S)
+#define LOCK_ASSERTED_F LOCK_ASSERTED_V(1U)
+
+#define LOCK_LOST_S 0
+#define LOCK_LOST_V(x) ((x) << LOCK_LOST_S)
+#define LOCK_LOST_F LOCK_LOST_V(1U)
+
+#define MPS_CMN_CTL_A 0x9000
+
+#define COUNTPAUSEMCRX_S 5
+#define COUNTPAUSEMCRX_V(x) ((x) << COUNTPAUSEMCRX_S)
+#define COUNTPAUSEMCRX_F COUNTPAUSEMCRX_V(1U)
+
+#define COUNTPAUSESTATRX_S 4
+#define COUNTPAUSESTATRX_V(x) ((x) << COUNTPAUSESTATRX_S)
+#define COUNTPAUSESTATRX_F COUNTPAUSESTATRX_V(1U)
+
+#define COUNTPAUSEMCTX_S 3
+#define COUNTPAUSEMCTX_V(x) ((x) << COUNTPAUSEMCTX_S)
+#define COUNTPAUSEMCTX_F COUNTPAUSEMCTX_V(1U)
+
+#define COUNTPAUSESTATTX_S 2
+#define COUNTPAUSESTATTX_V(x) ((x) << COUNTPAUSESTATTX_S)
#define COUNTPAUSESTATTX_F COUNTPAUSESTATTX_V(1U)
-#define NUMPORTS_S 0
-#define NUMPORTS_M 0x3U
-#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
+#define NUMPORTS_S 0
+#define NUMPORTS_M 0x3U
+#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
+
+#define MPS_INT_CAUSE_A 0x9008
+#define MPS_TX_INT_ENABLE_A 0x9404
+#define MPS_TX_INT_CAUSE_A 0x9408
+#define MPS_TX_INT2_ENABLE_A 0x9498
+#define MPS_TX_INT2_CAUSE_A 0x949c
+#define MPS_TX_INT3_ENABLE_A 0x94a4
+#define MPS_TX_INT3_CAUSE_A 0x94a8
+#define MPS_TX_INT4_ENABLE_A 0x94b0
+#define MPS_TX_INT4_CAUSE_A 0x94b4
+
+#define RX_FINAL_TF_FIFO_PERR_S 19
+#define RX_FINAL_TF_FIFO_PERR_V(x) ((x) << RX_FINAL_TF_FIFO_PERR_S)
+#define RX_FINAL_TF_FIFO_PERR_F RX_FINAL_TF_FIFO_PERR_V(1U)
+
+#define MPS_STAT_CTL_A 0x9600
+
+#define PORTERR_S 16
+#define PORTERR_V(x) ((x) << PORTERR_S)
+#define PORTERR_F PORTERR_V(1U)
+
+#define FRMERR_S 15
+#define FRMERR_V(x) ((x) << FRMERR_S)
+#define FRMERR_F FRMERR_V(1U)
+
+#define SECNTERR_S 14
+#define SECNTERR_V(x) ((x) << SECNTERR_S)
+#define SECNTERR_F SECNTERR_V(1U)
+
+#define BUBBLE_S 13
+#define BUBBLE_V(x) ((x) << BUBBLE_S)
+#define BUBBLE_F BUBBLE_V(1U)
+
+#define TXDESCFIFO_S 9
+#define TXDESCFIFO_M 0xfU
+#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
+
+#define TXDATAFIFO_S 5
+#define TXDATAFIFO_M 0xfU
+#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
+
+#define NCSIFIFO_S 4
+#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
+#define NCSIFIFO_F NCSIFIFO_V(1U)
+
+#define TPFIFO_S 0
+#define TPFIFO_M 0xfU
+#define TPFIFO_V(x) ((x) << TPFIFO_S)
+
+#define T7_PORTERR_S 28
+#define T7_PORTERR_V(x) ((x) << T7_PORTERR_S)
+#define T7_PORTERR_F T7_PORTERR_V(1U)
+
+#define T7_FRMERR_S 27
+#define T7_FRMERR_V(x) ((x) << T7_FRMERR_S)
+#define T7_FRMERR_F T7_FRMERR_V(1U)
+
+#define T7_SECNTERR_S 26
+#define T7_SECNTERR_V(x) ((x) << T7_SECNTERR_S)
+#define T7_SECNTERR_F T7_SECNTERR_V(1U)
+
+#define T7_BUBBLE_S 25
+#define T7_BUBBLE_V(x) ((x) << T7_BUBBLE_S)
+#define T7_BUBBLE_F T7_BUBBLE_V(1U)
+
+#define TX_TF_FIFO_PERR_S 19
+#define TX_TF_FIFO_PERR_V(x) ((x) << TX_TF_FIFO_PERR_S)
+#define TX_TF_FIFO_PERR_F TX_TF_FIFO_PERR_V(1U)
+
+#define TX_FIFO_PERR_S 18
+#define TX_FIFO_PERR_V(x) ((x) << TX_FIFO_PERR_S)
+#define TX_FIFO_PERR_F TX_FIFO_PERR_V(1U)
+
+#define NCSI2MPS_S 5
+#define NCSI2MPS_V(x) ((x) << NCSI2MPS_S)
+#define NCSI2MPS_F NCSI2MPS_V(1U)
+
+#define MPS_STAT_INT_ENABLE_A 0x9608
+#define MPS_STAT_INT_CAUSE_A 0x960c
+
+#define PLREADSYNCERR_S 0
+#define PLREADSYNCERR_V(x) ((x) << PLREADSYNCERR_S)
+#define PLREADSYNCERR_F PLREADSYNCERR_V(1U)
+
+#define MPS_STAT_PERR_INT_ENABLE_SRAM_A 0x9610
+#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
+
+#define MPS_STAT_PERR_INT_ENABLE_TX_FIFO_A 0x961c
+#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
+#define MPS_STAT_PERR_INT_ENABLE_RX_FIFO_A 0x9628
+#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
+
+#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
+#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
+#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
+#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
+#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
+#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
+#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
+#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
+#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
+#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
+#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
+#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
+#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
+#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
+#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
+#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
+#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
+#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
+#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
+#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
+#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
+#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
+#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
+#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
+#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
+#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
+#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
+#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
+#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
+#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
+#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
+#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
+#define MPS_STAT_PERR_INT_ENABLE_SRAM1_A 0x96c0
+#define MPS_STAT_PERR_INT_CAUSE_SRAM1_A 0x96c4
+
+#define MPS_TRC_CFG_A 0x9800
+
+#define TRCFIFOEMPTY_S 4
+#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
+#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
+
+#define TRCIGNOREDROPINPUT_S 3
+#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
+#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
+
+#define TRCKEEPDUPLICATES_S 2
+#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
+#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
+
+#define TRCEN_S 1
+#define TRCEN_V(x) ((x) << TRCEN_S)
+#define TRCEN_F TRCEN_V(1U)
+
+#define TRCMULTIFILTER_S 0
+#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
+#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
+
+#define MPS_TRC_RSS_CONTROL_A 0x9808
+#define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4
+#define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc
+#define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004
+#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
+
+#define RSSCONTROL_S 16
+#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
+
+#define QUEUENUMBER_S 0
+#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
+
+#define TFINVERTMATCH_S 24
+#define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)
+#define TFINVERTMATCH_F TFINVERTMATCH_V(1U)
+
+#define TFEN_S 22
+#define TFEN_V(x) ((x) << TFEN_S)
+#define TFEN_F TFEN_V(1U)
+
+#define TFPORT_S 18
+#define TFPORT_M 0xfU
+#define TFPORT_V(x) ((x) << TFPORT_S)
+#define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)
+
+#define TFLENGTH_S 8
+#define TFLENGTH_M 0x1fU
+#define TFLENGTH_V(x) ((x) << TFLENGTH_S)
+#define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)
+
+#define TFOFFSET_S 0
+#define TFOFFSET_M 0x1fU
+#define TFOFFSET_V(x) ((x) << TFOFFSET_S)
+#define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)
+
+#define T5_TFINVERTMATCH_S 25
+#define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)
+#define T5_TFINVERTMATCH_F T5_TFINVERTMATCH_V(1U)
+
+#define T5_TFEN_S 23
+#define T5_TFEN_V(x) ((x) << T5_TFEN_S)
+#define T5_TFEN_F T5_TFEN_V(1U)
+
+#define T5_TFPORT_S 18
+#define T5_TFPORT_M 0x1fU
+#define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)
+#define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)
+
+#define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
+#define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
+#define T7_MPS_TRC_FILTER_MATCH_CTL_A_A 0xa460
+#define T7_MPS_TRC_FILTER_MATCH_CTL_B_A 0xa480
+#define T7_MPS_T5_TRC_RSS_CONTROL_A 0xa434
+
+#define TFMINPKTSIZE_S 16
+#define TFMINPKTSIZE_M 0x1ffU
+#define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)
+#define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)
+
+#define TFCAPTUREMAX_S 0
+#define TFCAPTUREMAX_M 0x3fffU
+#define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)
+#define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)
+
+#define MPS_TRC_FILTER0_MATCH_A 0x9c00
+#define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
+#define MPS_TRC_FILTER1_MATCH_A 0x9d00
+
+#define TP_RSS_CONFIG_A 0x7df0
+
+#define TNL4TUPENIPV6_S 31
+#define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
+#define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U)
+
+#define TNL2TUPENIPV6_S 30
+#define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
+#define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U)
+
+#define TNL4TUPENIPV4_S 29
+#define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
+#define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U)
+
+#define TNL2TUPENIPV4_S 28
+#define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
+#define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U)
+
+#define TNLTCPSEL_S 27
+#define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
+#define TNLTCPSEL_F TNLTCPSEL_V(1U)
+
+#define TNLIP6SEL_S 26
+#define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
+#define TNLIP6SEL_F TNLIP6SEL_V(1U)
+
+#define TNLVRTSEL_S 25
+#define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
+#define TNLVRTSEL_F TNLVRTSEL_V(1U)
+
+#define TNLMAPEN_S 24
+#define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
+#define TNLMAPEN_F TNLMAPEN_V(1U)
+
+#define OFDHASHSAVE_S 19
+#define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
+#define OFDHASHSAVE_F OFDHASHSAVE_V(1U)
+
+#define OFDVRTSEL_S 18
+#define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
+#define OFDVRTSEL_F OFDVRTSEL_V(1U)
+
+#define OFDMAPEN_S 17
+#define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
+#define OFDMAPEN_F OFDMAPEN_V(1U)
+
+#define OFDLKPEN_S 16
+#define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
+#define OFDLKPEN_F OFDLKPEN_V(1U)
+
+#define SYN4TUPENIPV6_S 15
+#define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
+#define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U)
+
+#define SYN2TUPENIPV6_S 14
+#define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
+#define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U)
+
+#define SYN4TUPENIPV4_S 13
+#define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
+#define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U)
+
+#define SYN2TUPENIPV4_S 12
+#define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
+#define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U)
+
+#define SYNIP6SEL_S 11
+#define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
+#define SYNIP6SEL_F SYNIP6SEL_V(1U)
+
+#define SYNVRTSEL_S 10
+#define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
+#define SYNVRTSEL_F SYNVRTSEL_V(1U)
+
+#define SYNMAPEN_S 9
+#define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
+#define SYNMAPEN_F SYNMAPEN_V(1U)
+
+#define SYNLKPEN_S 8
+#define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
+#define SYNLKPEN_F SYNLKPEN_V(1U)
+
+#define CHANNELENABLE_S 7
+#define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
+#define CHANNELENABLE_F CHANNELENABLE_V(1U)
+
+#define PORTENABLE_S 6
+#define PORTENABLE_V(x) ((x) << PORTENABLE_S)
+#define PORTENABLE_F PORTENABLE_V(1U)
+
+#define TNLALLLOOKUP_S 5
+#define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
+#define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U)
+
+#define VIRTENABLE_S 4
+#define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
+#define VIRTENABLE_F VIRTENABLE_V(1U)
+
+#define CONGESTIONENABLE_S 3
+#define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
+#define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U)
+
+#define HASHTOEPLITZ_S 2
+#define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
+#define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U)
+
+#define UDPENABLE_S 1
+#define UDPENABLE_V(x) ((x) << UDPENABLE_S)
+#define UDPENABLE_F UDPENABLE_V(1U)
+
+#define DISABLE_S 0
+#define DISABLE_V(x) ((x) << DISABLE_S)
+#define DISABLE_F DISABLE_V(1U)
+
+#define TP_RSS_CONFIG_TNL_A 0x7df4
+
+#define MASKSIZE_S 28
+#define MASKSIZE_M 0xfU
+#define MASKSIZE_V(x) ((x) << MASKSIZE_S)
+#define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
+
+#define MASKFILTER_S 16
+#define MASKFILTER_M 0x7ffU
+#define MASKFILTER_V(x) ((x) << MASKFILTER_S)
+#define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
+
+#define USEWIRECH_S 0
+#define USEWIRECH_V(x) ((x) << USEWIRECH_S)
+#define USEWIRECH_F USEWIRECH_V(1U)
+
+#define HASHALL_S 2
+#define HASHALL_V(x) ((x) << HASHALL_S)
+#define HASHALL_F HASHALL_V(1U)
+
+#define HASHETH_S 1
+#define HASHETH_V(x) ((x) << HASHETH_S)
+#define HASHETH_F HASHETH_V(1U)
+
+#define TP_RSS_CONFIG_OFD_A 0x7df8
+
+#define RRCPLMAPEN_S 20
+#define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
+#define RRCPLMAPEN_F RRCPLMAPEN_V(1U)
+
+#define RRCPLQUEWIDTH_S 16
+#define RRCPLQUEWIDTH_M 0xfU
+#define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
+#define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
+
+#define TP_RSS_CONFIG_SYN_A 0x7dfc
+#define TP_RSS_CONFIG_VRT_A 0x7e00
+
+#define VFRDRG_S 25
+#define VFRDRG_V(x) ((x) << VFRDRG_S)
+#define VFRDRG_F VFRDRG_V(1U)
+
+#define VFRDEN_S 24
+#define VFRDEN_V(x) ((x) << VFRDEN_S)
+#define VFRDEN_F VFRDEN_V(1U)
+
+#define VFPERREN_S 23
+#define VFPERREN_V(x) ((x) << VFPERREN_S)
+#define VFPERREN_F VFPERREN_V(1U)
+
+#define KEYPERREN_S 22
+#define KEYPERREN_V(x) ((x) << KEYPERREN_S)
+#define KEYPERREN_F KEYPERREN_V(1U)
+
+#define DISABLEVLAN_S 21
+#define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
+#define DISABLEVLAN_F DISABLEVLAN_V(1U)
+
+#define ENABLEUP0_S 20
+#define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
+#define ENABLEUP0_F ENABLEUP0_V(1U)
+
+#define HASHDELAY_S 16
+#define HASHDELAY_M 0xfU
+#define HASHDELAY_V(x) ((x) << HASHDELAY_S)
+#define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
+
+#define VFWRADDR_S 8
+#define VFWRADDR_M 0x7fU
+#define VFWRADDR_V(x) ((x) << VFWRADDR_S)
+#define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
+
+#define KEYMODE_S 6
+#define KEYMODE_M 0x3U
+#define KEYMODE_V(x) ((x) << KEYMODE_S)
+#define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
+
+#define VFWREN_S 5
+#define VFWREN_V(x) ((x) << VFWREN_S)
+#define VFWREN_F VFWREN_V(1U)
+
+#define KEYWREN_S 4
+#define KEYWREN_V(x) ((x) << KEYWREN_S)
+#define KEYWREN_F KEYWREN_V(1U)
+
+#define KEYWRADDR_S 0
+#define KEYWRADDR_M 0xfU
+#define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
+#define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
+
+#define KEYWRADDRX_S 30
+#define KEYWRADDRX_M 0x3U
+#define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
+#define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
+
+#define KEYEXTEND_S 26
+#define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
+#define KEYEXTEND_F KEYEXTEND_V(1U)
+
+#define LKPIDXSIZE_S 24
+#define LKPIDXSIZE_M 0x3U
+#define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
+#define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
+
+#define TP_RSS_VFL_CONFIG_A 0x3a
+#define TP_RSS_VFH_CONFIG_A 0x3b
+
+#define ENABLEUDPHASH_S 31
+#define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
+#define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U)
+
+#define VFUPEN_S 30
+#define VFUPEN_V(x) ((x) << VFUPEN_S)
+#define VFUPEN_F VFUPEN_V(1U)
+
+#define VFVLNEX_S 28
+#define VFVLNEX_V(x) ((x) << VFVLNEX_S)
+#define VFVLNEX_F VFVLNEX_V(1U)
+
+#define VFPRTEN_S 27
+#define VFPRTEN_V(x) ((x) << VFPRTEN_S)
+#define VFPRTEN_F VFPRTEN_V(1U)
+
+#define VFCHNEN_S 26
+#define VFCHNEN_V(x) ((x) << VFCHNEN_S)
+#define VFCHNEN_F VFCHNEN_V(1U)
+
+#define DEFAULTQUEUE_S 16
+#define DEFAULTQUEUE_M 0x3ffU
+#define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
+
+#define VFIP6TWOTUPEN_S 6
+#define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
+#define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U)
+
+#define VFIP4FOURTUPEN_S 5
+#define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
+#define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U)
+
+#define VFIP4TWOTUPEN_S 4
+#define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
+#define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U)
+
+#define KEYINDEX_S 0
+#define KEYINDEX_M 0xfU
+#define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
+
+#define MAPENABLE_S 31
+#define MAPENABLE_V(x) ((x) << MAPENABLE_S)
+#define MAPENABLE_F MAPENABLE_V(1U)
+
+#define CHNENABLE_S 30
+#define CHNENABLE_V(x) ((x) << CHNENABLE_S)
+#define CHNENABLE_F CHNENABLE_V(1U)
+
+#define LE_DB_DBGI_CONFIG_A 0x19cf0
+
+#define DBGICMDBUSY_S 3
+#define DBGICMDBUSY_V(x) ((x) << DBGICMDBUSY_S)
+#define DBGICMDBUSY_F DBGICMDBUSY_V(1U)
+
+#define DBGICMDSTRT_S 2
+#define DBGICMDSTRT_V(x) ((x) << DBGICMDSTRT_S)
+#define DBGICMDSTRT_F DBGICMDSTRT_V(1U)
+
+#define DBGICMDMODE_S 0
+#define DBGICMDMODE_M 0x3U
+#define DBGICMDMODE_V(x) ((x) << DBGICMDMODE_S)
+
+#define LE_DB_DBGI_REQ_TCAM_CMD_A 0x19cf4
+
+#define DBGICMD_S 20
+#define DBGICMD_M 0xfU
+#define DBGICMD_V(x) ((x) << DBGICMD_S)
+
+#define DBGITID_S 0
+#define DBGITID_M 0xfffffU
+#define DBGITID_V(x) ((x) << DBGITID_S)
+
+#define LE_DB_DBGI_REQ_DATA_A 0x19d00
+#define LE_DB_DBGI_RSP_STATUS_A 0x19d94
+
+#define LE_DB_DBGI_RSP_DATA_A 0x19da0
+
+#define PRTENABLE_S 29
+#define PRTENABLE_V(x) ((x) << PRTENABLE_S)
+#define PRTENABLE_F PRTENABLE_V(1U)
+
+#define UDPFOURTUPEN_S 28
+#define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
+#define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U)
+
+#define IP6FOURTUPEN_S 27
+#define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
+#define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U)
+
+#define IP6TWOTUPEN_S 26
+#define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
+#define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U)
+
+#define IP4FOURTUPEN_S 25
+#define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
+#define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U)
+
+#define IP4TWOTUPEN_S 24
+#define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
+#define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U)
+
+#define IVFWIDTH_S 20
+#define IVFWIDTH_M 0xfU
+#define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
+#define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
+
+#define CH1DEFAULTQUEUE_S 10
+#define CH1DEFAULTQUEUE_M 0x3ffU
+#define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
+#define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
+
+#define CH0DEFAULTQUEUE_S 0
+#define CH0DEFAULTQUEUE_M 0x3ffU
+#define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
+#define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
+
+#define VFLKPIDX_S 8
+#define VFLKPIDX_M 0xffU
+#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
+
+#define T6_VFWRADDR_S 8
+#define T6_VFWRADDR_M 0xffU
+#define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
+#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
+
+#define TP_RSS_CONFIG_CNG_A 0x7e04
+#define TP_RSS_CONFIG_SRAM_A 0x7e0c
+#define TP_RSS_SECRET_KEY0_A 0x40
+#define TP_RSS_PF0_CONFIG_A 0x30
+#define TP_RSS_PF_MAP_A 0x38
+#define TP_RSS_PF_MSK_A 0x39
+
+#define PF1LKPIDX_S 3
+
+#define PF0LKPIDX_M 0x7U
+
+#define PF1MSKSIZE_S 4
+#define PF1MSKSIZE_M 0xfU
+
+#define CHNCOUNT3_S 31
+#define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
+#define CHNCOUNT3_F CHNCOUNT3_V(1U)
+
+#define CHNCOUNT2_S 30
+#define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
+#define CHNCOUNT2_F CHNCOUNT2_V(1U)
+
+#define CHNCOUNT1_S 29
+#define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
+#define CHNCOUNT1_F CHNCOUNT1_V(1U)
+
+#define CHNCOUNT0_S 28
+#define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
+#define CHNCOUNT0_F CHNCOUNT0_V(1U)
+
+#define CHNUNDFLOW3_S 27
+#define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
+#define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U)
+
+#define CHNUNDFLOW2_S 26
+#define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
+#define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U)
+
+#define CHNUNDFLOW1_S 25
+#define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
+#define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U)
+
+#define CHNUNDFLOW0_S 24
+#define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
+#define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U)
+
+#define RSTCHN3_S 19
+#define RSTCHN3_V(x) ((x) << RSTCHN3_S)
+#define RSTCHN3_F RSTCHN3_V(1U)
+
+#define RSTCHN2_S 18
+#define RSTCHN2_V(x) ((x) << RSTCHN2_S)
+#define RSTCHN2_F RSTCHN2_V(1U)
+
+#define RSTCHN1_S 17
+#define RSTCHN1_V(x) ((x) << RSTCHN1_S)
+#define RSTCHN1_F RSTCHN1_V(1U)
+
+#define RSTCHN0_S 16
+#define RSTCHN0_V(x) ((x) << RSTCHN0_S)
+#define RSTCHN0_F RSTCHN0_V(1U)
+
+#define UPDVLD_S 15
+#define UPDVLD_V(x) ((x) << UPDVLD_S)
+#define UPDVLD_F UPDVLD_V(1U)
+
+#define XOFF_S 14
+#define XOFF_V(x) ((x) << XOFF_S)
+#define XOFF_F XOFF_V(1U)
+
+#define UPDCHN3_S 13
+#define UPDCHN3_V(x) ((x) << UPDCHN3_S)
+#define UPDCHN3_F UPDCHN3_V(1U)
+
+#define UPDCHN2_S 12
+#define UPDCHN2_V(x) ((x) << UPDCHN2_S)
+#define UPDCHN2_F UPDCHN2_V(1U)
+
+#define UPDCHN1_S 11
+#define UPDCHN1_V(x) ((x) << UPDCHN1_S)
+#define UPDCHN1_F UPDCHN1_V(1U)
+
+#define UPDCHN0_S 10
+#define UPDCHN0_V(x) ((x) << UPDCHN0_S)
+#define UPDCHN0_F UPDCHN0_V(1U)
+
+#define QUEUE_S 0
+#define QUEUE_M 0x3ffU
+#define QUEUE_V(x) ((x) << QUEUE_S)
+#define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
+
+#define MPS_TRC_INT_ENABLE_A 0x9858
+#define MPS_TRC_INT_CAUSE_A 0x985c
+
+#define T7_TRCPLERRENB_S 17
+#define T7_TRCPLERRENB_V(x) ((x) << T7_TRCPLERRENB_S)
+#define T7_TRCPLERRENB_F T7_TRCPLERRENB_V(1U)
+
+#define T7_MISCPERR_S 16
+#define T7_MISCPERR_V(x) ((x) << T7_MISCPERR_S)
+#define T7_MISCPERR_F T7_MISCPERR_V(1U)
+
+#define MISCPERR_S 8
+#define MISCPERR_V(x) ((x) << MISCPERR_S)
+#define MISCPERR_F MISCPERR_V(1U)
+
+#define PKTFIFO_S 4
+#define PKTFIFO_M 0xfU
+#define PKTFIFO_V(x) ((x) << PKTFIFO_S)
+
+#define FILTMEM_S 0
+#define FILTMEM_M 0xfU
+#define FILTMEM_V(x) ((x) << FILTMEM_S)
+
+#define CIM2MPS_INTF_PAR_S 4
+#define CIM2MPS_INTF_PAR_V(x) ((x) << CIM2MPS_INTF_PAR_S)
+#define CIM2MPS_INTF_PAR_F CIM2MPS_INTF_PAR_V(1U)
+
+#define TCAM_CRC_SRAM_S 3
+#define TCAM_CRC_SRAM_V(x) ((x) << TCAM_CRC_SRAM_S)
+#define TCAM_CRC_SRAM_F TCAM_CRC_SRAM_V(1U)
+
+#define MPS_CLS_INT_ENABLE_A 0xd024
+#define MPS_CLS_INT_CAUSE_A 0xd028
+
+#define T7_PLERRENB_S 5
+#define T7_PLERRENB_V(x) ((x) << T7_PLERRENB_S)
+#define T7_PLERRENB_F T7_PLERRENB_V(1U)
+
+#define HASHSRAM_S 2
+#define HASHSRAM_V(x) ((x) << HASHSRAM_S)
+#define HASHSRAM_F HASHSRAM_V(1U)
+
+#define MATCHTCAM_S 1
+#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
+#define MATCHTCAM_F MATCHTCAM_V(1U)
+
+#define MATCHSRAM_S 0
+#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
+#define MATCHSRAM_F MATCHSRAM_V(1U)
+
+#define MPS_RX_PERR_INT_ENABLE_A 0x11078
+#define MPS_RX_FUNC_INT_CAUSE_A 0x11084
+
+#define MTU_ERR3_S 19
+#define MTU_ERR3_V(x) ((x) << MTU_ERR3_S)
+#define MTU_ERR3_F MTU_ERR3_V(1U)
+
+#define MTU_ERR2_S 18
+#define MTU_ERR2_V(x) ((x) << MTU_ERR2_S)
+#define MTU_ERR2_F MTU_ERR2_V(1U)
+
+#define MTU_ERR1_S 17
+#define MTU_ERR1_V(x) ((x) << MTU_ERR1_S)
+#define MTU_ERR1_F MTU_ERR1_V(1U)
+
+#define MTU_ERR0_S 16
+#define MTU_ERR0_V(x) ((x) << MTU_ERR0_S)
+#define MTU_ERR0_F MTU_ERR0_V(1U)
+
+#define DBG_LEN_ERR_S 15
+#define DBG_LEN_ERR_V(x) ((x) << DBG_LEN_ERR_S)
+#define DBG_LEN_ERR_F DBG_LEN_ERR_V(1U)
+
+#define DBG_SPI_ERR_S 14
+#define DBG_SPI_ERR_V(x) ((x) << DBG_SPI_ERR_S)
+#define DBG_SPI_ERR_F DBG_SPI_ERR_V(1U)
+
+#define DBG_SE_CNT_ERR_S 13
+#define DBG_SE_CNT_ERR_V(x) ((x) << DBG_SE_CNT_ERR_S)
+#define DBG_SE_CNT_ERR_F DBG_SE_CNT_ERR_V(1U)
+
+#define DBG_SPI_LEN_SE_CNT_ERR_S 12
+#define DBG_SPI_LEN_SE_CNT_ERR_V(x) ((x) << DBG_SPI_LEN_SE_CNT_ERR_S)
+#define DBG_SPI_LEN_SE_CNT_ERR_F DBG_SPI_LEN_SE_CNT_ERR_V(1U)
+
+#define MPS_RX_FUNC_INT_ENABLE_A 0x11088
+#define MPS_RX_PERR_INT_ENABLE2_A 0x11090
+#define MPS_RX_PERR_INT_CAUSE2_A 0x1108c
+
+#define CRYPTO2MPS_RX0_PERR_S 31
+#define CRYPTO2MPS_RX0_PERR_V(x) ((x) << CRYPTO2MPS_RX0_PERR_S)
+#define CRYPTO2MPS_RX0_PERR_F CRYPTO2MPS_RX0_PERR_V(1U)
+
+#define CRYPTO2MPS_RX1_PERR_S 30
+#define CRYPTO2MPS_RX1_PERR_V(x) ((x) << CRYPTO2MPS_RX1_PERR_S)
+#define CRYPTO2MPS_RX1_PERR_F CRYPTO2MPS_RX1_PERR_V(1U)
+
+#define CRYPTO2MPS_RX2_PERR_S 29
+#define CRYPTO2MPS_RX2_PERR_V(x) ((x) << CRYPTO2MPS_RX2_PERR_S)
+#define CRYPTO2MPS_RX2_PERR_F CRYPTO2MPS_RX2_PERR_V(1U)
+
+#define CRYPTO2MPS_RX3_PERR_S 28
+#define CRYPTO2MPS_RX3_PERR_V(x) ((x) << CRYPTO2MPS_RX3_PERR_S)
+#define CRYPTO2MPS_RX3_PERR_F CRYPTO2MPS_RX3_PERR_V(1U)
+
+#define INIC2MPS_TX1_PERR_S 27
+#define INIC2MPS_TX1_PERR_V(x) ((x) << INIC2MPS_TX1_PERR_S)
+#define INIC2MPS_TX1_PERR_F INIC2MPS_TX1_PERR_V(1U)
+
+#define INIC2MPS_TX0_PERR_S 26
+#define INIC2MPS_TX0_PERR_V(x) ((x) << INIC2MPS_TX0_PERR_S)
+#define INIC2MPS_TX0_PERR_F INIC2MPS_TX0_PERR_V(1U)
+
+#define XGMAC2MPS_RX1_PERR_S 25
+#define XGMAC2MPS_RX1_PERR_V(x) ((x) << XGMAC2MPS_RX1_PERR_S)
+#define XGMAC2MPS_RX1_PERR_F XGMAC2MPS_RX1_PERR_V(1U)
+
+#define XGMAC2MPS_RX0_PERR_S 24
+#define XGMAC2MPS_RX0_PERR_V(x) ((x) << XGMAC2MPS_RX0_PERR_S)
+#define XGMAC2MPS_RX0_PERR_F XGMAC2MPS_RX0_PERR_V(1U)
+
+#define MPS_DWRR_FIFO_PERR_S 14
+#define MPS_DWRR_FIFO_PERR_V(x) ((x) << MPS_DWRR_FIFO_PERR_S)
+#define MPS_DWRR_FIFO_PERR_F MPS_DWRR_FIFO_PERR_V(1U)
+
+#define MAC_TF_FIFO_PERR_S 13
+#define MAC_TF_FIFO_PERR_V(x) ((x) << MAC_TF_FIFO_PERR_S)
+#define MAC_TF_FIFO_PERR_F MAC_TF_FIFO_PERR_V(1U)
+
+#define MAC2MPS_PT3_PERR_S 12
+#define MAC2MPS_PT3_PERR_V(x) ((x) << MAC2MPS_PT3_PERR_S)
+#define MAC2MPS_PT3_PERR_F MAC2MPS_PT3_PERR_V(1U)
+
+#define MAC2MPS_PT2_PERR_S 11
+#define MAC2MPS_PT2_PERR_V(x) ((x) << MAC2MPS_PT2_PERR_S)
+#define MAC2MPS_PT2_PERR_F MAC2MPS_PT2_PERR_V(1U)
+
+#define MAC2MPS_PT1_PERR_S 10
+#define MAC2MPS_PT1_PERR_V(x) ((x) << MAC2MPS_PT1_PERR_S)
+#define MAC2MPS_PT1_PERR_F MAC2MPS_PT1_PERR_V(1U)
+
+#define MAC2MPS_PT0_PERR_S 9
+#define MAC2MPS_PT0_PERR_V(x) ((x) << MAC2MPS_PT0_PERR_S)
+#define MAC2MPS_PT0_PERR_F MAC2MPS_PT0_PERR_V(1U)
+
+#define TP_LPBK_FIFO_PERR_S 8
+#define TP_LPBK_FIFO_PERR_V(x) ((x) << TP_LPBK_FIFO_PERR_S)
+#define TP_LPBK_FIFO_PERR_F TP_LPBK_FIFO_PERR_V(1U)
+
+#define TP_LPBK_TF_PERR_S 7
+#define TP_LPBK_TF_PERR_V(x) ((x) << TP_LPBK_TF_PERR_S)
+#define TP_LPBK_TF_PERR_F TP_LPBK_TF_PERR_V(1U)
+
+#define MPS_RX_PERR_INT_ENABLE3_A 0x11314
+#define MPS_RX_PERR_INT_CAUSE3_A 0x11310
+
+#define FIFO_REPL_CH3_CERR_S 28
+#define FIFO_REPL_CH3_CERR_V(x) ((x) << FIFO_REPL_CH3_CERR_S)
+#define FIFO_REPL_CH3_CERR_F FIFO_REPL_CH3_CERR_V(1U)
+
+#define FIFO_REPL_CH2_CERR_S 27
+#define FIFO_REPL_CH2_CERR_V(x) ((x) << FIFO_REPL_CH2_CERR_S)
+#define FIFO_REPL_CH2_CERR_F FIFO_REPL_CH2_CERR_V(1U)
+
+#define FIFO_REPL_CH1_CERR_S 26
+#define FIFO_REPL_CH1_CERR_V(x) ((x) << FIFO_REPL_CH1_CERR_S)
+#define FIFO_REPL_CH1_CERR_F FIFO_REPL_CH1_CERR_V(1U)
+
+#define FIFO_REPL_CH0_CERR_S 25
+#define FIFO_REPL_CH0_CERR_V(x) ((x) << FIFO_REPL_CH0_CERR_S)
+#define FIFO_REPL_CH0_CERR_F FIFO_REPL_CH0_CERR_V(1U)
+
+#define VLAN_FILTER_RAM_CERR_S 24
+#define VLAN_FILTER_RAM_CERR_V(x) ((x) << VLAN_FILTER_RAM_CERR_S)
+#define VLAN_FILTER_RAM_CERR_F VLAN_FILTER_RAM_CERR_V(1U)
+
+#define MPS_RX_TD_STAT_FIFO_PERR_CH3_S 23
+#define MPS_RX_TD_STAT_FIFO_PERR_CH3_V(x) ((x) << MPS_RX_TD_STAT_FIFO_PERR_CH3_S)
+#define MPS_RX_TD_STAT_FIFO_PERR_CH3_F MPS_RX_TD_STAT_FIFO_PERR_CH3_V(1U)
+
+#define RPLCT_HDR_FIFO_IN_PERR_CH3_S 22
+#define RPLCT_HDR_FIFO_IN_PERR_CH3_V(x) ((x) << RPLCT_HDR_FIFO_IN_PERR_CH3_S)
+#define RPLCT_HDR_FIFO_IN_PERR_CH3_F RPLCT_HDR_FIFO_IN_PERR_CH3_V(1U)
+
+#define ID_FIFO_IN_PERR_CH3_S 21
+#define ID_FIFO_IN_PERR_CH3_V(x) ((x) << ID_FIFO_IN_PERR_CH3_S)
+#define ID_FIFO_IN_PERR_CH3_F ID_FIFO_IN_PERR_CH3_V(1U)
+
+#define DESC_HDR2_PERR_CH3_S 20
+#define DESC_HDR2_PERR_CH3_V(x) ((x) << DESC_HDR2_PERR_CH3_S)
+#define DESC_HDR2_PERR_CH3_F DESC_HDR2_PERR_CH3_V(1U)
+
+#define FIFO_REPL_PERR_CH3_S 19
+#define FIFO_REPL_PERR_CH3_V(x) ((x) << FIFO_REPL_PERR_CH3_S)
+#define FIFO_REPL_PERR_CH3_F FIFO_REPL_PERR_CH3_V(1U)
+
+#define MPS_RX_TD_PERR_CH3_S 18
+#define MPS_RX_TD_PERR_CH3_V(x) ((x) << MPS_RX_TD_PERR_CH3_S)
+#define MPS_RX_TD_PERR_CH3_F MPS_RX_TD_PERR_CH3_V(1U)
+
+#define MPS_RX_TD_STAT_FIFO_PERR_CH2_S 17
+#define MPS_RX_TD_STAT_FIFO_PERR_CH2_V(x) ((x) << MPS_RX_TD_STAT_FIFO_PERR_CH2_S)
+#define MPS_RX_TD_STAT_FIFO_PERR_CH2_F MPS_RX_TD_STAT_FIFO_PERR_CH2_V(1U)
+
+#define RPLCT_HDR_FIFO_IN_PERR_CH2_S 16
+#define RPLCT_HDR_FIFO_IN_PERR_CH2_V(x) ((x) << RPLCT_HDR_FIFO_IN_PERR_CH2_S)
+#define RPLCT_HDR_FIFO_IN_PERR_CH2_F RPLCT_HDR_FIFO_IN_PERR_CH2_V(1U)
+
+#define ID_FIFO_IN_PERR_CH2_S 15
+#define ID_FIFO_IN_PERR_CH2_V(x) ((x) << ID_FIFO_IN_PERR_CH2_S)
+#define ID_FIFO_IN_PERR_CH2_F ID_FIFO_IN_PERR_CH2_V(1U)
+
+#define DESC_HDR2_PERR_CH2_S 14
+#define DESC_HDR2_PERR_CH2_V(x) ((x) << DESC_HDR2_PERR_CH2_S)
+#define DESC_HDR2_PERR_CH2_F DESC_HDR2_PERR_CH2_V(1U)
+
+#define FIFO_REPL_PERR_CH2_S 13
+#define FIFO_REPL_PERR_CH2_V(x) ((x) << FIFO_REPL_PERR_CH2_S)
+#define FIFO_REPL_PERR_CH2_F FIFO_REPL_PERR_CH2_V(1U)
+
+#define MPS_RX_TD_PERR_CH2_S 12
+#define MPS_RX_TD_PERR_CH2_V(x) ((x) << MPS_RX_TD_PERR_CH2_S)
+#define MPS_RX_TD_PERR_CH2_F MPS_RX_TD_PERR_CH2_V(1U)
+
+#define MPS_RX_TD_STAT_FIFO_PERR_CH1_S 11
+#define MPS_RX_TD_STAT_FIFO_PERR_CH1_V(x) ((x) << MPS_RX_TD_STAT_FIFO_PERR_CH1_S)
+#define MPS_RX_TD_STAT_FIFO_PERR_CH1_F MPS_RX_TD_STAT_FIFO_PERR_CH1_V(1U)
+
+#define RPLCT_HDR_FIFO_IN_PERR_CH1_S 10
+#define RPLCT_HDR_FIFO_IN_PERR_CH1_V(x) ((x) << RPLCT_HDR_FIFO_IN_PERR_CH1_S)
+#define RPLCT_HDR_FIFO_IN_PERR_CH1_F RPLCT_HDR_FIFO_IN_PERR_CH1_V(1U)
+
+#define ID_FIFO_IN_PERR_CH1_S 9
+#define ID_FIFO_IN_PERR_CH1_V(x) ((x) << ID_FIFO_IN_PERR_CH1_S)
+#define ID_FIFO_IN_PERR_CH1_F ID_FIFO_IN_PERR_CH1_V(1U)
+
+#define DESC_HDR2_PERR_CH1_S 8
+#define DESC_HDR2_PERR_CH1_V(x) ((x) << DESC_HDR2_PERR_CH1_S)
+#define DESC_HDR2_PERR_CH1_F DESC_HDR2_PERR_CH1_V(1U)
+
+#define FIFO_REPL_PERR_CH1_S 7
+#define FIFO_REPL_PERR_CH1_V(x) ((x) << FIFO_REPL_PERR_CH1_S)
+#define FIFO_REPL_PERR_CH1_F FIFO_REPL_PERR_CH1_V(1U)
+
+#define MPS_RX_TD_PERR_CH1_S 6
+#define MPS_RX_TD_PERR_CH1_V(x) ((x) << MPS_RX_TD_PERR_CH1_S)
+#define MPS_RX_TD_PERR_CH1_F MPS_RX_TD_PERR_CH1_V(1U)
+
+#define MPS_RX_TD_STAT_FIFO_PERR_CH0_S 5
+#define MPS_RX_TD_STAT_FIFO_PERR_CH0_V(x) ((x) << MPS_RX_TD_STAT_FIFO_PERR_CH0_S)
+#define MPS_RX_TD_STAT_FIFO_PERR_CH0_F MPS_RX_TD_STAT_FIFO_PERR_CH0_V(1U)
+
+#define RPLCT_HDR_FIFO_IN_PERR_CH0_S 4
+#define RPLCT_HDR_FIFO_IN_PERR_CH0_V(x) ((x) << RPLCT_HDR_FIFO_IN_PERR_CH0_S)
+#define RPLCT_HDR_FIFO_IN_PERR_CH0_F RPLCT_HDR_FIFO_IN_PERR_CH0_V(1U)
+
+#define ID_FIFO_IN_PERR_CH0_S 3
+#define ID_FIFO_IN_PERR_CH0_V(x) ((x) << ID_FIFO_IN_PERR_CH0_S)
+#define ID_FIFO_IN_PERR_CH0_F ID_FIFO_IN_PERR_CH0_V(1U)
+
+#define DESC_HDR2_PERR_CH0_S 2
+#define DESC_HDR2_PERR_CH0_V(x) ((x) << DESC_HDR2_PERR_CH0_S)
+#define DESC_HDR2_PERR_CH0_F DESC_HDR2_PERR_CH0_V(1U)
+
+#define FIFO_REPL_PERR_CH0_S 1
+#define FIFO_REPL_PERR_CH0_V(x) ((x) << FIFO_REPL_PERR_CH0_S)
+#define FIFO_REPL_PERR_CH0_F FIFO_REPL_PERR_CH0_V(1U)
+
+#define MPS_RX_TD_PERR_CH0_S 0
+#define MPS_RX_TD_PERR_CH0_V(x) ((x) << MPS_RX_TD_PERR_CH0_S)
+#define MPS_RX_TD_PERR_CH0_F MPS_RX_TD_PERR_CH0_V(1U)
+
+#define MPS_RX_PERR_INT_ENABLE4_A 0x11320
+#define MPS_RX_PERR_INT_CAUSE4_A 0x1131c
+
+#define VNI_MULTICAST_FIFO_ECC_ERR_CH3_S 30
+#define VNI_MULTICAST_FIFO_ECC_ERR_CH3_V(x) ((x) << VNI_MULTICAST_FIFO_ECC_ERR_CH3_S)
+#define VNI_MULTICAST_FIFO_ECC_ERR_CH3_F VNI_MULTICAST_FIFO_ECC_ERR_CH3_V(1U)
+
+#define VNI_MULTICAST_FIFO_ECC_ERR_CH2_S 29
+#define VNI_MULTICAST_FIFO_ECC_ERR_CH2_V(x) ((x) << VNI_MULTICAST_FIFO_ECC_ERR_CH2_S)
+#define VNI_MULTICAST_FIFO_ECC_ERR_CH2_F VNI_MULTICAST_FIFO_ECC_ERR_CH2_V(1U)
+
+#define HASH_SRAM_CLS_ENG1_S 28
+#define HASH_SRAM_CLS_ENG1_V(x) ((x) << HASH_SRAM_CLS_ENG1_S)
+#define HASH_SRAM_CLS_ENG1_F HASH_SRAM_CLS_ENG1_V(1U)
+
+#define HASH_SRAM_CLS_ENG0_S 27
+#define HASH_SRAM_CLS_ENG0_V(x) ((x) << HASH_SRAM_CLS_ENG0_S)
+#define HASH_SRAM_CLS_ENG0_F HASH_SRAM_CLS_ENG0_V(1U)
+
+#define CLS_TCAM_SRAM_CLS_ENG1_S 26
+#define CLS_TCAM_SRAM_CLS_ENG1_V(x) ((x) << CLS_TCAM_SRAM_CLS_ENG1_S)
+#define CLS_TCAM_SRAM_CLS_ENG1_F CLS_TCAM_SRAM_CLS_ENG1_V(1U)
+
+#define CLS_TCAM_CRC_SRAM_CLS_ENG1_S 25
+#define CLS_TCAM_CRC_SRAM_CLS_ENG1_V(x) ((x) << CLS_TCAM_CRC_SRAM_CLS_ENG1_S)
+#define CLS_TCAM_CRC_SRAM_CLS_ENG1_F CLS_TCAM_CRC_SRAM_CLS_ENG1_V(1U)
+
+#define CLS_TCAM_SRAM_CLS_ENG0_S 24
+#define CLS_TCAM_SRAM_CLS_ENG0_V(x) ((x) << CLS_TCAM_SRAM_CLS_ENG0_S)
+#define CLS_TCAM_SRAM_CLS_ENG0_F CLS_TCAM_SRAM_CLS_ENG0_V(1U)
+
+#define CLS_TCAM_CRC_SRAM_CLS_ENG0_S 23
+#define CLS_TCAM_CRC_SRAM_CLS_ENG0_V(x) ((x) << CLS_TCAM_CRC_SRAM_CLS_ENG0_S)
+#define CLS_TCAM_CRC_SRAM_CLS_ENG0_F CLS_TCAM_CRC_SRAM_CLS_ENG0_V(1U)
+
+#define DWRR_CH_FIFO_ECC_ERR_S 18
+#define DWRR_CH_FIFO_ECC_ERR_V(x) ((x) << DWRR_CH_FIFO_ECC_ERR_S)
+#define DWRR_CH_FIFO_ECC_ERR_F DWRR_CH_FIFO_ECC_ERR_V(1U)
+
+#define MAC_RX_FIFO_ECC_ERR_S 17
+#define MAC_RX_FIFO_ECC_ERR_V(x) ((x) << MAC_RX_FIFO_ECC_ERR_S)
+#define MAC_RX_FIFO_ECC_ERR_F MAC_RX_FIFO_ECC_ERR_V(1U)
+
+#define LPBK_RX_FIFO_ECC_ERR_S 16
+#define LPBK_RX_FIFO_ECC_ERR_V(x) ((x) << LPBK_RX_FIFO_ECC_ERR_S)
+#define LPBK_RX_FIFO_ECC_ERR_F LPBK_RX_FIFO_ECC_ERR_V(1U)
+
+#define CRS_DATA_STORE_N_FWD_CH3_S 15
+#define CRS_DATA_STORE_N_FWD_CH3_V(x) ((x) << CRS_DATA_STORE_N_FWD_CH3_S)
+#define CRS_DATA_STORE_N_FWD_CH3_F CRS_DATA_STORE_N_FWD_CH3_V(1U)
+
+#define TRACE_FWD_FIFO_CERR_CH3_S 14
+#define TRACE_FWD_FIFO_CERR_CH3_V(x) ((x) << TRACE_FWD_FIFO_CERR_CH3_S)
+#define TRACE_FWD_FIFO_CERR_CH3_F TRACE_FWD_FIFO_CERR_CH3_V(1U)
+
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3_S 13
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3_V(x) ((x) << TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3_S)
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3_F TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3_V(1U)
+
+#define PTP_TRACE_FWD_FIFO_CERR_CH3_S 12
+#define PTP_TRACE_FWD_FIFO_CERR_CH3_V(x) ((x) << PTP_TRACE_FWD_FIFO_CERR_CH3_S)
+#define PTP_TRACE_FWD_FIFO_CERR_CH3_F PTP_TRACE_FWD_FIFO_CERR_CH3_V(1U)
+
+#define CRS_DATA_STORE_N_FWD_CH2_S 11
+#define CRS_DATA_STORE_N_FWD_CH2_V(x) ((x) << CRS_DATA_STORE_N_FWD_CH2_S)
+#define CRS_DATA_STORE_N_FWD_CH2_F CRS_DATA_STORE_N_FWD_CH2_V(1U)
+
+#define TRACE_FWD_FIFO_CERR_CH2_S 10
+#define TRACE_FWD_FIFO_CERR_CH2_V(x) ((x) << TRACE_FWD_FIFO_CERR_CH2_S)
+#define TRACE_FWD_FIFO_CERR_CH2_F TRACE_FWD_FIFO_CERR_CH2_V(1U)
+
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2_S 9
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2_V(x) ((x) << TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2_S)
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2_F TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2_V(1U)
+
+#define PTP_TRACE_FWD_FIFO_CERR_CH2_S 8
+#define PTP_TRACE_FWD_FIFO_CERR_CH2_V(x) ((x) << PTP_TRACE_FWD_FIFO_CERR_CH2_S)
+#define PTP_TRACE_FWD_FIFO_CERR_CH2_F PTP_TRACE_FWD_FIFO_CERR_CH2_V(1U)
+
+#define CRS_DATA_STORE_N_FWD_CH1_S 7
+#define CRS_DATA_STORE_N_FWD_CH1_V(x) ((x) << CRS_DATA_STORE_N_FWD_CH1_S)
+#define CRS_DATA_STORE_N_FWD_CH1_F CRS_DATA_STORE_N_FWD_CH1_V(1U)
+
+#define TRACE_FWD_FIFO_CERR_CH1_S 6
+#define TRACE_FWD_FIFO_CERR_CH1_V(x) ((x) << TRACE_FWD_FIFO_CERR_CH1_S)
+#define TRACE_FWD_FIFO_CERR_CH1_F TRACE_FWD_FIFO_CERR_CH1_V(1U)
+
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1_S 5
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1_V(x) ((x) << TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1_S)
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1_F TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1_V(1U)
+
+#define PTP_TRACE_FWD_FIFO_CERR_CH1_S 4
+#define PTP_TRACE_FWD_FIFO_CERR_CH1_V(x) ((x) << PTP_TRACE_FWD_FIFO_CERR_CH1_S)
+#define PTP_TRACE_FWD_FIFO_CERR_CH1_F PTP_TRACE_FWD_FIFO_CERR_CH1_V(1U)
+
+#define CRS_DATA_STORE_N_FWD_CH0_S 3
+#define CRS_DATA_STORE_N_FWD_CH0_V(x) ((x) << CRS_DATA_STORE_N_FWD_CH0_S)
+#define CRS_DATA_STORE_N_FWD_CH0_F CRS_DATA_STORE_N_FWD_CH0_V(1U)
+
+#define TRACE_FWD_FIFO_CERR_CH0_S 2
+#define TRACE_FWD_FIFO_CERR_CH0_V(x) ((x) << TRACE_FWD_FIFO_CERR_CH0_S)
+#define TRACE_FWD_FIFO_CERR_CH0_F TRACE_FWD_FIFO_CERR_CH0_V(1U)
+
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0_S 1
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0_V(x) ((x) << TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0_S)
+#define TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0_F TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0_V(1U)
+
+#define PTP_TRACE_FWD_FIFO_CERR_CH0_S 0
+#define PTP_TRACE_FWD_FIFO_CERR_CH0_V(x) ((x) << PTP_TRACE_FWD_FIFO_CERR_CH0_S)
+#define PTP_TRACE_FWD_FIFO_CERR_CH0_F PTP_TRACE_FWD_FIFO_CERR_CH0_V(1U)
+
+#define MPS_RX_PERR_INT_ENABLE5_A 0x1132c
+#define MPS_RX_PERR_INT_CAUSE5_A 0x11328
+
+#define MPS2CRYP_RX_FIFO3_PERR_S 31
+#define MPS2CRYP_RX_FIFO3_PERR_V(x) ((x) << MPS2CRYP_RX_FIFO3_PERR_S)
+#define MPS2CRYP_RX_FIFO3_PERR_F MPS2CRYP_RX_FIFO3_PERR_V(1U)
+
+#define MPS2CRYP_RX_FIFO2_PERR_S 30
+#define MPS2CRYP_RX_FIFO2_PERR_V(x) ((x) << MPS2CRYP_RX_FIFO2_PERR_S)
+#define MPS2CRYP_RX_FIFO2_PERR_F MPS2CRYP_RX_FIFO2_PERR_V(1U)
+
+#define MPS2CRYP_RX_FIFO1_PERR_S 29
+#define MPS2CRYP_RX_FIFO1_PERR_V(x) ((x) << MPS2CRYP_RX_FIFO1_PERR_S)
+#define MPS2CRYP_RX_FIFO1_PERR_F MPS2CRYP_RX_FIFO1_PERR_V(1U)
+
+#define MPS2CRYP_RX_FIFO0_PERR_S 28
+#define MPS2CRYP_RX_FIFO0_PERR_V(x) ((x) << MPS2CRYP_RX_FIFO0_PERR_S)
+#define MPS2CRYP_RX_FIFO0_PERR_F MPS2CRYP_RX_FIFO0_PERR_V(1U)
+
+#define VNI_MULTICAST_SRAM2_PERR_S 27
+#define VNI_MULTICAST_SRAM2_PERR_V(x) ((x) << VNI_MULTICAST_SRAM2_PERR_S)
+#define VNI_MULTICAST_SRAM2_PERR_F VNI_MULTICAST_SRAM2_PERR_V(1U)
+
+#define VNI_MULTICAST_SRAM1_PERR_S 26
+#define VNI_MULTICAST_SRAM1_PERR_V(x) ((x) << VNI_MULTICAST_SRAM1_PERR_S)
+#define VNI_MULTICAST_SRAM1_PERR_F VNI_MULTICAST_SRAM1_PERR_V(1U)
+
+#define VNI_MULTICAST_SRAM0_PERR_S 25
+#define VNI_MULTICAST_SRAM0_PERR_V(x) ((x) << VNI_MULTICAST_SRAM0_PERR_S)
+#define VNI_MULTICAST_SRAM0_PERR_F VNI_MULTICAST_SRAM0_PERR_V(1U)
+
+#define MAC_MULTICAST_SRAM4_PERR_S 24
+#define MAC_MULTICAST_SRAM4_PERR_V(x) ((x) << MAC_MULTICAST_SRAM4_PERR_S)
+#define MAC_MULTICAST_SRAM4_PERR_F MAC_MULTICAST_SRAM4_PERR_V(1U)
+
+#define MAC_MULTICAST_SRAM3_PERR_S 23
+#define MAC_MULTICAST_SRAM3_PERR_V(x) ((x) << MAC_MULTICAST_SRAM3_PERR_S)
+#define MAC_MULTICAST_SRAM3_PERR_F MAC_MULTICAST_SRAM3_PERR_V(1U)
+
+#define MAC_MULTICAST_SRAM2_PERR_S 22
+#define MAC_MULTICAST_SRAM2_PERR_V(x) ((x) << MAC_MULTICAST_SRAM2_PERR_S)
+#define MAC_MULTICAST_SRAM2_PERR_F MAC_MULTICAST_SRAM2_PERR_V(1U)
+
+#define MAC_MULTICAST_SRAM1_PERR_S 21
+#define MAC_MULTICAST_SRAM1_PERR_V(x) ((x) << MAC_MULTICAST_SRAM1_PERR_S)
+#define MAC_MULTICAST_SRAM1_PERR_F MAC_MULTICAST_SRAM1_PERR_V(1U)
+
+#define MAC_MULTICAST_SRAM0_PERR_S 20
+#define MAC_MULTICAST_SRAM0_PERR_V(x) ((x) << MAC_MULTICAST_SRAM0_PERR_S)
+#define MAC_MULTICAST_SRAM0_PERR_F MAC_MULTICAST_SRAM0_PERR_V(1U)
+
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_S 19
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_V(x) ((x) << MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_S)
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_F MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_V(1U)
+
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_S 18
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_V(x) ((x) << MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_S)
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_F MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_V(1U)
+
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_S 17
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_V(x) ((x) << MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_S)
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_F MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_V(1U)
+
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_S 16
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_V(x) ((x) << MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_S)
+#define MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_F MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_V(1U)
+
+#define MEM_WRAP_CR2MPS_RX_FIFO3_PERR_S 15
+#define MEM_WRAP_CR2MPS_RX_FIFO3_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_RX_FIFO3_PERR_S)
+#define MEM_WRAP_CR2MPS_RX_FIFO3_PERR_F MEM_WRAP_CR2MPS_RX_FIFO3_PERR_V(1U)
+
+#define MEM_WRAP_CR2MPS_RX_FIFO2_PERR_S 14
+#define MEM_WRAP_CR2MPS_RX_FIFO2_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_RX_FIFO2_PERR_S)
+#define MEM_WRAP_CR2MPS_RX_FIFO2_PERR_F MEM_WRAP_CR2MPS_RX_FIFO2_PERR_V(1U)
+
+#define MEM_WRAP_CR2MPS_RX_FIFO1_PERR_S 13
+#define MEM_WRAP_CR2MPS_RX_FIFO1_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_RX_FIFO1_PERR_S)
+#define MEM_WRAP_CR2MPS_RX_FIFO1_PERR_F MEM_WRAP_CR2MPS_RX_FIFO1_PERR_V(1U)
-#define MPS_INT_CAUSE_A 0x9008
-#define MPS_TX_INT_CAUSE_A 0x9408
-#define MPS_STAT_CTL_A 0x9600
+#define MEM_WRAP_CR2MPS_RX_FIFO0_PERR_S 12
+#define MEM_WRAP_CR2MPS_RX_FIFO0_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_RX_FIFO0_PERR_S)
+#define MEM_WRAP_CR2MPS_RX_FIFO0_PERR_F MEM_WRAP_CR2MPS_RX_FIFO0_PERR_V(1U)
-#define FRMERR_S 15
-#define FRMERR_V(x) ((x) << FRMERR_S)
-#define FRMERR_F FRMERR_V(1U)
+#define MEM_WRAP_NON_IPSEC_FIFO3_PERR_S 11
+#define MEM_WRAP_NON_IPSEC_FIFO3_PERR_V(x) ((x) << MEM_WRAP_NON_IPSEC_FIFO3_PERR_S)
+#define MEM_WRAP_NON_IPSEC_FIFO3_PERR_F MEM_WRAP_NON_IPSEC_FIFO3_PERR_V(1U)
-#define SECNTERR_S 14
-#define SECNTERR_V(x) ((x) << SECNTERR_S)
-#define SECNTERR_F SECNTERR_V(1U)
+#define MEM_WRAP_NON_IPSEC_FIFO2_PERR_S 10
+#define MEM_WRAP_NON_IPSEC_FIFO2_PERR_V(x) ((x) << MEM_WRAP_NON_IPSEC_FIFO2_PERR_S)
+#define MEM_WRAP_NON_IPSEC_FIFO2_PERR_F MEM_WRAP_NON_IPSEC_FIFO2_PERR_V(1U)
-#define BUBBLE_S 13
-#define BUBBLE_V(x) ((x) << BUBBLE_S)
-#define BUBBLE_F BUBBLE_V(1U)
+#define MEM_WRAP_NON_IPSEC_FIFO1_PERR_S 9
+#define MEM_WRAP_NON_IPSEC_FIFO1_PERR_V(x) ((x) << MEM_WRAP_NON_IPSEC_FIFO1_PERR_S)
+#define MEM_WRAP_NON_IPSEC_FIFO1_PERR_F MEM_WRAP_NON_IPSEC_FIFO1_PERR_V(1U)
-#define TXDESCFIFO_S 9
-#define TXDESCFIFO_M 0xfU
-#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
+#define MEM_WRAP_NON_IPSEC_FIFO0_PERR_S 8
+#define MEM_WRAP_NON_IPSEC_FIFO0_PERR_V(x) ((x) << MEM_WRAP_NON_IPSEC_FIFO0_PERR_S)
+#define MEM_WRAP_NON_IPSEC_FIFO0_PERR_F MEM_WRAP_NON_IPSEC_FIFO0_PERR_V(1U)
-#define TXDATAFIFO_S 5
-#define TXDATAFIFO_M 0xfU
-#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
+#define MEM_WRAP_TP_DB_REQ_FIFO3_PERR_S 7
+#define MEM_WRAP_TP_DB_REQ_FIFO3_PERR_V(x) ((x) << MEM_WRAP_TP_DB_REQ_FIFO3_PERR_S)
+#define MEM_WRAP_TP_DB_REQ_FIFO3_PERR_F MEM_WRAP_TP_DB_REQ_FIFO3_PERR_V(1U)
-#define NCSIFIFO_S 4
-#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
-#define NCSIFIFO_F NCSIFIFO_V(1U)
+#define MEM_WRAP_TP_DB_REQ_FIFO2_PERR_S 6
+#define MEM_WRAP_TP_DB_REQ_FIFO2_PERR_V(x) ((x) << MEM_WRAP_TP_DB_REQ_FIFO2_PERR_S)
+#define MEM_WRAP_TP_DB_REQ_FIFO2_PERR_F MEM_WRAP_TP_DB_REQ_FIFO2_PERR_V(1U)
-#define TPFIFO_S 0
-#define TPFIFO_M 0xfU
-#define TPFIFO_V(x) ((x) << TPFIFO_S)
+#define MEM_WRAP_TP_DB_REQ_FIFO1_PERR_S 5
+#define MEM_WRAP_TP_DB_REQ_FIFO1_PERR_V(x) ((x) << MEM_WRAP_TP_DB_REQ_FIFO1_PERR_S)
+#define MEM_WRAP_TP_DB_REQ_FIFO1_PERR_F MEM_WRAP_TP_DB_REQ_FIFO1_PERR_V(1U)
-#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
-#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
-#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
+#define MEM_WRAP_TP_DB_REQ_FIFO0_PERR_S 4
+#define MEM_WRAP_TP_DB_REQ_FIFO0_PERR_V(x) ((x) << MEM_WRAP_TP_DB_REQ_FIFO0_PERR_S)
+#define MEM_WRAP_TP_DB_REQ_FIFO0_PERR_F MEM_WRAP_TP_DB_REQ_FIFO0_PERR_V(1U)
-#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
-#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
-#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
-#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
-#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
-#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
-#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
-#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
-#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
-#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
-#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
-#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
-#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
-#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
-#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
-#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
-#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
-#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
-#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
-#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
-#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
-#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
-#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
-#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
-#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
-#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
-#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
-#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
-#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
-#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
-#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
-#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
+#define MEM_WRAP_CNTRL_FIFO3_PERR_S 3
+#define MEM_WRAP_CNTRL_FIFO3_PERR_V(x) ((x) << MEM_WRAP_CNTRL_FIFO3_PERR_S)
+#define MEM_WRAP_CNTRL_FIFO3_PERR_F MEM_WRAP_CNTRL_FIFO3_PERR_V(1U)
-#define MPS_TRC_CFG_A 0x9800
+#define MEM_WRAP_CNTRL_FIFO2_PERR_S 2
+#define MEM_WRAP_CNTRL_FIFO2_PERR_V(x) ((x) << MEM_WRAP_CNTRL_FIFO2_PERR_S)
+#define MEM_WRAP_CNTRL_FIFO2_PERR_F MEM_WRAP_CNTRL_FIFO2_PERR_V(1U)
-#define TRCFIFOEMPTY_S 4
-#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
-#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
+#define MEM_WRAP_CNTRL_FIFO1_PERR_S 1
+#define MEM_WRAP_CNTRL_FIFO1_PERR_V(x) ((x) << MEM_WRAP_CNTRL_FIFO1_PERR_S)
+#define MEM_WRAP_CNTRL_FIFO1_PERR_F MEM_WRAP_CNTRL_FIFO1_PERR_V(1U)
-#define TRCIGNOREDROPINPUT_S 3
-#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
-#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
+#define MEM_WRAP_CNTRL_FIFO0_PERR_S 0
+#define MEM_WRAP_CNTRL_FIFO0_PERR_V(x) ((x) << MEM_WRAP_CNTRL_FIFO0_PERR_S)
+#define MEM_WRAP_CNTRL_FIFO0_PERR_F MEM_WRAP_CNTRL_FIFO0_PERR_V(1U)
-#define TRCKEEPDUPLICATES_S 2
-#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
-#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
+#define MPS_RX_PERR_INT_ENABLE6_A 0x11338
+#define MPS_RX_PERR_INT_CAUSE6_A 0x11334
-#define TRCEN_S 1
-#define TRCEN_V(x) ((x) << TRCEN_S)
-#define TRCEN_F TRCEN_V(1U)
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_S 23
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_V(x) ((x) << T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_S)
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_F T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_V(1U)
-#define TRCMULTIFILTER_S 0
-#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
-#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_S 22
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_V(x) ((x) << T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_S)
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_F T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_V(1U)
-#define MPS_TRC_RSS_CONTROL_A 0x9808
-#define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4
-#define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc
-#define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004
-#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_S 21
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_V(x) ((x) << T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_S)
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_F T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_V(1U)
-#define RSSCONTROL_S 16
-#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_S 20
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_V(x) ((x) << T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_S)
+#define T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_F T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_V(1U)
-#define QUEUENUMBER_S 0
-#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR_S 19
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR_S)
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR_F MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR_V(1U)
-#define TFINVERTMATCH_S 24
-#define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)
-#define TFINVERTMATCH_F TFINVERTMATCH_V(1U)
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR_S 18
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR_S)
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR_F MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR_V(1U)
-#define TFEN_S 22
-#define TFEN_V(x) ((x) << TFEN_S)
-#define TFEN_F TFEN_V(1U)
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR_S 17
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR_S)
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR_F MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR_V(1U)
+
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR_S 16
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR_V(x) ((x) << MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR_S)
+#define MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR_F MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR_V(1U)
+
+#define MPS_RX_PG_RSV0_A 0x11010
+#define MPS_RX_PG_RSV4_A 0x11020
+#define MPS_RX_PERR_INT_CAUSE_A 0x11074
+#define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
+#define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
+
+#define MPS_RX_VXLAN_TYPE_A 0x11234
+
+#define VXLAN_EN_S 16
+#define VXLAN_EN_V(x) ((x) << VXLAN_EN_S)
+#define VXLAN_EN_F VXLAN_EN_V(1U)
+
+#define VXLAN_S 0
+#define VXLAN_M 0xffffU
+#define VXLAN_V(x) ((x) << VXLAN_S)
+#define VXLAN_G(x) (((x) >> VXLAN_S) & VXLAN_M)
+
+#define MPS_RX_GENEVE_TYPE_A 0x11238
+
+#define GENEVE_EN_S 16
+#define GENEVE_EN_V(x) ((x) << GENEVE_EN_S)
+#define GENEVE_EN_F GENEVE_EN_V(1U)
+
+#define GENEVE_S 0
+#define GENEVE_M 0xffffU
+#define GENEVE_V(x) ((x) << GENEVE_S)
+#define GENEVE_G(x) (((x) >> GENEVE_S) & GENEVE_M)
+
+#define T7_MPS_TRC_INT_ENABLE_A 0xa4e0
+#define T7_MPS_TRC_INT_CAUSE_A 0xa4e4
+#define T7_MPS_RX_VXLAN_TYPE_A 0x1123c
+#define T7_MPS_RX_GENEVE_TYPE_A 0x11240
+#define MPS_CLS_TCAM_Y_L_A 0xf000
+#define MPS_CLS_TCAM_DATA0_A 0xf000
+#define MPS_CLS_TCAM_DATA1_A 0xf004
+#define MPS_TRC_INT_ENABLE2_A 0xa4f4
+#define MPS_TRC_INT_CAUSE2_A 0xa4f8
+
+#define CTLREQID_S 30
+#define CTLREQID_V(x) ((x) << CTLREQID_S)
+
+#define MPS_VF_RPLCT_MAP0_A 0x1111c
+#define MPS_VF_RPLCT_MAP1_A 0x11120
+#define MPS_VF_RPLCT_MAP2_A 0x11124
+#define MPS_VF_RPLCT_MAP3_A 0x11128
+#define MPS_VF_RPLCT_MAP4_A 0x11300
+#define MPS_VF_RPLCT_MAP5_A 0x11304
+#define MPS_VF_RPLCT_MAP6_A 0x11308
+#define MPS_VF_RPLCT_MAP7_A 0x1130c
+
+#define VIDL_S 16
+#define VIDL_M 0xffffU
+#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
+
+#define DATALKPTYPE_S 10
+#define DATALKPTYPE_M 0x3U
+#define DATALKPTYPE_V(x) ((x) << DATALKPTYPE_S)
+#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
+
+#define DATAPORTNUM_S 12
+#define DATAPORTNUM_M 0xfU
+#define DATAPORTNUM_V(x) ((x) << DATAPORTNUM_S)
+#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)
+
+#define DATADIPHIT_S 8
+#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
+#define DATADIPHIT_F DATADIPHIT_V(1U)
+
+#define DATAVIDH2_S 7
+#define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)
+#define DATAVIDH2_F DATAVIDH2_V(1U)
+
+#define DATAVIDH1_S 0
+#define DATAVIDH1_M 0x7fU
+#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
+
+#define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf020
+#define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf024
+#define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf028
+
+#define USED_S 16
+#define USED_M 0x7ffU
+#define USED_G(x) (((x) >> USED_S) & USED_M)
+
+#define ALLOC_S 0
+#define ALLOC_M 0x7ffU
+#define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)
+
+#define T5_USED_S 16
+#define T5_USED_M 0xfffU
+#define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)
+
+#define T5_ALLOC_S 0
+#define T5_ALLOC_M 0xfffU
+#define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)
+
+#define DMACH_S 0
+#define DMACH_M 0xffffU
+#define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
+
+#define MPS_CLS_TCAM_X_L_A 0xf008
+#define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
+
+#define CTLCMDTYPE_S 31
+#define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
+#define CTLCMDTYPE_F CTLCMDTYPE_V(1U)
+
+#define CTLTCAMSEL_S 25
+#define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
+
+#define CTLTCAMINDEX_S 17
+#define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
+
+#define CTLXYBITSEL_S 16
+#define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
+
+#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
+#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
+
+#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
+#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
+
+#define T7_CTLTCAMSEL_S 26
+#define T7_CTLTCAMSEL_V(x) ((x) << T7_CTLTCAMSEL_S)
+
+#define T7_1_CTLTCAMINDEX_S 17
+#define T7_1_CTLTCAMINDEX_V(x) ((x) << T7_1_CTLTCAMINDEX_S)
+
+#define MPS_CLS_SRAM_L_A 0xe000
+
+#define T6_MULTILISTEN0_S 26
+
+#define T6_SRAM_PRIO3_S 23
+#define T6_SRAM_PRIO3_M 0x7U
+#define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
+
+#define T6_SRAM_PRIO2_S 20
+#define T6_SRAM_PRIO2_M 0x7U
+#define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
+
+#define T6_SRAM_PRIO1_S 17
+#define T6_SRAM_PRIO1_M 0x7U
+#define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
+
+#define T6_SRAM_PRIO0_S 14
+#define T6_SRAM_PRIO0_M 0x7U
+#define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
+
+#define T6_SRAM_VLD_S 13
+#define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
+#define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U)
+
+#define T6_REPLICATE_S 12
+#define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
+#define T6_REPLICATE_F T6_REPLICATE_V(1U)
+
+#define T6_PF_S 9
+#define T6_PF_M 0x7U
+#define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
+
+#define T6_VF_VALID_S 8
+#define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
+#define T6_VF_VALID_F T6_VF_VALID_V(1U)
+
+#define T6_VF_S 0
+#define T6_VF_M 0xffU
+#define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
+
+#define MPS_CLS_SRAM_H_A 0xe004
+
+#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
+#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
-#define TFPORT_S 18
-#define TFPORT_M 0xfU
-#define TFPORT_V(x) ((x) << TFPORT_S)
-#define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)
+#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
+#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
-#define TFLENGTH_S 8
-#define TFLENGTH_M 0x1fU
-#define TFLENGTH_V(x) ((x) << TFLENGTH_S)
-#define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)
+#define MULTILISTEN0_S 25
-#define TFOFFSET_S 0
-#define TFOFFSET_M 0x1fU
-#define TFOFFSET_V(x) ((x) << TFOFFSET_S)
-#define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)
+#define REPLICATE_S 11
+#define REPLICATE_V(x) ((x) << REPLICATE_S)
+#define REPLICATE_F REPLICATE_V(1U)
-#define T5_TFINVERTMATCH_S 25
-#define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)
-#define T5_TFINVERTMATCH_F T5_TFINVERTMATCH_V(1U)
+#define PF_S 8
+#define PF_M 0x7U
+#define PF_G(x) (((x) >> PF_S) & PF_M)
-#define T5_TFEN_S 23
-#define T5_TFEN_V(x) ((x) << T5_TFEN_S)
-#define T5_TFEN_F T5_TFEN_V(1U)
+#define VF_VALID_S 7
+#define VF_VALID_V(x) ((x) << VF_VALID_S)
+#define VF_VALID_F VF_VALID_V(1U)
-#define T5_TFPORT_S 18
-#define T5_TFPORT_M 0x1fU
-#define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)
-#define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)
+#define VF_S 0
+#define VF_M 0x7fU
+#define VF_G(x) (((x) >> VF_S) & VF_M)
-#define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
-#define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
+#define SRAM_PRIO3_S 22
+#define SRAM_PRIO3_M 0x7U
+#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
-#define TFMINPKTSIZE_S 16
-#define TFMINPKTSIZE_M 0x1ffU
-#define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)
-#define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)
+#define SRAM_PRIO2_S 19
+#define SRAM_PRIO2_M 0x7U
+#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
-#define TFCAPTUREMAX_S 0
-#define TFCAPTUREMAX_M 0x3fffU
-#define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)
-#define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)
+#define SRAM_PRIO1_S 16
+#define SRAM_PRIO1_M 0x7U
+#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
-#define MPS_TRC_FILTER0_MATCH_A 0x9c00
-#define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
-#define MPS_TRC_FILTER1_MATCH_A 0x9d00
+#define SRAM_PRIO0_S 13
+#define SRAM_PRIO0_M 0x7U
+#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
-#define TP_RSS_CONFIG_A 0x7df0
+#define SRAM_VLD_S 12
+#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
+#define SRAM_VLD_F SRAM_VLD_V(1U)
-#define TNL4TUPENIPV6_S 31
-#define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
-#define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U)
+#define PORTMAP_S 0
+#define PORTMAP_M 0xfU
+#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
-#define TNL2TUPENIPV6_S 30
-#define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
-#define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U)
+#define CPL_INTR_ENABLE_A 0x19050
+#define CPL_INTR_CAUSE_A 0x19054
-#define TNL4TUPENIPV4_S 29
-#define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
-#define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U)
+#define CIM_OP_MAP_PERR_S 5
+#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
+#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
-#define TNL2TUPENIPV4_S 28
-#define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
-#define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U)
+#define CIM_OVFL_ERROR_S 4
+#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
+#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
-#define TNLTCPSEL_S 27
-#define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
-#define TNLTCPSEL_F TNLTCPSEL_V(1U)
+#define TP_FRAMING_ERROR_S 3
+#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
+#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
-#define TNLIP6SEL_S 26
-#define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
-#define TNLIP6SEL_F TNLIP6SEL_V(1U)
+#define SGE_FRAMING_ERROR_S 2
+#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
+#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
-#define TNLVRTSEL_S 25
-#define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
-#define TNLVRTSEL_F TNLVRTSEL_V(1U)
+#define CIM_FRAMING_ERROR_S 1
+#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
+#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
-#define TNLMAPEN_S 24
-#define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
-#define TNLMAPEN_F TNLMAPEN_V(1U)
+#define ZERO_SWITCH_ERROR_S 0
+#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
+#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
-#define OFDHASHSAVE_S 19
-#define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
-#define OFDHASHSAVE_F OFDHASHSAVE_V(1U)
+#define PERR_CPL_128TO128_1_S 7
+#define PERR_CPL_128TO128_1_V(x) ((x) << PERR_CPL_128TO128_1_S)
+#define PERR_CPL_128TO128_1_F PERR_CPL_128TO128_1_V(1U)
-#define OFDVRTSEL_S 18
-#define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
-#define OFDVRTSEL_F OFDVRTSEL_V(1U)
+#define PERR_CPL_128TO128_0_S 6
+#define PERR_CPL_128TO128_0_V(x) ((x) << PERR_CPL_128TO128_0_S)
+#define PERR_CPL_128TO128_0_F PERR_CPL_128TO128_0_V(1U)
-#define OFDMAPEN_S 17
-#define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
-#define OFDMAPEN_F OFDMAPEN_V(1U)
+#define PERR_CPL_128TO128_3_S 9
+#define PERR_CPL_128TO128_3_V(x) ((x) << PERR_CPL_128TO128_3_S)
+#define PERR_CPL_128TO128_3_F PERR_CPL_128TO128_3_V(1U)
-#define OFDLKPEN_S 16
-#define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
-#define OFDLKPEN_F OFDLKPEN_V(1U)
+#define PERR_CPL_128TO128_2_S 8
+#define PERR_CPL_128TO128_2_V(x) ((x) << PERR_CPL_128TO128_2_S)
+#define PERR_CPL_128TO128_2_F PERR_CPL_128TO128_2_V(1U)
-#define SYN4TUPENIPV6_S 15
-#define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
-#define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U)
+#define SMB_INT_ENABLE_A 0x1908c
+#define SMB_INT_CAUSE_A 0x19090
-#define SYN2TUPENIPV6_S 14
-#define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
-#define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U)
+#define MSTTXFIFOPARINT_S 21
+#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
+#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
-#define SYN4TUPENIPV4_S 13
-#define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
-#define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U)
+#define MSTRXFIFOPARINT_S 20
+#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
+#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
-#define SYN2TUPENIPV4_S 12
-#define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
-#define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U)
+#define SLVFIFOPARINT_S 19
+#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
+#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
-#define SYNIP6SEL_S 11
-#define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
-#define SYNIP6SEL_F SYNIP6SEL_V(1U)
+#define SLVUNEXPBUSSTOPINT_S 18
+#define SLVUNEXPBUSSTOPINT_V(x) ((x) << SLVUNEXPBUSSTOPINT_S)
+#define SLVUNEXPBUSSTOPINT_F SLVUNEXPBUSSTOPINT_V(1U)
-#define SYNVRTSEL_S 10
-#define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
-#define SYNVRTSEL_F SYNVRTSEL_V(1U)
+#define SLVUNEXPBUSSTARTINT_S 17
+#define SLVUNEXPBUSSTARTINT_V(x) ((x) << SLVUNEXPBUSSTARTINT_S)
+#define SLVUNEXPBUSSTARTINT_F SLVUNEXPBUSSTARTINT_V(1U)
-#define SYNMAPEN_S 9
-#define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
-#define SYNMAPEN_F SYNMAPEN_V(1U)
+#define SLVCOMMANDCODEINVINT_S 16
+#define SLVCOMMANDCODEINVINT_V(x) ((x) << SLVCOMMANDCODEINVINT_S)
+#define SLVCOMMANDCODEINVINT_F SLVCOMMANDCODEINVINT_V(1U)
-#define SYNLKPEN_S 8
-#define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
-#define SYNLKPEN_F SYNLKPEN_V(1U)
+#define SLVBYTECNTERRINT_S 15
+#define SLVBYTECNTERRINT_V(x) ((x) << SLVBYTECNTERRINT_S)
+#define SLVBYTECNTERRINT_F SLVBYTECNTERRINT_V(1U)
-#define CHANNELENABLE_S 7
-#define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
-#define CHANNELENABLE_F CHANNELENABLE_V(1U)
+#define SLVUNEXPACKMSTINT_S 14
+#define SLVUNEXPACKMSTINT_V(x) ((x) << SLVUNEXPACKMSTINT_S)
+#define SLVUNEXPACKMSTINT_F SLVUNEXPACKMSTINT_V(1U)
-#define PORTENABLE_S 6
-#define PORTENABLE_V(x) ((x) << PORTENABLE_S)
-#define PORTENABLE_F PORTENABLE_V(1U)
+#define SLVUNEXPNACKMSTINT_S 13
+#define SLVUNEXPNACKMSTINT_V(x) ((x) << SLVUNEXPNACKMSTINT_S)
+#define SLVUNEXPNACKMSTINT_F SLVUNEXPNACKMSTINT_V(1U)
-#define TNLALLLOOKUP_S 5
-#define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
-#define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U)
+#define SLVNOBUSSTOPINT_S 12
+#define SLVNOBUSSTOPINT_V(x) ((x) << SLVNOBUSSTOPINT_S)
+#define SLVNOBUSSTOPINT_F SLVNOBUSSTOPINT_V(1U)
-#define VIRTENABLE_S 4
-#define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
-#define VIRTENABLE_F VIRTENABLE_V(1U)
+#define SLVNOREPSTARTINT_S 11
+#define SLVNOREPSTARTINT_V(x) ((x) << SLVNOREPSTARTINT_S)
+#define SLVNOREPSTARTINT_F SLVNOREPSTARTINT_V(1U)
-#define CONGESTIONENABLE_S 3
-#define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
-#define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U)
+#define SLVRXADDRINT_S 10
+#define SLVRXADDRINT_V(x) ((x) << SLVRXADDRINT_S)
+#define SLVRXADDRINT_F SLVRXADDRINT_V(1U)
-#define HASHTOEPLITZ_S 2
-#define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
-#define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U)
+#define SLVRXPECERRINT_S 9
+#define SLVRXPECERRINT_V(x) ((x) << SLVRXPECERRINT_S)
+#define SLVRXPECERRINT_F SLVRXPECERRINT_V(1U)
-#define UDPENABLE_S 1
-#define UDPENABLE_V(x) ((x) << UDPENABLE_S)
-#define UDPENABLE_F UDPENABLE_V(1U)
+#define SLVPREPTOARPINT_S 8
+#define SLVPREPTOARPINT_V(x) ((x) << SLVPREPTOARPINT_S)
+#define SLVPREPTOARPINT_F SLVPREPTOARPINT_V(1U)
-#define DISABLE_S 0
-#define DISABLE_V(x) ((x) << DISABLE_S)
-#define DISABLE_F DISABLE_V(1U)
+#define SLVTIMEOUTINT_S 7
+#define SLVTIMEOUTINT_V(x) ((x) << SLVTIMEOUTINT_S)
+#define SLVTIMEOUTINT_F SLVTIMEOUTINT_V(1U)
-#define TP_RSS_CONFIG_TNL_A 0x7df4
+#define SLVERRINT_S 6
+#define SLVERRINT_V(x) ((x) << SLVERRINT_S)
+#define SLVERRINT_F SLVERRINT_V(1U)
-#define MASKSIZE_S 28
-#define MASKSIZE_M 0xfU
-#define MASKSIZE_V(x) ((x) << MASKSIZE_S)
-#define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
+#define SLVDONEINT_S 5
+#define SLVDONEINT_V(x) ((x) << SLVDONEINT_S)
+#define SLVDONEINT_F SLVDONEINT_V(1U)
-#define MASKFILTER_S 16
-#define MASKFILTER_M 0x7ffU
-#define MASKFILTER_V(x) ((x) << MASKFILTER_S)
-#define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
+#define SLVRXRDYINT_S 4
+#define SLVRXRDYINT_V(x) ((x) << SLVRXRDYINT_S)
+#define SLVRXRDYINT_F SLVRXRDYINT_V(1U)
-#define USEWIRECH_S 0
-#define USEWIRECH_V(x) ((x) << USEWIRECH_S)
-#define USEWIRECH_F USEWIRECH_V(1U)
+#define MSTTIMEOUTINT_S 3
+#define MSTTIMEOUTINT_V(x) ((x) << MSTTIMEOUTINT_S)
+#define MSTTIMEOUTINT_F MSTTIMEOUTINT_V(1U)
-#define HASHALL_S 2
-#define HASHALL_V(x) ((x) << HASHALL_S)
-#define HASHALL_F HASHALL_V(1U)
+#define MSTNACKINT_S 2
+#define MSTNACKINT_V(x) ((x) << MSTNACKINT_S)
+#define MSTNACKINT_F MSTNACKINT_V(1U)
-#define HASHETH_S 1
-#define HASHETH_V(x) ((x) << HASHETH_S)
-#define HASHETH_F HASHETH_V(1U)
+#define MSTLOSTARBINT_S 1
+#define MSTLOSTARBINT_V(x) ((x) << MSTLOSTARBINT_S)
+#define MSTLOSTARBINT_F MSTLOSTARBINT_V(1U)
-#define TP_RSS_CONFIG_OFD_A 0x7df8
+#define MSTDONEINT_S 0
+#define MSTDONEINT_V(x) ((x) << MSTDONEINT_S)
+#define MSTDONEINT_F MSTDONEINT_V(1U)
-#define RRCPLMAPEN_S 20
-#define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
-#define RRCPLMAPEN_F RRCPLMAPEN_V(1U)
+#define ULP_RX_INT_ENABLE_A 0x19154
+#define ULP_RX_INT_CAUSE_A 0x19158
-#define RRCPLQUEWIDTH_S 16
-#define RRCPLQUEWIDTH_M 0xfU
-#define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
-#define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
+#define CAUSE_CTX_1_S 24
+#define CAUSE_CTX_1_V(x) ((x) << CAUSE_CTX_1_S)
+#define CAUSE_CTX_1_F CAUSE_CTX_1_V(1U)
-#define TP_RSS_CONFIG_SYN_A 0x7dfc
-#define TP_RSS_CONFIG_VRT_A 0x7e00
+#define CAUSE_CTX_0_S 23
+#define CAUSE_CTX_0_V(x) ((x) << CAUSE_CTX_0_S)
+#define CAUSE_CTX_0_F CAUSE_CTX_0_V(1U)
-#define VFRDRG_S 25
-#define VFRDRG_V(x) ((x) << VFRDRG_S)
-#define VFRDRG_F VFRDRG_V(1U)
+#define CAUSE_FF_S 22
+#define CAUSE_FF_V(x) ((x) << CAUSE_FF_S)
+#define CAUSE_FF_F CAUSE_FF_V(1U)
-#define VFRDEN_S 24
-#define VFRDEN_V(x) ((x) << VFRDEN_S)
-#define VFRDEN_F VFRDEN_V(1U)
+#define CAUSE_APF_1_S 21
+#define CAUSE_APF_1_V(x) ((x) << CAUSE_APF_1_S)
+#define CAUSE_APF_1_F CAUSE_APF_1_V(1U)
-#define VFPERREN_S 23
-#define VFPERREN_V(x) ((x) << VFPERREN_S)
-#define VFPERREN_F VFPERREN_V(1U)
+#define CAUSE_APF_0_S 20
+#define CAUSE_APF_0_V(x) ((x) << CAUSE_APF_0_S)
+#define CAUSE_APF_0_F CAUSE_APF_0_V(1U)
-#define KEYPERREN_S 22
-#define KEYPERREN_V(x) ((x) << KEYPERREN_S)
-#define KEYPERREN_F KEYPERREN_V(1U)
+#define CAUSE_AF_1_S 19
+#define CAUSE_AF_1_V(x) ((x) << CAUSE_AF_1_S)
+#define CAUSE_AF_1_F CAUSE_AF_1_V(1U)
-#define DISABLEVLAN_S 21
-#define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
-#define DISABLEVLAN_F DISABLEVLAN_V(1U)
+#define CAUSE_AF_0_S 18
+#define CAUSE_AF_0_V(x) ((x) << CAUSE_AF_0_S)
+#define CAUSE_AF_0_F CAUSE_AF_0_V(1U)
-#define ENABLEUP0_S 20
-#define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
-#define ENABLEUP0_F ENABLEUP0_V(1U)
+#define CAUSE_DDPDF_1_S 17
+#define CAUSE_DDPDF_1_V(x) ((x) << CAUSE_DDPDF_1_S)
+#define CAUSE_DDPDF_1_F CAUSE_DDPDF_1_V(1U)
-#define HASHDELAY_S 16
-#define HASHDELAY_M 0xfU
-#define HASHDELAY_V(x) ((x) << HASHDELAY_S)
-#define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
+#define CAUSE_DDPMF_1_S 16
+#define CAUSE_DDPMF_1_V(x) ((x) << CAUSE_DDPMF_1_S)
+#define CAUSE_DDPMF_1_F CAUSE_DDPMF_1_V(1U)
-#define VFWRADDR_S 8
-#define VFWRADDR_M 0x7fU
-#define VFWRADDR_V(x) ((x) << VFWRADDR_S)
-#define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
+#define CAUSE_MEMRF_1_S 15
+#define CAUSE_MEMRF_1_V(x) ((x) << CAUSE_MEMRF_1_S)
+#define CAUSE_MEMRF_1_F CAUSE_MEMRF_1_V(1U)
-#define KEYMODE_S 6
-#define KEYMODE_M 0x3U
-#define KEYMODE_V(x) ((x) << KEYMODE_S)
-#define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
+#define CAUSE_PRSDF_1_S 14
+#define CAUSE_PRSDF_1_V(x) ((x) << CAUSE_PRSDF_1_S)
+#define CAUSE_PRSDF_1_F CAUSE_PRSDF_1_V(1U)
-#define VFWREN_S 5
-#define VFWREN_V(x) ((x) << VFWREN_S)
-#define VFWREN_F VFWREN_V(1U)
+#define CAUSE_DDPDF_0_S 13
+#define CAUSE_DDPDF_0_V(x) ((x) << CAUSE_DDPDF_0_S)
+#define CAUSE_DDPDF_0_F CAUSE_DDPDF_0_V(1U)
-#define KEYWREN_S 4
-#define KEYWREN_V(x) ((x) << KEYWREN_S)
-#define KEYWREN_F KEYWREN_V(1U)
+#define CAUSE_DDPMF_0_S 12
+#define CAUSE_DDPMF_0_V(x) ((x) << CAUSE_DDPMF_0_S)
+#define CAUSE_DDPMF_0_F CAUSE_DDPMF_0_V(1U)
-#define KEYWRADDR_S 0
-#define KEYWRADDR_M 0xfU
-#define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
-#define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
+#define CAUSE_MEMRF_0_S 11
+#define CAUSE_MEMRF_0_V(x) ((x) << CAUSE_MEMRF_0_S)
+#define CAUSE_MEMRF_0_F CAUSE_MEMRF_0_V(1U)
-#define KEYWRADDRX_S 30
-#define KEYWRADDRX_M 0x3U
-#define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
-#define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
+#define CAUSE_PRSDF_0_S 10
+#define CAUSE_PRSDF_0_V(x) ((x) << CAUSE_PRSDF_0_S)
+#define CAUSE_PRSDF_0_F CAUSE_PRSDF_0_V(1U)
-#define KEYEXTEND_S 26
-#define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
-#define KEYEXTEND_F KEYEXTEND_V(1U)
+#define CAUSE_PCMDF_1_S 9
+#define CAUSE_PCMDF_1_V(x) ((x) << CAUSE_PCMDF_1_S)
+#define CAUSE_PCMDF_1_F CAUSE_PCMDF_1_V(1U)
-#define LKPIDXSIZE_S 24
-#define LKPIDXSIZE_M 0x3U
-#define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
-#define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
+#define CAUSE_TPTCF_1_S 8
+#define CAUSE_TPTCF_1_V(x) ((x) << CAUSE_TPTCF_1_S)
+#define CAUSE_TPTCF_1_F CAUSE_TPTCF_1_V(1U)
-#define TP_RSS_VFL_CONFIG_A 0x3a
-#define TP_RSS_VFH_CONFIG_A 0x3b
+#define CAUSE_DDPCF_1_S 7
+#define CAUSE_DDPCF_1_V(x) ((x) << CAUSE_DDPCF_1_S)
+#define CAUSE_DDPCF_1_F CAUSE_DDPCF_1_V(1U)
-#define ENABLEUDPHASH_S 31
-#define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
-#define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U)
+#define CAUSE_MPARF_1_S 6
+#define CAUSE_MPARF_1_V(x) ((x) << CAUSE_MPARF_1_S)
+#define CAUSE_MPARF_1_F CAUSE_MPARF_1_V(1U)
-#define VFUPEN_S 30
-#define VFUPEN_V(x) ((x) << VFUPEN_S)
-#define VFUPEN_F VFUPEN_V(1U)
+#define CAUSE_MPARC_1_S 5
+#define CAUSE_MPARC_1_V(x) ((x) << CAUSE_MPARC_1_S)
+#define CAUSE_MPARC_1_F CAUSE_MPARC_1_V(1U)
-#define VFVLNEX_S 28
-#define VFVLNEX_V(x) ((x) << VFVLNEX_S)
-#define VFVLNEX_F VFVLNEX_V(1U)
+#define CAUSE_PCMDF_0_S 4
+#define CAUSE_PCMDF_0_V(x) ((x) << CAUSE_PCMDF_0_S)
+#define CAUSE_PCMDF_0_F CAUSE_PCMDF_0_V(1U)
-#define VFPRTEN_S 27
-#define VFPRTEN_V(x) ((x) << VFPRTEN_S)
-#define VFPRTEN_F VFPRTEN_V(1U)
+#define CAUSE_TPTCF_0_S 3
+#define CAUSE_TPTCF_0_V(x) ((x) << CAUSE_TPTCF_0_S)
+#define CAUSE_TPTCF_0_F CAUSE_TPTCF_0_V(1U)
-#define VFCHNEN_S 26
-#define VFCHNEN_V(x) ((x) << VFCHNEN_S)
-#define VFCHNEN_F VFCHNEN_V(1U)
+#define CAUSE_DDPCF_0_S 2
+#define CAUSE_DDPCF_0_V(x) ((x) << CAUSE_DDPCF_0_S)
+#define CAUSE_DDPCF_0_F CAUSE_DDPCF_0_V(1U)
-#define DEFAULTQUEUE_S 16
-#define DEFAULTQUEUE_M 0x3ffU
-#define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
+#define CAUSE_MPARF_0_S 1
+#define CAUSE_MPARF_0_V(x) ((x) << CAUSE_MPARF_0_S)
+#define CAUSE_MPARF_0_F CAUSE_MPARF_0_V(1U)
-#define VFIP6TWOTUPEN_S 6
-#define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
-#define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U)
+#define CAUSE_MPARC_0_S 0
+#define CAUSE_MPARC_0_V(x) ((x) << CAUSE_MPARC_0_S)
+#define CAUSE_MPARC_0_F CAUSE_MPARC_0_V(1U)
-#define VFIP4FOURTUPEN_S 5
-#define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
-#define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U)
+#define SE_CNT_MISMATCH_1_S 26
+#define SE_CNT_MISMATCH_1_V(x) ((x) << SE_CNT_MISMATCH_1_S)
+#define SE_CNT_MISMATCH_1_F SE_CNT_MISMATCH_1_V(1U)
-#define VFIP4TWOTUPEN_S 4
-#define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
-#define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U)
+#define SE_CNT_MISMATCH_0_S 25
+#define SE_CNT_MISMATCH_0_V(x) ((x) << SE_CNT_MISMATCH_0_S)
+#define SE_CNT_MISMATCH_0_F SE_CNT_MISMATCH_0_V(1U)
-#define KEYINDEX_S 0
-#define KEYINDEX_M 0xfU
-#define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
+#define CERR_PCMD_FIFO_3_S 19
+#define CERR_PCMD_FIFO_3_V(x) ((x) << CERR_PCMD_FIFO_3_S)
+#define CERR_PCMD_FIFO_3_F CERR_PCMD_FIFO_3_V(1U)
-#define MAPENABLE_S 31
-#define MAPENABLE_V(x) ((x) << MAPENABLE_S)
-#define MAPENABLE_F MAPENABLE_V(1U)
+#define CERR_PCMD_FIFO_2_S 18
+#define CERR_PCMD_FIFO_2_V(x) ((x) << CERR_PCMD_FIFO_2_S)
+#define CERR_PCMD_FIFO_2_F CERR_PCMD_FIFO_2_V(1U)
-#define CHNENABLE_S 30
-#define CHNENABLE_V(x) ((x) << CHNENABLE_S)
-#define CHNENABLE_F CHNENABLE_V(1U)
+#define CERR_PCMD_FIFO_1_S 17
+#define CERR_PCMD_FIFO_1_V(x) ((x) << CERR_PCMD_FIFO_1_S)
+#define CERR_PCMD_FIFO_1_F CERR_PCMD_FIFO_1_V(1U)
-#define LE_DB_DBGI_CONFIG_A 0x19cf0
+#define CERR_PCMD_FIFO_0_S 16
+#define CERR_PCMD_FIFO_0_V(x) ((x) << CERR_PCMD_FIFO_0_S)
+#define CERR_PCMD_FIFO_0_F CERR_PCMD_FIFO_0_V(1U)
-#define DBGICMDBUSY_S 3
-#define DBGICMDBUSY_V(x) ((x) << DBGICMDBUSY_S)
-#define DBGICMDBUSY_F DBGICMDBUSY_V(1U)
+#define CERR_DATA_FIFO_3_S 15
+#define CERR_DATA_FIFO_3_V(x) ((x) << CERR_DATA_FIFO_3_S)
+#define CERR_DATA_FIFO_3_F CERR_DATA_FIFO_3_V(1U)
-#define DBGICMDSTRT_S 2
-#define DBGICMDSTRT_V(x) ((x) << DBGICMDSTRT_S)
-#define DBGICMDSTRT_F DBGICMDSTRT_V(1U)
+#define CERR_DATA_FIFO_2_S 14
+#define CERR_DATA_FIFO_2_V(x) ((x) << CERR_DATA_FIFO_2_S)
+#define CERR_DATA_FIFO_2_F CERR_DATA_FIFO_2_V(1U)
-#define DBGICMDMODE_S 0
-#define DBGICMDMODE_M 0x3U
-#define DBGICMDMODE_V(x) ((x) << DBGICMDMODE_S)
+#define CERR_DATA_FIFO_1_S 13
+#define CERR_DATA_FIFO_1_V(x) ((x) << CERR_DATA_FIFO_1_S)
+#define CERR_DATA_FIFO_1_F CERR_DATA_FIFO_1_V(1U)
-#define LE_DB_DBGI_REQ_TCAM_CMD_A 0x19cf4
+#define CERR_DATA_FIFO_0_S 12
+#define CERR_DATA_FIFO_0_V(x) ((x) << CERR_DATA_FIFO_0_S)
+#define CERR_DATA_FIFO_0_F CERR_DATA_FIFO_0_V(1U)
-#define DBGICMD_S 20
-#define DBGICMD_M 0xfU
-#define DBGICMD_V(x) ((x) << DBGICMD_S)
+#define SE_CNT_MISMATCH_3_S 11
+#define SE_CNT_MISMATCH_3_V(x) ((x) << SE_CNT_MISMATCH_3_S)
+#define SE_CNT_MISMATCH_3_F SE_CNT_MISMATCH_3_V(1U)
-#define DBGITID_S 0
-#define DBGITID_M 0xfffffU
-#define DBGITID_V(x) ((x) << DBGITID_S)
+#define SE_CNT_MISMATCH_2_S 10
+#define SE_CNT_MISMATCH_2_V(x) ((x) << SE_CNT_MISMATCH_2_S)
+#define SE_CNT_MISMATCH_2_F SE_CNT_MISMATCH_2_V(1U)
-#define LE_DB_DBGI_REQ_DATA_A 0x19d00
-#define LE_DB_DBGI_RSP_STATUS_A 0x19d94
+#define T7_SE_CNT_MISMATCH_1_S 9
+#define T7_SE_CNT_MISMATCH_1_V(x) ((x) << T7_SE_CNT_MISMATCH_1_S)
+#define T7_SE_CNT_MISMATCH_1_F T7_SE_CNT_MISMATCH_1_V(1U)
-#define LE_DB_DBGI_RSP_DATA_A 0x19da0
+#define T7_SE_CNT_MISMATCH_0_S 8
+#define T7_SE_CNT_MISMATCH_0_V(x) ((x) << T7_SE_CNT_MISMATCH_0_S)
+#define T7_SE_CNT_MISMATCH_0_F T7_SE_CNT_MISMATCH_0_V(1U)
-#define PRTENABLE_S 29
-#define PRTENABLE_V(x) ((x) << PRTENABLE_S)
-#define PRTENABLE_F PRTENABLE_V(1U)
+#define T7_ENABLE_CTX_3_S 7
+#define T7_ENABLE_CTX_3_V(x) ((x) << T7_ENABLE_CTX_3_S)
+#define T7_ENABLE_CTX_3_F T7_ENABLE_CTX_3_V(1U)
-#define UDPFOURTUPEN_S 28
-#define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
-#define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U)
+#define T7_ENABLE_CTX_2_S 6
+#define T7_ENABLE_CTX_2_V(x) ((x) << T7_ENABLE_CTX_2_S)
+#define T7_ENABLE_CTX_2_F T7_ENABLE_CTX_2_V(1U)
-#define IP6FOURTUPEN_S 27
-#define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
-#define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U)
+#define T7_ENABLE_CTX_1_S 5
+#define T7_ENABLE_CTX_1_V(x) ((x) << T7_ENABLE_CTX_1_S)
+#define T7_ENABLE_CTX_1_F T7_ENABLE_CTX_1_V(1U)
-#define IP6TWOTUPEN_S 26
-#define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
-#define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U)
+#define T7_ENABLE_CTX_0_S 4
+#define T7_ENABLE_CTX_0_V(x) ((x) << T7_ENABLE_CTX_0_S)
+#define T7_ENABLE_CTX_0_F T7_ENABLE_CTX_0_V(1U)
-#define IP4FOURTUPEN_S 25
-#define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
-#define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U)
+#define T7_ENABLE_ALN_SDC_ERR_3_S 3
+#define T7_ENABLE_ALN_SDC_ERR_3_V(x) ((x) << T7_ENABLE_ALN_SDC_ERR_3_S)
+#define T7_ENABLE_ALN_SDC_ERR_3_F T7_ENABLE_ALN_SDC_ERR_3_V(1U)
-#define IP4TWOTUPEN_S 24
-#define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
-#define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U)
+#define T7_ENABLE_ALN_SDC_ERR_2_S 2
+#define T7_ENABLE_ALN_SDC_ERR_2_V(x) ((x) << T7_ENABLE_ALN_SDC_ERR_2_S)
+#define T7_ENABLE_ALN_SDC_ERR_2_F T7_ENABLE_ALN_SDC_ERR_2_V(1U)
-#define IVFWIDTH_S 20
-#define IVFWIDTH_M 0xfU
-#define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
-#define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
+#define T7_ENABLE_ALN_SDC_ERR_1_S 1
+#define T7_ENABLE_ALN_SDC_ERR_1_V(x) ((x) << T7_ENABLE_ALN_SDC_ERR_1_S)
+#define T7_ENABLE_ALN_SDC_ERR_1_F T7_ENABLE_ALN_SDC_ERR_1_V(1U)
-#define CH1DEFAULTQUEUE_S 10
-#define CH1DEFAULTQUEUE_M 0x3ffU
-#define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
-#define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
+#define T7_ENABLE_ALN_SDC_ERR_0_S 0
+#define T7_ENABLE_ALN_SDC_ERR_0_V(x) ((x) << T7_ENABLE_ALN_SDC_ERR_0_S)
+#define T7_ENABLE_ALN_SDC_ERR_0_F T7_ENABLE_ALN_SDC_ERR_0_V(1U)
-#define CH0DEFAULTQUEUE_S 0
-#define CH0DEFAULTQUEUE_M 0x3ffU
-#define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
-#define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
+#define ULP_RX_ISCSI_LLIMIT_A 0x1915c
+#define ULP_RX_ISCSI_ULIMIT_A 0x19160
+#define ULP_RX_ISCSI_TAGMASK_A 0x19164
+#define ULP_RX_ISCSI_PSZ_A 0x19168
+#define ULP_RX_TDDP_LLIMIT_A 0x1916c
+#define ULP_RX_TDDP_ULIMIT_A 0x19170
+#define ULP_RX_STAG_LLIMIT_A 0x1917c
+#define ULP_RX_STAG_ULIMIT_A 0x19180
+#define ULP_RX_RQ_LLIMIT_A 0x19184
+#define ULP_RX_RQ_ULIMIT_A 0x19188
+#define ULP_RX_PBL_LLIMIT_A 0x1918c
+#define ULP_RX_PBL_ULIMIT_A 0x19190
+#define ULP_RX_CTX_BASE_A 0x19194
+#define ULP_RX_RQUDP_LLIMIT_A 0x191a4
+#define ULP_RX_RQUDP_ULIMIT_A 0x191a8
+#define ULP_RX_LA_CTL_A 0x1923c
+#define ULP_RX_LA_RDPTR_A 0x19240
+#define ULP_RX_LA_RDDATA_A 0x19244
+#define ULP_RX_LA_WRPTR_A 0x19248
+#define ULP_RX_TLS_KEY_LLIMIT_A 0x192ac
+#define ULP_RX_TLS_KEY_ULIMIT_A 0x192b0
-#define VFLKPIDX_S 8
-#define VFLKPIDX_M 0xffU
-#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
+#define ULP_RX_INT_ENABLE_INTERFACE_A 0x191c0
+#define ULP_RX_INT_CAUSE_INTERFACE_A 0x191c4
-#define T6_VFWRADDR_S 8
-#define T6_VFWRADDR_M 0xffU
-#define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
-#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
+#define CAUSE_ULPRX2SBT_RSPPERR_S 31
+#define CAUSE_ULPRX2SBT_RSPPERR_V(x) ((x) << CAUSE_ULPRX2SBT_RSPPERR_S)
+#define CAUSE_ULPRX2SBT_RSPPERR_F CAUSE_ULPRX2SBT_RSPPERR_V(1U)
-#define TP_RSS_CONFIG_CNG_A 0x7e04
-#define TP_RSS_SECRET_KEY0_A 0x40
-#define TP_RSS_PF0_CONFIG_A 0x30
-#define TP_RSS_PF_MAP_A 0x38
-#define TP_RSS_PF_MSK_A 0x39
+#define CAUSE_ULPRX2MA_RSPPERR_S 30
+#define CAUSE_ULPRX2MA_RSPPERR_V(x) ((x) << CAUSE_ULPRX2MA_RSPPERR_S)
+#define CAUSE_ULPRX2MA_RSPPERR_F CAUSE_ULPRX2MA_RSPPERR_V(1U)
-#define PF1LKPIDX_S 3
+#define CAUSE_PIO_BUS_PERR_S 29
+#define CAUSE_PIO_BUS_PERR_V(x) ((x) << CAUSE_PIO_BUS_PERR_S)
+#define CAUSE_PIO_BUS_PERR_F CAUSE_PIO_BUS_PERR_V(1U)
-#define PF0LKPIDX_M 0x7U
+#define CAUSE_PM2ULP_SNOOPDATA_3_S 19
+#define CAUSE_PM2ULP_SNOOPDATA_3_V(x) ((x) << CAUSE_PM2ULP_SNOOPDATA_3_S)
+#define CAUSE_PM2ULP_SNOOPDATA_3_F CAUSE_PM2ULP_SNOOPDATA_3_V(1U)
-#define PF1MSKSIZE_S 4
-#define PF1MSKSIZE_M 0xfU
+#define CAUSE_PM2ULP_SNOOPDATA_2_S 18
+#define CAUSE_PM2ULP_SNOOPDATA_2_V(x) ((x) << CAUSE_PM2ULP_SNOOPDATA_2_S)
+#define CAUSE_PM2ULP_SNOOPDATA_2_F CAUSE_PM2ULP_SNOOPDATA_2_V(1U)
-#define CHNCOUNT3_S 31
-#define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
-#define CHNCOUNT3_F CHNCOUNT3_V(1U)
+#define CAUSE_PM2ULP_SNOOPDATA_1_S 17
+#define CAUSE_PM2ULP_SNOOPDATA_1_V(x) ((x) << CAUSE_PM2ULP_SNOOPDATA_1_S)
+#define CAUSE_PM2ULP_SNOOPDATA_1_F CAUSE_PM2ULP_SNOOPDATA_1_V(1U)
-#define CHNCOUNT2_S 30
-#define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
-#define CHNCOUNT2_F CHNCOUNT2_V(1U)
+#define CAUSE_PM2ULP_SNOOPDATA_0_S 16
+#define CAUSE_PM2ULP_SNOOPDATA_0_V(x) ((x) << CAUSE_PM2ULP_SNOOPDATA_0_S)
+#define CAUSE_PM2ULP_SNOOPDATA_0_F CAUSE_PM2ULP_SNOOPDATA_0_V(1U)
-#define CHNCOUNT1_S 29
-#define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
-#define CHNCOUNT1_F CHNCOUNT1_V(1U)
+#define CAUSE_TLS2ULP_DATA_3_S 15
+#define CAUSE_TLS2ULP_DATA_3_V(x) ((x) << CAUSE_TLS2ULP_DATA_3_S)
+#define CAUSE_TLS2ULP_DATA_3_F CAUSE_TLS2ULP_DATA_3_V(1U)
-#define CHNCOUNT0_S 28
-#define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
-#define CHNCOUNT0_F CHNCOUNT0_V(1U)
+#define CAUSE_TLS2ULP_DATA_2_S 14
+#define CAUSE_TLS2ULP_DATA_2_V(x) ((x) << CAUSE_TLS2ULP_DATA_2_S)
+#define CAUSE_TLS2ULP_DATA_2_F CAUSE_TLS2ULP_DATA_2_V(1U)
-#define CHNUNDFLOW3_S 27
-#define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
-#define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U)
+#define CAUSE_TLS2ULP_DATA_1_S 13
+#define CAUSE_TLS2ULP_DATA_1_V(x) ((x) << CAUSE_TLS2ULP_DATA_1_S)
+#define CAUSE_TLS2ULP_DATA_1_F CAUSE_TLS2ULP_DATA_1_V(1U)
-#define CHNUNDFLOW2_S 26
-#define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
-#define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U)
+#define CAUSE_TLS2ULP_DATA_0_S 12
+#define CAUSE_TLS2ULP_DATA_0_V(x) ((x) << CAUSE_TLS2ULP_DATA_0_S)
+#define CAUSE_TLS2ULP_DATA_0_F CAUSE_TLS2ULP_DATA_0_V(1U)
-#define CHNUNDFLOW1_S 25
-#define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
-#define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U)
+#define CAUSE_TLS2ULP_PLENDATA_3_S 11
+#define CAUSE_TLS2ULP_PLENDATA_3_V(x) ((x) << CAUSE_TLS2ULP_PLENDATA_3_S)
+#define CAUSE_TLS2ULP_PLENDATA_3_F CAUSE_TLS2ULP_PLENDATA_3_V(1U)
-#define CHNUNDFLOW0_S 24
-#define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
-#define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U)
+#define CAUSE_TLS2ULP_PLENDATA_2_S 10
+#define CAUSE_TLS2ULP_PLENDATA_2_V(x) ((x) << CAUSE_TLS2ULP_PLENDATA_2_S)
+#define CAUSE_TLS2ULP_PLENDATA_2_F CAUSE_TLS2ULP_PLENDATA_2_V(1U)
-#define RSTCHN3_S 19
-#define RSTCHN3_V(x) ((x) << RSTCHN3_S)
-#define RSTCHN3_F RSTCHN3_V(1U)
+#define CAUSE_TLS2ULP_PLENDATA_1_S 9
+#define CAUSE_TLS2ULP_PLENDATA_1_V(x) ((x) << CAUSE_TLS2ULP_PLENDATA_1_S)
+#define CAUSE_TLS2ULP_PLENDATA_1_F CAUSE_TLS2ULP_PLENDATA_1_V(1U)
-#define RSTCHN2_S 18
-#define RSTCHN2_V(x) ((x) << RSTCHN2_S)
-#define RSTCHN2_F RSTCHN2_V(1U)
+#define CAUSE_TLS2ULP_PLENDATA_0_S 8
+#define CAUSE_TLS2ULP_PLENDATA_0_V(x) ((x) << CAUSE_TLS2ULP_PLENDATA_0_S)
+#define CAUSE_TLS2ULP_PLENDATA_0_F CAUSE_TLS2ULP_PLENDATA_0_V(1U)
-#define RSTCHN1_S 17
-#define RSTCHN1_V(x) ((x) << RSTCHN1_S)
-#define RSTCHN1_F RSTCHN1_V(1U)
+#define CAUSE_PM2ULP_DATA_3_S 7
+#define CAUSE_PM2ULP_DATA_3_V(x) ((x) << CAUSE_PM2ULP_DATA_3_S)
+#define CAUSE_PM2ULP_DATA_3_F CAUSE_PM2ULP_DATA_3_V(1U)
-#define RSTCHN0_S 16
-#define RSTCHN0_V(x) ((x) << RSTCHN0_S)
-#define RSTCHN0_F RSTCHN0_V(1U)
+#define CAUSE_PM2ULP_DATA_2_S 6
+#define CAUSE_PM2ULP_DATA_2_V(x) ((x) << CAUSE_PM2ULP_DATA_2_S)
+#define CAUSE_PM2ULP_DATA_2_F CAUSE_PM2ULP_DATA_2_V(1U)
-#define UPDVLD_S 15
-#define UPDVLD_V(x) ((x) << UPDVLD_S)
-#define UPDVLD_F UPDVLD_V(1U)
+#define CAUSE_PM2ULP_DATA_1_S 5
+#define CAUSE_PM2ULP_DATA_1_V(x) ((x) << CAUSE_PM2ULP_DATA_1_S)
+#define CAUSE_PM2ULP_DATA_1_F CAUSE_PM2ULP_DATA_1_V(1U)
-#define XOFF_S 14
-#define XOFF_V(x) ((x) << XOFF_S)
-#define XOFF_F XOFF_V(1U)
+#define CAUSE_PM2ULP_DATA_0_S 4
+#define CAUSE_PM2ULP_DATA_0_V(x) ((x) << CAUSE_PM2ULP_DATA_0_S)
+#define CAUSE_PM2ULP_DATA_0_F CAUSE_PM2ULP_DATA_0_V(1U)
-#define UPDCHN3_S 13
-#define UPDCHN3_V(x) ((x) << UPDCHN3_S)
-#define UPDCHN3_F UPDCHN3_V(1U)
+#define CAUSE_TP2ULP_PCMD_3_S 3
+#define CAUSE_TP2ULP_PCMD_3_V(x) ((x) << CAUSE_TP2ULP_PCMD_3_S)
+#define CAUSE_TP2ULP_PCMD_3_F CAUSE_TP2ULP_PCMD_3_V(1U)
-#define UPDCHN2_S 12
-#define UPDCHN2_V(x) ((x) << UPDCHN2_S)
-#define UPDCHN2_F UPDCHN2_V(1U)
+#define CAUSE_TP2ULP_PCMD_2_S 2
+#define CAUSE_TP2ULP_PCMD_2_V(x) ((x) << CAUSE_TP2ULP_PCMD_2_S)
+#define CAUSE_TP2ULP_PCMD_2_F CAUSE_TP2ULP_PCMD_2_V(1U)
-#define UPDCHN1_S 11
-#define UPDCHN1_V(x) ((x) << UPDCHN1_S)
-#define UPDCHN1_F UPDCHN1_V(1U)
+#define CAUSE_TP2ULP_PCMD_1_S 1
+#define CAUSE_TP2ULP_PCMD_1_V(x) ((x) << CAUSE_TP2ULP_PCMD_1_S)
+#define CAUSE_TP2ULP_PCMD_1_F CAUSE_TP2ULP_PCMD_1_V(1U)
-#define UPDCHN0_S 10
-#define UPDCHN0_V(x) ((x) << UPDCHN0_S)
-#define UPDCHN0_F UPDCHN0_V(1U)
+#define CAUSE_TP2ULP_PCMD_0_S 0
+#define CAUSE_TP2ULP_PCMD_0_V(x) ((x) << CAUSE_TP2ULP_PCMD_0_S)
+#define CAUSE_TP2ULP_PCMD_0_F CAUSE_TP2ULP_PCMD_0_V(1U)
-#define QUEUE_S 0
-#define QUEUE_M 0x3ffU
-#define QUEUE_V(x) ((x) << QUEUE_S)
-#define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
+#define ULP_RX_INT_ENABLE_2_A 0x1926c
+#define ULP_RX_INT_CAUSE_2_A 0x19270
-#define MPS_TRC_INT_CAUSE_A 0x985c
+#define ULPRX2MA_INTFPERR_S 8
+#define ULPRX2MA_INTFPERR_V(x) ((x) << ULPRX2MA_INTFPERR_S)
+#define ULPRX2MA_INTFPERR_F ULPRX2MA_INTFPERR_V(1U)
-#define MISCPERR_S 8
-#define MISCPERR_V(x) ((x) << MISCPERR_S)
-#define MISCPERR_F MISCPERR_V(1U)
+#define ALN_SDC_ERR_1_S 7
+#define ALN_SDC_ERR_1_V(x) ((x) << ALN_SDC_ERR_1_S)
+#define ALN_SDC_ERR_1_F ALN_SDC_ERR_1_V(1U)
-#define PKTFIFO_S 4
-#define PKTFIFO_M 0xfU
-#define PKTFIFO_V(x) ((x) << PKTFIFO_S)
+#define ALN_SDC_ERR_0_S 6
+#define ALN_SDC_ERR_0_V(x) ((x) << ALN_SDC_ERR_0_S)
+#define ALN_SDC_ERR_0_F ALN_SDC_ERR_0_V(1U)
-#define FILTMEM_S 0
-#define FILTMEM_M 0xfU
-#define FILTMEM_V(x) ((x) << FILTMEM_S)
+#define PF_UNTAGGED_TPT_1_S 5
+#define PF_UNTAGGED_TPT_1_V(x) ((x) << PF_UNTAGGED_TPT_1_S)
+#define PF_UNTAGGED_TPT_1_F PF_UNTAGGED_TPT_1_V(1U)
-#define MPS_CLS_INT_CAUSE_A 0xd028
+#define PF_UNTAGGED_TPT_0_S 4
+#define PF_UNTAGGED_TPT_0_V(x) ((x) << PF_UNTAGGED_TPT_0_S)
+#define PF_UNTAGGED_TPT_0_F PF_UNTAGGED_TPT_0_V(1U)
-#define HASHSRAM_S 2
-#define HASHSRAM_V(x) ((x) << HASHSRAM_S)
-#define HASHSRAM_F HASHSRAM_V(1U)
+#define PF_PBL_1_S 3
+#define PF_PBL_1_V(x) ((x) << PF_PBL_1_S)
+#define PF_PBL_1_F PF_PBL_1_V(1U)
-#define MATCHTCAM_S 1
-#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
-#define MATCHTCAM_F MATCHTCAM_V(1U)
+#define PF_PBL_0_S 2
+#define PF_PBL_0_V(x) ((x) << PF_PBL_0_S)
+#define PF_PBL_0_F PF_PBL_0_V(1U)
-#define MATCHSRAM_S 0
-#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
-#define MATCHSRAM_F MATCHSRAM_V(1U)
+#define DDP_HINT_1_S 1
+#define DDP_HINT_1_V(x) ((x) << DDP_HINT_1_S)
+#define DDP_HINT_1_F DDP_HINT_1_V(1U)
-#define MPS_RX_PG_RSV0_A 0x11010
-#define MPS_RX_PG_RSV4_A 0x11020
-#define MPS_RX_PERR_INT_CAUSE_A 0x11074
-#define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
-#define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
+#define DDP_HINT_0_S 0
+#define DDP_HINT_0_V(x) ((x) << DDP_HINT_0_S)
+#define DDP_HINT_0_F DDP_HINT_0_V(1U)
-#define MPS_RX_VXLAN_TYPE_A 0x11234
+#define ULP_RX_INT_ENABLE_PCMD_A 0x19300
+#define ULP_RX_INT_CAUSE_PCMD_A 0x19304
-#define VXLAN_EN_S 16
-#define VXLAN_EN_V(x) ((x) << VXLAN_EN_S)
-#define VXLAN_EN_F VXLAN_EN_V(1U)
+#define CAUSE_PCMD_SFIFO_3_S 30
+#define CAUSE_PCMD_SFIFO_3_V(x) ((x) << CAUSE_PCMD_SFIFO_3_S)
+#define CAUSE_PCMD_SFIFO_3_F CAUSE_PCMD_SFIFO_3_V(1U)
-#define VXLAN_S 0
-#define VXLAN_M 0xffffU
-#define VXLAN_V(x) ((x) << VXLAN_S)
-#define VXLAN_G(x) (((x) >> VXLAN_S) & VXLAN_M)
+#define CAUSE_PCMD_FIFO_3_S 29
+#define CAUSE_PCMD_FIFO_3_V(x) ((x) << CAUSE_PCMD_FIFO_3_S)
+#define CAUSE_PCMD_FIFO_3_F CAUSE_PCMD_FIFO_3_V(1U)
-#define MPS_RX_GENEVE_TYPE_A 0x11238
+#define CAUSE_PCMD_DDP_HINT_3_S 28
+#define CAUSE_PCMD_DDP_HINT_3_V(x) ((x) << CAUSE_PCMD_DDP_HINT_3_S)
+#define CAUSE_PCMD_DDP_HINT_3_F CAUSE_PCMD_DDP_HINT_3_V(1U)
-#define GENEVE_EN_S 16
-#define GENEVE_EN_V(x) ((x) << GENEVE_EN_S)
-#define GENEVE_EN_F GENEVE_EN_V(1U)
+#define CAUSE_PCMD_TPT_3_S 27
+#define CAUSE_PCMD_TPT_3_V(x) ((x) << CAUSE_PCMD_TPT_3_S)
+#define CAUSE_PCMD_TPT_3_F CAUSE_PCMD_TPT_3_V(1U)
-#define GENEVE_S 0
-#define GENEVE_M 0xffffU
-#define GENEVE_V(x) ((x) << GENEVE_S)
-#define GENEVE_G(x) (((x) >> GENEVE_S) & GENEVE_M)
+#define CAUSE_PCMD_DDP_3_S 26
+#define CAUSE_PCMD_DDP_3_V(x) ((x) << CAUSE_PCMD_DDP_3_S)
+#define CAUSE_PCMD_DDP_3_F CAUSE_PCMD_DDP_3_V(1U)
-#define MPS_CLS_TCAM_Y_L_A 0xf000
-#define MPS_CLS_TCAM_DATA0_A 0xf000
-#define MPS_CLS_TCAM_DATA1_A 0xf004
+#define CAUSE_PCMD_MPAR_3_S 25
+#define CAUSE_PCMD_MPAR_3_V(x) ((x) << CAUSE_PCMD_MPAR_3_S)
+#define CAUSE_PCMD_MPAR_3_F CAUSE_PCMD_MPAR_3_V(1U)
-#define CTLREQID_S 30
-#define CTLREQID_V(x) ((x) << CTLREQID_S)
+#define CAUSE_PCMD_MPAC_3_S 24
+#define CAUSE_PCMD_MPAC_3_V(x) ((x) << CAUSE_PCMD_MPAC_3_S)
+#define CAUSE_PCMD_MPAC_3_F CAUSE_PCMD_MPAC_3_V(1U)
-#define MPS_VF_RPLCT_MAP0_A 0x1111c
-#define MPS_VF_RPLCT_MAP1_A 0x11120
-#define MPS_VF_RPLCT_MAP2_A 0x11124
-#define MPS_VF_RPLCT_MAP3_A 0x11128
-#define MPS_VF_RPLCT_MAP4_A 0x11300
-#define MPS_VF_RPLCT_MAP5_A 0x11304
-#define MPS_VF_RPLCT_MAP6_A 0x11308
-#define MPS_VF_RPLCT_MAP7_A 0x1130c
+#define CAUSE_PCMD_SFIFO_2_S 22
+#define CAUSE_PCMD_SFIFO_2_V(x) ((x) << CAUSE_PCMD_SFIFO_2_S)
+#define CAUSE_PCMD_SFIFO_2_F CAUSE_PCMD_SFIFO_2_V(1U)
-#define VIDL_S 16
-#define VIDL_M 0xffffU
-#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
+#define CAUSE_PCMD_FIFO_2_S 21
+#define CAUSE_PCMD_FIFO_2_V(x) ((x) << CAUSE_PCMD_FIFO_2_S)
+#define CAUSE_PCMD_FIFO_2_F CAUSE_PCMD_FIFO_2_V(1U)
-#define DATALKPTYPE_S 10
-#define DATALKPTYPE_M 0x3U
-#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
+#define CAUSE_PCMD_DDP_HINT_2_S 20
+#define CAUSE_PCMD_DDP_HINT_2_V(x) ((x) << CAUSE_PCMD_DDP_HINT_2_S)
+#define CAUSE_PCMD_DDP_HINT_2_F CAUSE_PCMD_DDP_HINT_2_V(1U)
-#define DATAPORTNUM_S 12
-#define DATAPORTNUM_M 0xfU
-#define DATAPORTNUM_V(x) ((x) << DATAPORTNUM_S)
-#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)
+#define CAUSE_PCMD_TPT_2_S 19
+#define CAUSE_PCMD_TPT_2_V(x) ((x) << CAUSE_PCMD_TPT_2_S)
+#define CAUSE_PCMD_TPT_2_F CAUSE_PCMD_TPT_2_V(1U)
+
+#define CAUSE_PCMD_DDP_2_S 18
+#define CAUSE_PCMD_DDP_2_V(x) ((x) << CAUSE_PCMD_DDP_2_S)
+#define CAUSE_PCMD_DDP_2_F CAUSE_PCMD_DDP_2_V(1U)
+
+#define CAUSE_PCMD_MPAR_2_S 17
+#define CAUSE_PCMD_MPAR_2_V(x) ((x) << CAUSE_PCMD_MPAR_2_S)
+#define CAUSE_PCMD_MPAR_2_F CAUSE_PCMD_MPAR_2_V(1U)
-#define DATALKPTYPE_S 10
-#define DATALKPTYPE_M 0x3U
-#define DATALKPTYPE_V(x) ((x) << DATALKPTYPE_S)
-#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
+#define CAUSE_PCMD_MPAC_2_S 16
+#define CAUSE_PCMD_MPAC_2_V(x) ((x) << CAUSE_PCMD_MPAC_2_S)
+#define CAUSE_PCMD_MPAC_2_F CAUSE_PCMD_MPAC_2_V(1U)
-#define DATADIPHIT_S 8
-#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
-#define DATADIPHIT_F DATADIPHIT_V(1U)
+#define CAUSE_PCMD_SFIFO_1_S 14
+#define CAUSE_PCMD_SFIFO_1_V(x) ((x) << CAUSE_PCMD_SFIFO_1_S)
+#define CAUSE_PCMD_SFIFO_1_F CAUSE_PCMD_SFIFO_1_V(1U)
-#define DATAVIDH2_S 7
-#define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)
-#define DATAVIDH2_F DATAVIDH2_V(1U)
+#define CAUSE_PCMD_FIFO_1_S 13
+#define CAUSE_PCMD_FIFO_1_V(x) ((x) << CAUSE_PCMD_FIFO_1_S)
+#define CAUSE_PCMD_FIFO_1_F CAUSE_PCMD_FIFO_1_V(1U)
-#define DATAVIDH1_S 0
-#define DATAVIDH1_M 0x7fU
-#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
+#define CAUSE_PCMD_DDP_HINT_1_S 12
+#define CAUSE_PCMD_DDP_HINT_1_V(x) ((x) << CAUSE_PCMD_DDP_HINT_1_S)
+#define CAUSE_PCMD_DDP_HINT_1_F CAUSE_PCMD_DDP_HINT_1_V(1U)
-#define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf020
-#define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf024
-#define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf028
+#define CAUSE_PCMD_TPT_1_S 11
+#define CAUSE_PCMD_TPT_1_V(x) ((x) << CAUSE_PCMD_TPT_1_S)
+#define CAUSE_PCMD_TPT_1_F CAUSE_PCMD_TPT_1_V(1U)
-#define USED_S 16
-#define USED_M 0x7ffU
-#define USED_G(x) (((x) >> USED_S) & USED_M)
+#define CAUSE_PCMD_DDP_1_S 10
+#define CAUSE_PCMD_DDP_1_V(x) ((x) << CAUSE_PCMD_DDP_1_S)
+#define CAUSE_PCMD_DDP_1_F CAUSE_PCMD_DDP_1_V(1U)
-#define ALLOC_S 0
-#define ALLOC_M 0x7ffU
-#define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)
+#define CAUSE_PCMD_MPAR_1_S 9
+#define CAUSE_PCMD_MPAR_1_V(x) ((x) << CAUSE_PCMD_MPAR_1_S)
+#define CAUSE_PCMD_MPAR_1_F CAUSE_PCMD_MPAR_1_V(1U)
-#define T5_USED_S 16
-#define T5_USED_M 0xfffU
-#define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)
+#define CAUSE_PCMD_MPAC_1_S 8
+#define CAUSE_PCMD_MPAC_1_V(x) ((x) << CAUSE_PCMD_MPAC_1_S)
+#define CAUSE_PCMD_MPAC_1_F CAUSE_PCMD_MPAC_1_V(1U)
-#define T5_ALLOC_S 0
-#define T5_ALLOC_M 0xfffU
-#define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)
+#define CAUSE_PCMD_SFIFO_0_S 6
+#define CAUSE_PCMD_SFIFO_0_V(x) ((x) << CAUSE_PCMD_SFIFO_0_S)
+#define CAUSE_PCMD_SFIFO_0_F CAUSE_PCMD_SFIFO_0_V(1U)
-#define DMACH_S 0
-#define DMACH_M 0xffffU
-#define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
+#define CAUSE_PCMD_FIFO_0_S 5
+#define CAUSE_PCMD_FIFO_0_V(x) ((x) << CAUSE_PCMD_FIFO_0_S)
+#define CAUSE_PCMD_FIFO_0_F CAUSE_PCMD_FIFO_0_V(1U)
-#define MPS_CLS_TCAM_X_L_A 0xf008
-#define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
+#define CAUSE_PCMD_DDP_HINT_0_S 4
+#define CAUSE_PCMD_DDP_HINT_0_V(x) ((x) << CAUSE_PCMD_DDP_HINT_0_S)
+#define CAUSE_PCMD_DDP_HINT_0_F CAUSE_PCMD_DDP_HINT_0_V(1U)
-#define CTLCMDTYPE_S 31
-#define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
-#define CTLCMDTYPE_F CTLCMDTYPE_V(1U)
+#define CAUSE_PCMD_TPT_0_S 3
+#define CAUSE_PCMD_TPT_0_V(x) ((x) << CAUSE_PCMD_TPT_0_S)
+#define CAUSE_PCMD_TPT_0_F CAUSE_PCMD_TPT_0_V(1U)
-#define CTLTCAMSEL_S 25
-#define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
+#define CAUSE_PCMD_DDP_0_S 2
+#define CAUSE_PCMD_DDP_0_V(x) ((x) << CAUSE_PCMD_DDP_0_S)
+#define CAUSE_PCMD_DDP_0_F CAUSE_PCMD_DDP_0_V(1U)
-#define CTLTCAMINDEX_S 17
-#define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
+#define CAUSE_PCMD_MPAR_0_S 1
+#define CAUSE_PCMD_MPAR_0_V(x) ((x) << CAUSE_PCMD_MPAR_0_S)
+#define CAUSE_PCMD_MPAR_0_F CAUSE_PCMD_MPAR_0_V(1U)
-#define CTLXYBITSEL_S 16
-#define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
+#define CAUSE_PCMD_MPAC_0_S 0
+#define CAUSE_PCMD_MPAC_0_V(x) ((x) << CAUSE_PCMD_MPAC_0_S)
+#define CAUSE_PCMD_MPAC_0_F CAUSE_PCMD_MPAC_0_V(1U)
-#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
-#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
+#define ULP_RX_INT_ENABLE_DATA_A 0x19310
+#define ULP_RX_INT_CAUSE_DATA_A 0x19314
-#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
-#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
+#define CAUSE_DATA_SNOOP_3_S 29
+#define CAUSE_DATA_SNOOP_3_V(x) ((x) << CAUSE_DATA_SNOOP_3_S)
+#define CAUSE_DATA_SNOOP_3_F CAUSE_DATA_SNOOP_3_V(1U)
-#define MPS_CLS_SRAM_L_A 0xe000
+#define CAUSE_DATA_SFIFO_3_S 28
+#define CAUSE_DATA_SFIFO_3_V(x) ((x) << CAUSE_DATA_SFIFO_3_S)
+#define CAUSE_DATA_SFIFO_3_F CAUSE_DATA_SFIFO_3_V(1U)
-#define T6_MULTILISTEN0_S 26
+#define CAUSE_DATA_FIFO_3_S 27
+#define CAUSE_DATA_FIFO_3_V(x) ((x) << CAUSE_DATA_FIFO_3_S)
+#define CAUSE_DATA_FIFO_3_F CAUSE_DATA_FIFO_3_V(1U)
-#define T6_SRAM_PRIO3_S 23
-#define T6_SRAM_PRIO3_M 0x7U
-#define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
+#define CAUSE_DATA_DDP_3_S 26
+#define CAUSE_DATA_DDP_3_V(x) ((x) << CAUSE_DATA_DDP_3_S)
+#define CAUSE_DATA_DDP_3_F CAUSE_DATA_DDP_3_V(1U)
-#define T6_SRAM_PRIO2_S 20
-#define T6_SRAM_PRIO2_M 0x7U
-#define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
+#define CAUSE_DATA_CTX_3_S 25
+#define CAUSE_DATA_CTX_3_V(x) ((x) << CAUSE_DATA_CTX_3_S)
+#define CAUSE_DATA_CTX_3_F CAUSE_DATA_CTX_3_V(1U)
-#define T6_SRAM_PRIO1_S 17
-#define T6_SRAM_PRIO1_M 0x7U
-#define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
+#define CAUSE_DATA_PARSER_3_S 24
+#define CAUSE_DATA_PARSER_3_V(x) ((x) << CAUSE_DATA_PARSER_3_S)
+#define CAUSE_DATA_PARSER_3_F CAUSE_DATA_PARSER_3_V(1U)
-#define T6_SRAM_PRIO0_S 14
-#define T6_SRAM_PRIO0_M 0x7U
-#define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
+#define CAUSE_DATA_SNOOP_2_S 21
+#define CAUSE_DATA_SNOOP_2_V(x) ((x) << CAUSE_DATA_SNOOP_2_S)
+#define CAUSE_DATA_SNOOP_2_F CAUSE_DATA_SNOOP_2_V(1U)
-#define T6_SRAM_VLD_S 13
-#define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
-#define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U)
+#define CAUSE_DATA_SFIFO_2_S 20
+#define CAUSE_DATA_SFIFO_2_V(x) ((x) << CAUSE_DATA_SFIFO_2_S)
+#define CAUSE_DATA_SFIFO_2_F CAUSE_DATA_SFIFO_2_V(1U)
-#define T6_REPLICATE_S 12
-#define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
-#define T6_REPLICATE_F T6_REPLICATE_V(1U)
+#define CAUSE_DATA_FIFO_2_S 19
+#define CAUSE_DATA_FIFO_2_V(x) ((x) << CAUSE_DATA_FIFO_2_S)
+#define CAUSE_DATA_FIFO_2_F CAUSE_DATA_FIFO_2_V(1U)
-#define T6_PF_S 9
-#define T6_PF_M 0x7U
-#define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
+#define CAUSE_DATA_DDP_2_S 18
+#define CAUSE_DATA_DDP_2_V(x) ((x) << CAUSE_DATA_DDP_2_S)
+#define CAUSE_DATA_DDP_2_F CAUSE_DATA_DDP_2_V(1U)
-#define T6_VF_VALID_S 8
-#define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
-#define T6_VF_VALID_F T6_VF_VALID_V(1U)
+#define CAUSE_DATA_CTX_2_S 17
+#define CAUSE_DATA_CTX_2_V(x) ((x) << CAUSE_DATA_CTX_2_S)
+#define CAUSE_DATA_CTX_2_F CAUSE_DATA_CTX_2_V(1U)
-#define T6_VF_S 0
-#define T6_VF_M 0xffU
-#define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
+#define CAUSE_DATA_PARSER_2_S 16
+#define CAUSE_DATA_PARSER_2_V(x) ((x) << CAUSE_DATA_PARSER_2_S)
+#define CAUSE_DATA_PARSER_2_F CAUSE_DATA_PARSER_2_V(1U)
-#define MPS_CLS_SRAM_H_A 0xe004
+#define CAUSE_DATA_SNOOP_1_S 13
+#define CAUSE_DATA_SNOOP_1_V(x) ((x) << CAUSE_DATA_SNOOP_1_S)
+#define CAUSE_DATA_SNOOP_1_F CAUSE_DATA_SNOOP_1_V(1U)
-#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
-#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
+#define CAUSE_DATA_SFIFO_1_S 12
+#define CAUSE_DATA_SFIFO_1_V(x) ((x) << CAUSE_DATA_SFIFO_1_S)
+#define CAUSE_DATA_SFIFO_1_F CAUSE_DATA_SFIFO_1_V(1U)
-#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
-#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
+#define CAUSE_DATA_FIFO_1_S 11
+#define CAUSE_DATA_FIFO_1_V(x) ((x) << CAUSE_DATA_FIFO_1_S)
+#define CAUSE_DATA_FIFO_1_F CAUSE_DATA_FIFO_1_V(1U)
-#define MULTILISTEN0_S 25
+#define CAUSE_DATA_DDP_1_S 10
+#define CAUSE_DATA_DDP_1_V(x) ((x) << CAUSE_DATA_DDP_1_S)
+#define CAUSE_DATA_DDP_1_F CAUSE_DATA_DDP_1_V(1U)
-#define REPLICATE_S 11
-#define REPLICATE_V(x) ((x) << REPLICATE_S)
-#define REPLICATE_F REPLICATE_V(1U)
+#define CAUSE_DATA_CTX_1_S 9
+#define CAUSE_DATA_CTX_1_V(x) ((x) << CAUSE_DATA_CTX_1_S)
+#define CAUSE_DATA_CTX_1_F CAUSE_DATA_CTX_1_V(1U)
-#define PF_S 8
-#define PF_M 0x7U
-#define PF_G(x) (((x) >> PF_S) & PF_M)
+#define CAUSE_DATA_PARSER_1_S 8
+#define CAUSE_DATA_PARSER_1_V(x) ((x) << CAUSE_DATA_PARSER_1_S)
+#define CAUSE_DATA_PARSER_1_F CAUSE_DATA_PARSER_1_V(1U)
-#define VF_VALID_S 7
-#define VF_VALID_V(x) ((x) << VF_VALID_S)
-#define VF_VALID_F VF_VALID_V(1U)
+#define CAUSE_DATA_SNOOP_0_S 5
+#define CAUSE_DATA_SNOOP_0_V(x) ((x) << CAUSE_DATA_SNOOP_0_S)
+#define CAUSE_DATA_SNOOP_0_F CAUSE_DATA_SNOOP_0_V(1U)
-#define VF_S 0
-#define VF_M 0x7fU
-#define VF_G(x) (((x) >> VF_S) & VF_M)
+#define CAUSE_DATA_SFIFO_0_S 4
+#define CAUSE_DATA_SFIFO_0_V(x) ((x) << CAUSE_DATA_SFIFO_0_S)
+#define CAUSE_DATA_SFIFO_0_F CAUSE_DATA_SFIFO_0_V(1U)
-#define SRAM_PRIO3_S 22
-#define SRAM_PRIO3_M 0x7U
-#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
+#define CAUSE_DATA_FIFO_0_S 3
+#define CAUSE_DATA_FIFO_0_V(x) ((x) << CAUSE_DATA_FIFO_0_S)
+#define CAUSE_DATA_FIFO_0_F CAUSE_DATA_FIFO_0_V(1U)
-#define SRAM_PRIO2_S 19
-#define SRAM_PRIO2_M 0x7U
-#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
+#define CAUSE_DATA_DDP_0_S 2
+#define CAUSE_DATA_DDP_0_V(x) ((x) << CAUSE_DATA_DDP_0_S)
+#define CAUSE_DATA_DDP_0_F CAUSE_DATA_DDP_0_V(1U)
-#define SRAM_PRIO1_S 16
-#define SRAM_PRIO1_M 0x7U
-#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
+#define CAUSE_DATA_CTX_0_S 1
+#define CAUSE_DATA_CTX_0_V(x) ((x) << CAUSE_DATA_CTX_0_S)
+#define CAUSE_DATA_CTX_0_F CAUSE_DATA_CTX_0_V(1U)
-#define SRAM_PRIO0_S 13
-#define SRAM_PRIO0_M 0x7U
-#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
+#define CAUSE_DATA_PARSER_0_S 0
+#define CAUSE_DATA_PARSER_0_V(x) ((x) << CAUSE_DATA_PARSER_0_S)
+#define CAUSE_DATA_PARSER_0_F CAUSE_DATA_PARSER_0_V(1U)
-#define SRAM_VLD_S 12
-#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
-#define SRAM_VLD_F SRAM_VLD_V(1U)
+#define ULP_RX_INT_ENABLE_ARB_A 0x19320
+#define ULP_RX_INT_CAUSE_ARB_A 0x19324
-#define PORTMAP_S 0
-#define PORTMAP_M 0xfU
-#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
+#define CAUSE_ARB_PBL_PF_3_S 27
+#define CAUSE_ARB_PBL_PF_3_V(x) ((x) << CAUSE_ARB_PBL_PF_3_S)
+#define CAUSE_ARB_PBL_PF_3_F CAUSE_ARB_PBL_PF_3_V(1U)
-#define CPL_INTR_CAUSE_A 0x19054
+#define CAUSE_ARB_PF_3_S 26
+#define CAUSE_ARB_PF_3_V(x) ((x) << CAUSE_ARB_PF_3_S)
+#define CAUSE_ARB_PF_3_F CAUSE_ARB_PF_3_V(1U)
-#define CIM_OP_MAP_PERR_S 5
-#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
-#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
+#define CAUSE_ARB_TPT_PF_3_S 25
+#define CAUSE_ARB_TPT_PF_3_V(x) ((x) << CAUSE_ARB_TPT_PF_3_S)
+#define CAUSE_ARB_TPT_PF_3_F CAUSE_ARB_TPT_PF_3_V(1U)
-#define CIM_OVFL_ERROR_S 4
-#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
-#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
+#define CAUSE_ARB_F_3_S 24
+#define CAUSE_ARB_F_3_V(x) ((x) << CAUSE_ARB_F_3_S)
+#define CAUSE_ARB_F_3_F CAUSE_ARB_F_3_V(1U)
-#define TP_FRAMING_ERROR_S 3
-#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
-#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
+#define CAUSE_ARB_PBL_PF_2_S 19
+#define CAUSE_ARB_PBL_PF_2_V(x) ((x) << CAUSE_ARB_PBL_PF_2_S)
+#define CAUSE_ARB_PBL_PF_2_F CAUSE_ARB_PBL_PF_2_V(1U)
-#define SGE_FRAMING_ERROR_S 2
-#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
-#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
+#define CAUSE_ARB_PF_2_S 18
+#define CAUSE_ARB_PF_2_V(x) ((x) << CAUSE_ARB_PF_2_S)
+#define CAUSE_ARB_PF_2_F CAUSE_ARB_PF_2_V(1U)
-#define CIM_FRAMING_ERROR_S 1
-#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
-#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
+#define CAUSE_ARB_TPT_PF_2_S 17
+#define CAUSE_ARB_TPT_PF_2_V(x) ((x) << CAUSE_ARB_TPT_PF_2_S)
+#define CAUSE_ARB_TPT_PF_2_F CAUSE_ARB_TPT_PF_2_V(1U)
-#define ZERO_SWITCH_ERROR_S 0
-#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
-#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
+#define CAUSE_ARB_F_2_S 16
+#define CAUSE_ARB_F_2_V(x) ((x) << CAUSE_ARB_F_2_S)
+#define CAUSE_ARB_F_2_F CAUSE_ARB_F_2_V(1U)
-#define SMB_INT_CAUSE_A 0x19090
+#define CAUSE_ARB_PBL_PF_1_S 11
+#define CAUSE_ARB_PBL_PF_1_V(x) ((x) << CAUSE_ARB_PBL_PF_1_S)
+#define CAUSE_ARB_PBL_PF_1_F CAUSE_ARB_PBL_PF_1_V(1U)
-#define MSTTXFIFOPARINT_S 21
-#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
-#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
+#define CAUSE_ARB_PF_1_S 10
+#define CAUSE_ARB_PF_1_V(x) ((x) << CAUSE_ARB_PF_1_S)
+#define CAUSE_ARB_PF_1_F CAUSE_ARB_PF_1_V(1U)
-#define MSTRXFIFOPARINT_S 20
-#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
-#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
+#define CAUSE_ARB_TPT_PF_1_S 9
+#define CAUSE_ARB_TPT_PF_1_V(x) ((x) << CAUSE_ARB_TPT_PF_1_S)
+#define CAUSE_ARB_TPT_PF_1_F CAUSE_ARB_TPT_PF_1_V(1U)
-#define SLVFIFOPARINT_S 19
-#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
-#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
+#define CAUSE_ARB_F_1_S 8
+#define CAUSE_ARB_F_1_V(x) ((x) << CAUSE_ARB_F_1_S)
+#define CAUSE_ARB_F_1_F CAUSE_ARB_F_1_V(1U)
-#define ULP_RX_INT_CAUSE_A 0x19158
-#define ULP_RX_ISCSI_LLIMIT_A 0x1915c
-#define ULP_RX_ISCSI_ULIMIT_A 0x19160
-#define ULP_RX_ISCSI_TAGMASK_A 0x19164
-#define ULP_RX_ISCSI_PSZ_A 0x19168
-#define ULP_RX_TDDP_LLIMIT_A 0x1916c
-#define ULP_RX_TDDP_ULIMIT_A 0x19170
-#define ULP_RX_STAG_LLIMIT_A 0x1917c
-#define ULP_RX_STAG_ULIMIT_A 0x19180
-#define ULP_RX_RQ_LLIMIT_A 0x19184
-#define ULP_RX_RQ_ULIMIT_A 0x19188
-#define ULP_RX_PBL_LLIMIT_A 0x1918c
-#define ULP_RX_PBL_ULIMIT_A 0x19190
-#define ULP_RX_CTX_BASE_A 0x19194
-#define ULP_RX_RQUDP_LLIMIT_A 0x191a4
-#define ULP_RX_RQUDP_ULIMIT_A 0x191a8
-#define ULP_RX_LA_CTL_A 0x1923c
-#define ULP_RX_LA_RDPTR_A 0x19240
-#define ULP_RX_LA_RDDATA_A 0x19244
-#define ULP_RX_LA_WRPTR_A 0x19248
-#define ULP_RX_TLS_KEY_LLIMIT_A 0x192ac
-#define ULP_RX_TLS_KEY_ULIMIT_A 0x192b0
+#define CAUSE_ARB_PBL_PF_0_S 3
+#define CAUSE_ARB_PBL_PF_0_V(x) ((x) << CAUSE_ARB_PBL_PF_0_S)
+#define CAUSE_ARB_PBL_PF_0_F CAUSE_ARB_PBL_PF_0_V(1U)
+
+#define CAUSE_ARB_PF_0_S 2
+#define CAUSE_ARB_PF_0_V(x) ((x) << CAUSE_ARB_PF_0_S)
+#define CAUSE_ARB_PF_0_F CAUSE_ARB_PF_0_V(1U)
+
+#define CAUSE_ARB_TPT_PF_0_S 1
+#define CAUSE_ARB_TPT_PF_0_V(x) ((x) << CAUSE_ARB_TPT_PF_0_S)
+#define CAUSE_ARB_TPT_PF_0_F CAUSE_ARB_TPT_PF_0_V(1U)
+
+#define CAUSE_ARB_F_0_S 0
+#define CAUSE_ARB_F_0_V(x) ((x) << CAUSE_ARB_F_0_S)
+#define CAUSE_ARB_F_0_F CAUSE_ARB_F_0_V(1U)
#define HPZ3_S 24
#define HPZ3_V(x) ((x) << HPZ3_S)
@@ -2850,6 +6782,10 @@
#define ULP_RX_TDDP_PSZ_A 0x19178
+#define MPS_CLS_TCAM0_RDATA1_REQ_ID1_A 0xf020
+#define MPS_CLS_TCAM0_RDATA0_REQ_ID1_A 0xf01c
+#define MPS_CLS_TCAM0_RDATA2_REQ_ID1_A 0xf024
+
/* registers for module SF */
#define SF_DATA_A 0x193f8
#define SF_OP_A 0x193fc
@@ -2873,7 +6809,12 @@
#define OP_V(x) ((x) << OP_S)
#define OP_F OP_V(1U)
+#define QUADREADDISABLE_S 5
+#define QUADREADDISABLE_V(x) ((x) << QUADREADDISABLE_S)
+#define QUADREADDISABLE_F QUADREADDISABLE_V(1U)
+
#define PL_PF_INT_CAUSE_A 0x3c0
+#define PL_PF_INT_ENABLE_A 0x3c4
#define PFSW_S 3
#define PFSW_V(x) ((x) << PFSW_S)
@@ -2883,20 +6824,14 @@
#define PFCIM_V(x) ((x) << PFCIM_S)
#define PFCIM_F PFCIM_V(1U)
-#define PL_PF_INT_ENABLE_A 0x3c4
#define PL_PF_CTL_A 0x3c8
#define PL_WHOAMI_A 0x19400
+#define PL_PERR_CAUSE_A 0x19404
-#define SOURCEPF_S 8
-#define SOURCEPF_M 0x7U
-#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
-
-#define T6_SOURCEPF_S 9
-#define T6_SOURCEPF_M 0x7U
-#define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)
-
-#define PL_INT_CAUSE_A 0x1940c
+#define UART_S 28
+#define UART_V(x) ((x) << UART_S)
+#define UART_F UART_V(1U)
#define ULP_TX_S 27
#define ULP_TX_V(x) ((x) << ULP_TX_S)
@@ -2906,6 +6841,10 @@
#define SGE_V(x) ((x) << SGE_S)
#define SGE_F SGE_V(1U)
+#define HMA_S 25
+#define HMA_V(x) ((x) << HMA_S)
+#define HMA_F HMA_V(1U)
+
#define CPL_SWITCH_S 24
#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
#define CPL_SWITCH_F CPL_SWITCH_V(1U)
@@ -2950,6 +6889,10 @@
#define PCIE_V(x) ((x) << PCIE_S)
#define PCIE_F PCIE_V(1U)
+#define PMU_S 13
+#define PMU_V(x) ((x) << PMU_S)
+#define PMU_F PMU_V(1U)
+
#define XGMAC_KR1_S 12
#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
#define XGMAC_KR1_F XGMAC_KR1_V(1U)
@@ -2982,19 +6925,258 @@
#define NCSI_V(x) ((x) << NCSI_S)
#define NCSI_F NCSI_V(1U)
-#define MPS_S 4
-#define MPS_V(x) ((x) << MPS_S)
-#define MPS_F MPS_V(1U)
+#define MPS_S 4
+#define MPS_V(x) ((x) << MPS_S)
+#define MPS_F MPS_V(1U)
+
+#define MI_S 3
+#define MI_V(x) ((x) << MI_S)
+#define MI_F MI_V(1U)
+
+#define DBG_S 2
+#define DBG_V(x) ((x) << DBG_S)
+#define DBG_F DBG_V(1U)
+
+#define I2CM_S 1
+#define I2CM_V(x) ((x) << I2CM_S)
+#define I2CM_F I2CM_V(1U)
+
+#define CIM_S 0
+#define CIM_V(x) ((x) << CIM_S)
+#define CIM_F CIM_V(1U)
+
+#define T7_PL_PERR_CRYPTO_KEY_S 31
+#define T7_PL_PERR_CRYPTO_KEY_V(x) ((x) << T7_PL_PERR_CRYPTO_KEY_S)
+#define T7_PL_PERR_CRYPTO_KEY_F T7_PL_PERR_CRYPTO_KEY_V(1U)
+
+#define T7_PL_PERR_CRYPTO1_S 30
+#define T7_PL_PERR_CRYPTO1_V(x) ((x) << T7_PL_PERR_CRYPTO1_S)
+#define T7_PL_PERR_CRYPTO1_F T7_PL_PERR_CRYPTO1_V(1U)
+
+#define T7_PL_PERR_CRYPTO0_S 29
+#define T7_PL_PERR_CRYPTO0_V(x) ((x) << T7_PL_PERR_CRYPTO0_S)
+#define T7_PL_PERR_CRYPTO0_F T7_PL_PERR_CRYPTO0_V(1U)
+
+#define T7_PL_PERR_GCACHE_S 28
+#define T7_PL_PERR_GCACHE_V(x) ((x) << T7_PL_PERR_GCACHE_S)
+#define T7_PL_PERR_GCACHE_F T7_PL_PERR_GCACHE_V(1U)
+
+#define T7_PL_PERR_ULP_TX_S 26
+#define T7_PL_PERR_ULP_TX_V(x) ((x) << T7_PL_PERR_ULP_TX_S)
+#define T7_PL_PERR_ULP_TX_F T7_PL_PERR_ULP_TX_V(1U)
+
+#define T7_PL_PERR_SGE_S 25
+#define T7_PL_PERR_SGE_V(x) ((x) << T7_PL_PERR_SGE_S)
+#define T7_PL_PERR_SGE_F T7_PL_PERR_SGE_V(1U)
+
+#define T7_PL_PERR_HMA_S 24
+#define T7_PL_PERR_HMA_V(x) ((x) << T7_PL_PERR_HMA_S)
+#define T7_PL_PERR_HMA_F T7_PL_PERR_HMA_V(1U)
+
+#define T7_PL_PERR_CPL_SWITCH_S 23
+#define T7_PL_PERR_CPL_SWITCH_V(x) ((x) << T7_PL_PERR_CPL_SWITCH_S)
+#define T7_PL_PERR_CPL_SWITCH_F T7_PL_PERR_CPL_SWITCH_V(1U)
+
+#define T7_PL_PERR_ULP_RX_S 22
+#define T7_PL_PERR_ULP_RX_V(x) ((x) << T7_PL_PERR_ULP_RX_S)
+#define T7_PL_PERR_ULP_RX_F T7_PL_PERR_ULP_RX_V(1U)
+
+#define T7_PL_PERR_PM_RX_S 21
+#define T7_PL_PERR_PM_RX_V(x) ((x) << T7_PL_PERR_PM_RX_S)
+#define T7_PL_PERR_PM_RX_F T7_PL_PERR_PM_RX_V(1U)
+
+#define T7_PL_PERR_PM_TX_S 20
+#define T7_PL_PERR_PM_TX_V(x) ((x) << T7_PL_PERR_PM_TX_S)
+#define T7_PL_PERR_PM_TX_F T7_PL_PERR_PM_TX_V(1U)
+
+#define T7_PL_PERR_MA_S 19
+#define T7_PL_PERR_MA_V(x) ((x) << T7_PL_PERR_MA_S)
+#define T7_PL_PERR_MA_F T7_PL_PERR_MA_V(1U)
+
+#define T7_PL_PERR_TP_S 18
+#define T7_PL_PERR_TP_V(x) ((x) << T7_PL_PERR_TP_S)
+#define T7_PL_PERR_TP_F T7_PL_PERR_TP_V(1U)
+
+#define T7_PL_PERR_LE_S 17
+#define T7_PL_PERR_LE_V(x) ((x) << T7_PL_PERR_LE_S)
+#define T7_PL_PERR_LE_F T7_PL_PERR_LE_V(1U)
+
+#define T7_PL_PERR_EDC1_S 16
+#define T7_PL_PERR_EDC1_V(x) ((x) << T7_PL_PERR_EDC1_S)
+#define T7_PL_PERR_EDC1_F T7_PL_PERR_EDC1_V(1U)
+
+#define T7_PL_PERR_EDC0_S 15
+#define T7_PL_PERR_EDC0_V(x) ((x) << T7_PL_PERR_EDC0_S)
+#define T7_PL_PERR_EDC0_F T7_PL_PERR_EDC0_V(1U)
+
+#define T7_PL_PERR_MC1_S 14
+#define T7_PL_PERR_MC1_V(x) ((x) << T7_PL_PERR_MC1_S)
+#define T7_PL_PERR_MC1_F T7_PL_PERR_MC1_V(1U)
+
+#define T7_PL_PERR_MC0_S 13
+#define T7_PL_PERR_MC0_V(x) ((x) << T7_PL_PERR_MC0_S)
+#define T7_PL_PERR_MC0_F T7_PL_PERR_MC0_V(1U)
+
+#define T7_PL_PERR_PCIE_S 12
+#define T7_PL_PERR_PCIE_V(x) ((x) << T7_PL_PERR_PCIE_S)
+#define T7_PL_PERR_PCIE_F T7_PL_PERR_PCIE_V(1U)
+
+#define T7_PL_PERR_UART_S 11
+#define T7_PL_PERR_UART_V(x) ((x) << T7_PL_PERR_UART_S)
+#define T7_PL_PERR_UART_F T7_PL_PERR_UART_V(1U)
+
+#define T7_PL_PERR_PMU_S 10
+#define T7_PL_PERR_PMU_V(x) ((x) << T7_PL_PERR_PMU_S)
+#define T7_PL_PERR_PMU_F T7_PL_PERR_PMU_V(1U)
+
+#define T7_PL_PERR_MAC_S 9
+#define T7_PL_PERR_MAC_V(x) ((x) << T7_PL_PERR_MAC_S)
+#define T7_PL_PERR_MAC_F T7_PL_PERR_MAC_V(1U)
+
+#define T7_PL_PERR_SMB_S 8
+#define T7_PL_PERR_SMB_V(x) ((x) << T7_PL_PERR_SMB_S)
+#define T7_PL_PERR_SMB_F T7_PL_PERR_SMB_V(1U)
+
+#define T7_PL_PERR_SF_S 7
+#define T7_PL_PERR_SF_V(x) ((x) << T7_PL_PERR_SF_S)
+#define T7_PL_PERR_SF_F T7_PL_PERR_SF_V(1U)
+
+#define T7_PL_PERR_PL_S 6
+#define T7_PL_PERR_PL_V(x) ((x) << T7_PL_PERR_PL_S)
+#define T7_PL_PERR_PL_F T7_PL_PERR_PL_V(1U)
+
+#define T7_PL_PERR_NCSI_S 5
+#define T7_PL_PERR_NCSI_V(x) ((x) << T7_PL_PERR_NCSI_S)
+#define T7_PL_PERR_NCSI_F T7_PL_PERR_NCSI_V(1U)
+
+#define T7_PL_PERR_MPS_S 4
+#define T7_PL_PERR_MPS_V(x) ((x) << T7_PL_PERR_MPS_S)
+#define T7_PL_PERR_MPS_F T7_PL_PERR_MPS_V(1U)
+
+#define T7_PL_PERR_MI_S 3
+#define T7_PL_PERR_MI_V(x) ((x) << T7_PL_PERR_MI_S)
+#define T7_PL_PERR_MI_F T7_PL_PERR_MI_V(1U)
+
+#define T7_PL_PERR_DBG_S 2
+#define T7_PL_PERR_DBG_V(x) ((x) << T7_PL_PERR_DBG_S)
+#define T7_PL_PERR_DBG_F T7_PL_PERR_DBG_V(1U)
+
+#define T7_PL_PERR_I2CM_S 1
+#define T7_PL_PERR_I2CM_V(x) ((x) << T7_PL_PERR_I2CM_S)
+#define T7_PL_PERR_I2CM_F T7_PL_PERR_I2CM_V(1U)
+
+#define T7_PL_PERR_CIM_S 0
+#define T7_PL_PERR_CIM_V(x) ((x) << T7_PL_PERR_CIM_S)
+#define T7_PL_PERR_CIM_F T7_PL_PERR_CIM_V(1U)
+
+#define SOURCEPF_S 8
+#define SOURCEPF_M 0x7U
+#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
+
+#define T6_SOURCEPF_S 9
+#define T6_SOURCEPF_M 0x7U
+#define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)
+
+#define PL_PERR_ENABLE_A 0x19408
+#define PL_INT_ENABLE_A 0x19410
+#define PL_INT_CAUSE_A 0x1940c
+
+#define MC1_S 31
+#define MC1_V(x) ((x) << MC1_S)
+#define MC1_F MC1_V(1U)
+
+#define MAC3_S 12
+#define MAC3_V(x) ((x) << MAC3_S)
+#define MAC3_F MAC3_V(1U)
+
+#define MAC2_S 11
+#define MAC2_V(x) ((x) << MAC2_S)
+#define MAC2_F MAC2_V(1U)
+
+#define MC0_S 15
+#define MC0_V(x) ((x) << MC0_S)
+#define MC0_F MC0_V(1U)
+
+#define MAC1_S 10
+#define MAC1_V(x) ((x) << MAC1_S)
+#define MAC1_F MAC1_V(1U)
+
+#define MAC0_S 9
+#define MAC0_V(x) ((x) << MAC0_S)
+#define MAC0_F MAC0_V(1U)
+
+#define T7_FLR_S 31
+#define T7_FLR_V(x) ((x) << T7_FLR_S)
+#define T7_FLR_F T7_FLR_V(1U)
+
+#define T7_SW_CIM_S 30
+#define T7_SW_CIM_V(x) ((x) << T7_SW_CIM_S)
+#define T7_SW_CIM_F T7_SW_CIM_V(1U)
+
+#define T7_HMA_S 27
+#define T7_HMA_V(x) ((x) << T7_HMA_S)
+#define T7_HMA_F T7_HMA_V(1U)
+
+#define T7_UART_S 14
+#define T7_UART_V(x) ((x) << T7_UART_S)
+#define T7_UART_F T7_UART_V(1U)
+
+#define T7_ULP_TX_S 29
+#define T7_ULP_TX_V(x) ((x) << T7_ULP_TX_S)
+#define T7_ULP_TX_F T7_ULP_TX_V(1U)
+
+#define T7_SGE_S 28
+#define T7_SGE_V(x) ((x) << T7_SGE_S)
+#define T7_SGE_F T7_SGE_V(1U)
+
+#define T7_CPL_SWITCH_S 26
+#define T7_CPL_SWITCH_V(x) ((x) << T7_CPL_SWITCH_S)
+#define T7_CPL_SWITCH_F T7_CPL_SWITCH_V(1U)
+
+#define T7_ULP_RX_S 25
+#define T7_ULP_RX_V(x) ((x) << T7_ULP_RX_S)
+#define T7_ULP_RX_F T7_ULP_RX_V(1U)
+
+#define T7_PM_RX_S 24
+#define T7_PM_RX_V(x) ((x) << T7_PM_RX_S)
+#define T7_PM_RX_F T7_PM_RX_V(1U)
+
+#define T7_PM_TX_S 23
+#define T7_PM_TX_V(x) ((x) << T7_PM_TX_S)
+#define T7_PM_TX_F T7_PM_TX_V(1U)
+
+#define T7_MA_S 22
+#define T7_MA_V(x) ((x) << T7_MA_S)
+#define T7_MA_F T7_MA_V(1U)
+
+#define T7_TP_S 21
+#define T7_TP_V(x) ((x) << T7_TP_S)
+#define T7_TP_F T7_TP_V(1U)
+
+#define T7_LE_S 20
+#define T7_LE_V(x) ((x) << T7_LE_S)
+#define T7_LE_F T7_LE_V(1U)
+
+#define T7_EDC1_S 19
+#define T7_EDC1_V(x) ((x) << T7_EDC1_S)
+#define T7_EDC1_F T7_EDC1_V(1U)
+
+#define T7_EDC0_S 18
+#define T7_EDC0_V(x) ((x) << T7_EDC0_S)
+#define T7_EDC0_F T7_EDC0_V(1U)
-#define CIM_S 0
-#define CIM_V(x) ((x) << CIM_S)
-#define CIM_F CIM_V(1U)
+#define T7_PCIE_S 15
+#define T7_PCIE_V(x) ((x) << T7_PCIE_S)
+#define T7_PCIE_F T7_PCIE_V(1U)
-#define MC1_S 31
-#define MC1_V(x) ((x) << MC1_S)
-#define MC1_F MC1_V(1U)
+#define T7_MC1_S 17
+#define T7_MC1_V(x) ((x) << T7_MC1_S)
+#define T7_MC1_F T7_MC1_V(1U)
+
+#define T7_MC0_S 16
+#define T7_MC0_V(x) ((x) << T7_MC0_S)
+#define T7_MC0_F T7_MC0_V(1U)
-#define PL_INT_ENABLE_A 0x19410
#define PL_INT_MAP0_A 0x19414
#define PL_RST_A 0x19428
@@ -3006,16 +7188,33 @@
#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
#define PIORSTMODE_F PIORSTMODE_V(1U)
+#define PL_PL_INT_ENABLE_A 0x19434
#define PL_PL_INT_CAUSE_A 0x19430
#define FATALPERR_S 4
#define FATALPERR_V(x) ((x) << FATALPERR_S)
#define FATALPERR_F FATALPERR_V(1U)
+#define INVALIDACCESS_S 3
+#define INVALIDACCESS_V(x) ((x) << INVALIDACCESS_S)
+#define INVALIDACCESS_F INVALIDACCESS_V(1U)
+
+#define TIMEOUT_S 2
+#define TIMEOUT_V(x) ((x) << TIMEOUT_S)
+#define TIMEOUT_F TIMEOUT_V(1U)
+
+#define PLERR_S 1
+#define PLERR_V(x) ((x) << PLERR_S)
+#define PLERR_F PLERR_V(1U)
+
#define PERRVFID_S 0
#define PERRVFID_V(x) ((x) << PERRVFID_S)
#define PERRVFID_F PERRVFID_V(1U)
+#define PL_BUSPERR_S 6
+#define PL_BUSPERR_V(x) ((x) << PL_BUSPERR_S)
+#define PL_BUSPERR_F PL_BUSPERR_V(1U)
+
#define PL_REV_A 0x1943c
#define REV_S 0
@@ -3023,25 +7222,24 @@
#define REV_V(x) ((x) << REV_S)
#define REV_G(x) (((x) >> REV_S) & REV_M)
-#define HASHTBLMEMCRCERR_S 27
-#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)
-#define HASHTBLMEMCRCERR_F HASHTBLMEMCRCERR_V(1U)
+#define PL_INT_ENABLE2_A 0x1947c
+#define PL_INT_CAUSE2_A 0x19478
-#define CMDTIDERR_S 22
-#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)
-#define CMDTIDERR_F CMDTIDERR_V(1U)
+#define CRYPTO_KEY_S 4
+#define CRYPTO_KEY_V(x) ((x) << CRYPTO_KEY_S)
+#define CRYPTO_KEY_F CRYPTO_KEY_V(1U)
-#define T6_UNKNOWNCMD_S 3
-#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
-#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
+#define CRYPTO1_S 3
+#define CRYPTO1_V(x) ((x) << CRYPTO1_S)
+#define CRYPTO1_F CRYPTO1_V(1U)
-#define T6_LIP0_S 2
-#define T6_LIP0_V(x) ((x) << T6_LIP0_S)
-#define T6_LIP0_F T6_LIP0_V(1U)
+#define CRYPTO0_S 2
+#define CRYPTO0_V(x) ((x) << CRYPTO0_S)
+#define CRYPTO0_F CRYPTO0_V(1U)
-#define T6_LIPMISS_S 1
-#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
-#define T6_LIPMISS_F T6_LIPMISS_V(1U)
+#define GCACHE_S 1
+#define GCACHE_V(x) ((x) << GCACHE_S)
+#define GCACHE_F GCACHE_V(1U)
#define LE_DB_CONFIG_A 0x19c04
#define LE_DB_ROUTING_TABLE_INDEX_A 0x19c10
@@ -3062,13 +7260,147 @@
#define HASHTBLSIZE_M 0x1ffffU
#define HASHTBLSIZE_G(x) (((x) >> HASHTBLSIZE_S) & HASHTBLSIZE_M)
+#define VFPARERR_S 14
+#define VFPARERR_V(x) ((x) << VFPARERR_S)
+#define VFPARERR_F VFPARERR_V(1U)
+
#define LE_DB_HASH_TID_BASE_A 0x19c30
#define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
-#define LE_DB_INT_CAUSE_A 0x19c3c
#define LE_DB_CLCAM_TID_BASE_A 0x19df4
#define LE_DB_TID_HASHBASE_A 0x19df8
#define T6_LE_DB_HASH_TID_BASE_A 0x19df8
+#define LE_DB_INT_ENABLE_A 0x19c38
+#define LE_DB_INT_CAUSE_A 0x19c3c
+
+#define CLIPSUBERR_S 29
+#define CLIPSUBERR_V(x) ((x) << CLIPSUBERR_S)
+#define CLIPSUBERR_F CLIPSUBERR_V(1U)
+
+#define CLCAMFIFOERR_S 28
+#define CLCAMFIFOERR_V(x) ((x) << CLCAMFIFOERR_S)
+#define CLCAMFIFOERR_F CLCAMFIFOERR_V(1U)
+
+#define HASHTBLMEMCRCERR_S 27
+#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)
+#define HASHTBLMEMCRCERR_F HASHTBLMEMCRCERR_V(1U)
+
+#define CTCAMINVLDENT_S 26
+#define CTCAMINVLDENT_V(x) ((x) << CTCAMINVLDENT_S)
+#define CTCAMINVLDENT_F CTCAMINVLDENT_V(1U)
+
+#define TCAMINVLDENT_S 25
+#define TCAMINVLDENT_V(x) ((x) << TCAMINVLDENT_S)
+#define TCAMINVLDENT_F TCAMINVLDENT_V(1U)
+
+#define TOTCNTERR_S 24
+#define TOTCNTERR_V(x) ((x) << TOTCNTERR_S)
+#define TOTCNTERR_F TOTCNTERR_V(1U)
+
+#define CMDPRSRINTERR_S 23
+#define CMDPRSRINTERR_V(x) ((x) << CMDPRSRINTERR_S)
+#define CMDPRSRINTERR_F CMDPRSRINTERR_V(1U)
+
+#define CMDTIDERR_S 22
+#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)
+#define CMDTIDERR_F CMDTIDERR_V(1U)
+
+#define T6_ACTRGNFULL_S 21
+#define T6_ACTRGNFULL_V(x) ((x) << T6_ACTRGNFULL_S)
+#define T6_ACTRGNFULL_F T6_ACTRGNFULL_V(1U)
+
+#define T6_ACTCNTIPV6TZERO_S 20
+#define T6_ACTCNTIPV6TZERO_V(x) ((x) << T6_ACTCNTIPV6TZERO_S)
+#define T6_ACTCNTIPV6TZERO_F T6_ACTCNTIPV6TZERO_V(1U)
+
+#define T6_ACTCNTIPV4TZERO_S 19
+#define T6_ACTCNTIPV4TZERO_V(x) ((x) << T6_ACTCNTIPV4TZERO_S)
+#define T6_ACTCNTIPV4TZERO_F T6_ACTCNTIPV4TZERO_V(1U)
+
+#define T6_ACTCNTIPV6ZERO_S 18
+#define T6_ACTCNTIPV6ZERO_V(x) ((x) << T6_ACTCNTIPV6ZERO_S)
+#define T6_ACTCNTIPV6ZERO_F T6_ACTCNTIPV6ZERO_V(1U)
+
+#define T6_ACTCNTIPV4ZERO_S 17
+#define T6_ACTCNTIPV4ZERO_V(x) ((x) << T6_ACTCNTIPV4ZERO_S)
+#define T6_ACTCNTIPV4ZERO_F T6_ACTCNTIPV4ZERO_V(1U)
+
+#define MAIFWRINTPERR_S 16
+#define MAIFWRINTPERR_V(x) ((x) << MAIFWRINTPERR_S)
+#define MAIFWRINTPERR_F MAIFWRINTPERR_V(1U)
+
+#define HASHTBLMEMACCERR_S 15
+#define HASHTBLMEMACCERR_V(x) ((x) << HASHTBLMEMACCERR_S)
+#define HASHTBLMEMACCERR_F HASHTBLMEMACCERR_V(1U)
+
+#define TCAMCRCERR_S 14
+#define TCAMCRCERR_V(x) ((x) << TCAMCRCERR_S)
+#define TCAMCRCERR_F TCAMCRCERR_V(1U)
+
+#define TCAMINTPERR_S 13
+#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
+#define TCAMINTPERR_F TCAMINTPERR_V(1U)
+
+#define VFSRAMPERR_S 12
+#define VFSRAMPERR_V(x) ((x) << VFSRAMPERR_S)
+#define VFSRAMPERR_F VFSRAMPERR_V(1U)
+
+#define SRVSRAMPERR_S 11
+#define SRVSRAMPERR_V(x) ((x) << SRVSRAMPERR_S)
+#define SRVSRAMPERR_F SRVSRAMPERR_V(1U)
+
+#define SSRAMINTPERR_S 10
+#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
+#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
+
+#define CLCAMINTPERR_S 9
+#define CLCAMINTPERR_V(x) ((x) << CLCAMINTPERR_S)
+#define CLCAMINTPERR_F CLCAMINTPERR_V(1U)
+
+#define CLCAMCRCPARERR_S 8
+#define CLCAMCRCPARERR_V(x) ((x) << CLCAMCRCPARERR_S)
+#define CLCAMCRCPARERR_F CLCAMCRCPARERR_V(1U)
+
+#define HASHTBLACCFAIL_S 7
+#define HASHTBLACCFAIL_V(x) ((x) << HASHTBLACCFAIL_S)
+#define HASHTBLACCFAIL_F HASHTBLACCFAIL_V(1U)
+
+#define TCAMACCFAIL_S 6
+#define TCAMACCFAIL_V(x) ((x) << TCAMACCFAIL_S)
+#define TCAMACCFAIL_F TCAMACCFAIL_V(1U)
+
+#define SRVSRAMACCFAIL_S 5
+#define SRVSRAMACCFAIL_V(x) ((x) << SRVSRAMACCFAIL_S)
+#define SRVSRAMACCFAIL_F SRVSRAMACCFAIL_V(1U)
+
+#define CLIPTCAMACCFAIL_S 4
+#define CLIPTCAMACCFAIL_V(x) ((x) << CLIPTCAMACCFAIL_S)
+#define CLIPTCAMACCFAIL_F CLIPTCAMACCFAIL_V(1U)
+
+#define T6_UNKNOWNCMD_S 3
+#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
+#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
+
+#define T6_LIP0_S 2
+#define T6_LIP0_V(x) ((x) << T6_LIP0_S)
+#define T6_LIP0_F T6_LIP0_V(1U)
+
+#define T6_LIPMISS_S 1
+#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
+#define T6_LIPMISS_F T6_LIPMISS_V(1U)
+
+#define PIPELINEERR_S 0
+#define PIPELINEERR_V(x) ((x) << PIPELINEERR_S)
+#define PIPELINEERR_F PIPELINEERR_V(1U)
+
+#define CACHEINTPERR_S 31
+#define CACHEINTPERR_V(x) ((x) << CACHEINTPERR_S)
+#define CACHEINTPERR_F CACHEINTPERR_V(1U)
+
+#define CACHESRAMPERR_S 30
+#define CACHESRAMPERR_V(x) ((x) << CACHESRAMPERR_S)
+#define CACHESRAMPERR_F CACHESRAMPERR_V(1U)
+
#define HASHEN_S 20
#define HASHEN_V(x) ((x) << HASHEN_S)
#define HASHEN_F HASHEN_V(1U)
@@ -3085,6 +7417,10 @@
#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
#define UNKNOWNCMD_F UNKNOWNCMD_V(1U)
+#define ACTRGNFULL_S 7
+#define ACTRGNFULL_V(x) ((x) << ACTRGNFULL_S)
+#define ACTRGNFULL_F ACTRGNFULL_V(1U)
+
#define PARITYERR_S 6
#define PARITYERR_V(x) ((x) << PARITYERR_S)
#define PARITYERR_F PARITYERR_V(1U)
@@ -3101,14 +7437,6 @@
#define BASEADDR_M 0x1fffffffU
#define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M)
-#define TCAMINTPERR_S 13
-#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
-#define TCAMINTPERR_F TCAMINTPERR_V(1U)
-
-#define SSRAMINTPERR_S 10
-#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
-#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
-
#define LE_DB_RSP_CODE_0_A 0x19c74
#define TCAM_ACTV_HIT_S 0
@@ -3126,8 +7454,13 @@
#define LE_3_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eac
#define LE_4_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eb0
+#define NCSI_INT_ENABLE_A 0x1a0d4
#define NCSI_INT_CAUSE_A 0x1a0d8
+#define CIM2NC_PERR_S 9
+#define CIM2NC_PERR_V(x) ((x) << CIM2NC_PERR_S)
+#define CIM2NC_PERR_F CIM2NC_PERR_V(1U)
+
#define CIM_DM_PRTY_ERR_S 8
#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)
@@ -3144,6 +7477,53 @@
#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)
+#define NCSI_XGMAC0_INT_ENABLE_A 0x1a2d4
+#define NCSI_XGMAC0_INT_CAUSE_A 0x1a2d8
+
+#define XAUIPCSDECERR_S 24
+#define XAUIPCSDECERR_V(x) ((x) << XAUIPCSDECERR_S)
+#define XAUIPCSDECERR_F XAUIPCSDECERR_V(1U)
+
+#define RGMIIRXFIFOOVERFLOW_S 23
+#define RGMIIRXFIFOOVERFLOW_V(x) ((x) << RGMIIRXFIFOOVERFLOW_S)
+#define RGMIIRXFIFOOVERFLOW_F RGMIIRXFIFOOVERFLOW_V(1U)
+
+#define RGMIIRXFIFOUNDERFLOW_S 22
+#define RGMIIRXFIFOUNDERFLOW_V(x) ((x) << RGMIIRXFIFOUNDERFLOW_S)
+#define RGMIIRXFIFOUNDERFLOW_F RGMIIRXFIFOUNDERFLOW_V(1U)
+
+#define RXPKTSIZEERROR_S 21
+#define RXPKTSIZEERROR_V(x) ((x) << RXPKTSIZEERROR_S)
+#define RXPKTSIZEERROR_F RXPKTSIZEERROR_V(1U)
+
+#define WOLPATDETECTED_S 20
+#define WOLPATDETECTED_V(x) ((x) << WOLPATDETECTED_S)
+#define WOLPATDETECTED_F WOLPATDETECTED_V(1U)
+
+#define TXFIFO_UNDERRUN_S 13
+#define TXFIFO_UNDERRUN_V(x) ((x) << TXFIFO_UNDERRUN_S)
+#define TXFIFO_UNDERRUN_F TXFIFO_UNDERRUN_V(1U)
+
+#define RXFIFO_OVERFLOW_S 12
+#define RXFIFO_OVERFLOW_V(x) ((x) << RXFIFO_OVERFLOW_S)
+#define RXFIFO_OVERFLOW_F RXFIFO_OVERFLOW_V(1U)
+
+#define XAUIPCSCTCERR_S 3
+#define XAUIPCSCTCERR_V(x) ((x) << XAUIPCSCTCERR_S)
+#define XAUIPCSCTCERR_F XAUIPCSCTCERR_V(1U)
+
+#define XAUIPCSALIGNCHANGE_S 2
+#define XAUIPCSALIGNCHANGE_V(x) ((x) << XAUIPCSALIGNCHANGE_S)
+#define XAUIPCSALIGNCHANGE_F XAUIPCSALIGNCHANGE_V(1U)
+
+#define RGMIILINKSTSCHANGE_S 1
+#define RGMIILINKSTSCHANGE_V(x) ((x) << RGMIILINKSTSCHANGE_S)
+#define RGMIILINKSTSCHANGE_F RGMIILINKSTSCHANGE_V(1U)
+
+#define XGM_INT_S 2
+#define XGM_INT_V(x) ((x) << XGM_INT_S)
+#define XGM_INT_F XGM_INT_V(1U)
+
#define XGMAC_PORT_CFG2_A 0x1018
#define PATEN_S 18
@@ -3171,8 +7551,180 @@
#define ADDRESS_V(x) ((x) << ADDRESS_S)
#define MAC_PORT_INT_CAUSE_A 0x8dc
+#define T7_MAC_PORT_INT_EN_A 0x868
+#define T7_MAC_PORT_INT_CAUSE_A 0x86c
+
+#define MAC2MPS_PERR_CAUSE_S 31
+#define MAC2MPS_PERR_CAUSE_V(x) ((x) << MAC2MPS_PERR_CAUSE_S)
+#define MAC2MPS_PERR_CAUSE_F MAC2MPS_PERR_CAUSE_V(1U)
+
+#define MAC_PPS_INT_CAUSE_S 30
+#define MAC_PPS_INT_CAUSE_V(x) ((x) << MAC_PPS_INT_CAUSE_S)
+#define MAC_PPS_INT_CAUSE_F MAC_PPS_INT_CAUSE_V(1U)
+
+#define MAC_TX_TS_AVAIL_INT_CAUSE_S 29
+#define MAC_TX_TS_AVAIL_INT_CAUSE_V(x) ((x) << MAC_TX_TS_AVAIL_INT_CAUSE_S)
+#define MAC_TX_TS_AVAIL_INT_CAUSE_F MAC_TX_TS_AVAIL_INT_CAUSE_V(1U)
+
+#define MAC_PATDETWAKE_INT_CAUSE_S 26
+#define MAC_PATDETWAKE_INT_CAUSE_V(x) ((x) << MAC_PATDETWAKE_INT_CAUSE_S)
+#define MAC_PATDETWAKE_INT_CAUSE_F MAC_PATDETWAKE_INT_CAUSE_V(1U)
+
+#define MAC_MAGIC_WAKE_INT_CAUSE_S 25
+#define MAC_MAGIC_WAKE_INT_CAUSE_V(x) ((x) << MAC_MAGIC_WAKE_INT_CAUSE_S)
+#define MAC_MAGIC_WAKE_INT_CAUSE_F MAC_MAGIC_WAKE_INT_CAUSE_V(1U)
+
+#define MAC_SIGDETCHG_INT_CAUSE_S 24
+#define MAC_SIGDETCHG_INT_CAUSE_V(x) ((x) << MAC_SIGDETCHG_INT_CAUSE_S)
+#define MAC_SIGDETCHG_INT_CAUSE_F MAC_SIGDETCHG_INT_CAUSE_V(1U)
+
+#define MAC_PCS_LINK_GOOD_CAUSE_S 12
+#define MAC_PCS_LINK_GOOD_CAUSE_V(x) ((x) << MAC_PCS_LINK_GOOD_CAUSE_S)
+#define MAC_PCS_LINK_GOOD_CAUSE_F MAC_PCS_LINK_GOOD_CAUSE_V(1U)
+
+#define MAC_PCS_LINK_FAIL_CAUSE_S 11
+#define MAC_PCS_LINK_FAIL_CAUSE_V(x) ((x) << MAC_PCS_LINK_FAIL_CAUSE_S)
+#define MAC_PCS_LINK_FAIL_CAUSE_F MAC_PCS_LINK_FAIL_CAUSE_V(1U)
+
+#define MAC_REM_FAULT_INT_CAUSE_S 7
+#define MAC_REM_FAULT_INT_CAUSE_V(x) ((x) << MAC_REM_FAULT_INT_CAUSE_S)
+#define MAC_REM_FAULT_INT_CAUSE_F MAC_REM_FAULT_INT_CAUSE_V(1U)
+
+#define MAC_LOC_FAULT_INT_CAUSE_S 6
+#define MAC_LOC_FAULT_INT_CAUSE_V(x) ((x) << MAC_LOC_FAULT_INT_CAUSE_S)
+#define MAC_LOC_FAULT_INT_CAUSE_F MAC_LOC_FAULT_INT_CAUSE_V(1U)
+
+#define MAC_LINK_DOWN_INT_CAUSE_S 5
+#define MAC_LINK_DOWN_INT_CAUSE_V(x) ((x) << MAC_LINK_DOWN_INT_CAUSE_S)
+#define MAC_LINK_DOWN_INT_CAUSE_F MAC_LINK_DOWN_INT_CAUSE_V(1U)
+
+#define MAC_LINK_UP_INT_CAUSE_S 4
+#define MAC_LINK_UP_INT_CAUSE_V(x) ((x) << MAC_LINK_UP_INT_CAUSE_S)
+#define MAC_LINK_UP_INT_CAUSE_F MAC_LINK_UP_INT_CAUSE_V(1U)
+
+#define MAC_AN_DONE_INT_CAUSE_S 3
+#define MAC_AN_DONE_INT_CAUSE_V(x) ((x) << MAC_AN_DONE_INT_CAUSE_S)
+#define MAC_AN_DONE_INT_CAUSE_F MAC_AN_DONE_INT_CAUSE_V(1U)
+
+#define MAC_AN_PGRD_INT_CAUSE_S 2
+#define MAC_AN_PGRD_INT_CAUSE_V(x) ((x) << MAC_AN_PGRD_INT_CAUSE_S)
+#define MAC_AN_PGRD_INT_CAUSE_F MAC_AN_PGRD_INT_CAUSE_V(1U)
+
+#define MAC_TXFIFO_ERR_INT_CAUSE_S 1
+#define MAC_TXFIFO_ERR_INT_CAUSE_V(x) ((x) << MAC_TXFIFO_ERR_INT_CAUSE_S)
+#define MAC_TXFIFO_ERR_INT_CAUSE_F MAC_TXFIFO_ERR_INT_CAUSE_V(1U)
+
+#define MAC_RXFIFO_ERR_INT_CAUSE_S 0
+#define MAC_RXFIFO_ERR_INT_CAUSE_V(x) ((x) << MAC_RXFIFO_ERR_INT_CAUSE_S)
+#define MAC_RXFIFO_ERR_INT_CAUSE_F MAC_RXFIFO_ERR_INT_CAUSE_V(1U)
+
+#define MAC_PORT_PERR_INT_EN_A 0x8e0
+#define MAC_PORT_PERR_INT_CAUSE_A 0x8e4
+#define T7_MAC_PORT_PERR_INT_EN_A 0x870
+#define T7_MAC_PORT_PERR_INT_CAUSE_A 0x874
+#define MAC_PORT_PERR_INT_EN_100G_A 0x884
+#define MAC_PORT_PERR_INT_CAUSE_100G_A 0x888
+#define T7_MAC_PORT_PERR_INT_EN_100G_A 0x82c
+#define T7_MAC_PORT_PERR_INT_CAUSE_100G_A 0x830
+
+#define MAC_PERR_INT_EN_MTIP_A 0x380d0
+#define MAC_PERR_INT_CAUSE_MTIP_A 0x380d4
+
+#define MAC_IOS_INTR_EN_QUAD0_A 0x3a090
+#define MAC_IOS_INTR_CAUSE_QUAD0_A 0x3a094
+
+#define Q0_MAILBOX_INT_ASSERT_S 24
+#define Q0_MAILBOX_INT_ASSERT_V(x) ((x) << Q0_MAILBOX_INT_ASSERT_S)
+#define Q0_MAILBOX_INT_ASSERT_F Q0_MAILBOX_INT_ASSERT_V(1U)
+
+#define MAC_IOS_INTR_EN_QUAD1_A 0x3a098
+#define MAC_IOS_INTR_CAUSE_QUAD1_A 0x3a09c
+
+#define Q1_MAILBOX_INT_ASSERT_S 24
+#define Q1_MAILBOX_INT_ASSERT_V(x) ((x) << Q1_MAILBOX_INT_ASSERT_S)
+#define Q1_MAILBOX_INT_ASSERT_F Q1_MAILBOX_INT_ASSERT_V(1U)
+
+#define PERR_MAC0_TX_S 19
+#define PERR_MAC0_TX_V(x) ((x) << PERR_MAC0_TX_S)
+#define PERR_MAC0_TX_F PERR_MAC0_TX_V(1U)
+
+#define PERR_MAC1_TX_S 18
+#define PERR_MAC1_TX_V(x) ((x) << PERR_MAC1_TX_S)
+#define PERR_MAC1_TX_F PERR_MAC1_TX_V(1U)
+
+#define PERR_MAC2_TX_S 17
+#define PERR_MAC2_TX_V(x) ((x) << PERR_MAC2_TX_S)
+#define PERR_MAC2_TX_F PERR_MAC2_TX_V(1U)
+
+#define PERR_MAC3_TX_S 16
+#define PERR_MAC3_TX_V(x) ((x) << PERR_MAC3_TX_S)
+#define PERR_MAC3_TX_F PERR_MAC3_TX_V(1U)
+
+#define PERR_MAC4_TX_S 15
+#define PERR_MAC4_TX_V(x) ((x) << PERR_MAC4_TX_S)
+#define PERR_MAC4_TX_F PERR_MAC4_TX_V(1U)
+
+#define PERR_MAC5_TX_S 14
+#define PERR_MAC5_TX_V(x) ((x) << PERR_MAC5_TX_S)
+#define PERR_MAC5_TX_F PERR_MAC5_TX_V(1U)
+
+#define PERR_MAC0_RX_S 13
+#define PERR_MAC0_RX_V(x) ((x) << PERR_MAC0_RX_S)
+#define PERR_MAC0_RX_F PERR_MAC0_RX_V(1U)
+
+#define PERR_MAC1_RX_S 12
+#define PERR_MAC1_RX_V(x) ((x) << PERR_MAC1_RX_S)
+#define PERR_MAC1_RX_F PERR_MAC1_RX_V(1U)
+
+#define PERR_MAC2_RX_S 11
+#define PERR_MAC2_RX_V(x) ((x) << PERR_MAC2_RX_S)
+#define PERR_MAC2_RX_F PERR_MAC2_RX_V(1U)
+
+#define PERR_MAC3_RX_S 10
+#define PERR_MAC3_RX_V(x) ((x) << PERR_MAC3_RX_S)
+#define PERR_MAC3_RX_F PERR_MAC3_RX_V(1U)
+
+#define PERR_MAC4_RX_S 9
+#define PERR_MAC4_RX_V(x) ((x) << PERR_MAC4_RX_S)
+#define PERR_MAC4_RX_F PERR_MAC4_RX_V(1U)
+
+#define PERR_MAC5_RX_S 8
+#define PERR_MAC5_RX_V(x) ((x) << PERR_MAC5_RX_S)
+#define PERR_MAC5_RX_F PERR_MAC5_RX_V(1U)
+
+#define PERR_MAC_STAT_RX_S 7
+#define PERR_MAC_STAT_RX_V(x) ((x) << PERR_MAC_STAT_RX_S)
+#define PERR_MAC_STAT_RX_F PERR_MAC_STAT_RX_V(1U)
+
+#define PERR_MAC_STAT_TX_S 3
+#define PERR_MAC_STAT_TX_V(x) ((x) << PERR_MAC_STAT_TX_S)
+#define PERR_MAC_STAT_TX_F PERR_MAC_STAT_TX_V(1U)
+
+#define PERR_MAC_STAT_CAP_S 2
+#define PERR_MAC_STAT_CAP_V(x) ((x) << PERR_MAC_STAT_CAP_S)
+#define PERR_MAC_STAT_CAP_F PERR_MAC_STAT_CAP_V(1U)
+
+#define XGMAC_PORT_INT_EN_A 0x10d8
#define XGMAC_PORT_INT_CAUSE_A 0x10dc
+#define RXFIFOOVERFLOW_S 10
+#define RXFIFOOVERFLOW_V(x) ((x) << RXFIFOOVERFLOW_S)
+#define RXFIFOOVERFLOW_F RXFIFOOVERFLOW_V(1U)
+
+#define MAC_PORT_INT_EN_A 0x8d8
+
+#define T6_PERR_PKT_RAM_S 31
+#define T6_PERR_PKT_RAM_V(x) ((x) << T6_PERR_PKT_RAM_S)
+#define T6_PERR_PKT_RAM_F T6_PERR_PKT_RAM_V(1U)
+
+#define T6_PERR_MASK_RAM_S 30
+#define T6_PERR_MASK_RAM_V(x) ((x) << T6_PERR_MASK_RAM_S)
+#define T6_PERR_MASK_RAM_F T6_PERR_MASK_RAM_V(1U)
+
+#define T6_PERR_CRC_RAM_S 29
+#define T6_PERR_CRC_RAM_V(x) ((x) << T6_PERR_CRC_RAM_S)
+#define T6_PERR_CRC_RAM_F T6_PERR_CRC_RAM_V(1U)
+
#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
@@ -3197,18 +7749,34 @@
#define TP_TX_SCHED_FIFO_A 0x24
#define TP_TX_SCHED_PCMD_A 0x25
-#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
+#define MPS_T5_CLS_SRAM_L_A 0xe000
+#define MPS_T5_CLS_SRAM_H_A 0xe004
+
+#define SRAMWRN_S 31
+#define SRAMWRN_V(x) ((x) << SRAMWRN_S)
+
+#define SRAMINDEX_S 16
+#define SRAMINDEX_M 0x7ffU
+#define SRAMINDEX_V(x) ((x) << SRAMINDEX_S)
+
#define T5_PORT0_BASE 0x30000
#define T5_PORT_STRIDE 0x4000
#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
+#define T7_PORT0_BASE 0x30000
+#define T7_PORT_STRIDE 0x2000
+#define T7_PORT_BASE(idx) (T7_PORT0_BASE + (idx) * T7_PORT_STRIDE)
+#define T7_PORT_REG(idx, reg) (T7_PORT_BASE(idx) + (reg))
+
#define MC_0_BASE_ADDR 0x40000
#define MC_1_BASE_ADDR 0x48000
#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
+#define MC_T7_STRIDE (MC_T71_BASE_ADDR - MC_T70_BASE_ADDR)
+#define MC_T7_REG(reg, idx) ((reg) + MC_T7_STRIDE * (idx))
#define MC_P_BIST_CMD_A 0x41400
#define MC_P_BIST_CMD_ADDR_A 0x41404
@@ -3223,6 +7791,10 @@
#define EDC_H_BIST_CMD_LEN_A 0x5000c
#define EDC_H_BIST_DATA_PATTERN_A 0x50010
#define EDC_H_BIST_STATUS_RDATA_A 0x50028
+#define EDC_H_INT_ENABLE_A 0x50074
+#define EDC_H_INT_CAUSE_A 0x50078
+
+#define EDC_H_ECC_STATUS_A 0x5007c
#define EDC_H_ECC_ERR_ADDR_A 0x50084
#define EDC_T51_BASE_ADDR 0x50800
@@ -3234,6 +7806,390 @@
#define PL_VF_WHOAMI_A 0x0
#define PL_VF_REVISION_A 0x8
+#define PL_TIMEOUT_STATUS0_A 0x194f4
+#define PL_TIMEOUT_STATUS1_A 0x194f8
+
+/* registers for module CRYPTO_0 */
+#define CRYPTO_0_BASE_ADDR 0x44000
+
+#define TLS_TX_CH_INT_ENABLE_A 0x44008
+#define TLS_TX_CH_INT_CAUSE_A 0x4400c
+
+#define TLS_TX_CH_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
+#define NUM_TLS_TX_CH_INSTANCES 6
+
+#define KEX_CERR_S 4
+#define KEX_CERR_V(x) ((x) << KEX_CERR_S)
+#define KEX_CERR_F KEX_CERR_V(1U)
+
+#define KEYLENERR_S 3
+#define KEYLENERR_V(x) ((x) << KEYLENERR_S)
+#define KEYLENERR_F KEYLENERR_V(1U)
+
+#define INTF1_PERR_S 2
+#define INTF1_PERR_V(x) ((x) << INTF1_PERR_S)
+#define INTF1_PERR_F INTF1_PERR_V(1U)
+
+#define INTF0_PERR_S 1
+#define INTF0_PERR_V(x) ((x) << INTF0_PERR_S)
+#define INTF0_PERR_F INTF0_PERR_V(1U)
+
+#define KEX_PERR_S 0
+#define KEX_PERR_V(x) ((x) << KEX_PERR_S)
+#define KEX_PERR_F KEX_PERR_V(1U)
+
+/* registers for module CRYPTO_1 */
+#define CRYPTO_1_BASE_ADDR 0x45000
+
+/* registers for module CRYPTO_KEY */
+
+#define CRYPTO_KEY_INT_ENABLE_A 0x46008
+#define CRYPTO_KEY_INT_CAUSE_A 0x4600c
+
+#define MA_FIFO_PERR_S 22
+#define MA_FIFO_PERR_V(x) ((x) << MA_FIFO_PERR_S)
+#define MA_FIFO_PERR_F MA_FIFO_PERR_V(1U)
+
+#define MA_RSP_PERR_S 21
+#define MA_RSP_PERR_V(x) ((x) << MA_RSP_PERR_S)
+#define MA_RSP_PERR_F MA_RSP_PERR_V(1U)
+
+#define ING_CACHE_DATA_PERR_S 19
+#define ING_CACHE_DATA_PERR_V(x) ((x) << ING_CACHE_DATA_PERR_S)
+#define ING_CACHE_DATA_PERR_F ING_CACHE_DATA_PERR_V(1U)
+
+#define ING_CACHE_TAG_PERR_S 18
+#define ING_CACHE_TAG_PERR_V(x) ((x) << ING_CACHE_TAG_PERR_S)
+#define ING_CACHE_TAG_PERR_F ING_CACHE_TAG_PERR_V(1U)
+
+#define LKP_KEY_REQ_PERR_S 17
+#define LKP_KEY_REQ_PERR_V(x) ((x) << LKP_KEY_REQ_PERR_S)
+#define LKP_KEY_REQ_PERR_F LKP_KEY_REQ_PERR_V(1U)
+
+#define LKP_CLIP_TCAM_PERR_S 16
+#define LKP_CLIP_TCAM_PERR_V(x) ((x) << LKP_CLIP_TCAM_PERR_S)
+#define LKP_CLIP_TCAM_PERR_F LKP_CLIP_TCAM_PERR_V(1U)
+
+#define LKP_MAIN_TCAM_PERR_S 15
+#define LKP_MAIN_TCAM_PERR_V(x) ((x) << LKP_MAIN_TCAM_PERR_S)
+#define LKP_MAIN_TCAM_PERR_F LKP_MAIN_TCAM_PERR_V(1U)
+
+#define EGR_KEY_REQ_PERR_S 14
+#define EGR_KEY_REQ_PERR_V(x) ((x) << EGR_KEY_REQ_PERR_S)
+#define EGR_KEY_REQ_PERR_F EGR_KEY_REQ_PERR_V(1U)
+
+#define EGR_CACHE_DATA_PERR_S 13
+#define EGR_CACHE_DATA_PERR_V(x) ((x) << EGR_CACHE_DATA_PERR_S)
+#define EGR_CACHE_DATA_PERR_F EGR_CACHE_DATA_PERR_V(1U)
+
+#define EGR_CACHE_TAG_PERR_S 12
+#define EGR_CACHE_TAG_PERR_V(x) ((x) << EGR_CACHE_TAG_PERR_S)
+#define EGR_CACHE_TAG_PERR_F EGR_CACHE_TAG_PERR_V(1U)
+
+#define CIM_PERR_S 11
+#define CIM_PERR_V(x) ((x) << CIM_PERR_S)
+#define CIM_PERR_F CIM_PERR_V(1U)
+
+#define MA_INV_RSP_TAG_S 10
+#define MA_INV_RSP_TAG_V(x) ((x) << MA_INV_RSP_TAG_S)
+#define MA_INV_RSP_TAG_F MA_INV_RSP_TAG_V(1U)
+
+#define ING_KEY_RANGE_ERR_S 9
+#define ING_KEY_RANGE_ERR_V(x) ((x) << ING_KEY_RANGE_ERR_S)
+#define ING_KEY_RANGE_ERR_F ING_KEY_RANGE_ERR_V(1U)
+
+#define ING_MFIFO_OVFL_S 8
+#define ING_MFIFO_OVFL_V(x) ((x) << ING_MFIFO_OVFL_S)
+#define ING_MFIFO_OVFL_F ING_MFIFO_OVFL_V(1U)
+
+#define LKP_REQ_OVFL_S 7
+#define LKP_REQ_OVFL_V(x) ((x) << LKP_REQ_OVFL_S)
+#define LKP_REQ_OVFL_F LKP_REQ_OVFL_V(1U)
+
+#define EOK_WAIT_ERR_S 6
+#define EOK_WAIT_ERR_V(x) ((x) << EOK_WAIT_ERR_S)
+#define EOK_WAIT_ERR_F EOK_WAIT_ERR_V(1U)
+
+#define EGR_KEY_RANGE_ERR_S 5
+#define EGR_KEY_RANGE_ERR_V(x) ((x) << EGR_KEY_RANGE_ERR_S)
+#define EGR_KEY_RANGE_ERR_F EGR_KEY_RANGE_ERR_V(1U)
+
+#define EGR_MFIFO_OVFL_S 4
+#define EGR_MFIFO_OVFL_V(x) ((x) << EGR_MFIFO_OVFL_S)
+#define EGR_MFIFO_OVFL_F EGR_MFIFO_OVFL_V(1U)
+
+#define SEQ_WRAP_HP_OVFL_S 3
+#define SEQ_WRAP_HP_OVFL_V(x) ((x) << SEQ_WRAP_HP_OVFL_S)
+#define SEQ_WRAP_HP_OVFL_F SEQ_WRAP_HP_OVFL_V(1U)
+
+#define SEQ_WRAP_LP_OVFL_S 2
+#define SEQ_WRAP_LP_OVFL_V(x) ((x) << SEQ_WRAP_LP_OVFL_S)
+#define SEQ_WRAP_LP_OVFL_F SEQ_WRAP_LP_OVFL_V(1U)
+
+#define EGR_SEQ_WRAP_HP_S 1
+#define EGR_SEQ_WRAP_HP_V(x) ((x) << EGR_SEQ_WRAP_HP_S)
+#define EGR_SEQ_WRAP_HP_F EGR_SEQ_WRAP_HP_V(1U)
+
+#define EGR_SEQ_WRAP_LP_S 0
+#define EGR_SEQ_WRAP_LP_V(x) ((x) << EGR_SEQ_WRAP_LP_S)
+#define EGR_SEQ_WRAP_LP_F EGR_SEQ_WRAP_LP_V(1U)
+
+/* registers for module MC_T70 */
+#define MC_T70_BASE_ADDR 0x48000
+
+#define MC_IND_ADDR_A 0x48000
+#define MC_IND_DATA_A 0x48004
+#define MC_P_DDRCTL_INT_ENABLE_A 0x4930c
+#define MC_P_DDRCTL_INT_CAUSE_A 0x49310
+
+#define HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE_S 5
+#define HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE_V(x) \
+ ((x) << HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE_S)
+#define HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE_F HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE_V(1U)
+
+#define HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE_S 4
+#define HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE_V(x) ((x) << HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE_S)
+#define HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE_F HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE_V(1U)
+
+#define HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE_S 3
+#define HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE_V(x) ((x) << HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE_S)
+#define HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE_F HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE_V(1U)
+
+#define HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE_S 2
+#define HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE_V(x) \
+ ((x) << HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE_S)
+#define HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE_F HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE_V(1U)
+
+#define HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE_S 1
+#define HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE_V(x) ((x) << HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE_S)
+#define HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE_F HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE_V(1U)
+
+#define HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE_S 0
+#define HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE_V(x) ((x) << HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE_S)
+#define HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE_F HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE_V(1U)
+
+#define T7_MC_P_PAR_ENABLE_A 0x49314
+#define T7_MC_P_PAR_CAUSE_A 0x49318
+
+#define HIF_WDATA_Q_PARERR_DCH1_CAUSE_S 13
+#define HIF_WDATA_Q_PARERR_DCH1_CAUSE_V(x) ((x) << HIF_WDATA_Q_PARERR_DCH1_CAUSE_S)
+#define HIF_WDATA_Q_PARERR_DCH1_CAUSE_F HIF_WDATA_Q_PARERR_DCH1_CAUSE_V(1U)
+
+#define DDRCTL_ECC_CE_PAR_DCH1_CAUSE_S 12
+#define DDRCTL_ECC_CE_PAR_DCH1_CAUSE_V(x) ((x) << DDRCTL_ECC_CE_PAR_DCH1_CAUSE_S)
+#define DDRCTL_ECC_CE_PAR_DCH1_CAUSE_F DDRCTL_ECC_CE_PAR_DCH1_CAUSE_V(1U)
+
+#define DDRCTL_ECC_CE_PAR_DCH0_CAUSE_S 11
+#define DDRCTL_ECC_CE_PAR_DCH0_CAUSE_V(x) ((x) << DDRCTL_ECC_CE_PAR_DCH0_CAUSE_S)
+#define DDRCTL_ECC_CE_PAR_DCH0_CAUSE_F DDRCTL_ECC_CE_PAR_DCH0_CAUSE_V(1U)
+
+#define DDRCTL_ECC_UE_PAR_DCH1_CAUSE_S 10
+#define DDRCTL_ECC_UE_PAR_DCH1_CAUSE_V(x) ((x) << DDRCTL_ECC_UE_PAR_DCH1_CAUSE_S)
+#define DDRCTL_ECC_UE_PAR_DCH1_CAUSE_F DDRCTL_ECC_UE_PAR_DCH1_CAUSE_V(1U)
+
+#define DDRCTL_ECC_UE_PAR_DCH0_CAUSE_S 9
+#define DDRCTL_ECC_UE_PAR_DCH0_CAUSE_V(x) ((x) << DDRCTL_ECC_UE_PAR_DCH0_CAUSE_S)
+#define DDRCTL_ECC_UE_PAR_DCH0_CAUSE_F DDRCTL_ECC_UE_PAR_DCH0_CAUSE_V(1U)
+
+#define WDATARAM_PARERR_DCH1_CAUSE_S 8
+#define WDATARAM_PARERR_DCH1_CAUSE_V(x) ((x) << WDATARAM_PARERR_DCH1_CAUSE_S)
+#define WDATARAM_PARERR_DCH1_CAUSE_F WDATARAM_PARERR_DCH1_CAUSE_V(1U)
+
+#define WDATARAM_PARERR_DCH0_CAUSE_S 7
+#define WDATARAM_PARERR_DCH0_CAUSE_V(x) ((x) << WDATARAM_PARERR_DCH0_CAUSE_S)
+#define WDATARAM_PARERR_DCH0_CAUSE_F WDATARAM_PARERR_DCH0_CAUSE_V(1U)
+
+#define BIST_ADDR_FIFO_PARERR_CAUSE_S 6
+#define BIST_ADDR_FIFO_PARERR_CAUSE_V(x) ((x) << BIST_ADDR_FIFO_PARERR_CAUSE_S)
+#define BIST_ADDR_FIFO_PARERR_CAUSE_F BIST_ADDR_FIFO_PARERR_CAUSE_V(1U)
+
+#define BIST_ERR_ADDR_FIFO_PARERR_CAUSE_S 5
+#define BIST_ERR_ADDR_FIFO_PARERR_CAUSE_V(x) ((x) << BIST_ERR_ADDR_FIFO_PARERR_CAUSE_S)
+#define BIST_ERR_ADDR_FIFO_PARERR_CAUSE_F BIST_ERR_ADDR_FIFO_PARERR_CAUSE_V(1U)
+
+#define HIF_WDATA_Q_PARERR_DCH0_CAUSE_S 4
+#define HIF_WDATA_Q_PARERR_DCH0_CAUSE_V(x) ((x) << HIF_WDATA_Q_PARERR_DCH0_CAUSE_S)
+#define HIF_WDATA_Q_PARERR_DCH0_CAUSE_F HIF_WDATA_Q_PARERR_DCH0_CAUSE_V(1U)
+
+#define HIF_RSPDATA_Q_PARERR_DCH1_CAUSE_S 3
+#define HIF_RSPDATA_Q_PARERR_DCH1_CAUSE_V(x) ((x) << HIF_RSPDATA_Q_PARERR_DCH1_CAUSE_S)
+#define HIF_RSPDATA_Q_PARERR_DCH1_CAUSE_F HIF_RSPDATA_Q_PARERR_DCH1_CAUSE_V(1U)
+
+#define HIF_RSPDATA_Q_PARERR_DCH0_CAUSE_S 2
+#define HIF_RSPDATA_Q_PARERR_DCH0_CAUSE_V(x) ((x) << HIF_RSPDATA_Q_PARERR_DCH0_CAUSE_S)
+#define HIF_RSPDATA_Q_PARERR_DCH0_CAUSE_F HIF_RSPDATA_Q_PARERR_DCH0_CAUSE_V(1U)
+
+#define HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE_S 1
+#define HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE_V(x) ((x) << HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE_S)
+#define HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE_F HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE_V(1U)
+
+#define HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE_S 0
+#define HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE_V(x) ((x) << HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE_S)
+#define HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE_F HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE_V(1U)
+
+#define MC_P_PAR_ENABLE_A 0x4130c
+#define MC_P_PAR_CAUSE_A 0x41310
+#define T7_MC_P_INT_ENABLE_A 0x4931c
+#define T7_MC_P_INT_CAUSE_A 0x49320
+#define MC_REGB_DDRC_CH0_ECCCTL_A 0x1060c
+#define MC_REGB_DDRC_CH1_ECCCTL_A 0x1160c
+
+#define ECC_UNCORRECTED_ERR_INTR_EN_S 9
+#define ECC_UNCORRECTED_ERR_INTR_EN_V(x) ((x) << ECC_UNCORRECTED_ERR_INTR_EN_S)
+#define ECC_UNCORRECTED_ERR_INTR_EN_F ECC_UNCORRECTED_ERR_INTR_EN_V(1U)
+
+#define ECC_CORRECTED_ERR_INTR_EN_S 8
+#define ECC_CORRECTED_ERR_INTR_EN_V(x) ((x) << ECC_CORRECTED_ERR_INTR_EN_S)
+#define ECC_CORRECTED_ERR_INTR_EN_F ECC_CORRECTED_ERR_INTR_EN_V(1U)
+
+#define ECC_UNCORRECTED_ERR_CLR_S 1
+#define ECC_UNCORRECTED_ERR_CLR_V(x) ((x) << ECC_UNCORRECTED_ERR_CLR_S)
+#define ECC_UNCORRECTED_ERR_CLR_F ECC_UNCORRECTED_ERR_CLR_V(1U)
+
+#define ECC_CORRECTED_ERR_CLR_S 0
+#define ECC_CORRECTED_ERR_CLR_V(x) ((x) << ECC_CORRECTED_ERR_CLR_S)
+#define ECC_CORRECTED_ERR_CLR_F ECC_CORRECTED_ERR_CLR_V(1U)
+
+#define DDRPHY_INT_CAUSE_S 4
+#define DDRPHY_INT_CAUSE_V(x) ((x) << DDRPHY_INT_CAUSE_S)
+#define DDRPHY_INT_CAUSE_F DDRPHY_INT_CAUSE_V(1U)
+
+#define DDRCTL_INT_CAUSE_S 3
+#define DDRCTL_INT_CAUSE_V(x) ((x) << DDRCTL_INT_CAUSE_S)
+#define DDRCTL_INT_CAUSE_F DDRCTL_INT_CAUSE_V(1U)
+
+#define T7_ECC_CE_INT_CAUSE_S 2
+#define T7_ECC_CE_INT_CAUSE_V(x) ((x) << T7_ECC_CE_INT_CAUSE_S)
+#define T7_ECC_CE_INT_CAUSE_F T7_ECC_CE_INT_CAUSE_V(1U)
+
+#define T7_ECC_UE_INT_CAUSE_S 1
+#define T7_ECC_UE_INT_CAUSE_V(x) ((x) << T7_ECC_UE_INT_CAUSE_S)
+#define T7_ECC_UE_INT_CAUSE_F T7_ECC_UE_INT_CAUSE_V(1U)
+
+#define MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTENABLE_A 0x20100
+#define MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTMASK_A 0x20102
+#define MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTCLEAR_A 0x20103
+#define MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTSTATUS_A 0x20104
+
+/* registers for module MC_T71 */
+#define MC_T71_BASE_ADDR 0x58000
+
+/* registers for module GCACHE */
+#define GCACHE_INT_ENABLE_A 0x51544
+#define GCACHE_INT_CAUSE_A 0x51548
+
+#define GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE_S 27
+#define GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE_V(x) ((x) << GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE_S)
+#define GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE_F GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE_V(1U)
+
+#define GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE_S 26
+#define GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE_V(x) ((x) << GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE_S)
+#define GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE_F GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE_V(1U)
+
+#define GC1_WQDATA_FIFO_PERR_INT_CAUSE_S 25
+#define GC1_WQDATA_FIFO_PERR_INT_CAUSE_V(x) ((x) << GC1_WQDATA_FIFO_PERR_INT_CAUSE_S)
+#define GC1_WQDATA_FIFO_PERR_INT_CAUSE_F GC1_WQDATA_FIFO_PERR_INT_CAUSE_V(1U)
+
+#define GC0_WQDATA_FIFO_PERR_INT_CAUSE_S 24
+#define GC0_WQDATA_FIFO_PERR_INT_CAUSE_V(x) ((x) << GC0_WQDATA_FIFO_PERR_INT_CAUSE_S)
+#define GC0_WQDATA_FIFO_PERR_INT_CAUSE_F GC0_WQDATA_FIFO_PERR_INT_CAUSE_V(1U)
+
+#define GC1_RDTAG_QUEUE_PERR_INT_CAUSE_S 23
+#define GC1_RDTAG_QUEUE_PERR_INT_CAUSE_V(x) ((x) << GC1_RDTAG_QUEUE_PERR_INT_CAUSE_S)
+#define GC1_RDTAG_QUEUE_PERR_INT_CAUSE_F GC1_RDTAG_QUEUE_PERR_INT_CAUSE_V(1U)
+
+#define GC0_RDTAG_QUEUE_PERR_INT_CAUSE_S 22
+#define GC0_RDTAG_QUEUE_PERR_INT_CAUSE_V(x) ((x) << GC0_RDTAG_QUEUE_PERR_INT_CAUSE_S)
+#define GC0_RDTAG_QUEUE_PERR_INT_CAUSE_F GC0_RDTAG_QUEUE_PERR_INT_CAUSE_V(1U)
+
+#define GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_S 21
+#define GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_V(x) ((x) << GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_S)
+#define GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_F GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_V(1U)
+
+#define GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_S 20
+#define GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_V(x) ((x) << GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_S)
+#define GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_F GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_V(1U)
+
+#define GC1_RSP_PERR_INT_CAUSE_S 19
+#define GC1_RSP_PERR_INT_CAUSE_V(x) ((x) << GC1_RSP_PERR_INT_CAUSE_S)
+#define GC1_RSP_PERR_INT_CAUSE_F GC1_RSP_PERR_INT_CAUSE_V(1U)
+
+#define GC0_RSP_PERR_INT_CAUSE_S 18
+#define GC0_RSP_PERR_INT_CAUSE_V(x) ((x) << GC0_RSP_PERR_INT_CAUSE_S)
+#define GC0_RSP_PERR_INT_CAUSE_F GC0_RSP_PERR_INT_CAUSE_V(1U)
+
+#define GC1_LRU_UERR_INT_CAUSE_S 17
+#define GC1_LRU_UERR_INT_CAUSE_V(x) ((x) << GC1_LRU_UERR_INT_CAUSE_S)
+#define GC1_LRU_UERR_INT_CAUSE_F GC1_LRU_UERR_INT_CAUSE_V(1U)
+
+#define GC0_LRU_UERR_INT_CAUSE_S 16
+#define GC0_LRU_UERR_INT_CAUSE_V(x) ((x) << GC0_LRU_UERR_INT_CAUSE_S)
+#define GC0_LRU_UERR_INT_CAUSE_F GC0_LRU_UERR_INT_CAUSE_V(1U)
+
+#define GC1_TAG_UERR_INT_CAUSE_S 15
+#define GC1_TAG_UERR_INT_CAUSE_V(x) ((x) << GC1_TAG_UERR_INT_CAUSE_S)
+#define GC1_TAG_UERR_INT_CAUSE_F GC1_TAG_UERR_INT_CAUSE_V(1U)
+
+#define GC0_TAG_UERR_INT_CAUSE_S 14
+#define GC0_TAG_UERR_INT_CAUSE_V(x) ((x) << GC0_TAG_UERR_INT_CAUSE_S)
+#define GC0_TAG_UERR_INT_CAUSE_F GC0_TAG_UERR_INT_CAUSE_V(1U)
+
+#define GC1_LRU_CERR_INT_CAUSE_S 13
+#define GC1_LRU_CERR_INT_CAUSE_V(x) ((x) << GC1_LRU_CERR_INT_CAUSE_S)
+#define GC1_LRU_CERR_INT_CAUSE_F GC1_LRU_CERR_INT_CAUSE_V(1U)
+
+#define GC0_LRU_CERR_INT_CAUSE_S 12
+#define GC0_LRU_CERR_INT_CAUSE_V(x) ((x) << GC0_LRU_CERR_INT_CAUSE_S)
+#define GC0_LRU_CERR_INT_CAUSE_F GC0_LRU_CERR_INT_CAUSE_V(1U)
+
+#define GC1_TAG_CERR_INT_CAUSE_S 11
+#define GC1_TAG_CERR_INT_CAUSE_V(x) ((x) << GC1_TAG_CERR_INT_CAUSE_S)
+#define GC1_TAG_CERR_INT_CAUSE_F GC1_TAG_CERR_INT_CAUSE_V(1U)
+
+#define GC0_TAG_CERR_INT_CAUSE_S 10
+#define GC0_TAG_CERR_INT_CAUSE_V(x) ((x) << GC0_TAG_CERR_INT_CAUSE_S)
+#define GC0_TAG_CERR_INT_CAUSE_F GC0_TAG_CERR_INT_CAUSE_V(1U)
+
+#define GC1_CE_INT_CAUSE_S 9
+#define GC1_CE_INT_CAUSE_V(x) ((x) << GC1_CE_INT_CAUSE_S)
+#define GC1_CE_INT_CAUSE_F GC1_CE_INT_CAUSE_V(1U)
+
+#define GC0_CE_INT_CAUSE_S 8
+#define GC0_CE_INT_CAUSE_V(x) ((x) << GC0_CE_INT_CAUSE_S)
+#define GC0_CE_INT_CAUSE_F GC0_CE_INT_CAUSE_V(1U)
+
+#define GC1_UE_INT_CAUSE_S 7
+#define GC1_UE_INT_CAUSE_V(x) ((x) << GC1_UE_INT_CAUSE_S)
+#define GC1_UE_INT_CAUSE_F GC1_UE_INT_CAUSE_V(1U)
+
+#define GC0_UE_INT_CAUSE_S 6
+#define GC0_UE_INT_CAUSE_V(x) ((x) << GC0_UE_INT_CAUSE_S)
+#define GC0_UE_INT_CAUSE_F GC0_UE_INT_CAUSE_V(1U)
+
+#define GC1_CMD_PAR_INT_CAUSE_S 5
+#define GC1_CMD_PAR_INT_CAUSE_V(x) ((x) << GC1_CMD_PAR_INT_CAUSE_S)
+#define GC1_CMD_PAR_INT_CAUSE_F GC1_CMD_PAR_INT_CAUSE_V(1U)
+
+#define GC1_DATA_PAR_INT_CAUSE_S 4
+#define GC1_DATA_PAR_INT_CAUSE_V(x) ((x) << GC1_DATA_PAR_INT_CAUSE_S)
+#define GC1_DATA_PAR_INT_CAUSE_F GC1_DATA_PAR_INT_CAUSE_V(1U)
+
+#define GC0_CMD_PAR_INT_CAUSE_S 3
+#define GC0_CMD_PAR_INT_CAUSE_V(x) ((x) << GC0_CMD_PAR_INT_CAUSE_S)
+#define GC0_CMD_PAR_INT_CAUSE_F GC0_CMD_PAR_INT_CAUSE_V(1U)
+
+#define GC0_DATA_PAR_INT_CAUSE_S 2
+#define GC0_DATA_PAR_INT_CAUSE_V(x) ((x) << GC0_DATA_PAR_INT_CAUSE_S)
+#define GC0_DATA_PAR_INT_CAUSE_F GC0_DATA_PAR_INT_CAUSE_V(1U)
+
+#define ILLADDRACCESS1_INT_CAUSE_S 1
+#define ILLADDRACCESS1_INT_CAUSE_V(x) ((x) << ILLADDRACCESS1_INT_CAUSE_S)
+#define ILLADDRACCESS1_INT_CAUSE_F ILLADDRACCESS1_INT_CAUSE_V(1U)
+
+#define ILLADDRACCESS0_INT_CAUSE_S 0
+#define ILLADDRACCESS0_INT_CAUSE_V(x) ((x) << ILLADDRACCESS0_INT_CAUSE_S)
+#define ILLADDRACCESS0_INT_CAUSE_F ILLADDRACCESS0_INT_CAUSE_V(1U)
+
/* registers for module CIM */
#define CIM_HOST_ACC_CTRL_A 0x7b50
#define CIM_HOST_ACC_DATA_A 0x7b54
@@ -3248,13 +8204,33 @@
#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
#define HOSTWRITE_F HOSTWRITE_V(1U)
+#define T7_HOSTBUSY_S 31
+#define T7_HOSTBUSY_V(x) ((x) << T7_HOSTBUSY_S)
+#define T7_HOSTBUSY_F T7_HOSTBUSY_V(1U)
+
+#define T7_HOSTWRITE_S 30
+#define T7_HOSTWRITE_V(x) ((x) << T7_HOSTWRITE_S)
+#define T7_HOSTWRITE_F T7_HOSTWRITE_V(1U)
+
+#define HOSTGRPSEL_S 28
+#define HOSTGRPSEL_V(x) ((x) << HOSTGRPSEL_S)
+
+#define HOSTCORESEL_S 24
+#define HOSTCORESEL_V(x) ((x) << HOSTCORESEL_S)
+
#define CIM_IBQ_DBG_CFG_A 0x7b60
+#define IBQDBGCORE_S 28
+#define IBQDBGCORE_V(x) ((x) << IBQDBGCORE_S)
+
#define IBQDBGADDR_S 16
#define IBQDBGADDR_M 0xfffU
#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
+#define T7_IBQDBGADDR_S 12
+#define T7_IBQDBGADDR_V(x) ((x) << T7_IBQDBGADDR_S)
+
#define IBQDBGBUSY_S 1
#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
#define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
@@ -3265,6 +8241,12 @@
#define CIM_OBQ_DBG_CFG_A 0x7b64
+#define OBQDBGCORE_S 28
+#define OBQDBGCORE_V(x) ((x) << OBQDBGCORE_S)
+
+#define T7_OBQDBGADDR_S 12
+#define T7_OBQDBGADDR_V(x) ((x) << T7_OBQDBGADDR_S)
+
#define OBQDBGADDR_S 16
#define OBQDBGADDR_M 0xfffU
#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
@@ -3329,6 +8311,21 @@
#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
#define CIM_QUEUE_CONFIG_REF_A 0x7b48
+
+#define CORESELECT_S 6
+#define CORESELECT_V(x) ((x) << CORESELECT_S)
+
+#define T7_OBQSELECT_S 5
+#define T7_OBQSELECT_V(x) ((x) << T7_OBQSELECT_S)
+#define T7_OBQSELECT_F T7_OBQSELECT_V(1U)
+
+#define T7_IBQSELECT_S 4
+#define T7_IBQSELECT_V(x) ((x) << T7_IBQSELECT_S)
+#define T7_IBQSELECT_F T7_IBQSELECT_V(1U)
+
+#define T7_QUENUMSELECT_S 0
+#define T7_QUENUMSELECT_V(x) ((x) << T7_QUENUMSELECT_S)
+
#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
#define CIMQSIZE_S 24
@@ -3383,4 +8380,43 @@
#define QUENUMSELECT_S 0
#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
+/* registers for module HMA */
+#define HMA_LOCAL_DEBUG_CFG_A 0x51320
+
+#define HMA_INT_ENABLE_A 0x51304
+#define HMA_INT_CAUSE_A 0x51308
+
+#define GK_UF_INT_CAUSE_S 6
+#define GK_UF_INT_CAUSE_V(x) ((x) << GK_UF_INT_CAUSE_S)
+#define GK_UF_INT_CAUSE_F GK_UF_INT_CAUSE_V(1U)
+
+#define IDTF_INT_CAUSE_S 5
+#define IDTF_INT_CAUSE_V(x) ((x) << IDTF_INT_CAUSE_S)
+#define IDTF_INT_CAUSE_F IDTF_INT_CAUSE_V(1U)
+
+#define OTF_INT_CAUSE_S 4
+#define OTF_INT_CAUSE_V(x) ((x) << OTF_INT_CAUSE_S)
+#define OTF_INT_CAUSE_F OTF_INT_CAUSE_V(1U)
+
+#define RTF_INT_CAUSE_S 3
+#define RTF_INT_CAUSE_V(x) ((x) << RTF_INT_CAUSE_S)
+#define RTF_INT_CAUSE_F RTF_INT_CAUSE_V(1U)
+
+#define PCIEMST_INT_CAUSE_S 2
+#define PCIEMST_INT_CAUSE_V(x) ((x) << PCIEMST_INT_CAUSE_S)
+#define PCIEMST_INT_CAUSE_F PCIEMST_INT_CAUSE_V(1U)
+
+#define MAMST_INT_CAUSE_S 1
+#define MAMST_INT_CAUSE_V(x) ((x) << MAMST_INT_CAUSE_S)
+#define MAMST_INT_CAUSE_F MAMST_INT_CAUSE_V(1U)
+
+/* registers for module UP */
+#define T7_UP_IBQ_0_SHADOW_RDADDR_A 0x400
+#define T7_UP_OBQ_0_SHADOW_RDADDR_A 0x600
+#define T7_UP_OBQ_0_SHADOW_REALADDR_A 0x704
+
+#define T7_QUEREMFLITS_S 0
+#define T7_QUEREMFLITS_M 0xfffU
+#define T7_QUEREMFLITS_G(x) (((x) >> T7_QUEREMFLITS_S) & T7_QUEREMFLITS_M)
+
#endif /* __T4_REGS_H */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h b/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
index 22a0220123ad..1b7fc71dd835 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
@@ -141,4 +141,20 @@
#define TF_NON_OFFLOAD_V(x) ((x) << TF_NON_OFFLOAD_S)
#define TF_NON_OFFLOAD_F TF_NON_OFFLOAD_V(1)
+#define TCB_T_RTT_TS_RECENT_AGE_W 6
+#define TCB_T_RTT_TS_RECENT_AGE_S 0
+#define TCB_T_RTT_TS_RECENT_AGE_M 0xffffffffULL
+#define TCB_T_RTT_TS_RECENT_AGE_V(x) ((x) << TCB_T_RTT_TS_RECENT_AGE_S)
+
+#define TF_MIGRATING_S 0
+#define TF_MIGRATING_V(x) ((x) << TF_MIGRATING_S)
+
+#define TF_RECV_TSTMP_S 53
+#define TF_RECV_TSTMP_V(x) ((__u64)(x) << TF_RECV_TSTMP_S)
+
+#define TF_PEND_CTL1_S 56
+#define TF_PEND_CTL1_V(x) ((__u64)(x) << TF_PEND_CTL1_S)
+
+#define TF_PEND_CTL2_S 57
+#define TF_PEND_CTL2_V(x) ((__u64)(x) << TF_PEND_CTL2_S)
#endif /* __T4_TCB_H */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
index eb1aa82149db..1598d8cdd696 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
@@ -125,12 +125,20 @@
/* PCI-E definitions */
#define WINDOW_SHIFT_X 10
#define PCIEOFST_SHIFT_X 10
+#define T7_MEMOFST_SHIFT_X 4
/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
* Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
* selects for a particular field being present. These fields, when present
* in the Compressed Filter Tuple, have the following widths in bits.
*/
+#define FT_FIRST_S FCOE_S
+#define FT_LAST_S FRAGMENTATION_S
+
+#define T7_FT_FIRST_S IPSECIDX_S
+#define T7_FT_LAST_S TCPFLAGS_S
+
+#define FT_IPSECIDX_W 12
#define FT_FCOE_W 1
#define FT_PORT_W 3
#define FT_VNIC_ID_W 17
@@ -141,6 +149,9 @@
#define FT_MACMATCH_W 9
#define FT_MPSHITTYPE_W 3
#define FT_FRAGMENTATION_W 1
+#define FT_ROCE_W 1
+#define FT_SYNONLY_W 1
+#define FT_TCPFLAGS_W 12
/* Some of the Compressed Filter Tuple fields have internal structure. These
* bit shifts/masks describe those structures. All shifts are relative to the
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index 2419459a0b85..7bd0c0d8a73c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -434,6 +434,13 @@ struct fw_filter2_wr {
#define FW_FILTER_WR_RX_RPL_IQ_G(x) \
(((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
+#define FW_FILTER2_WR_SWAPMAC_S 0
+#define FW_FILTER2_WR_SWAPMAC_M 0x1
+#define FW_FILTER2_WR_SWAPMAC_V(x) ((x) << FW_FILTER2_WR_SWAPMAC_S)
+#define FW_FILTER2_WR_SWAPMAC_G(x) \
+ (((x) >> FW_FILTER2_WR_SWAPMAC_S) & FW_FILTER2_WR_SWAPMAC_M)
+#define FW_FILTER2_WR_SWAPMAC_F FW_FILTER2_WR_SWAPMAC_V(1U)
+
#define FW_FILTER2_WR_FILTER_TYPE_S 1
#define FW_FILTER2_WR_FILTER_TYPE_M 0x1
#define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
@@ -460,6 +467,13 @@ struct fw_filter2_wr {
#define FW_FILTER2_WR_ULP_TYPE_G(x) \
(((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
+#define FW_FILTER2_WR_TX_LOOP_S 29
+#define FW_FILTER2_WR_TX_LOOP_M 0x1
+#define FW_FILTER2_WR_TX_LOOP_V(x) ((x) << FW_FILTER2_WR_TX_LOOP_S)
+#define FW_FILTER2_WR_TX_LOOP_G(x) \
+ (((x) >> FW_FILTER2_WR_TX_LOOP_S) & FW_FILTER2_WR_TX_LOOP_M)
+#define FW_FILTER2_WR_TX_LOOP_F FW_FILTER2_WR_TX_LOOP_V(1U)
+
#define FW_FILTER_WR_MACI_S 23
#define FW_FILTER_WR_MACI_M 0x1ff
#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
@@ -1414,6 +1428,9 @@ enum fw_params_param_dmaq {
FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
};
+#define T7_DMAQ_CONM_CTXT_CH_VEC_S 2
+#define T7_DMAQ_CONM_CTXT_CH_VEC_V(x) ((x) << T7_DMAQ_CONM_CTXT_CH_VEC_S)
+
enum fw_params_param_dev_ktls_hw {
FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE = 0x00,
FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE = 0x01,
@@ -1882,6 +1899,12 @@ struct fw_eq_eth_cmd {
#define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
#define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)
+#define FW_EQ_ETH_CMD_COREGROUP_S 16
+#define FW_EQ_ETH_CMD_COREGROUP_M 0x3f
+#define FW_EQ_ETH_CMD_COREGROUP_V(x) ((x) << FW_EQ_ETH_CMD_COREGROUP_S)
+#define FW_EQ_ETH_CMD_COREGROUP_G(x) \
+ (((x) >> FW_EQ_ETH_CMD_COREGROUP_S) & FW_EQ_ETH_CMD_COREGROUP_M)
+
#define FW_EQ_ETH_CMD_EQID_S 0
#define FW_EQ_ETH_CMD_EQID_M 0xfffff
#define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
@@ -2010,6 +2033,12 @@ struct fw_eq_ctrl_cmd {
#define FW_EQ_CTRL_CMD_CMPLIQID_S 20
#define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
+#define FW_EQ_CTRL_CMD_COREGROUP_S 16
+#define FW_EQ_CTRL_CMD_COREGROUP_M 0x3f
+#define FW_EQ_CTRL_CMD_COREGROUP_V(x) ((x) << FW_EQ_CTRL_CMD_COREGROUP_S)
+#define FW_EQ_CTRL_CMD_COREGROUP_G(x) \
+ (((x) >> FW_EQ_CTRL_CMD_COREGROUP_S) & FW_EQ_CTRL_CMD_COREGROUP_M)
+
#define FW_EQ_CTRL_CMD_EQID_S 0
#define FW_EQ_CTRL_CMD_EQID_M 0xfffff
#define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)
@@ -2597,7 +2626,7 @@ struct fw_acl_vlan_cmd {
#define FW_ACL_VLAN_CMD_EN_M 0x1
#define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
#define FW_ACL_VLAN_CMD_EN_G(x) \
- (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
+ (((x) >> FW_ACL_VLAN_CMD_EN_S_S) & FW_ACL_VLAN_CMD_EN_M)
#define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U)
#define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7
@@ -3107,8 +3136,26 @@ enum fw_port_type {
FW_PORT_TYPE_SFP28,
FW_PORT_TYPE_KR_SFP28,
FW_PORT_TYPE_KR_XLAUI,
-
- FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
+ /* Applicable on T7 */
+ FW_PORT_TYPE_BARE_LINK_50G = 23, /* No, 1, 50G */
+ FW_PORT_TYPE_BARE_LINK_100G = 24, /* No, 2, 100G/50G */
+ FW_PORT_TYPE_BARE_LINK_200G = 25, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_SFP56 = 26, /* No, 1, 50G/25G */
+ FW_PORT_TYPE_QSFP56 = 27, /* No, 4, 200G/100G/50G/25G */
+ FW_PORT_TYPE_QSFP56_4_50G = 28, /* No, 1, 50G */
+ FW_PORT_TYPE_KR_50G = 29, /* No, 1, 50G */
+ FW_PORT_TYPE_KR2_100G = 30, /* No, 2, 100G/50G */
+ FW_PORT_TYPE_KR4_200G = 31, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_QSFP56_2_50G = 32, /* No, 1, 50G */
+ FW_PORT_TYPE_OSFP = 33, /* No, 8, 400G/200G/100G/50G */
+ FW_PORT_TYPE_QSFPDD = 34, /* No, 8, 400G/200G/100G/50G */
+ FW_PORT_TYPE_OSFP_2_200G = 35, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_QSFP_4_100G = 36, /* No, 2, 100G/50G */
+ FW_PORT_TYPE_QSFPDD_2_200G = 37, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_KR8_400G = 38, /* No, 8, 400G/200G/100G/50G? */
+ FW_PORT_TYPE_MAX,
+
+ FW_PORT_TYPE_NONE = FW_PORT_CMD_PORTTYPE32_M
};
enum fw_port_module_type {
@@ -3119,6 +3166,7 @@ enum fw_port_module_type {
FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
FW_PORT_MOD_TYPE_LRM,
+ FW_PORT_MOD_TYPE_DR,
FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3,
FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2,
FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1,
@@ -3770,13 +3818,17 @@ struct fw_hdr {
__u32 reserved3;
__u32 reserved4;
__be32 flags;
- __be32 reserved6[23];
+ __be32 reserved6[4];
+ __u8 reserved7[3];
+ __u8 dsign_len;
+ __u8 dsign[72]; /* fw binary digital signature */
};
enum fw_hdr_chip {
FW_HDR_CHIP_T4,
FW_HDR_CHIP_T5,
- FW_HDR_CHIP_T6
+ FW_HDR_CHIP_T6,
+ FW_HDR_CHIP_T7
};
#define FW_HDR_FW_VER_MAJOR_S 24
@@ -3888,7 +3940,9 @@ struct fw_devlog_cmd {
__u8 r2[7];
__be32 memtype_devlog_memaddr16_devlog;
__be32 memsize_devlog;
- __be32 r3[2];
+ __u8 num_devlog;
+ __u8 r3[3];
+ __be32 r4;
};
#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
@@ -3915,8 +3969,14 @@ struct fw_devlog_cmd {
*/
#define PCIE_FW_PF_DEVLOG 7
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_S 31
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_M 0x1
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_V(x) ((x) << PCIE_FW_PF_DEVLOG_COUNT_MSB_S)
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_G(x) \
+ (((x) >> PCIE_FW_PF_DEVLOG_COUNT_MSB_S) & PCIE_FW_PF_DEVLOG_COUNT_MSB_M)
+
#define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
-#define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
+#define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0x7
#define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
#define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
@@ -3929,8 +3989,15 @@ struct fw_devlog_cmd {
#define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
(((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_S 3
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_M 0x1
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_V(x) \
+ ((x) << PCIE_FW_PF_DEVLOG_COUNT_LSB_S)
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_G(x) \
+ (((x) >> PCIE_FW_PF_DEVLOG_COUNT_LSB_S) & PCIE_FW_PF_DEVLOG_COUNT_LSB_M)
+
#define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0
-#define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf
+#define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0x7
#define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
#define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
(((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
index a02b1dff403e..d19979c8bfc0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
@@ -61,4 +61,13 @@
#define T6FW_MIN_VERSION_MAJOR 0x00
#define T6FW_MIN_VERSION_MINOR 0x00
#define T6FW_MIN_VERSION_MICRO 0x00
+
+#define T7FW_VERSION_MAJOR 0x01
+#define T7FW_VERSION_MINOR 0x19
+#define T7FW_VERSION_MICRO 0x01
+#define T7FW_VERSION_BUILD 0x1B
+
+#define T7FW_MIN_VERSION_MAJOR 0x00
+#define T7FW_MIN_VERSION_MINOR 0x00
+#define T7FW_MIN_VERSION_MICRO 0x00
#endif
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 02/12] cxgb4: rework the interrupt handling framework
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 01/12] cxgb4: add T7 hardware definitions and firmware interfaces Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-09 13:56 ` Simon Horman
2026-10-05 22:48 ` [PATCH net-next v3 03/12] cxgb4: add T7 hardware management support Potnuri Bharat Teja
` (9 subsequent siblings)
11 siblings, 1 reply; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
The slow interrupt path used a per module handler that walked a table
of (mask, message) pairs with t4_handle_intr_status() and printed a
message for every bit it found set. Each module handler open coded
the read, report and clear sequence, and there was no way to express
that a cause bit should be handled by inspecting a sub-register, or
that a bit is only fatal when it is also enabled.
Replace it with a data driven framework:
struct intr_info describes one cause register: its name, the cause
and enable register offsets, the mask of fatal bits, a table of
struct intr_details for decoding individual bits, and an optional
table of struct intr_action entries naming a function to call for a
given cause bit.
t4_handle_intr() implements the common read, report, dispatch and
clear sequence once, so a module handler reduces to describing its
registers and any nested cause registers it owns.
The module interrupt handlers now return bool rather than void so a
fatal condition propagates back to t4_slow_intr_handler() instead of
being signalled out of band, and t4_slow_intr_handler() takes a
verbose flag controlling whether individual cause bits are decoded
and logged.
This changes the interrupt path for all supported adapters. No
functional change is intended for T4, T5 or T6 beyond the wording of
the messages emitted.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 2 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 2 +-
drivers/net/ethernet/chelsio/cxgb4/sge.c | 4 +-
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 4440 ++++++++++++++---
4 files changed, 3793 insertions(+), 655 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index f20f4bc58492..c3dcb7ea83ab 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -1788,7 +1788,7 @@ struct fw_filter_wr;
void t4_intr_enable(struct adapter *adapter);
void t4_intr_disable(struct adapter *adapter);
-int t4_slow_intr_handler(struct adapter *adapter);
+int t4_slow_intr_handler(struct adapter *adapter, bool verbose);
int t4_wait_dev_ready(void __iomem *regs);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 1ced6df6eac8..5189016c3ef6 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -682,7 +682,7 @@ static irqreturn_t t4_nondata_intr(int irq, void *cookie)
t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
}
if (adap->flags & CXGB4_MASTER_PF)
- t4_slow_intr_handler(adap);
+ t4_slow_intr_handler(adap, true);
return IRQ_HANDLED;
}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 9fccb8ea9bcd..4fe6c10d50e0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -4193,7 +4193,7 @@ static irqreturn_t t4_intr_msi(int irq, void *cookie)
struct adapter *adap = cookie;
if (adap->flags & CXGB4_MASTER_PF)
- t4_slow_intr_handler(adap);
+ t4_slow_intr_handler(adap, true);
process_intrq(adap);
return IRQ_HANDLED;
}
@@ -4208,7 +4208,7 @@ static irqreturn_t t4_intr_intx(int irq, void *cookie)
struct adapter *adap = cookie;
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
- if (((adap->flags & CXGB4_MASTER_PF) && t4_slow_intr_handler(adap)) |
+ if (((adap->flags & CXGB4_MASTER_PF) && t4_slow_intr_handler(adap, true)) |
process_intrq(adap))
return IRQ_HANDLED;
return IRQ_NONE; /* probably shared interrupt */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 29d7b786e51e..f761fc64c86e 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -4261,804 +4261,3936 @@ int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
-typedef void (*int_handler_t)(struct adapter *adap);
+struct intr_details {
+ u32 mask;
+ const char *msg;
+};
+
+struct intr_action {
+ u32 mask;
+ int arg;
+ bool (*action)(struct adapter *adap, int arg, bool verbose);
+};
+#define NONFATAL_IF_DISABLED 1
struct intr_info {
- unsigned int mask; /* bits to check in interrupt status */
- const char *msg; /* message to print or NULL */
- short stat_idx; /* stat counter to increment or -1 */
- unsigned short fatal; /* whether the condition reported is fatal */
- int_handler_t int_handler; /* platform-specific int handler */
+ const char *name; /* name of the INT_CAUSE register */
+ int cause_reg; /* INT_CAUSE register */
+ int enable_reg; /* INT_ENABLE register */
+ u32 fatal; /* bits that are fatal */
+ int flags; /* hints */
+ int skip_clear; /* 1 if it should not be cleared */
+ const struct intr_details *details;
+ const struct intr_action *actions;
};
-/**
- * t4_handle_intr_status - table driven interrupt handler
- * @adapter: the adapter that generated the interrupt
- * @reg: the interrupt status register to process
- * @acts: table of interrupt actions
- *
- * A table driven interrupt handler that applies a set of masks to an
- * interrupt status word and performs the corresponding actions if the
- * interrupts described by the mask have occurred. The actions include
- * optionally emitting a warning or alert message. The table is terminated
- * by an entry specifying mask 0. Returns the number of fatal interrupt
- * conditions.
- */
-static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
- const struct intr_info *acts)
+static void clear_int_cause_reg(struct adapter *adap, const struct intr_info *ii)
{
- int fatal = 0;
- unsigned int mask = 0;
- unsigned int status = t4_read_reg(adapter, reg);
+ u32 cause;
- for ( ; acts->mask; ++acts) {
- if (!(status & acts->mask))
+ cause = t4_read_reg(adap, ii->cause_reg);
+ if (cause == 0)
+ return;
+
+ t4_write_reg(adap, ii->cause_reg, cause);
+ (void)t4_read_reg(adap, ii->cause_reg);
+}
+
+static inline char intr_alert_char(u32 cause, u32 enable, u32 fatal)
+{
+ if (cause & fatal)
+ return '!';
+ if (cause & enable)
+ return '*';
+ return '-';
+}
+
+static void t4_show_intr_info(struct adapter *adap, const struct intr_info *ii,
+ u32 cause, u32 enable)
+{
+ u32 fatal, leftover;
+ const struct intr_details *details;
+ char alert;
+
+ if (ii->flags & NONFATAL_IF_DISABLED)
+ fatal = ii->fatal & enable;
+ else
+ fatal = ii->fatal;
+ alert = intr_alert_char(cause, enable, fatal);
+ dev_alert(adap->pdev_dev, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
+ alert, ii->name, ii->cause_reg, cause, enable, fatal);
+
+ leftover = cause;
+ for (details = ii->details; details && details->mask != 0; details++) {
+ u32 msgbits = details->mask & cause;
+
+ if (msgbits == 0)
continue;
- if (acts->fatal) {
- fatal++;
- dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
- status & acts->mask);
- } else if (acts->msg && printk_ratelimit())
- dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
- status & acts->mask);
- if (acts->int_handler)
- acts->int_handler(adapter);
- mask |= acts->mask;
- }
- status &= mask;
- if (status) /* clear processed interrupts */
- t4_write_reg(adapter, reg, status);
- return fatal;
+ alert = intr_alert_char(msgbits, enable, ii->fatal);
+ dev_alert(adap->pdev_dev, " %c [0x%08x] %s\n", alert, msgbits,
+ details->msg);
+ leftover &= ~msgbits;
+ }
+ if (leftover != 0 && leftover != cause)
+ dev_alert(adap->pdev_dev, " ? [0x%08x]\n", leftover);
}
+/*
+ * Returns true for fatal error.
+ */
+static bool t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
+ u32 additional_cause, bool verbose)
+{
+ u32 cause, enable, active, fatal;
+ const struct intr_action *action;
+ bool rc;
+
+ cause = t4_read_reg(adap, ii->cause_reg);
+ enable = t4_read_reg(adap, ii->enable_reg);
+
+ if (verbose && cause != 0)
+ t4_show_intr_info(adap, ii, cause, enable);
+ fatal = cause & ii->fatal;
+ if (ii->flags & NONFATAL_IF_DISABLED)
+ fatal &= enable;
+ active = (cause & enable) | additional_cause;
+ if (active == 0)
+ return false;
+
+ rc = fatal != 0;
+ for (action = ii->actions; action && action->mask != 0; action++) {
+ if (!(action->mask & active))
+ continue;
+ rc |= action->action(adap, action->arg, verbose);
+ }
+
+ /* clear only if register doesn't have a sub-register to check on */
+ if (!ii->skip_clear) {
+ t4_write_reg(adap, ii->cause_reg, cause);
+ (void)t4_read_reg(adap, ii->cause_reg);
+ }
+ return rc;
+}
/*
* Interrupt handler for the PCIE module.
*/
-static void pcie_intr_handler(struct adapter *adapter)
+static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details sysbus_intr_details[] = {
+ { RNPP_F, "RXNP array parity error" },
+ { RPCP_F, "RXPC array parity error" },
+ { RCIP_F, "RXCIF array parity error" },
+ { RCCP_F, "Rx completions control array parity error" },
+ { RFTP_F, "RXFT array parity error" },
+ { 0 }
+ };
+ static const struct intr_info sysbus_intr_info = {
+ .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
+ .cause_reg = PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
+ .enable_reg = PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE_A,
+ .fatal = RFTP_F | RCCP_F | RCIP_F | RPCP_F | RNPP_F,
+ .flags = 0,
+ .details = sysbus_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details pcie_port_intr_details[] = {
+ { TPCP_F, "TXPC array parity error" },
+ { TNPP_F, "TXNP array parity error" },
+ { TFTP_F, "TXFT array parity error" },
+ { TCAP_F, "TXCA array parity error" },
+ { TCIP_F, "TXCIF array parity error" },
+ { RCAP_F, "RXCA array parity error" },
+ { OTDD_F, "outbound request TLP discarded" },
+ { RDPE_F, "Rx data parity error" },
+ { TDUE_F, "Tx uncorrectable data error" },
+ { 0 }
+ };
+ static const struct intr_info pcie_port_intr_info = {
+ .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
+ .cause_reg = PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
+ .enable_reg = PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE_A,
+ .fatal = TPCP_F | TNPP_F | TFTP_F | TCAP_F | TCIP_F | RCAP_F |
+ OTDD_F | RDPE_F | TDUE_F,
+ .flags = 0,
+ .details = pcie_port_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details pcie_intr_details[] = {
+ { MSIADDRLPERR_F, "MSI AddrL parity error" },
+ { MSIADDRHPERR_F, "MSI AddrH parity error" },
+ { MSIDATAPERR_F, "MSI data parity error" },
+ { MSIXADDRLPERR_F, "MSI-X AddrL parity error" },
+ { MSIXADDRHPERR_F, "MSI-X AddrH parity error" },
+ { MSIXDATAPERR_F, "MSI-X data parity error" },
+ { MSIXDIPERR_F, "MSI-X DI parity error" },
+ { PIOCPLPERR_F, "PCIe PIO completion FIFO parity error" },
+ { PIOREQPERR_F, "PCIe PIO request FIFO parity error" },
+ { TARTAGPERR_F, "PCIe target tag FIFO parity error" },
+ { CCNTPERR_F, "PCIe CMD channel count parity error" },
+ { CREQPERR_F, "PCIe CMD channel request parity error" },
+ { CRSPPERR_F, "PCIe CMD channel response parity error" },
+ { DCNTPERR_F, "PCIe DMA channel count parity error" },
+ { DREQPERR_F, "PCIe DMA channel request parity error" },
+ { DRSPPERR_F, "PCIe DMA channel response parity error" },
+ { HCNTPERR_F, "PCIe HMA channel count parity error" },
+ { HREQPERR_F, "PCIe HMA channel request parity error" },
+ { HRSPPERR_F, "PCIe HMA channel response parity error" },
+ { CFGSNPPERR_F, "PCIe config snoop FIFO parity error" },
+ { FIDPERR_F, "PCIe FID parity error" },
+ { INTXCLRPERR_F, "PCIe INTx clear parity error" },
+ { MATAGPERR_F, "PCIe MA tag parity error" },
+ { PIOTAGPERR_F, "PCIe PIO tag parity error" },
+ { RXCPLPERR_F, "PCIe Rx completion parity error" },
+ { RXWRPERR_F, "PCIe Rx write parity error" },
+ { RPLPERR_F, "PCIe replay buffer parity error" },
+ { PCIESINT_F, "PCIe core secondary fault" },
+ { PCIEPINT_F, "PCIe core primary fault" },
+ { UNXSPLCPLERR_F, "PCIe unexpected split completion error" },
+ { 0 }
+ };
+ static const struct intr_details t5_pcie_intr_details[] = {
+ { IPGRPPERR_F, "Parity errors observed by IP" },
+ { NONFATALERR_F, "PCIe non-fatal error" },
+ { READRSPERR_F, "Outbound read error" },
+ { TRGT1GRPPERR_F, "PCIe TRGT1 group FIFOs parity error" },
+ { IPSOTPERR_F, "PCIe IP SOT buffer SRAM parity error" },
+ { IPRETRYPERR_F, "PCIe IP replay buffer parity error" },
+ { IPRXDATAGRPPERR_F, "PCIe IP Rx data group SRAMs parity error" },
+ { IPRXHDRGRPPERR_F, "PCIe IP Rx header group SRAMs parity error" },
+ { PIOTAGQPERR_F, "PIO tag queue FIFO parity error" },
+ { MAGRPPERR_F, "MA group FIFO parity error" },
+ { VFIDPERR_F, "VFID SRAM parity error" },
+ { FIDPERR_F, "FID SRAM parity error" },
+ { CFGSNPPERR_F, "config snoop FIFO parity error" },
+ { HRSPPERR_F, "HMA channel response data SRAM parity error" },
+ { HREQRDPERR_F, "HMA channel read request SRAM parity error" },
+ { HREQWRPERR_F, "HMA channel write request SRAM parity error" },
+ { DRSPPERR_F, "DMA channel response data SRAM parity error" },
+ { DREQRDPERR_F, "DMA channel write request SRAM parity error" },
+ { CRSPPERR_F, "CMD channel response data SRAM parity error" },
+ { CREQRDPERR_F, "CMD channel read request SRAM parity error" },
+ { MSTTAGQPERR_F, "PCIe master tag queue SRAM parity error" },
+ { TGTTAGQPERR_F, "PCIe target tag queue FIFO parity error" },
+ { PIOREQGRPPERR_F, "PIO request group FIFOs parity error" },
+ { PIOCPLGRPPERR_F, "PIO completion group FIFOs parity error" },
+ { MSIXDIPERR_F, "MSI-X DI SRAM parity error" },
+ { MSIXDATAPERR_F, "MSI-X data SRAM parity error" },
+ { MSIXADDRHPERR_F, "MSI-X AddrH SRAM parity error" },
+ { MSIXADDRLPERR_F, "MSI-X AddrL SRAM parity error" },
+ { MSIXSTIPERR_F, "MSI-X STI SRAM parity error" },
+ { MSTTIMEOUTPERR_F, "Master timeout FIFO parity error" },
+ { MSTGRPPERR_F, "Master response read queue SRAM parity error" },
+ { 0 }
+ };
+ struct intr_info pcie_intr_info = {
+ .name = "PCIE_INT_CAUSE",
+ .cause_reg = PCIE_INT_CAUSE_A,
+ .enable_reg = PCIE_INT_ENABLE_A,
+ .fatal = 0x9fffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details pcie_intr_cause_ext_details[] = {
+ { IPFORMQPERR_F, "PCIe IP FormQ Buffer PERR" },
+ { IPFORMQCERR_F, "PCIe IP FormQ Buffer CERR" },
+ { TRGT1GRPCERR_F, "TRGT1 Group FIFOs CERR" },
+ { IPSOTCERR_F, "PCIe IP SOT Buffer SRAM CERR" },
+ { IPRETRYCERR_F, "PCIe IP Replay Buffer CERR" },
+ { IPRXDATAGRPCERR_F, "PCIe IP Rx Data Group SRAMs CERR" },
+ { IPRXHDRGRPCERR_F, "PCIe IP Rx Header Group SRAMs CERR" },
+ { A0ARBRSPORDFIFOPERR_F, "A0 Arbiter Response Order FIFO Parity Error" },
+ { HRSPCERR_F, "Master HMA Channel Response Data SRAM CERR" },
+ { HREQRDCERR_F, "Master HMA Channel Read Request SRAM CERR" },
+ { HREQWRCERR_F, "Master HMA Channel Write Request SRAM CERR" },
+ { DRSPCERR_F, "Master DMA Channel Response Data SRAM CERR" },
+ { DREQRDCERR_F, "Master DMA Channel Read Request SRAM CERR" },
+ { DREQWRCERR_F, "Master DMA Channel Write Request SRAM CERR" },
+ { CRSPCERR_F, "Master CMD Channel Response Data SRAM CERR" },
+ { ARSPPERR_F, "Master ARM Channel Response Data SRAM PERR" },
+ { AREQRDPERR_F, "Master ARM Channel Read Request SRAM PERR" },
+ { AREQWRPERR_F, "Master ARM Channel Write Request SRAM PERR" },
+ { PIOREQGRPCERR_F, "PIO Request Group FIFOs CERR" },
+ { ARSPCERR_F, "Master ARM Channel Response Data SRAM CERR" },
+ { AREQRDCERR_F, "Master ARM Channel Read Request SRAM CERR" },
+ { AREQWRCERR_F, "Master ARM Channel Write Request SRAM CERR" },
+ { MARSPPERR_F, "INIC MA Ctrl and Data Rsp Perr" },
+ { INICMAWDATAORDPERR_F, "INIC Ma Arb Write Ord Data Fifo Perr" },
+ { EMUPERR_F, "CFG EMU SRAM PERR" },
+ { ERRSPPERR_F, "CFG EMU SRAM CERR" },
+ { MSTGRPCERR_F, "Master Data Path and Response Read Queue SRAM CERR" },
+ { 0 }
+ };
+ struct intr_info pcie_int_cause_ext = {
+ .name = "PCIE_INT_CAUSE_EXT",
+ .cause_reg = PCIE_INT_CAUSE_EXT_A,
+ .enable_reg = PCIE_INT_ENABLE_EXT_A,
+ .fatal = IPFORMQPERR_F | A0ARBRSPORDFIFOPERR_F | ARSPPERR_F | AREQRDPERR_F |
+ AREQWRPERR_F | MARSPPERR_F | INICMAWDATAORDPERR_F | EMUPERR_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = pcie_intr_cause_ext_details,
+ .actions = NULL,
+ };
+ static const struct intr_details pcie_intr_cause_x8_details[] = {
+ { X8TGTGRPPERR_F, "x8 TGT Group FIFOs parity error" },
+ { X8IPSOTPERR_F, "PCIe x8 IP SOT Buffer SRAM PERR" },
+ { X8IPRETRYPERR_F, "PCIe x8 IP Replay Buffer PERR" },
+ { X8IPRXDATAGRPPERR_F, "PCIe x8 IP Rx Data Group SRAMs PERR" },
+ { X8IPRXHDRGRPPERR_F, "PCIe x8 IP Rx Header Group SRAMs PERR" },
+ { X8IPCORECERR_F, "x8 IP SOT, Retry, RxData, RxHdr SRAM CERR" },
+ { X8MSTGRPPERR_F, "x8 Master Data Path and Response Read Queue SRAM PERR" },
+ { X8MSTGRPCERR_F, "x8 Master Data Path and Response Read Queue SRAM CERR" },
+ { 0 }
+ };
+ struct intr_info pcie_int_cause_x8 = {
+ .name = "PCIE_INT_CAUSE_X8",
+ .cause_reg = PCIE_INT_CAUSE_X8_A,
+ .enable_reg = PCIE_INT_ENABLE_X8_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = pcie_intr_cause_x8_details,
+ .actions = NULL,
+ };
+ bool fatal = false;
+
+ if (is_t4(adap->params.chip)) {
+ fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
+
+ pcie_intr_info.details = pcie_intr_details;
+ } else {
+ pcie_intr_info.details = t5_pcie_intr_details;
+ }
+ fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
+ if (is_t7(adap->params.chip)) {
+ fatal |= t4_handle_intr(adap, &pcie_int_cause_ext, 0, verbose);
+ fatal |= t4_handle_intr(adap, &pcie_int_cause_x8, 0, verbose);
+ }
+
+ return fatal;
+}
+
+/*
+ * TP interrupt handler.
+ */
+static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
{
- static const struct intr_info sysbus_intr_info[] = {
- { RNPP_F, "RXNP array parity error", -1, 1 },
- { RPCP_F, "RXPC array parity error", -1, 1 },
- { RCIP_F, "RXCIF array parity error", -1, 1 },
- { RCCP_F, "Rx completions control array parity error", -1, 1 },
- { RFTP_F, "RXFT array parity error", -1, 1 },
+ static const struct intr_details tp_intr_details[] = {
+ { 0x3fffffff, "TP parity error" },
+ { FLMTXFLSTEMPTY_F, "TP out of Tx pages" },
+ { 0 }
+ };
+ static const struct intr_details t7_tp_intr_details[] = {
+ { FLMTXFLSTEMPTY_F, "Offload memory manager Tx free list empty" },
+ { TPCERR_F, "TP modules flagged Correctable Error" },
+ { OTHERPERR_F, "TP Other modules (Core, TM, FLM, MMGR, DB) Parity Error" },
+ { TPEING1PERR_F, "TP-ESide Ingress1 Parity Error" },
+ { TPEING0PERR_F, "TP-ESide Ingress0 Parity Error" },
+ { TPEEGPERR_F, "TP-ESide Egress Parity Error" },
+ { TPCPERR_F, "TP-CSide Parity Error" },
+ { 0 }
+ };
+ struct intr_info tp_intr_info = {
+ .name = "TP_INT_CAUSE",
+ .cause_reg = TP_INT_CAUSE_A,
+ .enable_reg = TP_INT_ENABLE_A,
+ .fatal = 0x7fffffdf,
+ .skip_clear = 1,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details tp_cerr_cause_details[] = {
+ { TPCEGDATAFIFO_F, "TPCSide Egress Data FIFO" },
+ { TPCLBKDATAFIFO_F, "TPCSide Loopback Data FIFO" },
+ { RSSLKPSRAM_F, "RSS Lookup SRAM" },
+ { SRQSRAM_F, "SRQ SRAM" },
+ { ARPDASRAM_F, "ARP DA SRAM" },
+ { ARPSASRAM_F, "ARP SA SRAM" },
+ { ARPGRESRAM_F, "ARP GRE SRAM" },
+ { ARPIPSECSRAM1_F, "ARP IPSec SRAM0" },
+ { ARPIPSECSRAM0_F, "ARP IPSec SRAM1" },
+ { 0 }
+ };
+ static const struct intr_info tp_cerr_cause = {
+ .name = "TP_CERR_CAUSE",
+ .cause_reg = TP_CERR_CAUSE_A,
+ .enable_reg = TP_CERR_ENABLE_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = tp_cerr_cause_details,
+ .actions = NULL,
+ };
+ static const struct intr_details tp_c_perr_details[] = {
+ { DMXFIFOOVFL_F, "Demux FIFO Overflow" },
+ { URX2TPCDDPINTF_F, "ULPRX to TPC DDP Interface and FIFO" },
+ { TPCDISPTOKENFIFO_F, "TPC Dispatch Token FIFO" },
+ { TPCDISPCPLFIFO3_F, "TPC Dispatch CPL FIFO Ch3" },
+ { TPCDISPCPLFIFO2_F, "TPC Dispatch CPL FIFO Ch2" },
+ { TPCDISPCPLFIFO1_F, "TPC Dispatch CPL FIFO Ch1" },
+ { TPCDISPCPLFIFO0_F, "TPC Dispatch CPL FIFO Ch0" },
+ { URXPLDINTFCRC3_F, "ULPRX to TPC Payload Interface CRC Error Ch3" },
+ { URXPLDINTFCRC2_F, "ULPRX to TPC Payload Interface CRC Error Ch2" },
+ { URXPLDINTFCRC1_F, "ULPRX to TPC Payload Interface CRC Error Ch1" },
+ { URXPLDINTFCRC0_F, "ULPRX to TPC Payload Interface CRC Error Ch0" },
+ { DMXDBFIFO_F, "Demux DB FIFO" },
+ { DMXDBSRAM_F, "Demux DB SRAM" },
+ { DMXCPLFIFO_F, "Demux CPL FIFO" },
+ { DMXCPLSRAM_F, "Demux CPL SRAM" },
+ { DMXCSUMFIFO_F, "Demux Checksum FIFO" },
+ { DMXLENFIFO_F, "Demux Length FIFO" },
+ { DMXCHECKFIFO_F, "Demux Check CRC16 FIFO" },
+ { DMXWINFIFO_F, "Demux Winner FIFO" },
+ { EGTOKENFIFO_F, "Egress Token FIFO Parity Error" },
+ { EGDATAFIFO_F, "Egress FIFO Parity Error" },
+ { UTX2TPCINTF3_F, "ULPTX to TPC Interface Parity Error Ch3" },
+ { UTX2TPCINTF2_F, "ULPTX to TPC Interface Parity Error Ch2" },
+ { UTX2TPCINTF1_F, "ULPTX to TPC Interface Parity Error Ch1" },
+ { UTX2TPCINTF0_F, "ULPTX to TPC Interface Parity Error Ch0" },
+ { LBKTOKENFIFO_F, "Loopback Token FIFO Parity Error" },
+ { LBKDATAFIFO_F, "Loopback FIFO Parity Error" },
+ { 0 }
+ };
+ static const struct intr_info tp_c_perr_cause = {
+ .name = "TP_C_PERR_CAUSE",
+ .cause_reg = TP_C_PERR_CAUSE_A,
+ .enable_reg = TP_C_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = tp_c_perr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details tp_e_eg_perr_details[] = {
+ { MPSLPBKTOKENFIFO_F, "MPS Loopback Token FIFO parity error" },
+ { MPSMACTOKENFIFO_F, "MPS MAC Token FIFO parity error" },
+ { DISPIPSECFIFO3_F, "Ch3 Dispatch IPSec FIFO parity error" },
+ { DISPTCPFIFO3_F, "Ch3 Dispatch TCP FIFO parity error" },
+ { DISPIPFIFO3_F, "Ch3 Dispatch IP FIFO parity error" },
+ { DISPETHFIFO3_F, "Ch3 Dispatch ETH FIFO parity error" },
+ { DISPGREFIFO3_F, "Ch3 Dispatch GRE FIFO parity error" },
+ { DISPCPL5FIFO3_F, "Ch3 Dispatch CPL5 FIFO parity error" },
+ { DISPIPSECFIFO2_F, "Ch2 Dispatch IPSec FIFO parity error" },
+ { DISPTCPFIFO2_F, "Ch2 Dispatch TCP FIFO parity error" },
+ { DISPIPFIFO2_F, "Ch2 Dispatch IP FIFO parity error" },
+ { DISPETHFIFO2_F, "Ch2 Dispatch ETH FIFO parity error" },
+ { DISPGREFIFO2_F, "Ch2 Dispatch GRE FIFO parity error" },
+ { DISPCPL5FIFO2_F, "Ch2 Dispatch CPL5 FIFO parity error" },
+ { DISPIPSECFIFO1_F, "Ch1 Dispatch IPSec FIFO parity error" },
+ { DISPTCPFIFO1_F, "Ch1 Dispatch TCP FIFO parity error" },
+ { DISPIPFIFO1_F, "Ch1 Dispatch IP FIFO parity error" },
+ { DISPETHFIFO1_F, "Ch1 Dispatch ETH FIFO parity error" },
+ { DISPGREFIFO1_F, "Ch1 Dispatch GRE FIFO parity error" },
+ { DISPCPL5FIFO1_F, "Ch1 Dispatch CPL5 FIFO parity error" },
+ { DISPIPSECFIFO0_F, "Ch0 Dispatch IPSec FIFO parity error" },
+ { DISPTCPFIFO0_F, "Ch0 Dispatch TCP FIFO parity error" },
+ { DISPIPFIFO0_F, "Ch0 Dispatch IP FIFO parity error" },
+ { DISPETHFIFO0_F, "Ch0 Dispatch ETH FIFO parity error" },
+ { DISPGREFIFO0_F, "Ch0 Dispatch GRE FIFO parity error" },
+ { DISPCPL5FIFO0_F, "Ch0 Dispatch CPL5 FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info tp_e_eg_perr_cause = {
+ .name = "TP_E_EG_PERR_CAUSE",
+ .cause_reg = TP_E_EG_PERR_CAUSE_A,
+ .enable_reg = TP_E_EG_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = tp_e_eg_perr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details tp_e_in0_perr_details[] = {
+ { DMXISSFIFO_F, "Demux ISS FIFO parity error" },
+ { DMXERRFIFO_F, "Demux Error FIFO parity error" },
+ { DMXATTFIFO_F, "Demux Attributes FIFO parity error" },
+ { DMXTCPFIFO_F, "Demux TCP Fields FIFO parity error" },
+ { DMXMPAFIFO_F, "Demux MPA FIFO parity error" },
+ { DMXOPTFIFO_F, "Demux TCP Options FIFO parity error" },
+ { INGTOKENFIFO_F, "Demux Ingress Token FIFO parity error" },
+ { DMXPLDCHKOVFL1_F, "Ch1 PLD TxCheck FIFO Overflow" },
+ { DMXPLDCHKFIFO1_F, "Ch1 PLD TxCheck FIFO parity error" },
+ { DMXOPTFIFO1_F, "Ch1 Options buffer parity error" },
+ { DMXMPAFIFO1_F, "Ch1 MPA FIFO parity error" },
+ { DMXDBFIFO1_F, "Ch1 DB FIFO parity error" },
+ { DMXATTFIFO1_F, "Ch1 Attribute FIFO parity error" },
+ { DMXISSFIFO1_F, "Ch1 ISS FIFO parity error" },
+ { DMXTCPFIFO1_F, "Ch1 TCP Fields FIFO parity error" },
+ { DMXERRFIFO1_F, "Ch1 Error FIFO parity error" },
+ { MPS2TPINTF1_F, "Ch1 MPS2TP Interface parity error" },
+ { DMXPLDCHKOVFL0_F, "Ch0 PLD TxCheck FIFO Overflow" },
+ { DMXPLDCHKFIFO0_F, "Ch0 PLD TxCheck FIFO parity error" },
+ { DMXOPTFIFO0_F, "Ch0 Options buffer parity error" },
+ { DMXMPAFIFO0_F, "Ch0 MPA FIFO parity error" },
+ { DMXDBFIFO0_F, "Ch0 DB FIFO parity error" },
+ { DMXATTFIFO0_F, "Ch0 Attribute FIFO parity error" },
+ { DMXISSFIFO0_F, "Ch0 ISS FIFO parity error" },
+ { DMXTCPFIFO0_F, "Ch0 TCP Fields FIFO parity error" },
+ { DMXERRFIFO0_F, "Ch0 Error FIFO parity error" },
+ { MPS2TPINTF0_F, "Ch0 MPS2TP Interface parity error" },
+ { 0 }
+ };
+ static const struct intr_info tp_e_in0_perr_cause = {
+ .name = "TP_E_IN0_PERR_CAUSE",
+ .cause_reg = TP_E_IN0_PERR_CAUSE_A,
+ .enable_reg = TP_E_IN0_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = tp_e_in0_perr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details tp_e_in1_perr_details[] = {
+ { DMXPLDCHKOVFL3_F, "Ch3 PLD TxCheck FIFO Overflow" },
+ { DMXPLDCHKFIFO3_F, "Ch3 PLD TxCheck FIFO parity error" },
+ { DMXOPTFIFO3_F, "Ch3 Options buffer parity error" },
+ { DMXMPAFIFO3_F, "Ch3 MPA FIFO parity error" },
+ { DMXDBFIFO3_F, "Ch3 DB FIFO parity error" },
+ { DMXATTFIFO3_F, "Ch3 Attribute FIFO parity error" },
+ { DMXISSFIFO3_F, "Ch3 ISS FIFO parity error" },
+ { DMXTCPFIFO3_F, "Ch3 TCP Fields FIFO parity error" },
+ { DMXERRFIFO3_F, "Ch3 Error FIFO parity error" },
+ { MPS2TPINTF3_F, "Ch3 MPS2TP Interface parity error" },
+ { DMXPLDCHKOVFL2_F, "Ch2 PLD TxCheck FIFO Overflow" },
+ { DMXPLDCHKFIFO2_F, "Ch2 PLD TxCheck FIFO parity error" },
+ { DMXOPTFIFO2_F, "Ch2 Options buffer parity error" },
+ { DMXMPAFIFO2_F, "Ch2 MPA FIFO parity error" },
+ { DMXDBFIFO2_F, "Ch2 DB FIFO parity error" },
+ { DMXATTFIFO2_F, "Ch2 Attribute FIFO parity error" },
+ { DMXISSFIFO2_F, "Ch2 ISS FIFO parity error" },
+ { DMXTCPFIFO2_F, "Ch2 TCP Fields FIFO parity error" },
+ { DMXERRFIFO2_F, "Ch2 Error FIFO parity error" },
+ { MPS2TPINTF2_F, "Ch2 MPS2TP Interface parity error" },
+ { 0 }
+ };
+ static const struct intr_info tp_e_in1_perr_cause = {
+ .name = "TP_E_IN1_PERR_CAUSE",
+ .cause_reg = TP_E_IN1_PERR_CAUSE_A,
+ .enable_reg = TP_E_IN1_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = tp_e_in1_perr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details tp_other_perr_details[] = {
+ { DMARBTPERR_F, "DMARBT MA Rsp Interface parity Error" },
+ { MMGRCACHEDATASRAM_F, "TP MMGR Cache Data SRAM" },
+ { MMGRCACHETAGFIFO_F, "TP MMGR Cache Tag FIFO" },
+ { DBL2TLUTPERR_F, "TP DB Lookup Table" },
+ { DBTXTIDPERR_F, "TP DB FIFOs" },
+ { DBEXTPERR_F, "TP DB Extended Opcode FIFO" },
+ { DBOPPERR_F, "TP DB Opcode FIFO" },
+ { TMCACHEPERR_F, "TP TM Cache SRAM" },
+ { TPPROTOSRAM_F, "TP Protocol SRAM" },
+ { HSPSRAM_F, "HighSpeed SRAM" },
+ { RATEGRPSRAM_F, "Rate Group SRAM" },
+ { TXFBSEQFIFO_F, "Tx Feedback Sequence Number FIFO" },
+ { CMDATASRAM_F, "Cache Data SRAM" },
+ { CMTAGFIFO_F, "Cache Tag FIFO" },
+ { RFCOPFIFO_F, "RCF Opcode FIFO" },
+ { DELINVFIFO_F, "Delete Invalid FIFO" },
+ { RSSCFGSRAM_F, "RSS Config or Round-Robin SRAM" },
+ { RSSKEYSRAM_F, "RSS Key SRAM" },
+ { RSSLKPSRAM_F, "RSS Lookup SRAM" },
+ { SRQSRAM_F, "SRQ SRAM" },
+ { ARPDASRAM_F, "ARP DA SRAM" },
+ { ARPSASRAM_F, "ARP SA SRAM" },
+ { ARPGRESRAM_F, "ARP GRE SRAM" },
+ { ARPIPSECSRAM1_F, "ARP IPSec SRAM0" },
+ { ARPIPSECSRAM0_F, "ARP IPSec SRAM1" },
+ { 0 }
+ };
+ static const struct intr_info tp_o_perr_cause = {
+ .name = "TP_O_PERR_CAUSE",
+ .cause_reg = TP_O_PERR_CAUSE_A,
+ .enable_reg = TP_O_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = tp_other_perr_details,
+ .actions = NULL,
+ };
+ bool fatal;
+
+ if (is_t7(adap->params.chip)) {
+ tp_intr_info.details = t7_tp_intr_details;
+ fatal = t4_handle_intr(adap, &tp_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &tp_cerr_cause, 0, verbose);
+ fatal |= t4_handle_intr(adap, &tp_c_perr_cause, 0, verbose);
+ fatal |= t4_handle_intr(adap, &tp_e_eg_perr_cause, 0, verbose);
+ fatal |= t4_handle_intr(adap, &tp_e_in0_perr_cause, 0, verbose);
+ fatal |= t4_handle_intr(adap, &tp_e_in1_perr_cause, 0, verbose);
+ fatal |= t4_handle_intr(adap, &tp_o_perr_cause, 0, verbose);
+ } else {
+ tp_intr_info.details = tp_intr_details;
+ fatal = t4_handle_intr(adap, &tp_intr_info, 0, verbose);
+ }
+
+ clear_int_cause_reg(adap, &tp_intr_info);
+ return fatal;
+}
+
+/*
+ * SGE interrupt handler.
+ */
+static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details sge_int1_details[] = {
+ { PERR_FLM_CREDITFIFO_F, "SGE FLM credit FIFO parity error" },
+ { PERR_IMSG_HINT_FIFO_F, "SGE IMSG hint FIFO parity error" },
+ { PERR_HEADERSPLIT_FIFO3_F | PERR_HEADERSPLIT_FIFO2_F,
+ "SGE header split FIFO parity error" },
+ { PERR_PAYLOAD_FIFO3_F | PERR_PAYLOAD_FIFO2_F,
+ "SGE payload FIFO parity error" },
+ { PERR_PC_RSP_F, "SGE PC response parity error" },
+ { PERR_PC_REQ_F, "SGE PC request parity error" },
+ { 0x003c0000, "SGE DBP PC response FIFO parity error" },
+ { PERR_DMARBT_F, "SGE DMA RBT parity error" },
+ { PERR_FLM_DBPFIFO_F, "SGE FLM DBP FIFO parity error" },
+ { PERR_FLM_MCREQ_FIFO_F, "SGE FLM MC request FIFO parity error" },
+ { PERR_FLM_HINTFIFO_F, "SGE FLM hint FIFO parity error" },
+ { 0x00003c00, "SGE align control FIFO parity error" },
+ { 0x000003c0, "SGE EDMA FIFO parity error" },
+ { 0x0000003c, "SGE PD FIFO parity error" },
+ { PERR_ING_CTXT_MIFRSP_F, "SGE Ingress context MIF response parity error" },
+ { PERR_EGR_CTXT_MIFRSP_F, "SGE Egress context MIF response parity error" },
+ { 0 }
+ };
+ static const struct intr_info sge_int1_info = {
+ .name = "SGE_INT_CAUSE1",
+ .cause_reg = SGE_INT_CAUSE1_A,
+ .enable_reg = SGE_INT_ENABLE1_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = sge_int1_details,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_sge_int2_details[] = {
+ { TF_FIFO_PERR_F, "SGE TF FIFO parity error" },
+ { PERR_EGR_DBP_TX_COAL_F, "SGE egress DBP TX coal parity error" },
+ { PERR_DBP_FL_FIFO_F, "SGE DBP FL FIFO parity error" },
+ { DEQ_LL_PERR_F, "SGE linked list SRAM parity error" },
+ { ENQ_PERR_F, "SGE enq tag SRAM parity error" },
+ { DEQ_OUT_PERR_F, "SGE tbuf deq output FIFO parity error" },
+ { BUF_PERR_F, "SGE tbuf main buffer parity error" },
+ { PERR_CONM_SRAM_F, "SGE CONM SRAM parity error" },
+ { PERR_ISW_IDMA3_FIFO_F | PERR_ISW_IDMA2_FIFO_F |
+ PERR_ISW_IDMA1_FIFO_F | PERR_ISW_IDMA0_FIFO_F,
+ "SGE ISW IDMA FIFO parity error" },
+ { PERR_ISW_DBP_FIFO_F, "SGE ISW DBP FIFO parity error" },
+ { PERR_ISW_GTS_FIFO_F, "SGE ISW GTS FIFO parity error" },
+ { PERR_ITP_EVR_F, "SGE ITP EVR parity error" },
+ { PERR_FLM_CNTXMEM_F, "SGE FLM context memory parity error" },
+ { PERR_FLM_L1CACHE_F, "SGE FLM L1 cache parity error" },
+ { SGE_IPP_FIFO_PERR_F, "SGE IPP FIFO parity error" },
+ { PERR_DBP_HP_FIFO_F, "SGE DBP HP FIFO parity error" },
+ { PERR_DB_FIFO_F, "SGE doorbell FIFO parity error" },
+ { PERR_ING_CTXT_CACHE_F | PERR_EGR_CTXT_CACHE_F,
+ "SGE context cache parity error" },
+ { PERR_BASE_SIZE_F, "SGE base size parity error" },
+ { 0 }
+ };
+ static const struct intr_details t6_sge_int2_details[] = {
+ { PERR_DBP_HINT_FL_FIFO_F, "SGE DBP hint FL FIFO parity error" },
+ { PERR_EGR_DBP_TX_COAL_F, "SGE egress DBP TX coal parity error" },
+ { PERR_DBP_FL_FIFO_F, "SGE DBP FL FIFO parity error" },
+ { DEQ_LL_PERR_F, "SGE tbuf dequeue linked list SRAM parity error" },
+ { ENQ_PERR_F, "SGE tbuf enqueue tag SRAM parity error" },
+ { DEQ_OUT_PERR_F, "SGE tbuf dequeue output FIFO parity error" },
+ { BUF_PERR_F, "SGE tbuf main buffer parity error" },
+ { PERR_CONM_SRAM_F, "SGE CONM SRAM parity error" },
+ { PERR_ISW_IDMA1_FIFO_F, "SGE ISW IDMA FIFO parity error" },
+ { PERR_ISW_IDMA0_FIFO_F, "SGE ISW IDMA FIFO parity error" },
+ { PERR_ISW_DBP_FIFO_F, "SGE ISW DBP FIFO parity error" },
+ { PERR_ISW_GTS_FIFO_F, "SGE ISW GTS FIFO parity error" },
+ { PERR_ITP_EVR_F, "SGE ITP EVR parity error" },
+ { PERR_FLM_CNTXMEM_F, "SGE FLM context memory parity error" },
+ { PERR_FLM_L1CACHE_F, "SGE FLM L1 cache parity error" },
+ { PERR_DBP_HINT_FIFO_F, "SGE DBP hint FIFO parity error" },
+ { PERR_DBP_HP_FIFO_F, "SGE DBP high priority FIFO parity error" },
+ { PERR_DB_FIFO_F, "SGE DBP merge DB FIFO parity error" },
+ { PERR_ING_CTXT_CACHE_F, "SGE ingress context cache parity error" },
+ { PERR_EGR_CTXT_CACHE_F, "SGE egress context cache parity error" },
+ { PERR_BASE_SIZE_F, "SGE base size parity error" },
+ { 0 }
+ };
+ struct intr_info sge_int2_info = {
+ .name = "SGE_INT_CAUSE2",
+ .cause_reg = SGE_INT_CAUSE2_A,
+ .enable_reg = SGE_INT_ENABLE2_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details sge_int3_details[] = {
+ { ERR_FLM_DBP_F,
+ "DBP pointer delivery for invalid context or QID" },
+ { ERR_FLM_IDMA1_F | ERR_FLM_IDMA0_F,
+ "Invalid QID or header request by IDMA" },
+ { ERR_FLM_HINT_F, "FLM hint is for invalid context or QID" },
+ { ERR_PCIE_ERROR3_F, "SGE PCIe error for DBP thread 3" },
+ { ERR_PCIE_ERROR2_F, "SGE PCIe error for DBP thread 2" },
+ { ERR_PCIE_ERROR1_F, "SGE PCIe error for DBP thread 1" },
+ { ERR_PCIE_ERROR0_F, "SGE PCIe error for DBP thread 0" },
+ { ERR_TIMER_ABOVE_MAX_QID_F,
+ "SGE GTS with timer 0-5 for IQID > 1023" },
+ { ERR_CPL_EXCEED_IQE_SIZE_F,
+ "SGE received CPL exceeding IQE size" },
+ { ERR_INVALID_CIDX_INC_F, "SGE GTS CIDX increment too large" },
+ { ERR_ITP_TIME_PAUSED_F, "SGE ITP error" },
+ { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL" },
+ { ERR_DROPPED_DB_F, "SGE DB dropped" },
+ { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
+ "SGE IQID > 1023 received CPL for FL" },
+ { ERR_BAD_DB_PIDX3_F | ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
+ ERR_BAD_DB_PIDX0_F, "SGE DBP pidx increment too large" },
+ { ERR_ING_PCIE_CHAN_F, "SGE Ingress PCIe channel mismatch" },
+ { ERR_ING_CTXT_PRIO_F,
+ "Ingress context manager priority user error" },
+ { ERR_EGR_CTXT_PRIO_F,
+ "Egress context manager priority user error" },
+ { DBFIFO_HP_INT_F, "High priority DB FIFO threshold reached" },
+ { DBFIFO_LP_INT_F, "Low priority DB FIFO threshold reached" },
+ { REG_ADDRESS_ERR_F, "Undefined SGE register accessed" },
+ { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID" },
+ { EGRESS_SIZE_ERR_F, "SGE illegal egress QID" },
+ { 0x0000000f, "SGE context access for invalid queue" },
+ { 0 }
+ };
+ static const struct intr_details t6_sge_int3_details[] = {
+ { ERR_FLM_DBP_F,
+ "DBP pointer delivery for invalid context or QID" },
+ { ERR_FLM_IDMA1_F | ERR_FLM_IDMA0_F,
+ "Invalid QID or header request by IDMA" },
+ { ERR_FLM_HINT_F, "FLM hint is for invalid context or QID" },
+ { ERR_PCIE_ERROR3_F, "SGE PCIe error for DBP thread 3" },
+ { ERR_PCIE_ERROR2_F, "SGE PCIe error for DBP thread 2" },
+ { ERR_PCIE_ERROR1_F, "SGE PCIe error for DBP thread 1" },
+ { ERR_PCIE_ERROR0_F, "SGE PCIe error for DBP thread 0" },
+ { ERR_TIMER_ABOVE_MAX_QID_F,
+ "SGE GTS with timer 0-5 for IQID > 1023" },
+ { ERR_CPL_EXCEED_IQE_SIZE_F,
+ "SGE received CPL exceeding IQE size" },
+ { ERR_INVALID_CIDX_INC_F, "SGE GTS CIDX increment too large" },
+ { ERR_ITP_TIME_PAUSED_F, "SGE ITP error" },
+ { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL" },
+ { ERR_DROPPED_DB_F, "SGE DB dropped" },
+ { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
+ "SGE IQID > 1023 received CPL for FL" },
+ { ERR_BAD_DB_PIDX3_F | ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
+ ERR_BAD_DB_PIDX0_F, "SGE DBP pidx increment too large" },
+ { ERR_ING_PCIE_CHAN_F, "SGE Ingress PCIe channel mismatch" },
+ { ERR_ING_CTXT_PRIO_F,
+ "Ingress context manager priority user error" },
+ { ERR_EGR_CTXT_PRIO_F,
+ "Egress context manager priority user error" },
+ { DBP_TBUF_FULL_F, "SGE DBP tbuf full" },
+ { FATAL_WRE_LEN_F,
+ "SGE WRE packet less than advertized length" },
+ { REG_ADDRESS_ERR_F, "Undefined SGE register accessed" },
+ { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID" },
+ { EGRESS_SIZE_ERR_F, "SGE illegal egress QID" },
+ { 0x0000000f, "SGE context access for invalid queue" },
+ { 0 }
+ };
+ struct intr_info sge_int3_info = {
+ .name = "SGE_INT_CAUSE3",
+ .cause_reg = SGE_INT_CAUSE3_A,
+ .enable_reg = SGE_INT_ENABLE3_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details sge_int4_details[] = {
+ { ERR_ISHIFT_UR1_F | ERR_ISHIFT_UR0_F, "SGE ishift underrun" },
+ { BAR2_EGRESS_LEN_OR_ADDR_ERR_F, "SGE BAR2 PL access length or alignment error" },
+ { ERR_CPL_EXCEED_MAX_IQE_SIZE1_F | ERR_CPL_EXCEED_MAX_IQE_SIZE0_F,
+ "SGE CPL exceeds max IQE size" },
+ { ERR_WR_LEN_TOO_LARGE3_F | ERR_WR_LEN_TOO_LARGE2_F |
+ ERR_WR_LEN_TOO_LARGE1_F | ERR_WR_LEN_TOO_LARGE0_F,
+ "SGE WR length too large" },
+ { ERR_LARGE_MINFETCH_WITH_TXCOAL3_F | ERR_LARGE_MINFETCH_WITH_TXCOAL2_F |
+ ERR_LARGE_MINFETCH_WITH_TXCOAL1_F | ERR_LARGE_MINFETCH_WITH_TXCOAL0_F,
+ "SGE invalid MinFetchBurst with TxCoalesce" },
+ { COAL_WITH_HP_DISABLE_ERR_F, "SGE coalesce with HP disable error" },
+ { BAR2_EGRESS_COAL0_ERR_F, "SGE BAR2 PL access addr offset 0" },
+ { BAR2_EGRESS_SIZE_ERR_F, "SGE BAR2 illegal egress QID access" },
+ { FLM_PC_RSP_ERR_F, "SGE FLM PC response error" },
+ { ERR_TH3_MAX_FETCH_F | ERR_TH2_MAX_FETCH_F |
+ ERR_TH1_MAX_FETCH_F | ERR_TH0_MAX_FETCH_F,
+ "SGE max fetch violation" },
+ { ERR_RX_CPL_PACKET_SIZE1_F | ERR_RX_CPL_PACKET_SIZE0_F,
+ "SGE CPL length mismatch error" },
+ { ERR_BAD_UPFL_INC_CREDIT3_F | ERR_BAD_UPFL_INC_CREDIT2_F |
+ ERR_BAD_UPFL_INC_CREDIT1_F | ERR_BAD_UPFL_INC_CREDIT0_F,
+ "SGE upfl credit wrap error" },
+ { ERR_PHYSADDR_LEN0_IDMA1_F | ERR_PHYSADDR_LEN0_IDMA0_F,
+ "SGE CPL_RX_PHYS_ADDR length 0 error" },
+ { ERR_FLM_INVALID_PKT_DROP1_F | ERR_FLM_INVALID_PKT_DROP0_F,
+ "SGE IDMA packet drop due to invalid FLM context" },
+ { ERR_UNEXPECTED_TIMER_F, "SGE unexpected timer error" },
+ { 0 }
+ };
+ static const struct intr_info sge_int4_info = {
+ .name = "SGE_INT_CAUSE4",
+ .cause_reg = SGE_INT_CAUSE4_A,
+ .enable_reg = SGE_INT_ENABLE4_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = sge_int4_details,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_sge_int5_details[] = {
+ { ERR_T_RXCRC_F, "SGE RxCRC error" },
+ { PERR_MC_RSPDATA_F, "SGE MC response data parity error" },
+ { PERR_PC_RSPDATA_F, "SGE PC response data parity error" },
+ { PERR_PD_RDRSPDATA_F, "SGE PD read response data parity error" },
+ { PERR_U_RXDATA_F, "SGE U Rx data parity error" },
+ { PERR_UD_RXDATA_F, "SGE UD Rx data parity error" },
+ { PERR_UP_DATA_F, "SGE uP data parity error" },
+ { PERR_CIM2SGE_RXDATA_F, "SGE CIM2SGE Rx data parity error" },
+ { PERR_IMSG_PD_FIFO_F, "SGE IMSG PD FIFO parity error" },
+ { PERR_ULPTX_FIFO1_F | PERR_ULPTX_FIFO0_F, "SGE ULPTX FIFO parity error" },
+ { PERR_IDMA2IMSG_FIFO3_F | PERR_IDMA2IMSG_FIFO2_F |
+ PERR_IDMA2IMSG_FIFO1_F | PERR_IDMA2IMSG_FIFO0_F,
+ "SGE IDMA2IMSG FIFO parity error" },
+ { PERR_POINTER_DATA_FIFO3_F | PERR_POINTER_DATA_FIFO2_F |
+ PERR_POINTER_DATA_FIFO1_F | PERR_POINTER_DATA_FIFO0_F,
+ "SGE pointer data FIFO parity error" },
+ { PERR_POINTER_HDR_FIFO3_F | PERR_POINTER_HDR_FIFO2_F |
+ PERR_POINTER_HDR_FIFO1_F | PERR_POINTER_HDR_FIFO0_F,
+ "SGE pointer header FIFO parity error" },
+ { PERR_PAYLOAD_FIFO1_F | PERR_PAYLOAD_FIFO0_F,
+ "SGE payload FIFO parity error" },
+ { PERR_MGT_BAR2_FIFO_F, "SGE MGT BAR2 FIFO parity error" },
+ { PERR_HEADERSPLIT_FIFO1_F | PERR_HEADERSPLIT_FIFO0_F,
+ "SGE header split FIFO parity error" },
+ { PERR_HINT_DELAY_FIFO_F, "SGE hint delay FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_details t6_sge_int5_details[] = {
+ { ERR_T_RXCRC_F, "SGE T RxCRC parity error" },
+ { PERR_MC_RSPDATA_F, "SGE MC response data parity error" },
+ { PERR_PC_RSPDATA_F, "SGE PC response data parity error" },
+ { PERR_U_RXDATA_F | PERR_UD_RXDATA_F, "SGE ULP Rx data parity error" },
+ { PERR_UP_DATA_F, "SGE uP data parity error" },
+ { PERR_CIM2SGE_RXDATA_F, "SGE CIM2SGE Rx data parity error" },
+ { PERR_HINT_DELAY_FIFO1_F | PERR_HINT_DELAY_FIFO0_F,
+ "SGE hint delay FIFO parity error" },
+ { PERR_IMSG_PD_FIFO_F, "SGE IMSG PD FIFO parity error" },
+ { PERR_ULPTX_FIFO1_F | PERR_ULPTX_FIFO0_F,
+ "SGE ULPTX FIFO parity error" },
+ { PERR_IDMA2IMSG_FIFO1_F | PERR_IDMA2IMSG_FIFO0_F,
+ "SGE IDMA2IMSG FIFO parity error" },
+ { PERR_POINTER_DATA_FIFO1_F | PERR_POINTER_DATA_FIFO0_F,
+ "SGE pointer data FIFO parity error" },
+ { PERR_POINTER_HDR_FIFO1_F | PERR_POINTER_HDR_FIFO0_F,
+ "SGE pointer header FIFO parity error" },
+ { PERR_PAYLOAD_FIFO1_F | PERR_PAYLOAD_FIFO0_F,
+ "SGE payload FIFO parity error" },
+ { PERR_EDMA_INPUT_FIFO3_F | PERR_EDMA_INPUT_FIFO2_F |
+ PERR_EDMA_INPUT_FIFO1_F | PERR_EDMA_INPUT_FIFO0_F,
+ "SGE EDMA input FIFO parity error" },
+ { PERR_MGT_BAR2_FIFO_F, "SGE MGT BAR2 FIFO parity error" },
+ { PERR_HEADERSPLIT_FIFO1_F | PERR_HEADERSPLIT_FIFO0_F,
+ "SGE header split FIFO parity error" },
+ { PERR_CIM_FIFO1_F | PERR_CIM_FIFO0_F, "SGE CIM FIFO parity error" },
+ { PERR_IDMA_SWITCH_OUTPUT_FIFO1_F | PERR_IDMA_SWITCH_OUTPUT_FIFO0_F,
+ "SGE IDMA switch output FIFO parity error" },
+ { 0 }
+ };
+ struct intr_info sge_int5_info = {
+ .name = "SGE_INT_CAUSE5",
+ .cause_reg = SGE_INT_CAUSE5_A,
+ .enable_reg = SGE_INT_ENABLE5_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details sge_int6_details[] = {
+ /* T7+ */
+ { 0xe0000000, "SGE fatal DEQ0 DRDY error" },
+ { 0x1c000000, "SGE fatal OUT0 DRDY error" },
+ { IMSG_DBG3_STUCK_F | IMSG_DBG2_STUCK_F |
+ IMSG_DBG1_STUCK_F | IMSG_DBG0_STUCK_F,
+ "SGE IMSG stuck due to insufficient credits" },
+ /* T6 + */
+ { ERR_DB_SYNC_F, "SGE doorbell sync failed" },
+ { ERR_GTS_SYNC_F, "SGE GTS sync failed" },
+ { FATAL_LARGE_COAL_F, "SGE BAR2 payload too large" },
+ { PL_BAR2_FRM_ERR_F, "SGE BAR2 framing error" },
+ { SILENT_DROP_TX_COAL_F, "SGE silent drop of Tx coal WR" },
+ { ERR_INV_CTXT4_F, "SGE context access for invalid queue thread 4" },
+ { ERR_BAD_DB_PIDX4_F, "SGE doorbell pidx too large thread 4" },
+ { ERR_BAD_UPFL_INC_CREDIT4_F, "SGE upfl credit wrap thread 4" },
+ { FATAL_TAG_MISMATCH_F, "SGE doorbell tag mismatch" },
+ { FATAL_ENQ_CTL_RDY_F, "SGE enq_ctl_fifo overflow" },
+ { ERR_PC_RSP_LEN3_F | ERR_PC_RSP_LEN2_F |
+ ERR_PC_RSP_LEN1_F | ERR_PC_RSP_LEN0_F,
+ "SGE PCIe response error for DBP threads" },
+ { FATAL_ENQ2LL_VLD_F, "SGE tbuf fatal_enq2ll_vld" },
+ { FATAL_LL_EMPTY_F, "SGE tbuf fatal_ll_empty" },
+ { FATAL_OFF_WDENQ_F, "SGE tbuf fatal_off_wdenq" },
+ { 0x00000018, "SGE tbuf fatal_deq1_drdy" },
+ { 0x00000006, "SGE tbuf fatal_out1_drdy" },
+ { FATAL_DEQ_F, "SGE tbuf fatal_deq" },
+ { 0 }
+ };
+ static const struct intr_info sge_int6_info = {
+ .name = "SGE_INT_CAUSE6",
+ .cause_reg = SGE_INT_CAUSE6_A,
+ .enable_reg = SGE_INT_ENABLE6_A,
+ .fatal = 0x3c30ff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = sge_int6_details,
+ .actions = NULL,
+ };
+ static const struct intr_details sge_int7_details[] = {
+ { HINT_FIFO_FULL_F, "SGE hint FIFO full" },
+ { CERR_HINT_DELAY_FIFO_F, "SGE hint delay FIFO ECC error" },
+ { COAL_TIMER_FIFO_PERR_F, "SGE coalescing timer FIFO parity error" },
+ { CMP_FIFO_PERR_F, "SGE CMP FIFO parity error" },
+ { SGE_IPP_FIFO_CERR_F, "SGE IPP FIFO ECC error" },
+ { CERR_ING_CTXT_CACHE_F | CERR_EGR_CTXT_CACHE_F,
+ "SGE context cache ECC error" },
+ { IMSG_CNTX_PERR_F, "SGE IMSG context parity error" },
+ { PD_FIFO_PERR_F, "SGE PD FIFO parity error" },
+ { IMSG_512_FIFO_PERR_F, "SGE IMSG 512 FIFO parity error" },
+ { CPLSW_FIFO_PERR_F, "SGE CPLSW FIFO parity error" },
+ { IMSG_FIFO_PERR_F, "SGE IMSG FIFO parity error" },
+ { CERR_ITP_EVR_F, "SGE ITP EVR ECC error" },
+ { CERR_CONM_SRAM_F, "SGE CONM SRAM ECC error" },
+ { CERR_FLM_CNTXMEM_F, "SGE FLM context memory ECC error" },
+ { CERR_FUNC_QBASE_F, "SGE function queue base ECC error" },
+ { IMSG_CNTX_CERR_F, "SGE IMSG context ECC error" },
+ { PD_FIFO_CERR_F, "SGE PD FIFO ECC error" },
+ { IMSG_512_FIFO_CERR_F, "SGE IMSG 512 FIFO ECC error" },
+ { CPLSW_FIFO_CERR_F, "SGE CPLSW FIFO ECC error" },
+ { IMSG_FIFO_CERR_F, "SGE IMSG FIFO ECC error" },
+ { 0x0000001e, "SGE header split FIFO ECC error" }, // Bits 4:1
+ { CERR_FLM_L1CACHE_F, "SGE FLM L1 cache ECC error" },
+ { 0 }
+ };
+ static const struct intr_info sge_int7_info = {
+ .name = "SGE_INT_CAUSE7",
+ .cause_reg = SGE_INT_CAUSE7_A,
+ .enable_reg = SGE_INT_ENABLE7_A,
+ .fatal = CERR_HINT_DELAY_FIFO_F | COAL_TIMER_FIFO_PERR_F | CMP_FIFO_PERR_F |
+ IMSG_CNTX_PERR_F | PD_FIFO_PERR_F | IMSG_512_FIFO_PERR_F |
+ CPLSW_FIFO_PERR_F | IMSG_FIFO_PERR_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = sge_int7_details,
+ .actions = NULL,
+ };
+ static const struct intr_details sge_int8_details[] = {
+ { TRACE_RXPERR_F, "SGE trace packet parity error" },
+ { U3_RXPERR_F | U2_RXPERR_F | U1_RXPERR_F | U0_RXPERR_F,
+ "SGE ULP interface parity error" },
+ { T3_RXPERR_F | T2_RXPERR_F | T1_RXPERR_F | T0_RXPERR_F,
+ "SGE TP interface parity error" },
+ { 0 }
+ };
+ static const struct intr_info sge_int8_info = {
+ .name = "SGE_INT_CAUSE8",
+ .cause_reg = SGE_INT_CAUSE8_A,
+ .enable_reg = SGE_INT_ENABLE8_A,
+ .fatal = 0xffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = sge_int8_details,
+ .actions = NULL,
+ };
+ bool fatal;
+ u32 v;
+
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ if (chip <= CHELSIO_T5) {
+ sge_int3_info.details = sge_int3_details;
+ sge_int2_info.details = t6_sge_int2_details;
+ sge_int5_info.details = t6_sge_int5_details;
+ } else if (chip == CHELSIO_T6) {
+ sge_int3_info.details = t6_sge_int3_details;
+ sge_int2_info.details = t6_sge_int2_details;
+ sge_int5_info.details = t6_sge_int5_details;
+ } else {
+ sge_int3_info.details = t6_sge_int3_details;
+ sge_int2_info.details = t7_sge_int2_details;
+ sge_int5_info.details = t7_sge_int5_details;
+ }
+
+ fatal = false;
+ fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5)
+ fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T6)
+ fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ fatal |= t4_handle_intr(adap, &sge_int7_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sge_int8_info, 0, verbose);
+ }
+
+ v = t4_read_reg(adap, SGE_ERROR_STATS_A);
+ if (v & ERROR_QID_VALID_F) {
+ dev_err(adap->pdev_dev, "SGE error for QID %u\n", ERROR_QID_G(v));
+ if (v & UNCAPTURED_ERROR_F)
+ dev_err(adap->pdev_dev, "SGE UNCAPTURED_ERROR set (clearing)\n");
+ t4_write_reg(adap, SGE_ERROR_STATS_A, ERROR_QID_VALID_F | UNCAPTURED_ERROR_F);
+ }
+
+ return fatal;
+}
+
+/*
+ * CIM interrupt handler.
+ */
+static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details cim_host_T7_intr_details[] = {
+ { CORE7ACCINT_F, "CIM slave core 7 access interrupt "},
+ { CORE6ACCINT_F, "CIM slave core 6 access interrupt "},
+ { CORE5ACCINT_F, "CIM slave core 5 access interrupt "},
+ { CORE4ACCINT_F, "CIM slave core 4 access interrupt "},
+ { CORE3ACCINT_F, "CIM slave core 3 access interrupt "},
+ { CORE2ACCINT_F, "CIM slave core 2 access interrupt "},
+ { CORE1ACCINT_F, "CIM slave core 1 access interrupt "},
+ { TIMER1INT_F, "CIM TIMER0 interrupt" },
+ { TIMER0INT_F, "CIM TIMER0 interrupt" },
+ { PREFDROPINT_F, "CIM control register prefetch drop" },
+ { 0}
+ };
+ static const struct intr_details cim_host_intr_details[] = {
+ /* T6+ */
+ { PCIE2CIMINTFPARERR_F, "CIM IBQ PCIe interface parity error" },
+
+ /* T5+ */
+ { MA_CIM_INTFPERR_F, "MA2CIM interface parity error" },
+ { PLCIM_MSTRSPDATAPARERR_F,
+ "PL2CIM master response data parity error" },
+ { NCSI2CIMINTFPARERR_F, "CIM IBQ NC-SI interface parity error" },
+ { SGE2CIMINTFPARERR_F, "CIM IBQ SGE interface parity error" },
+ { ULP2CIMINTFPARERR_F, "CIM IBQ ULP_TX interface parity error" },
+ { TP2CIMINTFPARERR_F, "CIM IBQ TP interface parity error" },
+ { OBQSGERX1PARERR_F, "CIM OBQ PCIE_RX parity error" },
+ { OBQSGERX0PARERR_F, "CIM OBQ SGE_RX parity error" },
+
+ /* T4+ */
+ { TIEQOUTPARERRINT_F, "CIM TIEQ outgoing FIFO parity error" },
+ { TIEQINPARERRINT_F, "CIM TIEQ incoming FIFO parity error" },
+ { MBHOSTPARERR_F, "CIM mailbox host read parity error" },
+ { MBUPPARERR_F, "CIM mailbox uP parity error" },
+ { IBQTP0PARERR_F, "CIM IBQ TP0 parity error" },
+ { IBQTP1PARERR_F, "CIM IBQ TP1 parity error" },
+ { IBQULPPARERR_F, "CIM IBQ ULP parity error" },
+ { IBQSGELOPARERR_F, "CIM IBQ SGE_LO parity error" },
+ { IBQSGEHIPARERR_F | IBQPCIEPARERR_F, /* same bit */
+ "CIM IBQ PCIe/SGE_HI parity error" },
+ { IBQNCSIPARERR_F, "CIM IBQ NC-SI parity error" },
+ { OBQULP0PARERR_F, "CIM OBQ ULP0 parity error" },
+ { OBQULP1PARERR_F, "CIM OBQ ULP1 parity error" },
+ { OBQULP2PARERR_F, "CIM OBQ ULP2 parity error" },
+ { OBQULP3PARERR_F, "CIM OBQ ULP3 parity error" },
+ { OBQSGEPARERR_F, "CIM OBQ SGE parity error" },
+ { OBQNCSIPARERR_F, "CIM OBQ NC-SI parity error" },
+ { TIMER1INT_F, "CIM TIMER0 interrupt" },
+ { TIMER0INT_F, "CIM TIMER0 interrupt" },
+ { PREFDROPINT_F, "CIM control register prefetch drop" },
+ { 0}
+ };
+ struct intr_info cim_host_intr_info = {
+ .name = "CIM_HOST_INT_CAUSE",
+ .cause_reg = CIM_HOST_INT_CAUSE_A,
+ .enable_reg = CIM_HOST_INT_ENABLE_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details cim_host_upacc_intr_details[] = {
+ { CONWRERRINT_F, "CIM condition write error "},
+ { EEPROMWRINT_F, "CIM EEPROM came out of busy state" },
+ { TIMEOUTMAINT_F, "CIM PIF MA timeout" },
+ { TIMEOUTINT_F, "CIM PIF timeout" },
+ { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite" },
+ { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite" },
+ { BLKWRPLINT_F, "CIM block write to PL space" },
+ { BLKRDPLINT_F, "CIM block read from PL space" },
+ { SGLWRPLINT_F,
+ "CIM single write to PL space with illegal BEs" },
+ { SGLRDPLINT_F,
+ "CIM single read from PL space with illegal BEs" },
+ { BLKWRCTLINT_F, "CIM block write to CTL space" },
+ { BLKRDCTLINT_F, "CIM block read from CTL space" },
+ { SGLWRCTLINT_F,
+ "CIM single write to CTL space with illegal BEs" },
+ { SGLRDCTLINT_F,
+ "CIM single read from CTL space with illegal BEs" },
+ { BLKWREEPROMINT_F, "CIM block write to EEPROM space" },
+ { BLKRDEEPROMINT_F, "CIM block read from EEPROM space" },
+ { SGLWREEPROMINT_F,
+ "CIM single write to EEPROM space with illegal BEs" },
+ { SGLRDEEPROMINT_F,
+ "CIM single read from EEPROM space with illegal BEs" },
+ { BLKWRFLASHINT_F, "CIM block write to flash space" },
+ { BLKRDFLASHINT_F, "CIM block read from flash space" },
+ { SGLWRFLASHINT_F, "CIM single write to flash space" },
+ { SGLRDFLASHINT_F,
+ "CIM single read from flash space with illegal BEs" },
+ { BLKWRBOOTINT_F, "CIM block write to boot space" },
+ { BLKRDBOOTINT_F, "CIM block read from boot space" },
+ { SGLWRBOOTINT_F, "CIM single write to boot space" },
+ { SGLRDBOOTINT_F,
+ "CIM single read from boot space with illegal BEs" },
+ { ILLWRBEINT_F, "CIM illegal write BEs" },
+ { ILLRDBEINT_F, "CIM illegal read BEs" },
+ { ILLRDINT_F, "CIM illegal read" },
+ { ILLWRINT_F, "CIM illegal write" },
+ { ILLTRANSINT_F, "CIM illegal transaction" },
+ { RSVDSPACEINT_F, "CIM reserved space access" },
+ {0}
+ };
+ static const struct intr_info cim_host_upacc_intr_info = {
+ .name = "CIM_HOST_UPACC_INT_CAUSE",
+ .cause_reg = CIM_HOST_UPACC_INT_CAUSE_A,
+ .enable_reg = CIM_HOST_UPACC_INT_ENABLE_A,
+ .fatal = 0xbfffeeff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = cim_host_upacc_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_info cim_pf_host_intr_info = {
+ .name = "CIM_PF_HOST_INT_CAUSE",
+ .cause_reg = MYPF_REG(CIM_PF_HOST_INT_CAUSE_A),
+ .enable_reg = MYPF_REG(CIM_PF_HOST_INT_ENABLE_A),
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details cim_perr_cause_details[] = {
+ { T7_MA_CIM_INTFPERR_F, "MA2CIM interface parity error" },
+ { T7_MBHOSTPARERR_F, "Mailbox Host Read parity error" },
+ { MAARBINVRSPTAG_F, "MA Arbiter Invalid Response Tag (Fatal)" },
+ { MAARBFIFOPARERR_F, "MA Arbiter FIFO Parity Error" },
+ { SEMSRAMPARERR_F, "Semaphore logic SRAM Parity Error" },
+ { RSACPARERR_F, "RSA Code SRAM Parity Error" },
+ { RSADPARERR_F, "RSA Data SRAM Parity Error" },
+ { T7_PLCIM_MSTRSPDATAPARERR_F, "PL2CIM Master response data parity error" },
+ { T7_PCIE2CIMINTFPARERR_F, "IBQ PCIE intf parity error" },
+ { T7_NCSI2CIMINTFPARERR_F, "IBQ NCSI intf parity error" },
+ { T7_SGE2CIMINTFPARERR_F, "IBQ SGE Intf Parity error" },
+ { T7_ULP2CIMINTFPARERR_F, "IBQ ULP_TX intf parity error" },
+ { T7_TP2CIMINTFPARERR_F, "IBQ TP intf parity error" },
+ { CORE7PARERR_F, "Slave Core7 parity error" },
+ { CORE6PARERR_F, "Slave Core6 parity error" },
+ { CORE5PARERR_F, "Slave Core5 parity error" },
+ { CORE4PARERR_F, "Slave Core4 parity error" },
+ { CORE3PARERR_F, "Slave Core3 parity error" },
+ { CORE2PARERR_F, "Slave Core2 parity error" },
+ { CORE1PARERR_F, "Slave Core1 parity error" },
+ { GFTPARERR_F, "GFT block Memory parity error" },
+ { MPSRSPDATAPARERR_F, "MPS lookup interface Response parity error" },
+ { ER_RSPDATAPARERR_F, "Expansion ROM/Flash Interface Response Parity Error" },
+ { FLOWFIFOPARERR_F, "SGE FlowID Prefetch FIFO Parity Error" },
+ { OBQSRAMPARERR_F, "OBQ SRAM Parity Error" },
+ { TIEQOUTPARERR_F, "TIE Queue Outgoing FIFO parity error" },
+ { TIEQINPARERR_F, "TIE Queue Incoming FIFO parity error" },
+ { PIFRSPPARERR_F, "PIF Response interface FIFO Parity error" },
+ { PIFREQPARERR_F, "PIF Request interface FIFO Parity error" },
+ { 0 }
+ };
+ static const struct intr_info cim_perr_cause = {
+ .name = "CIM_PERR_CAUSE",
+ .cause_reg = CIM_PERR_CAUSE_A,
+ .enable_reg = CIM_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = cim_perr_cause_details,
+ .actions = NULL,
+ };
+ u32 val, fw_err;
+ bool fatal;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ cim_host_intr_info.details = cim_host_T7_intr_details;
+ else
+ cim_host_intr_info.details = cim_host_intr_details;
+ /*
+ * When the Firmware detects an internal error which normally wouldn't
+ * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
+ * to make sure the Host sees the Firmware Crash. So if we have a
+ * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
+ * interrupt.
+ */
+ fw_err = t4_read_reg(adap, PCIE_FW_A);
+ val = t4_read_reg(adap, CIM_HOST_INT_CAUSE_A);
+ if (val & TIMER0INT_F && (!(fw_err & PCIE_FW_ERR_F) ||
+ PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH)) {
+ t4_write_reg(adap, CIM_HOST_INT_CAUSE_A, TIMER0INT_F);
+ }
+
+ fatal = (fw_err & PCIE_FW_ERR_F) != 0;
+ fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
+ if (is_t7(adap->params.chip))
+ fatal |= t4_handle_intr(adap, &cim_perr_cause, 0, verbose);
+
+ return fatal;
+}
+
+/*
+ * ULP RX interrupt handler.
+ */
+static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details ulprx_intr_details[] = {
+ /* T5+ */
+ { SE_CNT_MISMATCH_1_F, "ULPRX SE count mismatch in channel 1" },
+ { SE_CNT_MISMATCH_0_F, "ULPRX SE count mismatch in channel 0" },
+
+ /* T4+ */
+ { CAUSE_CTX_1_F, "ULPRX channel 1 context error" },
+ { CAUSE_CTX_0_F, "ULPRX channel 0 context error" },
+ { 0x007fffff, "ULPRX parity error" },
+ { 0 }
+ };
+ static const struct intr_details t6_ulprx_int_cause_details[] = {
+ { SE_CNT_MISMATCH_1_F, "SE count mismatch in channel1" },
+ { SE_CNT_MISMATCH_0_F, "SE count mismatch in channel 0" },
+ { CAUSE_CTX_1_F, "Context access error on channel 1" },
+ { CAUSE_CTX_0_F, "Context access error on channel 0" },
+ { CAUSE_FF_F, "filp-flop based fifos" },
+ { CAUSE_APF_1_F, "Arb prefetch memory, channel 1" },
+ { CAUSE_APF_0_F, "Arb prefetch memory, channel 0" },
+ { CAUSE_AF_1_F, "Arb fetch memory, channel 1" },
+ { CAUSE_AF_0_F, "Arb fetch memory, channel 0" },
+ { CAUSE_DDPDF_1_F, "ddp_data_fifo Fifo, channel 1" },
+ { CAUSE_DDPMF_1_F, "ddp_msg_fifo Fifo, channel 1" },
+ { CAUSE_MEMRF_1_F, "mem_req_fifo_d Fifo, channel 1" },
+ { CAUSE_PRSDF_1_F, "prsr_data_fifo Fifo, channel 1" },
+ { CAUSE_DDPDF_0_F, "ddp_data_fifo Fifo, channel 0" },
+ { CAUSE_DDPMF_0_F, "ddp_msg_fifo Fifo, channel 0" },
+ { CAUSE_MEMRF_0_F, "mem_req_fifo_d Fifo, channel 0" },
+ { CAUSE_PRSDF_0_F, "prsr_data_fifo Fifo, channel 0" },
+ { CAUSE_PCMDF_1_F, "Pcmd Fifo, channel 1" },
+ { CAUSE_TPTCF_1_F, "tpt_ctl_fifo Fifo, channel 1" },
+ { CAUSE_DDPCF_1_F, "ddp_ctl_fifo Fifo, channel 1" },
+ { CAUSE_MPARF_1_F, "mpar_ctl_fifo Fifo, channel 1" },
+ { CAUSE_MPARC_1_F, "mpac_ctl_fifo Fifo, channel 1" },
+ { CAUSE_PCMDF_0_F, "Pcmd Fifo, channel 0" },
+ { CAUSE_TPTCF_0_F, "tpt_ctl_fifo Fifo, channel 0" },
+ { CAUSE_DDPCF_0_F, "ddp_ctl_fifo Fifo, channel 0" },
+ { CAUSE_MPARF_0_F, "mpar_ctl_fifo Fifo, channel 0" },
+ { CAUSE_MPARC_0_F, "mpac_ctl_fifo Fifo, channel 0" },
+ { 0 }
+ };
+ static const struct intr_details t7_ulprx_int_cause_details[] = {
+ { CERR_PCMD_FIFO_3_F, "PCMD FIFO correctable Error3" },
+ { CERR_PCMD_FIFO_2_F, "PCMD FIFO correctable Error2" },
+ { CERR_PCMD_FIFO_1_F, "PCMD FIFO correctable Error1" },
+ { CERR_PCMD_FIFO_0_F, "PCMD FIFO correctable Error0" },
+ { CERR_DATA_FIFO_3_F, "DDP Data FIFO correctable Error3" },
+ { CERR_DATA_FIFO_2_F, "DDP Data FIFO correctable Error2" },
+ { CERR_DATA_FIFO_1_F, "DDP Data FIFO correctable Error1" },
+ { CERR_DATA_FIFO_0_F, "DDP Data FIFO correctable Error0" },
+ { SE_CNT_MISMATCH_3_F, "SE count mismatch in channel3" },
+ { SE_CNT_MISMATCH_2_F, "SE count mismatch in channel2" },
+ { T7_SE_CNT_MISMATCH_1_F, "SE count mismatch in channel1" },
+ { T7_SE_CNT_MISMATCH_0_F, "SE count mismatch in channel 0" },
+ { T7_ENABLE_CTX_3_F, "Context access error on channel 3" },
+ { T7_ENABLE_CTX_2_F, "Context access error on channel 2" },
+ { T7_ENABLE_CTX_1_F, "Context access error on channel 1" },
+ { T7_ENABLE_CTX_0_F, "Context access error on channel 0" },
+ { T7_ENABLE_ALN_SDC_ERR_3_F, "SDC error reported by aligner in channel3" },
+ { T7_ENABLE_ALN_SDC_ERR_2_F, "SDC error reported by aligner in channel2" },
+ { T7_ENABLE_ALN_SDC_ERR_1_F, "SDC error reported by aligner in channel1" },
+ { T7_ENABLE_ALN_SDC_ERR_0_F, "SDC error reported by aligner in channel0" },
+ { 0 }
+ };
+ struct intr_info ulprx_intr_info = {
+ .name = "ULP_RX_INT_CAUSE",
+ .cause_reg = ULP_RX_INT_CAUSE_A,
+ .enable_reg = ULP_RX_INT_ENABLE_A,
+ .fatal = T7_ENABLE_ALN_SDC_ERR_3_F | T7_ENABLE_ALN_SDC_ERR_2_F |
+ T7_ENABLE_ALN_SDC_ERR_1_F | T7_ENABLE_ALN_SDC_ERR_0_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details ulprx_int_cause_2_details[] = {
+ { ULPRX2MA_INTFPERR_F, "SDC error reported by ULPRX2MA interface parity checker" },
+ { ALN_SDC_ERR_1_F, "SDC error reported by aligner in channel 1" },
+ { ALN_SDC_ERR_0_F, "SDC error reported by aligner in channel 0" },
+ { PF_UNTAGGED_TPT_1_F, "Parity error from Untagged TPT prefetch fifo channel 1" },
+ { PF_UNTAGGED_TPT_0_F, "Parity error from Untagged TPT prefetch fifo channel 0" },
+ { PF_PBL_1_F, "Parity error from PBL prefetch fifo channel 1" },
+ { PF_PBL_0_F, "Parity error from PBL prefetch fifo channel 0" },
+ { DDP_HINT_1_F, "DDP hint fifo Perr in channel 1" },
+ { DDP_HINT_0_F, "DDP hint fifo Perr in channel 0" },
+ { 0 }
+ };
+ static const struct intr_info ulprx_intr2_info = {
+ .name = "ULP_RX_INT_CAUSE_2",
+ .cause_reg = ULP_RX_INT_CAUSE_2_A,
+ .enable_reg = ULP_RX_INT_ENABLE_2_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = ulprx_int_cause_2_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulprx_int_cause_pcmd_details[] = {
+ { CAUSE_PCMD_SFIFO_3_F, "Small FIFOs, channel 3" },
+ { CAUSE_PCMD_FIFO_3_F, "pcmd_ctl_fifo, channel 3" },
+ { CAUSE_PCMD_DDP_HINT_3_F, "ddp_hint_ctl_fifo FIFO, channel 3" },
+ { CAUSE_PCMD_TPT_3_F, "tpt_ctl_fifo FIFO, channel 3" },
+ { CAUSE_PCMD_DDP_3_F, "ddp_ctl_fifo FIFO, channel 3" },
+ { CAUSE_PCMD_MPAR_3_F, "mpar_ctl_fifo FIFO, channel 3" },
+ { CAUSE_PCMD_MPAC_3_F, "mpac_ctl_fifo FIFO, channel 3" },
+ { CAUSE_PCMD_SFIFO_2_F, "Small FIFOs, channel 2" },
+ { CAUSE_PCMD_FIFO_2_F, "pcmd_ctl_fifo, channel 2" },
+ { CAUSE_PCMD_DDP_HINT_2_F, "ddp_hint_ctl_fifo FIFO, channel 2" },
+ { CAUSE_PCMD_TPT_2_F, "tpt_ctl_fifo FIFO, channel 2" },
+ { CAUSE_PCMD_DDP_2_F, "ddp_ctl_fifo FIFO, channel 2" },
+ { CAUSE_PCMD_MPAR_2_F, "mpar_ctl_fifo FIFO, channel 2" },
+ { CAUSE_PCMD_MPAC_2_F, "mpac_ctl_fifo FIFO, channel 2" },
+ { CAUSE_PCMD_SFIFO_1_F, "Small FIFOs, channel 1" },
+ { CAUSE_PCMD_FIFO_1_F, "pcmd_ctl_fifo, channel 1" },
+ { CAUSE_PCMD_DDP_HINT_1_F, "ddp_hint_ctl_fifo FIFO, channel 1" },
+ { CAUSE_PCMD_TPT_1_F, "tpt_ctl_fifo FIFO, channel 1" },
+ { CAUSE_PCMD_DDP_1_F, "ddp_ctl_fifo FIFO, channel 1" },
+ { CAUSE_PCMD_MPAR_1_F, "mpar_ctl_fifo FIFO, channel 1" },
+ { CAUSE_PCMD_MPAC_1_F, "mpac_ctl_fifo FIFO, channel 1" },
+ { CAUSE_PCMD_SFIFO_0_F, "Small FIFOs, channel 0" },
+ { CAUSE_PCMD_FIFO_0_F, "pcmd_ctl_fifo, channel 0" },
+ { CAUSE_PCMD_DDP_HINT_0_F, "ddp_hint_ctl_fifo FIFO, channel 0" },
+ { CAUSE_PCMD_TPT_0_F, "tpt_ctl_fifo FIFO, channel 0" },
+ { CAUSE_PCMD_DDP_0_F, "ddp_ctl_fifo FIFO, channel 0" },
+ { CAUSE_PCMD_MPAR_0_F, "mpar_ctl_fifo FIFO, channel 0" },
+ { CAUSE_PCMD_MPAC_0_F, "mpac_ctl_fifo FIFO, channel 0" },
+ { 0 }
+ };
+ static const struct intr_info ulprx_int_cause_pcmd = {
+ .name = "ULP_RX_INT_CAUSE_PCMD",
+ .cause_reg = ULP_RX_INT_CAUSE_PCMD_A,
+ .enable_reg = ULP_RX_INT_ENABLE_PCMD_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulprx_int_cause_pcmd_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulprx_int_cause_data_details[] = {
+ { CAUSE_DATA_SNOOP_3_F, "Snoop FIFO, channel 3" },
+ { CAUSE_DATA_SFIFO_3_F, "Small FIFO, channel 3" },
+ { CAUSE_DATA_FIFO_3_F, "data_ctl_fifo FIFO, channel 3" },
+ { CAUSE_DATA_DDP_3_F, "ddp_ctl_fifo FIFO, channel 3" },
+ { CAUSE_DATA_CTX_3_F, "ctx_ctl_fifo FIFO, channel 3" },
+ { CAUSE_DATA_PARSER_3_F, "parser_ctl_fifo FIFO, channel 3" },
+ { CAUSE_DATA_SNOOP_2_F, "Snoop FIFO, channel 2" },
+ { CAUSE_DATA_SFIFO_2_F, "Small FIFO, channel 2" },
+ { CAUSE_DATA_FIFO_2_F, "data_ctl_fifo FIFO, channel 2" },
+ { CAUSE_DATA_DDP_2_F, "ddp_ctl_fifo FIFO, channel 2" },
+ { CAUSE_DATA_CTX_2_F, "ctx_ctl_fifo FIFO, channel 2" },
+ { CAUSE_DATA_PARSER_2_F, "parser_ctl_fifo FIFO, channel 2" },
+ { CAUSE_DATA_SNOOP_1_F, "Snoop FIFO, channel 1" },
+ { CAUSE_DATA_SFIFO_1_F, "Small FIFO, channel 1" },
+ { CAUSE_DATA_FIFO_1_F, "data_ctl_fifo FIFO, channel 1" },
+ { CAUSE_DATA_DDP_1_F, "ddp_ctl_fifo FIFO, channel 1" },
+ { CAUSE_DATA_CTX_1_F, "ctx_ctl_fifo FIFO, channel 1" },
+ { CAUSE_DATA_PARSER_1_F, "parser_ctl_fifo FIFO, channel 1" },
+ { CAUSE_DATA_SNOOP_0_F, "Snoop FIFO, channel 0" },
+ { CAUSE_DATA_SFIFO_0_F, "Small FIFO, channel 0" },
+ { CAUSE_DATA_FIFO_0_F, "data_ctl_fifo FIFO, channel 0" },
+ { CAUSE_DATA_DDP_0_F, "ddp_ctl_fifo FIFO, channel 0" },
+ { CAUSE_DATA_CTX_0_F, "ctx_ctl_fifo FIFO, channel 0" },
+ { CAUSE_DATA_PARSER_0_F, "parser_ctl_fifo FIFO, channel 0" },
+ { 0 }
+ };
+ static const struct intr_info ulprx_int_cause_data = {
+ .name = "ULP_RX_INT_CAUSE_DATA",
+ .cause_reg = ULP_RX_INT_CAUSE_DATA_A,
+ .enable_reg = ULP_RX_INT_ENABLE_DATA_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulprx_int_cause_data_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulprx_int_cause_arb_details[] = {
+ { CAUSE_ARB_PBL_PF_3_F, "pbl_pf_ctl_fifo FIFO, channel 3" },
+ { CAUSE_ARB_PF_3_F, "pf_ctl_fifo FIFO, channel 3" },
+ { CAUSE_ARB_TPT_PF_3_F, "tpt_pf_ctl_fifo FIFO, channel 3" },
+ { CAUSE_ARB_F_3_F, "f_ctl_fifo FIFO, channel 3" },
+ { CAUSE_ARB_PBL_PF_2_F, "pbl_pf_ctl_fifo FIFO, channel 2" },
+ { CAUSE_ARB_PF_2_F, "pf_ctl_fifo FIFO, channel 2" },
+ { CAUSE_ARB_TPT_PF_2_F, "tpt_pf_ctl_fifo FIFO, channel 2" },
+ { CAUSE_ARB_F_2_F, "f_ctl_fifo FIFO, channel 2" },
+ { CAUSE_ARB_PBL_PF_1_F, "pbl_pf_ctl_fifo FIFO, channel 1" },
+ { CAUSE_ARB_PF_1_F, "pf_ctl_fifo FIFO, channel 1" },
+ { CAUSE_ARB_TPT_PF_1_F, "tpt_pf_ctl_fifo FIFO, channel 1" },
+ { CAUSE_ARB_F_1_F, "f_ctl_fifo FIFO, channel 1" },
+ { CAUSE_ARB_PBL_PF_0_F, "pbl_pf_ctl_fifo FIFO, channel 0" },
+ { CAUSE_ARB_PF_0_F, "pf_ctl_fifo FIFO, channel 0" },
+ { CAUSE_ARB_TPT_PF_0_F, "tpt_pf_ctl_fifo FIFO, channel 0" },
+ { CAUSE_ARB_F_0_F, "f_ctl_fifo FIFO, channel 0" },
+ { 0 }
+ };
+ static const struct intr_info ulprx_int_cause_arb = {
+ .name = "ULP_RX_INT_CAUSE_ARB",
+ .cause_reg = ULP_RX_INT_CAUSE_ARB_A,
+ .enable_reg = ULP_RX_INT_ENABLE_ARB_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulprx_int_cause_arb_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulprx_int_cause_interface_details[] = {
+ { CAUSE_ULPRX2SBT_RSPPERR_F, "ULPRX2SBT_RspPerr" },
+ { CAUSE_ULPRX2MA_RSPPERR_F, "ULPRX2MA_RspPerr" },
+ { CAUSE_PIO_BUS_PERR_F, "Pio_Bus_Perr" },
+ { CAUSE_PM2ULP_SNOOPDATA_3_F, "PM2ULP_SnoopData, channel 3" },
+ { CAUSE_PM2ULP_SNOOPDATA_2_F, "PM2ULP_SnoopData, channel 2" },
+ { CAUSE_PM2ULP_SNOOPDATA_1_F, "PM2ULP_SnoopData, channel 1" },
+ { CAUSE_PM2ULP_SNOOPDATA_0_F, "PM2ULP_SnoopData, channel 0" },
+ { CAUSE_TLS2ULP_DATA_3_F, "TLS2ULP_Data, channel 3" },
+ { CAUSE_TLS2ULP_DATA_2_F, "TLS2ULP_Data, channel 2" },
+ { CAUSE_TLS2ULP_DATA_1_F, "TLS2ULP_Data, channel 1" },
+ { CAUSE_TLS2ULP_DATA_0_F, "TLS2ULP_Data, channel 0" },
+ { CAUSE_TLS2ULP_PLENDATA_3_F, "TLS2ULP_PLenData, channel 3" },
+ { CAUSE_TLS2ULP_PLENDATA_2_F, "TLS2ULP_PLenData, channel 2" },
+ { CAUSE_TLS2ULP_PLENDATA_1_F, "TLS2ULP_PLenData, channel 1" },
+ { CAUSE_TLS2ULP_PLENDATA_0_F, "TLS2ULP_PLenData, channel 0" },
+ { CAUSE_PM2ULP_DATA_3_F, "Pm2Ulp_Data, channel 3" },
+ { CAUSE_PM2ULP_DATA_2_F, "Pm2Ulp_Data, channel 2" },
+ { CAUSE_PM2ULP_DATA_1_F, "Pm2Ulp_Data, channel 1" },
+ { CAUSE_PM2ULP_DATA_0_F, "Pm2Ulp_Data, channel 0" },
+ { CAUSE_TP2ULP_PCMD_3_F, "Tp2Ulp_Pcmd, channel 3" },
+ { CAUSE_TP2ULP_PCMD_2_F, "Tp2Ulp_Pcmd, channel 2" },
+ { CAUSE_TP2ULP_PCMD_1_F, "Tp2Ulp_Pcmd, channel 1" },
+ { CAUSE_TP2ULP_PCMD_0_F, "Tp2Ulp_Pcmd, channel 0" },
+ { 0 }
+ };
+ static const struct intr_info ulprx_int_cause_intf = {
+ .name = "ULP_RX_INT_CAUSE_INTERFACE",
+ .cause_reg = ULP_RX_INT_CAUSE_INTERFACE_A,
+ .enable_reg = ULP_RX_INT_ENABLE_INTERFACE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulprx_int_cause_interface_details,
+ .actions = NULL,
+ };
+ bool fatal = false;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
+ ulprx_intr_info.details = ulprx_intr_details;
+ else if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T6)
+ ulprx_intr_info.details = t6_ulprx_int_cause_details;
+ else
+ ulprx_intr_info.details = t7_ulprx_int_cause_details;
+
+ fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7) {
+ fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
+ } else {
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_pcmd, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_data, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_arb, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_intf, 0, verbose);
+ }
+
+ return fatal;
+}
+
+/*
+ * ULP TX interrupt handler.
+ */
+static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details ulptx_intr_details[] = {
+ { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds" },
+ { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds" },
+ { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds" },
+ { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds" },
+ { 0x0fffffff, "ULPTX parity error" },
+ { 0 }
+ };
+ static const struct intr_details t6_ulptx_int_cause_details[] = {
+ { PBL_BOUND_ERR_CH3_F | PBL_BOUND_ERR_CH2_F |
+ PBL_BOUND_ERR_CH1_F | PBL_BOUND_ERR_CH0_F,
+ "PBL address out of bounds" },
+ { SGE2ULP_FIFO_PERR_SET3_F | SGE2ULP_FIFO_PERR_SET2_F |
+ SGE2ULP_FIFO_PERR_SET1_F | SGE2ULP_FIFO_PERR_SET0_F,
+ "SGE2ULP fifo parity error" },
+ { CIM2ULP_FIFO_PERR_SET3_F | CIM2ULP_FIFO_PERR_SET2_F |
+ CIM2ULP_FIFO_PERR_SET1_F | CIM2ULP_FIFO_PERR_SET0_F,
+ "CIM2ULP fifo parity error" },
+ { CQE_FIFO_PERR_SET3_F | CQE_FIFO_PERR_SET2_F |
+ CQE_FIFO_PERR_SET1_F | CQE_FIFO_PERR_SET0_F,
+ "CQE fifo parity error" },
+ { PBL_FIFO_PERR_SET3_F | PBL_FIFO_PERR_SET2_F |
+ PBL_FIFO_PERR_SET1_F | PBL_FIFO_PERR_SET0_F,
+ "PBL fifo parity error" },
+ { CMD_FIFO_PERR_SET3_F | CMD_FIFO_PERR_SET2_F |
+ CMD_FIFO_PERR_SET1_F | CMD_FIFO_PERR_SET0_F,
+ "Command fifo parity error" },
+ { LSO_HDR_SRAM_PERR_SET3_F | LSO_HDR_SRAM_PERR_SET2_F |
+ LSO_HDR_SRAM_PERR_SET1_F | LSO_HDR_SRAM_PERR_SET0_F,
+ "LSO hdr parity error" },
+ { 0 }
+ };
+ struct intr_info ulptx_intr_info = {
+ .name = "ULP_TX_INT_CAUSE",
+ .cause_reg = ULP_TX_INT_CAUSE_A,
+ .enable_reg = ULP_TX_INT_ENABLE_A,
+ .fatal = 0x0fffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_1_details[] = {
+ { PBL_BOUND_ERR_CH3_F | PBL_BOUND_ERR_CH2_F |
+ PBL_BOUND_ERR_CH1_F | PBL_BOUND_ERR_CH0_F,
+ "PBL address out of bounds (configured PBL_ULIMIT/LLIMIT)" },
+ { SGE2ULP_FIFO_PERR_SET3_F | SGE2ULP_FIFO_PERR_SET2_F |
+ SGE2ULP_FIFO_PERR_SET1_F | SGE2ULP_FIFO_PERR_SET0_F,
+ "SGE2ULP FIFO parity error" },
+ { CIM2ULP_FIFO_PERR_SET3_F | CIM2ULP_FIFO_PERR_SET2_F |
+ CIM2ULP_FIFO_PERR_SET1_F | CIM2ULP_FIFO_PERR_SET0_F,
+ "CIM2ULP FIFO parity error" },
+ { CQE_FIFO_PERR_SET3_F | CQE_FIFO_PERR_SET2_F |
+ CQE_FIFO_PERR_SET1_F | CQE_FIFO_PERR_SET0_F,
+ "CQE FIFO parity error" },
+ { PBL_FIFO_PERR_SET3_F | PBL_FIFO_PERR_SET2_F |
+ PBL_FIFO_PERR_SET1_F | PBL_FIFO_PERR_SET0_F,
+ "PBL FIFO parity error" },
+ { CMD_FIFO_PERR_SET3_F | CMD_FIFO_PERR_SET2_F |
+ CMD_FIFO_PERR_SET1_F | CMD_FIFO_PERR_SET0_F,
+ "Command FIFO parity error" },
+ { LSO_HDR_SRAM_PERR_SET3_F | LSO_HDR_SRAM_PERR_SET2_F |
+ LSO_HDR_SRAM_PERR_SET1_F | LSO_HDR_SRAM_PERR_SET0_F,
+ "LSO HDR parity error" },
+ { TLS_DSGL_PARERR3_F | TLS_DSGL_PARERR2_F |
+ TLS_DSGL_PARERR1_F | TLS_DSGL_PARERR0_F,
+ "TLS Glue DSGL FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info1 = {
+ .name = "ULP_TX_INT_CAUSE_1",
+ .cause_reg = ULP_TX_INT_CAUSE_1_A,
+ .enable_reg = ULP_TX_INT_ENABLE_1_A,
+ .fatal = 0x0fffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulptx_int_cause_1_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_2_details[] = {
+ { EDMA_IN_FIFO_PERR_SET3_F | EDMA_IN_FIFO_PERR_SET2_F |
+ EDMA_IN_FIFO_PERR_SET1_F | EDMA_IN_FIFO_PERR_SET0_F,
+ "EDMA input FIFO parity error" },
+ { ALIGN_CTL_FIFO_PERR_SET3_F | ALIGN_CTL_FIFO_PERR_SET2_F |
+ ALIGN_CTL_FIFO_PERR_SET1_F | ALIGN_CTL_FIFO_PERR_SET0_F,
+ "Align control FIFO parity error" },
+ { SGE_FIFO_PERR_SET3_F | SGE_FIFO_PERR_SET2_F |
+ SGE_FIFO_PERR_SET1_F | SGE_FIFO_PERR_SET0_F,
+ "SGE FIFO parity error" },
+ { STAG_FIFO_PERR_SET3_F | STAG_FIFO_PERR_SET2_F |
+ STAG_FIFO_PERR_SET1_F | STAG_FIFO_PERR_SET0_F,
+ "STAG FIFO parity error" },
+ { MAP_FIFO_PERR_SET3_F | MAP_FIFO_PERR_SET2_F |
+ MAP_FIFO_PERR_SET1_F | MAP_FIFO_PERR_SET0_F,
+ "MAP FIFO parity error" },
+ { DMA_FIFO_PERR_SET3_F | DMA_FIFO_PERR_SET2_F |
+ DMA_FIFO_PERR_SET1_F | DMA_FIFO_PERR_SET0_F,
+ "DMA FIFO parity error" },
+ { FSO_HDR_SRAM_PERR_SET3_F | FSO_HDR_SRAM_PERR_SET2_F |
+ FSO_HDR_SRAM_PERR_SET1_F | FSO_HDR_SRAM_PERR_SET0_F,
+ "FSO HDR memory parity error" },
+ { T10_PI_SRAM_PERR_SET3_F | T10_PI_SRAM_PERR_SET2_F |
+ T10_PI_SRAM_PERR_SET1_F | T10_PI_SRAM_PERR_SET0_F,
+ "T10 PI memory parity error" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info2 = {
+ .name = "ULP_TX_INT_CAUSE_2",
+ .cause_reg = ULP_TX_INT_CAUSE_2_A,
+ .enable_reg = ULP_TX_INT_ENABLE_2_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulptx_int_cause_2_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_3_details[] = {
+ { GF_SGE_FIFO_PARERR3_F | GF_SGE_FIFO_PARERR2_F |
+ GF_SGE_FIFO_PARERR1_F | GF_SGE_FIFO_PARERR0_F,
+ "GF SGE interface FIFO parity error" },
+ { DEDUPE_SGE_FIFO_PARERR3_F | DEDUPE_SGE_FIFO_PARERR2_F |
+ DEDUPE_SGE_FIFO_PARERR1_F | DEDUPE_SGE_FIFO_PARERR0_F,
+ "DeDupe SGE interface FIFO parity error" },
+ { GF3_DSGL_FIFO_PARERR_F | GF2_DSGL_FIFO_PARERR_F |
+ GF1_DSGL_FIFO_PARERR_F | GF0_DSGL_FIFO_PARERR_F,
+ "GF DSGL FIFO parity error" },
+ { DEDUPE3_DSGL_FIFO_PARERR_F | DEDUPE2_DSGL_FIFO_PARERR_F |
+ DEDUPE1_DSGL_FIFO_PARERR_F | DEDUPE0_DSGL_FIFO_PARERR_F,
+ "DeDupe DSGL FIFO parity error" },
+ { XP10_SGE_FIFO_PARERR_F, "XP10 SGE FIFO parity error (Ch0)" },
+ { DSGL_PAR_ERR_F, "XP10 DSGL interface parity error" },
+ { CDDIP_INT_F, "XP10 decompression interrupt" },
+ { CCEIP_INT_F, "XP10 compression interrupt" },
+ { TLS_SGE_FIFO_PARERR3_F | TLS_SGE_FIFO_PARERR2_F |
+ TLS_SGE_FIFO_PARERR1_F | TLS_SGE_FIFO_PARERR0_F,
+ "TLS Glue SGE FIFO parity error" },
+ { ULP2SMARBT_RSP_PERR_F, "ULP2SMARBT response data/CTL parity error" },
+ { ULPTX2MA_RSP_PERR_F, "ULP2MA response data/CTL parity error" },
+ { PCIE2ULP_PERR3_F | PCIE2ULP_PERR2_F |
+ PCIE2ULP_PERR1_F | PCIE2ULP_PERR0_F,
+ "PCIE2ULP EDMA response parity error" },
+ { CIM2ULP_PERR_F, "CIM2ULP command parity error (all ports)" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info3 = {
+ .name = "ULP_TX_INT_CAUSE_3",
+ .cause_reg = ULP_TX_INT_CAUSE_3_A,
+ .enable_reg = ULP_TX_INT_ENABLE_3_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulptx_int_cause_3_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_4_details[] = {
+ { 0xffff0000, "DMA fifo parity error"},
+ { 0x0000ff00, "core cmd fifo lb error"},
+ { XP10_2_ULP_PERR_F, "XP10 to ULP parity error" },
+ { ULP_2_XP10_PERR_F, "ULP to XP10 parity error" },
+ { CMD_FIFO_LB1_F | CMD_FIFO_LB0_F,
+ "Command FIFO LB error" },
+ { TF_TP_PERR_F, "TF TP parity error" },
+ { TF_SGE_PERR_F, "TF SGE parity error" },
+ { TF_MEM_PERR_F, "TF memory parity error" },
+ { TF_MP_PERR_F, "TF MP parity error" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info4 = {
+ .name = "ULP_TX_INT_CAUSE_4",
+ .cause_reg = ULP_TX_INT_CAUSE_4_A,
+ .enable_reg = ULP_TX_INT_ENABLE_4_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulptx_int_cause_4_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_5_details[] = {
+ { DEDUPE_PERR3_F | DEDUPE_PERR2_F |
+ DEDUPE_PERR1_F | DEDUPE_PERR0_F,
+ "DeDupe parity error" },
+ { GF_PERR3_F | GF_PERR2_F |
+ GF_PERR1_F | GF_PERR0_F,
+ "GF parity error" },
+ { SGE2ULP_INV_PERR_F, "SGE2ULP invalid parity error" },
+ { T7_PL_BUSPERR_F, "PL bus parity error" },
+ { TLSTX2ULPTX_PERR3_F | TLSTX2ULPTX_PERR2_F |
+ TLSTX2ULPTX_PERR1_F | TLSTX2ULPTX_PERR0_F,
+ "TLS to ULP parity error" },
+ { XP10_2_ULP_PL_PERR_F, "XP10 to ULP PL parity error" },
+ { ULP_2_XP10_PL_PERR_F, "ULP to XP10 PL parity error" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info5 = {
+ .name = "ULP_TX_INT_CAUSE_5",
+ .cause_reg = ULP_TX_INT_CAUSE_5_A,
+ .enable_reg = ULP_TX_INT_ENABLE_5_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulptx_int_cause_5_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_6_details[] = {
+ { DDR_HDR_FIFO_PERR_SET3_F | DDR_HDR_FIFO_PERR_SET2_F |
+ DDR_HDR_FIFO_PERR_SET1_F | DDR_HDR_FIFO_PERR_SET0_F,
+ "DDR HDR FIFO parity error" },
+ { PRE_MP_RSP_PERR_SET3_F | PRE_MP_RSP_PERR_SET2_F |
+ PRE_MP_RSP_PERR_SET1_F | PRE_MP_RSP_PERR_SET0_F,
+ "Pre-MP response parity error" },
+ { PRE_CQE_FIFO_PERR_SET3_F | PRE_CQE_FIFO_PERR_SET2_F |
+ PRE_CQE_FIFO_PERR_SET1_F | PRE_CQE_FIFO_PERR_SET0_F,
+ "Pre-CQE FIFO parity error" },
+ { RSP_FIFO_PERR_SET_F, "Response FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info6 = {
+ .name = "ULP_TX_INT_CAUSE_6",
+ .cause_reg = ULP_TX_INT_CAUSE_6_A,
+ .enable_reg = ULP_TX_INT_ENABLE_6_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ulptx_int_cause_6_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_7_details[] = {
+ { TLS_SGE_FIFO_CORERR3_F | TLS_SGE_FIFO_CORERR2_F |
+ TLS_SGE_FIFO_CORERR1_F | TLS_SGE_FIFO_CORERR0_F,
+ "TLS SGE FIFO correctable error" },
+ { LSO_HDR_SRAM_CERR_SET3_F | LSO_HDR_SRAM_CERR_SET2_F |
+ LSO_HDR_SRAM_CERR_SET1_F | LSO_HDR_SRAM_CERR_SET0_F,
+ "LSO HDR SRAM correctable error" },
+ { CORE_CMD_FIFO_CERR_SET_CH3_LB1_F | CORE_CMD_FIFO_CERR_SET_CH2_LB1_F |
+ CORE_CMD_FIFO_CERR_SET_CH1_LB1_F | CORE_CMD_FIFO_CERR_SET_CH0_LB1_F,
+ "Core command FIFO LB1 correctable error" },
+ { CORE_CMD_FIFO_CERR_SET_CH3_LB0_F | CORE_CMD_FIFO_CERR_SET_CH2_LB0_F |
+ CORE_CMD_FIFO_CERR_SET_CH1_LB0_F | CORE_CMD_FIFO_CERR_SET_CH0_LB0_F,
+ "Core command FIFO LB0 correctable error" },
+ { CQE_FIFO_CERR_SET3_F | CQE_FIFO_CERR_SET2_F |
+ CQE_FIFO_CERR_SET1_F | CQE_FIFO_CERR_SET0_F,
+ "CQE FIFO correctable error" },
+ { PRE_CQE_FIFO_CERR_SET3_F | PRE_CQE_FIFO_CERR_SET2_F |
+ PRE_CQE_FIFO_CERR_SET1_F | PRE_CQE_FIFO_CERR_SET0_F,
+ "Pre-CQE FIFO correctable error" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info7 = {
+ .name = "ULP_TX_INT_CAUSE_7",
+ .cause_reg = ULP_TX_INT_CAUSE_7_A,
+ .enable_reg = ULP_TX_INT_ENABLE_7_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = ulptx_int_cause_7_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ulptx_int_cause_8_details[] = {
+ { MEM_RSP_FIFO_CERR_SET3_F | MEM_RSP_FIFO_CERR_SET2_F |
+ MEM_RSP_FIFO_CERR_SET1_F | MEM_RSP_FIFO_CERR_SET0_F,
+ "Memory response FIFO correctable error" },
+ { PI_SRAM_CERR_SET3_F | PI_SRAM_CERR_SET2_F |
+ PI_SRAM_CERR_SET1_F | PI_SRAM_CERR_SET0_F,
+ "PI SRAM correctable error" },
+ { PRE_MP_RSP_CERR_SET3_F | PRE_MP_RSP_CERR_SET2_F |
+ PRE_MP_RSP_CERR_SET1_F | PRE_MP_RSP_CERR_SET0_F,
+ "Pre-MP response correctable error" },
+ { DDR_HDR_FIFO_CERR_SET3_F | DDR_HDR_FIFO_CERR_SET2_F |
+ DDR_HDR_FIFO_CERR_SET1_F | DDR_HDR_FIFO_CERR_SET0_F,
+ "DDR HDR FIFO correctable error" },
+ { CMD_FIFO_CERR_SET3_F | CMD_FIFO_CERR_SET2_F |
+ CMD_FIFO_CERR_SET1_F | CMD_FIFO_CERR_SET0_F,
+ "Command FIFO correctable error" },
+ { GF_SGE_FIFO_CORERR3_F | GF_SGE_FIFO_CORERR2_F |
+ GF_SGE_FIFO_CORERR1_F | GF_SGE_FIFO_CORERR0_F,
+ "GF SGE FIFO correctable error" },
+ { DEDUPE_SGE_FIFO_CORERR3_F | DEDUPE_SGE_FIFO_CORERR2_F |
+ DEDUPE_SGE_FIFO_CORERR1_F | DEDUPE_SGE_FIFO_CORERR0_F,
+ "DeDupe SGE FIFO correctable error" },
+ { RSP_FIFO_CERR_SET_F, "Response FIFO correctable error" },
+ { 0 }
+ };
+ static const struct intr_info ulptx_intr_info8 = {
+ .name = "ULP_TX_INT_CAUSE_8",
+ .cause_reg = ULP_TX_INT_CAUSE_8_A,
+ .enable_reg = ULP_TX_INT_ENABLE_8_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = ulptx_int_cause_8_details,
+ .actions = NULL,
+ };
+
+ bool fatal = false;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) == CHELSIO_T6)
+ ulptx_intr_info.details = t6_ulptx_int_cause_details;
+ else
+ ulptx_intr_info.details = ulptx_intr_details;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info1, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info2, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info3, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info4, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info5, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info6, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info7, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info8, 0, verbose);
+ } else {
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T4)
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info2, 0, verbose);
+ }
+ return fatal;
+}
+
+static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
+{
+ int i;
+ u32 data[17];
+
+ t4_read_indirect(adap, PM_TX_DBG_CTRL_A, PM_TX_DBG_DATA_A, &data[0],
+ ARRAY_SIZE(data), PM_TX_DBG_STAT0_A);
+ for (i = 0; i < ARRAY_SIZE(data); i++) {
+ dev_alert(adap->pdev_dev, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
+ PM_TX_DBG_STAT0_A + i, data[i]);
+ }
+
+ return false;
+}
+
+static bool pm_indirect_intr_handler(struct adapter *adap,
+ const struct intr_info *ii, int pm_tx,
+ bool verbose)
+{
+ u32 enable, cause, active, fatal;
+ bool rc;
+
+ if (pm_tx) {
+ t4_read_indirect(adap, PM_TX_DBG_CTRL_A, PM_TX_DBG_DATA_A, &enable, 1,
+ ii->enable_reg);
+ t4_read_indirect(adap, PM_TX_DBG_CTRL_A, PM_TX_DBG_DATA_A, &cause, 1,
+ ii->cause_reg);
+ } else {
+ t4_read_indirect(adap, PM_RX_DBG_CTRL_A, PM_RX_DBG_DATA_A, &enable, 1,
+ ii->enable_reg);
+ t4_read_indirect(adap, PM_RX_DBG_CTRL_A, PM_RX_DBG_DATA_A, &cause, 1,
+ ii->cause_reg);
+ }
+ if (verbose && cause != 0)
+ t4_show_intr_info(adap, ii, cause, enable);
+
+ fatal = cause & ii->fatal;
+ if (ii->flags & NONFATAL_IF_DISABLED)
+ fatal &= enable;
+
+ /* Only enabled causes are reported, but the full cause register is
+ * written back below, so that a bit which is asserted while its
+ * interrupt is disabled does not stay latched.
+ */
+ active = cause & enable;
+ if (active == 0)
+ return false;
+ rc = fatal != 0;
+
+ if (pm_tx)
+ t4_write_indirect(adap, PM_TX_DBG_CTRL_A, PM_TX_DBG_DATA_A,
+ &cause, 1, ii->cause_reg);
+ else
+ t4_write_indirect(adap, PM_RX_DBG_CTRL_A, PM_RX_DBG_DATA_A,
+ &cause, 1, ii->cause_reg);
+
+ return rc;
+}
+
+/*
+ * PM TX interrupt handler.
+ */
+static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details t7_pmtx_int_cause_fields[] = {
+ { MASTER_PERR_F, "PM_TX master parity error" },
+ { T7_ZERO_C_CMD_ERROR_F, "PM_TX PCMD with zero length error" },
+ { OESPI_COR_ERR_F, " oespi FIFO Correctable Error" },
+ { ICSPI_COR_ERR_F, " icspi FIFO Correctable Error" },
+ { ICSPI_OVFL_F, " icspi FIFO overflow" },
+ { T7_PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large" },
+ { T7_PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large" },
+ { T7_PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large" },
+ { PCMD_LEN_OVFL3_F, "PMTX channel 2 pcmd too large" },
+ { T7_ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd" },
+ { 0x00f00000, "PM_TX PCMD length larger than oespi capacity" },
+ { 0x000f0000, "PM_TX icspi 2x FIFO Rx framing error" },
+ { 0x0000f000, "PM_TX icspi FIFO Tx framing error" },
+ { 0x00000f00, "PM_TX oespi FIFO Rx framing error" },
+ { 0x000000f0, "PM_TX oespi FIFO Tx framing error" },
+ { 0x0000000f, "PM_TX oespi 2x FIFO Tx framing error" },
+ { 0 }
+ };
+ static const struct intr_details pmtx_int_cause_fields[] = {
+ { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large" },
+ { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large" },
+ { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large" },
+ { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd" },
+ { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
+ { 0x00f00000, "PMTX icspi FIFO Rx framing error" },
+ { 0x000f0000, "PMTX icspi FIFO Tx framing error" },
+ { 0x0000f000, "PMTX oespi FIFO Rx framing error" },
+ { 0x00000f00, "PMTX oespi FIFO Tx framing error" },
+ { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
+ { OESPI_PAR_ERROR_F, "PMTX oespi parity error" },
+ { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error" },
+ { ICSPI_PAR_ERROR_F, "PMTX icspi parity error" },
+ { C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error" },
+ { 0 }
+ };
+ static const struct intr_action pmtx_int_cause_actions[] = {
+ { 0x7fffffff, -1, pmtx_dump_dbg_stats },
+ { 0 },
+ };
+ struct intr_info pmtx_int_cause = {
+ .name = "PM_TX_INT_CAUSE",
+ .cause_reg = PM_TX_INT_CAUSE_A,
+ .enable_reg = PM_TX_INT_ENABLE_A,
+ .fatal = 0xc1ffffff,
+ .flags = 0,
+ .skip_clear = 1,
+ .details = NULL,
+ .actions = pmtx_int_cause_actions,
+ };
+ static const struct intr_details pmtx_perr_cause_details[] = {
+ { ICSPI_OVFL_F, "icspi FIFO Overflow" },
+ { OSPI_OVERFLOW3_TX_F, " OSPI overflow on channel 3 error." },
+ { OSPI_OVERFLOW2_TX_F, " OSPI overflow on channel 2 error." },
+ { OSPI_OVERFLOW1_TX_F, " OSPI overflow on channel 1 error." },
+ { OSPI_OVERFLOW0_TX_F, " OSPI overflow on channel 0 error." },
+ { T7_BUNDLE_LEN_OVFL_EN_F, "This bit indicates bundle_len_ovfl_err." },
+ { T7_M_INTFPERREN_F, "This bit indicates Parity error from MA interfaces." },
+ { T7_1_SDC_ERR_F,
+ "SDC Error reported by Check PCMD which carries CRC16 from TP-CSide." },
+ { MC_WCNT_FIFO_PERR_F, "MC Interface Write count FIFO Parity error" },
+ { MC_WDATA_FIFO_PERR_F, "MC Interface Write Data FIFO Parity error" },
+ { MC_RCNT_FIFO_PERR_F, "MC Interface Read count FIFO Parity error" },
+ { MC_RDATA_FIFO_PERR_F, "MC Interface Read Data FIFO Parity error" },
+ { TOKEN_PAR_ERROR_F, "c_pcmd, Token FIFO par error" },
+ { BUNDLE_LEN_PAR_ERROR_F, "oespi par error" },
+ { OESPI_PAR_ERROR_F, "oespi par error" },
+ { DB_OPTIONS_PAR_ERROR_F, "db_options par error" },
+ { ICSPI_PAR_ERROR_F, "icspi par error" },
+ { C_PCMD_TOKEN_PAR_ERROR_F, "c_pcmd par error" },
+ { 0 }
+ };
+ static const struct intr_info pmtx_perr_cause = {
+ .name = "PM_TX_PERR_CAUSE",
+ .cause_reg = PM_TX_PERR_CAUSE_A,
+ .enable_reg = PM_TX_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = 0,
+ .details = pmtx_perr_cause_details,
+ .actions = NULL,
+ };
+
+ bool fatal;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ pmtx_int_cause.details = t7_pmtx_int_cause_fields;
+ else
+ pmtx_int_cause.details = pmtx_int_cause_fields;
+
+ fatal = t4_handle_intr(adap, &pmtx_int_cause, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ fatal |= pm_indirect_intr_handler(adap, &pmtx_perr_cause, 1, verbose);
+
+ clear_int_cause_reg(adap, &pmtx_int_cause);
+ return fatal;
+}
+
+/*
+ * PM RX interrupt handler.
+ */
+static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details t7_pmrx_int_cause_fields[] = {
+ { MASTER_PERR_F, "PM_RX master parity error" },
+ { 0x18000000, "PMRX ospi overflow" },
+ { BUNDLE_LEN_OVFL_F, "PMRX bundle len FIFO overflow" },
+ { SDC_ERR_F, "PMRX SDC error" },
+ { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd" },
+ { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
+ { 0x0003c000, "PMRX iespi Rx framing error" },
+ { 0x00003c00, "PMRX iespi Tx framing error" },
+ { 0x00000300, "PMRX ocspi Rx framing error" },
+ { 0x000000c0, "PMRX ocspi Tx framing error" },
+ { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
+ { 0 }
+ };
+ static const struct intr_details pmrx_int_cause_fields[] = {
+ /* T6+ */
+ { 0x18000000, "PMRX ospi overflow" },
+ { MA_INTF_SDC_ERR_F, "PMRX MA interface SDC parity error" },
+ { BUNDLE_LEN_PARERR_F, "PMRX bundle len FIFO parity error" },
+ { BUNDLE_LEN_OVFL_F, "PMRX bundle len FIFO overflow" },
+ { SDC_ERR_F, "PMRX SDC error" },
+
+ /* T4+ */
+ { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd" },
+ { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
+ { 0x0003c000, "PMRX iespi Rx framing error" },
+ { 0x00003c00, "PMRX iespi Tx framing error" },
+ { 0x00000300, "PMRX ocspi Rx framing error" },
+ { 0x000000c0, "PMRX ocspi Tx framing error" },
+ { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
+ { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error" },
+ { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error" },
+ { IESPI_PAR_ERROR_F, "PMRX iespi parity error" },
+ { E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error"},
+ { 0 }
+ };
+ struct intr_info pmrx_int_cause = {
+ .name = "PM_RX_INT_CAUSE",
+ .cause_reg = PM_RX_INT_CAUSE_A,
+ .enable_reg = PM_RX_INT_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .skip_clear = 1,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details pm_rx_int_cause_2_details[] = {
+ { CACHE_SRAM_ODD_CERR_F, "Cache Data Odd SRAM Correctable Error" },
+ { CACHE_SRAM_EVEN_CERR_F, "Cache Data Even SRAM Correctable Error" },
+ { CACHE_LRU_LEFT_CERR_F, "Cache LRU Left SRAM Correctable Error" },
+ { CACHE_LRU_RIGHT_CERR_F, "Cache LRU Right SRAM Correctable Error" },
+ { CACHE_ISLAND_CERR_F, "Cache Island SRAM Correctable Error" },
+ { OCSPI_CERR_F, "ocspi FIFO Correctable Error" },
+ { IESPI_CERR_F, "iespi FIFO Correctable Error" },
+ { OCSPI2_RX_FRAMING_ERROR_F, "ocspi FIFO channel 2 Rx/wr framing error" },
+ { OCSPI3_RX_FRAMING_ERROR_F, "ocspi FIFO channel 3 Rx/wr framing error" },
+ { OCSPI2_TX_FRAMING_ERROR_F, "ocspi FIFO channel 2 Tx/rd framing error" },
+ { OCSPI3_TX_FRAMING_ERROR_F, "ocspi FIFO channel 3 Tx/rd framing error" },
+ { OCSPI2_OFIFO2X_TX_FRAMING_ERROR_F, "ocspi 2x FIFO 2 Tx/rd framing error" },
+ { OCSPI3_OFIFO2X_TX_FRAMING_ERROR_F, "ocspi 2x FIFO 3 Tx/rd framing error" },
+ { 0 }
+ };
+ static const struct intr_info pmrx_int_cause2 = {
+ .name = "PM_RX_INT_CAUSE_2",
+ .cause_reg = PM_RX_INT_CAUSE_2_A,
+ .enable_reg = PM_RX_INT_ENABLE_2_A,
+ .fatal = 0x0000003f,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = pm_rx_int_cause_2_details,
+ .actions = NULL,
+ };
+ static const struct intr_details pm_rx_perr_cause_details[] = {
+ { T7_SDC_ERR_F, "SDC error. CRC provided by TP and PM didn't match." },
+ { T7_MA_INTF_SDC_ERR_F, "MA intf SDC perr" },
+ { E_PCMD_PERR_F, "ulp_rx 2 pm_rx PCMD interface parity error." },
+ { CACHE_RSP_DFIFO_PERR_F, "Cache Response Data FIFO Parity error" },
+ { CACHE_SRAM_ODD_PERR_F, "Cache Odd SRAM error" },
+ { CACHE_SRAM_EVEN_PERR_F, "Cache Even SRAM error" },
+ { CACHE_RSVD_PERR_F, "Cache Reserved Parity error" },
+ { CACHE_LRU_LEFT_PERR_F, "Cache LRU Left SRAM error" },
+ { CACHE_LRU_RIGHT_PERR_F, "Cache LRU Rigth SRAM error" },
+ { CACHE_RSP_CMD_PERR_F, "Cache Response Command FIFO error" },
+ { CACHE_SRAM_CMD_PERR_F, "Cache SRAM Command FIFO error" },
+ { CACHE_MA_CMD_PERR_F, "Cache MA Command FIFO error" },
+ { CACHE_TCAM_PERR_F, "Cache TCAM Parity error" },
+ { CACHE_ISLAND_PERR_F, "Cache island SRAM Parity error" },
+ { MC_WCNT_FIFO_PERR_F, "MC Interface Write count FIFO Parity error" },
+ { MC_WDATA_FIFO_PERR_F, "MC Interface Write Data FIFO Parity error" },
+ { MC_RCNT_FIFO_PERR_F, "MC Interface Read count FIFO Parity error" },
+ { MC_RDATA_FIFO_PERR_F, "MC Interface Read Data FIFO Parity error" },
+ { TOKEN_FIFO_PERR_F, "Token FIFO Parity error" },
+ { T7_BUNDLE_LEN_PARERR_F, "Bundle len fifo had parity error." },
+ { OCSPI_PAR_ERROR_F, "ocspi par error vector" },
+ { DB_OPTIONS_PAR_ERROR_F, "db_options par error" },
+ { IESPI_PAR_ERROR_F, "iespi par error" },
+ { E_PCMD_PAR_ERROR_F, "e_pcmd par error" },
+ { 0 }
+ };
+ static const struct intr_info pmrx_perr_cause = {
+ .name = "PM_RX_PERR_CAUSE",
+ .cause_reg = PM_RX_PERR_CAUSE_A,
+ .enable_reg = PM_RX_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = pm_rx_perr_cause_details,
+ .actions = NULL,
+ };
+
+ bool fatal = false;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ pmrx_int_cause.details = t7_pmrx_int_cause_fields;
+ fatal = t4_handle_intr(adap, &pmrx_int_cause, 0, verbose);
+ fatal |= pm_indirect_intr_handler(adap, &pmrx_int_cause2, 0, verbose);
+ fatal |= pm_indirect_intr_handler(adap, &pmrx_perr_cause, 0, verbose);
+ } else {
+ pmrx_int_cause.details = pmrx_int_cause_fields;
+ fatal = t4_handle_intr(adap, &pmrx_int_cause, 0, verbose);
+ }
+
+ clear_int_cause_reg(adap, &pmrx_int_cause);
+ return fatal;
+}
+
+/*
+ * CPL switch interrupt handler.
+ */
+static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details cplsw_int_cause_fields[] = {
+ /* t7+ */
+ { PERR_CPL_128TO128_3_F, "CPLSW 128TO128 FIFO3 parity error" },
+ { PERR_CPL_128TO128_2_F, "CPLSW 128TO128 FIFO2 parity error" },
+ /* T5+ */
+ { PERR_CPL_128TO128_1_F, "CPLSW 128TO128 FIFO1 parity error" },
+ { PERR_CPL_128TO128_0_F, "CPLSW 128TO128 FIFO0 parity error" },
+
+ /* T4+ */
+ { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error" },
+ { CIM_OVFL_ERROR_F, "CPLSW CIM overflow" },
+ { TP_FRAMING_ERROR_F, "CPLSW TP framing error" },
+ { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error" },
+ { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error" },
+ { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error" },
+ { 0 }
+ };
+ static const struct intr_info cplsw_int_cause = {
+ .name = "CPL_INTR_CAUSE",
+ .cause_reg = CPL_INTR_CAUSE_A,
+ .enable_reg = CPL_INTR_ENABLE_A,
+ .fatal = CIM_OP_MAP_PERR_F | TP_FRAMING_ERROR_F | SGE_FRAMING_ERROR_F |
+ CIM_FRAMING_ERROR_F | ZERO_SWITCH_ERROR_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = cplsw_int_cause_fields,
+ .actions = NULL,
+ };
+
+ return t4_handle_intr(adap, &cplsw_int_cause, 0, verbose);
+}
+
+#define T4_LE_FATAL_MASK (PARITYERR_F | UNKNOWNCMD_F | REQQPARERR_F)
+#define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | VFPARERR_F)
+#define T6_LE_PERRCRC_MASK (PIPELINEERR_F | CLIPTCAMACCFAIL_F | \
+ SRVSRAMACCFAIL_F | CLCAMCRCPARERR_F | \
+ CLCAMINTPERR_F | SSRAMINTPERR_F | \
+ SRVSRAMPERR_F | VFSRAMPERR_F | \
+ TCAMINTPERR_F | TCAMCRCERR_F | \
+ HASHTBLMEMACCERR_F | MAIFWRINTPERR_F | \
+ HASHTBLMEMCRCERR_F)
+#define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | T6_UNKNOWNCMD_F | \
+ TCAMACCFAIL_F | HASHTBLACCFAIL_F | \
+ CMDTIDERR_F | CMDPRSRINTERR_F | \
+ TOTCNTERR_F | CLCAMFIFOERR_F | CLIPSUBERR_F)
+#define T7_LE_FATAL_MASK (T6_LE_FATAL_MASK | CACHESRAMPERR_F | CACHEINTPERR_F)
+
+/*
+ * LE interrupt handler.
+ */
+static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details le_intr_details[] = {
+ { REQQPARERR_F, "LE request queue parity error" },
+ { UNKNOWNCMD_F, "LE unknown command" },
+ { ACTRGNFULL_F, "LE active region full" },
+ { PARITYERR_F, "LE parity error" },
+ { LIPMISS_F, "LE LIP miss" },
+ { LIP0_F, "LE 0 LIP error" },
+ { 0 }
+ };
+ static const struct intr_details t6_le_intr_details[] = {
+ { CACHEINTPERR_F, "Parity error in cache module" },
+ { CACHESRAMPERR_F, "Parity error in data sram " },
+ { CLIPSUBERR_F, "LE CLIP CAM reverse substitution error" },
+ { CLCAMFIFOERR_F, "LE CLIP CAM internal FIFO error" },
+ { CTCAMINVLDENT_F, "Invalid IPv6 CLIP TCAM entry" },
+ { TCAMINVLDENT_F, "Invalid IPv6 TCAM entry" },
+ { TOTCNTERR_F, "LE total active < TCAM count" },
+ { CMDPRSRINTERR_F, "LE internal error in parser" },
+ { CMDTIDERR_F, "Incorrect tid in LE command" },
+ { T6_ACTRGNFULL_F, "LE active region full" },
+ { T6_ACTCNTIPV6TZERO_F, "LE IPv6 active open TCAM counter -ve" },
+ { T6_ACTCNTIPV4TZERO_F, "LE IPv4 active open TCAM counter -ve" },
+ { T6_ACTCNTIPV6ZERO_F, "LE IPv6 active open counter -ve" },
+ { T6_ACTCNTIPV4ZERO_F, "LE IPv4 active open counter -ve" },
+ { HASHTBLACCFAIL_F, "Hash table read error (proto conflict)" },
+ { TCAMACCFAIL_F, "LE TCAM access failure" },
+ { T6_UNKNOWNCMD_F, "LE unknown command" },
+ { T6_LIP0_F, "LE found 0 LIP during CLIP substitution" },
+ { T6_LIPMISS_F, "LE CLIP lookup miss" },
+ { T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
+ { 0 }
+ };
+ struct intr_info le_intr_info = {
+ .name = "LE_DB_INT_CAUSE",
+ .cause_reg = LE_DB_INT_CAUSE_A,
+ .enable_reg = LE_DB_INT_ENABLE_A,
+ .fatal = 0xf801fff9,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) {
+ le_intr_info.details = le_intr_details;
+ le_intr_info.fatal = T5_LE_FATAL_MASK;
+ } else {
+ le_intr_info.details = t6_le_intr_details;
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7)
+ le_intr_info.fatal = T6_LE_FATAL_MASK;
+ else
+ le_intr_info.fatal = T7_LE_FATAL_MASK;
+ }
+
+ return t4_handle_intr(adap, &le_intr_info, 0, verbose);
+}
+
+/*
+ * MPS interrupt handler.
+ */
+static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details mps_rx_perr_intr_details[] = {
+ { 0xffffffff, "MPS Rx parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_rx_perr_intr_info = {
+ .name = "MPS_RX_PERR_INT_CAUSE",
+ .cause_reg = MPS_RX_PERR_INT_CAUSE_A,
+ .enable_reg = MPS_RX_PERR_INT_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mps_rx_perr_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_rx_func_intr_details[] = {
+ { MTU_ERR3_F, "MTU error interrupt enable bit for loopback group 3" },
+ { MTU_ERR2_F, "MTU error interrupt enable bit for loopback group 2" },
+ { MTU_ERR1_F, "MTU error interrupt enable bit for loopback group 1" },
+ { MTU_ERR0_F, "MTU error interrupt enable bit for loopback group 0" },
+ { DBG_LEN_ERR_F, "Oring of len error in traffic transfer b/w internal modules" },
+ { DBG_SPI_ERR_F, "Oring of spi error in traffic transfer b/w internal modules" },
+ { DBG_SE_CNT_ERR_F, "Oring of se cnt error in traffic transfer" },
+ { DBG_SPI_LEN_SE_CNT_ERR_F, "Oring of all se_cnt|len|spi errors" },
+ { 0 }
+ };
+ static const struct intr_info mps_rx_func_intr_info = {
+ .name = "MPS_RX_FUNC_INT_CAUSE",
+ .cause_reg = MPS_RX_FUNC_INT_CAUSE_A,
+ .enable_reg = MPS_RX_FUNC_INT_ENABLE_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = mps_rx_func_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mpsrx_int_cause_2_details[] = {
+ { CRYPTO2MPS_RX0_PERR_F | CRYPTO2MPS_RX1_PERR_F |
+ CRYPTO2MPS_RX2_PERR_F | CRYPTO2MPS_RX3_PERR_F,
+ "Crypto to MPS RX interface parity error" },
+ { INIC2MPS_TX1_PERR_F | INIC2MPS_TX0_PERR_F,
+ "INIC to MPS TX interface parity error" },
+ { XGMAC2MPS_RX1_PERR_F | XGMAC2MPS_RX0_PERR_F,
+ "XGMAC to MPS RX interface parity error" },
+ { RX_FINAL_TF_FIFO_PERR_F,
+ "Final RX token FIFO output parity error" },
+ { MPS_DWRR_FIFO_PERR_F,
+ "MPS DWRR MTU FIFO parity error" },
+ { MAC_TF_FIFO_PERR_F,
+ "MAC token FIFO parity error" },
+ { MAC2MPS_PT3_PERR_F | MAC2MPS_PT2_PERR_F |
+ MAC2MPS_PT1_PERR_F | MAC2MPS_PT0_PERR_F,
+ "MAC to MPS interface parity error" },
+ { TP_LPBK_FIFO_PERR_F, "TP loopback FIFO parity error" },
+ { TP_LPBK_TF_PERR_F, "Loopback token FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_rx_perr_intr_info2 = {
+ .name = "MPS_RX_PERR_INT_CAUSE2",
+ .cause_reg = MPS_RX_PERR_INT_CAUSE2_A,
+ .enable_reg = MPS_RX_PERR_INT_ENABLE2_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mpsrx_int_cause_2_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mpsrx_int_cause_3_details[] = {
+ { FIFO_REPL_CH3_CERR_F | FIFO_REPL_CH2_CERR_F |
+ FIFO_REPL_CH1_CERR_F | FIFO_REPL_CH0_CERR_F,
+ "Replication FIFO ECC error" },
+ { VLAN_FILTER_RAM_CERR_F, "VLAN filter SRAM ECC error" },
+ { MPS_RX_TD_STAT_FIFO_PERR_CH3_F | MPS_RX_TD_STAT_FIFO_PERR_CH2_F |
+ MPS_RX_TD_STAT_FIFO_PERR_CH1_F | MPS_RX_TD_STAT_FIFO_PERR_CH0_F,
+ "MPS RX TD status descriptor FIFO parity error" },
+ { RPLCT_HDR_FIFO_IN_PERR_CH3_F | RPLCT_HDR_FIFO_IN_PERR_CH2_F |
+ RPLCT_HDR_FIFO_IN_PERR_CH1_F | RPLCT_HDR_FIFO_IN_PERR_CH0_F,
+ "MPS RX replication header input FIFO parity error" },
+ { ID_FIFO_IN_PERR_CH3_F | ID_FIFO_IN_PERR_CH2_F |
+ ID_FIFO_IN_PERR_CH1_F | ID_FIFO_IN_PERR_CH0_F,
+ "MPS RX replication ID input FIFO parity error" },
+ { DESC_HDR2_PERR_CH3_F | DESC_HDR2_PERR_CH2_F |
+ DESC_HDR2_PERR_CH1_F | DESC_HDR2_PERR_CH0_F,
+ "MPS RX replication descriptor/header2 FIFO parity error" },
+ { FIFO_REPL_PERR_CH3_F | FIFO_REPL_PERR_CH2_F |
+ FIFO_REPL_PERR_CH1_F | FIFO_REPL_PERR_CH0_F,
+ "Replication FIFO parity error" },
+ { MPS_RX_TD_PERR_CH3_F | MPS_RX_TD_PERR_CH2_F |
+ MPS_RX_TD_PERR_CH1_F | MPS_RX_TD_PERR_CH0_F,
+ "MPS RX TD input FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_rx_perr_intr_info3 = {
+ .name = "MPS_RX_PERR_INT_CAUSE3",
+ .cause_reg = MPS_RX_PERR_INT_CAUSE3_A,
+ .enable_reg = MPS_RX_PERR_INT_ENABLE3_A,
+ .fatal = 0x00ffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mpsrx_int_cause_3_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mpsrx_int_cause_4_details[] = {
+ { VNI_MULTICAST_FIFO_ECC_ERR_CH3_F | VNI_MULTICAST_FIFO_ECC_ERR_CH2_F,
+ "RX out VNI multicast SRAM ECC error" },
+ { HASH_SRAM_CLS_ENG1_F | HASH_SRAM_CLS_ENG0_F,
+ "Classification engine hash SRAM ECC error" },
+ { CLS_TCAM_SRAM_CLS_ENG1_F | CLS_TCAM_SRAM_CLS_ENG0_F,
+ "Classification engine TCAM SRAM ECC error" },
+ { CLS_TCAM_CRC_SRAM_CLS_ENG1_F | CLS_TCAM_CRC_SRAM_CLS_ENG0_F,
+ "Classification engine TCAM CRC SRAM ECC error" },
+ { DWRR_CH_FIFO_ECC_ERR_F, "DWRR output FIFO ECC error" },
+ { MAC_RX_FIFO_ECC_ERR_F, "MAC RX FIFO ECC error" },
+ { LPBK_RX_FIFO_ECC_ERR_F, "Loopback RX FIFO ECC error" },
+ { CRS_DATA_STORE_N_FWD_CH3_F | CRS_DATA_STORE_N_FWD_CH2_F |
+ CRS_DATA_STORE_N_FWD_CH1_F | CRS_DATA_STORE_N_FWD_CH0_F,
+ "CRS store and forward FIFO ECC error" },
+ { TRACE_FWD_FIFO_CERR_CH3_F | TRACE_FWD_FIFO_CERR_CH2_F |
+ TRACE_FWD_FIFO_CERR_CH1_F | TRACE_FWD_FIFO_CERR_CH0_F,
+ "Trace packet forward FIFO ECC error" },
+ { TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3_F | TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2_F |
+ TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1_F | TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0_F,
+ "Transparent encap forward FIFO ECC error" },
+ { PTP_TRACE_FWD_FIFO_CERR_CH3_F | PTP_TRACE_FWD_FIFO_CERR_CH2_F |
+ PTP_TRACE_FWD_FIFO_CERR_CH1_F | PTP_TRACE_FWD_FIFO_CERR_CH0_F,
+ "PTP packet forward FIFO ECC error" },
+ { 0 }
+ };
+ static const struct intr_info mps_rx_perr_intr_info4 = {
+ .name = "MPS_RX_PERR_INT_CAUSE4",
+ .cause_reg = MPS_RX_PERR_INT_CAUSE4_A,
+ .enable_reg = MPS_RX_PERR_INT_ENABLE4_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = mpsrx_int_cause_4_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mpsrx_int_cause_5_details[] = {
+ { MPS2CRYP_RX_FIFO3_PERR_F | MPS2CRYP_RX_FIFO2_PERR_F |
+ MPS2CRYP_RX_FIFO1_PERR_F | MPS2CRYP_RX_FIFO0_PERR_F,
+ "MPS to Crypto RX interface FIFO parity error" },
+ { VNI_MULTICAST_SRAM2_PERR_F | VNI_MULTICAST_SRAM1_PERR_F |
+ VNI_MULTICAST_SRAM0_PERR_F,
+ "VNI multicast SRAM parity error" },
+ { MAC_MULTICAST_SRAM4_PERR_F | MAC_MULTICAST_SRAM3_PERR_F |
+ MAC_MULTICAST_SRAM2_PERR_F | MAC_MULTICAST_SRAM1_PERR_F |
+ MAC_MULTICAST_SRAM0_PERR_F,
+ "MAC multicast SRAM parity error" },
+ { MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_F | MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_F |
+ MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_F | MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_F,
+ "IPsec header update storing FIFO parity error" },
+ { MEM_WRAP_CR2MPS_RX_FIFO3_PERR_F | MEM_WRAP_CR2MPS_RX_FIFO2_PERR_F |
+ MEM_WRAP_CR2MPS_RX_FIFO1_PERR_F | MEM_WRAP_CR2MPS_RX_FIFO0_PERR_F,
+ "IPsec storing FIFO parity error" },
+ { MEM_WRAP_NON_IPSEC_FIFO3_PERR_F | MEM_WRAP_NON_IPSEC_FIFO2_PERR_F |
+ MEM_WRAP_NON_IPSEC_FIFO1_PERR_F | MEM_WRAP_NON_IPSEC_FIFO0_PERR_F,
+ "Non-IPsec storing FIFO parity error" },
+ { MEM_WRAP_TP_DB_REQ_FIFO3_PERR_F | MEM_WRAP_TP_DB_REQ_FIFO2_PERR_F |
+ MEM_WRAP_TP_DB_REQ_FIFO1_PERR_F | MEM_WRAP_TP_DB_REQ_FIFO0_PERR_F,
+ "TP DB request storing FIFO parity error" },
+ { MEM_WRAP_CNTRL_FIFO3_PERR_F | MEM_WRAP_CNTRL_FIFO2_PERR_F |
+ MEM_WRAP_CNTRL_FIFO1_PERR_F | MEM_WRAP_CNTRL_FIFO0_PERR_F,
+ "Header flit storing FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_rx_perr_intr_info5 = {
+ .name = "MPS_RX_PERR_INT_CAUSE5",
+ .cause_reg = MPS_RX_PERR_INT_CAUSE5_A,
+ .enable_reg = MPS_RX_PERR_INT_ENABLE5_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mpsrx_int_cause_5_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mpsrx_int_cause_6_details[] = {
+ { T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR_F | T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR_F |
+ T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR_F | T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR_F,
+ "IPsec header update storing FIFO parity error" },
+ { MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR_F | MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR_F |
+ MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR_F | MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR_F,
+ "IPsec updated header only storing FIFO parity error" },
+ { MEM_WRAP_CR2MPS_RX_FIFO3_PERR_F | MEM_WRAP_CR2MPS_RX_FIFO2_PERR_F |
+ MEM_WRAP_CR2MPS_RX_FIFO1_PERR_F | MEM_WRAP_CR2MPS_RX_FIFO0_PERR_F,
+ "IPsec storing FIFO parity error" },
+ { MEM_WRAP_NON_IPSEC_FIFO3_PERR_F | MEM_WRAP_NON_IPSEC_FIFO2_PERR_F |
+ MEM_WRAP_NON_IPSEC_FIFO1_PERR_F | MEM_WRAP_NON_IPSEC_FIFO0_PERR_F,
+ "Non-IPsec storing FIFO parity error" },
+ { MEM_WRAP_TP_DB_REQ_FIFO3_PERR_F | MEM_WRAP_TP_DB_REQ_FIFO2_PERR_F |
+ MEM_WRAP_TP_DB_REQ_FIFO1_PERR_F | MEM_WRAP_TP_DB_REQ_FIFO0_PERR_F,
+ "TP DB request storing FIFO parity error" },
+ { MEM_WRAP_CNTRL_FIFO3_PERR_F | MEM_WRAP_CNTRL_FIFO2_PERR_F |
+ MEM_WRAP_CNTRL_FIFO1_PERR_F | MEM_WRAP_CNTRL_FIFO0_PERR_F,
+ "Header flit storing FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_rx_perr_intr_info6 = {
+ .name = "MPS_RX_PERR_INT_CAUSE6",
+ .cause_reg = MPS_RX_PERR_INT_CAUSE6_A,
+ .enable_reg = MPS_RX_PERR_INT_ENABLE6_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mpsrx_int_cause_6_details,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_mpstx_int_cause_details[] = {
+ { T7_PORTERR_F, "Tx received a frame for TP destined to a disable port" },
+ { T7_FRMERR_F, "Framing error in received Data from TP or Data to MAC" },
+ { T7_SECNTERR_F, "SOP-EOP count error in received Data from TP or Data to MAC" },
+ { T7_BUBBLE_F, "Valid is deasserted between SOP and EOP" },
+ { TX_TF_FIFO_PERR_F, "Parity error of TX token fifo" },
+ { TX_FIFO_PERR_F, "Parity error of TX MPS2MAC underrun fifo" },
+ { 0x0003c000, "Parity error of fifo storing non-ipsec +1 flit ipsec pkt" },
+ { 0x00003fc0, "Interface parity error on TP/Crypto to MPS TX" },
+ { NCSI2MPS_F, "interface Parity Error on ncsi2mps_tx_ch3" },
+ { NCSIFIFO_F, "Parity Error in mps_tx_arbiter input FIFO (from NCSI)" },
+ { 0x0000000f, "Parity Error in mps_tx_arbiter input FIFO (from TP)" },
+ { 0 }
+ };
+ static const struct intr_details mps_tx_intr_details[] = {
+ { PORTERR_F, "MPS Tx destination port is disabled" },
+ { FRMERR_F, "MPS Tx framing error" },
+ { SECNTERR_F, "MPS Tx SOP/EOP error" },
+ { BUBBLE_F, "MPS Tx underflow" },
+ { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error" },
+ { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error" },
+ { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error" },
+ { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error" },
+ { 0 }
+ };
+ struct intr_info mps_tx_intr_info = {
+ .name = "MPS_TX_INT_CAUSE",
+ .cause_reg = MPS_TX_INT_CAUSE_A,
+ .enable_reg = MPS_TX_INT_ENABLE_A,
+ .fatal = 0x0fffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details mpstx_int_cause_2_details[] = {
+ { TX_FIFO_PERR_F, "ECC error of TX MPS2MAC underrun fifo" },
+ { 0x0000000f, "ECC error of fifo storing non-ipsec +1 flit ipsec pkt" },
{ 0 }
};
- static const struct intr_info pcie_port_intr_info[] = {
- { TPCP_F, "TXPC array parity error", -1, 1 },
- { TNPP_F, "TXNP array parity error", -1, 1 },
- { TFTP_F, "TXFT array parity error", -1, 1 },
- { TCAP_F, "TXCA array parity error", -1, 1 },
- { TCIP_F, "TXCIF array parity error", -1, 1 },
- { RCAP_F, "RXCA array parity error", -1, 1 },
- { OTDD_F, "outbound request TLP discarded", -1, 1 },
- { RDPE_F, "Rx data parity error", -1, 1 },
- { TDUE_F, "Tx uncorrectable data error", -1, 1 },
+ static const struct intr_info mps_tx_intr_info2 = {
+ .name = "MPS_TX_INT2_CAUSE",
+ .cause_reg = MPS_TX_INT2_CAUSE_A,
+ .enable_reg = MPS_TX_INT2_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mpstx_int_cause_2_details,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_tx_intr_info3 = {
+ .name = "MPS_TX_INT3_CAUSE",
+ .cause_reg = MPS_TX_INT3_CAUSE_A,
+ .enable_reg = MPS_TX_INT3_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_tx_intr_info4 = {
+ .name = "MPS_TX_INT4_CAUSE",
+ .cause_reg = MPS_TX_INT4_CAUSE_A,
+ .enable_reg = MPS_TX_INT4_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_trc_intr_details[] = {
+ { MISCPERR_F, "MPS TRC misc parity error" },
+ { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error" },
+ { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error" },
{ 0 }
};
- static const struct intr_info pcie_intr_info[] = {
- { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
- { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
- { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
- { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
- { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
- { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
- { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
- { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
- { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
- { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
- { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
- { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
- { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
- { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
- { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
- { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
- { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
- { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
- { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
- { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
- { FIDPERR_F, "PCI FID parity error", -1, 1 },
- { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
- { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
- { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
- { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
- { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
- { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
- { PCIESINT_F, "PCI core secondary fault", -1, 1 },
- { PCIEPINT_F, "PCI core primary fault", -1, 1 },
- { UNXSPLCPLERR_F, "PCI unexpected split completion error",
- -1, 0 },
+ static const struct intr_info mps_trc_intr_info = {
+ .name = "MPS_TRC_INT_CAUSE",
+ .cause_reg = MPS_TRC_INT_CAUSE_A,
+ .enable_reg = MPS_TRC_INT_ENABLE_A,
+ .fatal = MISCPERR_F | PKTFIFO_V(PKTFIFO_M) | FILTMEM_V(FILTMEM_M),
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mps_trc_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_mps_trc_intr_details[] = {
+ { T7_TRCPLERRENB_F, "TRC PL error" },
+ { T7_MISCPERR_F, "TRC header register parity error" },
+ { 0x0000ff00, "TRC packet FIFO parity error" },
+ { 0x000000ff, "TRC filter memory parity error" },
{ 0 }
};
-
- static struct intr_info t5_pcie_intr_info[] = {
- { MSTGRPPERR_F, "Master Response Read Queue parity error",
- -1, 1 },
- { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
- { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
- { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
- { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
- { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
- { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
- { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
- -1, 1 },
- { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
- -1, 1 },
- { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
- { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
- { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
- { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
- { DREQWRPERR_F, "PCI DMA channel write request parity error",
- -1, 1 },
- { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
- { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
- { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
- { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
- { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
- { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
- { FIDPERR_F, "PCI FID parity error", -1, 1 },
- { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
- { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
- { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
- { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
- -1, 1 },
- { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
- -1, 1 },
- { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
- { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
- { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
- { READRSPERR_F, "Outbound read error", -1, 0 },
+ static const struct intr_info t7_mps_trc_intr_info = {
+ .name = "MPS_TRC_INT_CAUSE",
+ .cause_reg = T7_MPS_TRC_INT_CAUSE_A,
+ .enable_reg = T7_MPS_TRC_INT_ENABLE_A,
+ .fatal = T7_TRCPLERRENB_F | T7_MISCPERR_F | PKTFIFO_V(PKTFIFO_M) |
+ FILTMEM_V(FILTMEM_M),
+ .flags = NONFATAL_IF_DISABLED,
+ .details = t7_mps_trc_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_trc_int_cause2_details[] = {
+ { 0x0001e000, "TRC Tx2Rx down-converter correctable error" },
+ { 0x00001800, "TRC MPS2MAC down-converter correctable error" },
+ { 0x00000600, "TRC MAC2MPS down-converter correctable error" },
+ { 0x000001e0, "TRC Tx2Rx down-converter parity error" },
+ { 0x00000018, "TRC MAC2MPS down-converter parity error" },
+ { 0x00000006, "TRC MPS2MAC down-converter parity error" },
+ { 0 }
+ };
+ static const struct intr_info t7_mps_trc_intr_info2 = {
+ .name = "MPS_TRC_INT_CAUSE2",
+ .cause_reg = MPS_TRC_INT_CAUSE2_A,
+ .enable_reg = MPS_TRC_INT_ENABLE2_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = t7_trc_int_cause2_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_stat_intr_details[] = {
+ { PLREADSYNCERR_F, "MPS pl read sync error" },
+ { 0 }
+ };
+ static const struct intr_info mps_stat_intr_info = {
+ .name = "MPS_STAT_INT_CAUSE",
+ .cause_reg = MPS_STAT_INT_CAUSE_A,
+ .enable_reg = MPS_STAT_INT_ENABLE_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = mps_stat_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_stat_sram_intr_details[] = {
+ { 0xffffffff, "MPS statistics SRAM parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_stat_sram_intr_info = {
+ .name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
+ .cause_reg = MPS_STAT_PERR_INT_CAUSE_SRAM_A,
+ .enable_reg = MPS_STAT_PERR_INT_ENABLE_SRAM_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mps_stat_sram_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_stat_tx_intr_details[] = {
+ { 0xffffff, "MPS statistics Tx FIFO parity error" },
{ 0 }
};
+ static const struct intr_info mps_stat_tx_intr_info = {
+ .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
+ .cause_reg = MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
+ .enable_reg = MPS_STAT_PERR_INT_ENABLE_TX_FIFO_A,
+ .fatal = 0xffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mps_stat_tx_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_stat_rx_intr_details[] = {
+ { 0xffffff, "MPS statistics Rx FIFO parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_stat_rx_intr_info = {
+ .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
+ .cause_reg = MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
+ .enable_reg = MPS_STAT_PERR_INT_ENABLE_RX_FIFO_A,
+ .fatal = 0xffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mps_stat_rx_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_cls_intr_details[] = {
+ { T7_PLERRENB_F, "PL error"},
+ { CIM2MPS_INTF_PAR_F, "cim2mps interface parity"},
+ { TCAM_CRC_SRAM_F, "tcam crc sram parity error"},
+ { HASHSRAM_F, "MPS hash SRAM parity error" },
+ { MATCHTCAM_F, "MPS match TCAM parity error" },
+ { MATCHSRAM_F, "MPS match SRAM parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_cls_intr_info = {
+ .name = "MPS_CLS_INT_CAUSE",
+ .cause_reg = MPS_CLS_INT_CAUSE_A,
+ .enable_reg = MPS_CLS_INT_ENABLE_A,
+ .fatal = MATCHSRAM_F | MATCHTCAM_F | HASHSRAM_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mps_cls_intr_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mps_stat_sram1_intr_details[] = {
+ { 0xff, "MPS statistics SRAM1 parity error" },
+ { 0 }
+ };
+ static const struct intr_info mps_stat_sram1_intr_info = {
+ .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
+ .cause_reg = MPS_STAT_PERR_INT_CAUSE_SRAM1_A,
+ .enable_reg = MPS_STAT_PERR_INT_ENABLE_SRAM1_A,
+ .fatal = 0xffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mps_stat_sram1_intr_details,
+ .actions = NULL,
+ };
- int fat;
+ bool fatal = false;
- if (is_t4(adapter->params.chip))
- fat = t4_handle_intr_status(adapter,
- PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
- sysbus_intr_info) +
- t4_handle_intr_status(adapter,
- PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
- pcie_port_intr_info) +
- t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
- pcie_intr_info);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ mps_tx_intr_info.details = t7_mpstx_int_cause_details;
else
- fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
- t5_pcie_intr_info);
+ mps_tx_intr_info.details = mps_tx_intr_details;
+
+ fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T6) {
+ fatal |= t4_handle_intr(adap, &mps_rx_func_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info2, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info3, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info4, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info5, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info6, 0, verbose);
+ }
+ fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T6) {
+ fatal |= t4_handle_intr(adap, &mps_tx_intr_info2, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_tx_intr_info3, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_tx_intr_info4, 0, verbose);
+ fatal |= t4_handle_intr(adap, &t7_mps_trc_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &t7_mps_trc_intr_info2, 0, verbose);
+ } else {
+ fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
+ }
+ fatal |= t4_handle_intr(adap, &mps_stat_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T4) {
+ fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0,
+ verbose);
+ }
+
+ t4_write_reg(adap, MPS_INT_CAUSE_A, is_t4(adap->params.chip) ? 0 :
+ t4_read_reg(adap, MPS_INT_CAUSE_A));
+ t4_read_reg(adap, MPS_INT_CAUSE_A); /* flush */
- if (fat)
- t4_fatal_err(adapter);
+ return fatal;
}
-/*
- * TP interrupt handler.
+/**
+ * t4_ddr_indirect_rw - read indirectly ddr register
+ * @adap: adapter
+ * @vals: where the read register values are stored
+ * @reg : indirect register to read
+ * @idx : index of MC - (0/1)
+ * @rw : 0 - read, 1 - write
*/
-static void tp_intr_handler(struct adapter *adapter)
+static void t4_ddr_indirect_rw(struct adapter *adap, u32 *vals, unsigned int reg, int idx,
+ bool rw)
{
- static const struct intr_info tp_intr_info[] = {
- { 0x3fffffff, "TP parity error", -1, 1 },
- { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
- { 0 }
- };
+ unsigned int addr_reg, data_reg;
+
+ addr_reg = MC_T7_REG(MC_IND_ADDR_A, idx);
+ data_reg = MC_T7_REG(MC_IND_DATA_A, idx);
- if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
- t4_fatal_err(adapter);
+ t4_write_reg(adap, addr_reg, reg);
+
+ if (rw)
+ t4_write_reg(adap, data_reg, *vals);
+ else
+ *vals = t4_read_reg(adap, data_reg);
}
-/*
- * SGE interrupt handler.
- */
-static void sge_intr_handler(struct adapter *adapter)
+static bool mc_ddrphy_intr_handler(struct adapter *adap, int idx, bool verbose)
{
- u32 v = 0, perr;
- u32 err;
+ char rname[32];
+ u32 status, enable, mask, fatal;
- static const struct intr_info sge_intr_info[] = {
- { ERR_CPL_EXCEED_IQE_SIZE_F,
- "SGE received CPL exceeding IQE size", -1, 1 },
- { ERR_INVALID_CIDX_INC_F,
- "SGE GTS CIDX increment too large", -1, 0 },
- { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
- { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
- { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
- "SGE IQID > 1023 received CPL for FL", -1, 0 },
- { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
- 0 },
- { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
- 0 },
- { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
- 0 },
- { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
- 0 },
- { ERR_ING_CTXT_PRIO_F,
- "SGE too many priority ingress contexts", -1, 0 },
- { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
- { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
- { 0 }
+ struct intr_info ii = {
+ .name = &rname[0],
+ .fatal = 0xffffff,
+ .details = NULL,
+ .actions = NULL,
};
- static struct intr_info t4t5_sge_intr_info[] = {
- { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
- { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
- { ERR_EGR_CTXT_PRIO_F,
- "SGE too many priority egress contexts", -1, 0 },
+ snprintf(rname, sizeof(rname), "MC%u_DDRCTL_INT_CAUSE", idx);
+
+ /* read status, enable, mask regs */
+ t4_ddr_indirect_rw(adap, &status, MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTSTATUS_A,
+ idx, 0);
+ t4_ddr_indirect_rw(adap, &enable, MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTENABLE_A,
+ idx, 0);
+ t4_ddr_indirect_rw(adap, &mask, MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTMASK_A, idx, 0);
+
+ status &= enable;
+ if (verbose && status != 0)
+ t4_show_intr_info(adap, &ii, status, enable);
+ fatal = status & ii.fatal;
+ if (fatal != 0 && ii.flags & NONFATAL_IF_DISABLED)
+ fatal &= enable;
+ if (status == 0)
+ return false;
+
+ /* clearing the ddr register */
+ mask = ~mask;
+ t4_ddr_indirect_rw(adap, &mask, MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTCLEAR_A, idx, 1);
+
+ return true;
+}
+
+static bool mc_ddrctl_intr_handler(struct adapter *adap, int idx, bool verbose)
+{
+ static const struct intr_details mc_p_ddrctl_int_cause_details[] = {
+ { HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE_F,
+ "HIF write request (channel 1) invalid address" },
+ { HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE_F,
+ "HIF read data (channel 1) CRC error" },
+ { HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE_F,
+ "HIF read request (channel 1) invalid address" },
+ { HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE_F,
+ "HIF write request (channel 0) invalid address" },
+ { HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE_F, "HIF read data (channel 0) CRC error" },
+ { HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE_F,
+ "HIF read request (channel 0) invalid address" },
{ 0 }
};
- perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
- if (perr) {
- v |= perr;
- dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
- perr);
- }
+ int i = idx;
+ bool fatal;
+ char rname[32];
+ struct intr_info ii = {
+ .name = &rname[0],
+ .fatal = 0x0003f,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mc_p_ddrctl_int_cause_details,
+ .actions = NULL,
+ };
- perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
- if (perr) {
- v |= perr;
- dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
- perr);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T6) {
+ snprintf(rname, sizeof(rname), "MC%u_DDRCTL_INT_CAUSE", i);
+ ii.cause_reg = MC_T7_REG(MC_P_DDRCTL_INT_CAUSE_A, i);
+ ii.enable_reg = MC_T7_REG(MC_P_DDRCTL_INT_ENABLE_A, i);
+ fatal |= t4_handle_intr(adap, &ii, 0, verbose);
}
+ return fatal;
+}
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
- perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
- /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
- perr &= ~ERR_T_RXCRC_F;
- if (perr) {
- v |= perr;
- dev_alert(adapter->pdev_dev,
- "SGE Cause5 Parity Error %#x\n", perr);
- }
- }
+static bool mc_perr_intr_handler(struct adapter *adap, int i, bool verbose)
+{
+ static const struct intr_details mc_p_par_intr_details[] = {
+ { ECC_UE_PAR_CAUSE_F, "MC UE ECC Error on Read data Interrupt Cause status" },
+ { ECC_CE_PAR_CAUSE_F, "MC CE ECC Error on Read data Interrupt Cause status" },
+ { FIFOR_PAR_CAUSE_F, "LOGIC (register)FIFOR parity error" },
+ { RDATA_FIFOR_PAR_CAUSE_F, "Read data fifo block parity error" },
+ { 0 }
+ };
+ static const struct intr_details t7_mc_p_par_cause_details[] = {
+ { HIF_WDATA_Q_PARERR_DCH1_CAUSE_F, "HIF write data FIFO parity error" },
+ { DDRCTL_ECC_CE_PAR_DCH1_CAUSE_F, "DDRCTL ECC CE Interrupt parity error" },
+ { DDRCTL_ECC_CE_PAR_DCH0_CAUSE_F, "DDRCTL ECC CE Interrupt parity error" },
+ { DDRCTL_ECC_UE_PAR_DCH1_CAUSE_F, "DDRCTL ECC UE Interrupt parity error" },
+ { DDRCTL_ECC_UE_PAR_DCH0_CAUSE_F, "DDRCTL ECC UE Interrupt parity error" },
+ { WDATARAM_PARERR_DCH1_CAUSE_F, "DDRCTL WDATARAM channel 1 parity error" },
+ { WDATARAM_PARERR_DCH0_CAUSE_F, "DDRCTL WDATARAM channel 0 parity error" },
+ { BIST_ADDR_FIFO_PARERR_CAUSE_F, "BIST address FIFO parity error" },
+ { BIST_ERR_ADDR_FIFO_PARERR_CAUSE_F, "BIST error address FIFO parity error" },
+ { HIF_WDATA_Q_PARERR_DCH0_CAUSE_F,
+ "HIF write data FIFO for channel 0 parity error" },
+ { HIF_RSPDATA_Q_PARERR_DCH1_CAUSE_F,
+ "HIF read data FIFO for channel 1 parity error" },
+ { HIF_RSPDATA_Q_PARERR_DCH0_CAUSE_F,
+ "HIF read data FIFO for channel 0 parity error" },
+ { HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE_F,
+ "HIF write data mask FIFO for channel 1 parity error" },
+ { HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE_F,
+ "HIF write data mask FIFO for channel 0 parity error" },
+ { 0 }
+ };
- v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
- v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
- t4t5_sge_intr_info);
+ bool fatal;
+ char rname[32];
+ struct intr_info ii = {
+ .name = &rname[0],
+ .fatal = 0xffffffff,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
- err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
- if (err & ERROR_QID_VALID_F) {
- dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
- ERROR_QID_G(err));
- if (err & UNCAPTURED_ERROR_F)
- dev_err(adapter->pdev_dev,
- "SGE UNCAPTURED_ERROR set (clearing)\n");
- t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
- UNCAPTURED_ERROR_F);
+ snprintf(rname, sizeof(rname), "MC%u_PAR_CAUSE", i);
+ if (is_t4(adap->params.chip)) {
+ ii.details = mc_p_par_intr_details;
+ ii.cause_reg = MC_PAR_CAUSE_A;
+ ii.enable_reg = MC_PAR_ENABLE_A;
+ } else if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7) {
+ ii.details = mc_p_par_intr_details;
+ ii.cause_reg = MC_REG(MC_P_PAR_CAUSE_A, i);
+ ii.enable_reg = MC_REG(MC_P_PAR_ENABLE_A, i);
+ } else {
+ ii.details = t7_mc_p_par_cause_details;
+ ii.cause_reg = MC_T7_REG(T7_MC_P_PAR_CAUSE_A, i);
+ ii.enable_reg = MC_T7_REG(T7_MC_P_PAR_ENABLE_A, i);
}
+ ii.flags = NONFATAL_IF_DISABLED;
+ fatal = t4_handle_intr(adap, &ii, 0, verbose);
- if (v != 0)
- t4_fatal_err(adapter);
+ return fatal;
}
-#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
- OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
-#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
- IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
-
-/*
- * CIM interrupt handler.
- */
-static void cim_intr_handler(struct adapter *adapter)
-{
- static const struct intr_info cim_intr_info[] = {
- { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
- { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
- { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
- { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
- { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
- { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
- { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
- { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
- { 0 }
- };
- static const struct intr_info cim_upintr_info[] = {
- { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
- { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
- { ILLWRINT_F, "CIM illegal write", -1, 1 },
- { ILLRDINT_F, "CIM illegal read", -1, 1 },
- { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
- { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
- { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
- { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
- { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
- { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
- { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
- { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
- { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
- { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
- { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
- { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
- { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
- { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
- { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
- { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
- { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
- { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
- { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
- { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
- { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
- { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
- { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
- { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
- { 0 }
+static bool mc_ecc_intr_handler(struct adapter *adap, int i, bool verbose)
+{
+ unsigned int ctl_reg;
+ unsigned int ecc_regs[] = {
+ MC_REGB_DDRC_CH0_ECCCTL_A,
+ MC_REGB_DDRC_CH1_ECCCTL_A,
};
+ int ch;
- u32 val, fw_err;
- int fat;
+ for (ch = 0; ch < ARRAY_SIZE(ecc_regs); ch++) {
+ t4_ddr_indirect_rw(adap, &ctl_reg, ecc_regs[ch], i, 0);
- fw_err = t4_read_reg(adapter, PCIE_FW_A);
- if (fw_err & PCIE_FW_ERR_F)
- t4_report_fw_error(adapter);
+ if (ctl_reg & ECC_CORRECTED_ERR_INTR_EN_F)
+ ctl_reg |= ECC_CORRECTED_ERR_CLR_F;
- /* When the Firmware detects an internal error which normally
- * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
- * in order to make sure the Host sees the Firmware Crash. So
- * if we have a Timer0 interrupt and don't see a Firmware Crash,
- * ignore the Timer0 interrupt.
- */
+ if (ctl_reg & ECC_UNCORRECTED_ERR_INTR_EN_F)
+ ctl_reg |= ECC_UNCORRECTED_ERR_CLR_F;
- val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
- if (val & TIMER0INT_F)
- if (!(fw_err & PCIE_FW_ERR_F) ||
- (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
- t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
- TIMER0INT_F);
+ t4_ddr_indirect_rw(adap, &ctl_reg, ecc_regs[ch], i, 1);
+ }
- fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
- cim_intr_info) +
- t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
- cim_upintr_info);
- if (fat)
- t4_fatal_err(adapter);
+ return true;
}
/*
- * ULP RX interrupt handler.
+ * EDC/MC interrupt handler.
*/
-static void ulprx_intr_handler(struct adapter *adapter)
+static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
{
- static const struct intr_info ulprx_intr_info[] = {
- { 0x1800000, "ULPRX context error", -1, 1 },
- { 0x7fffff, "ULPRX parity error", -1, 1 },
+ static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
+ unsigned int count_reg, v;
+ static int i;
+ static const struct intr_details mem_intr_details[] = {
+ { ECC_UE_INT_CAUSE_F, "Uncorrectable ECC data error(s)" },
+ { ECC_CE_INT_CAUSE_F, "Correctable ECC data error(s)" },
+ { PERR_INT_CAUSE_F, "FIFO parity error" },
{ 0 }
};
-
- if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
- t4_fatal_err(adapter);
-}
-
-/*
- * ULP TX interrupt handler.
- */
-static void ulptx_intr_handler(struct adapter *adapter)
-{
- static const struct intr_info ulptx_intr_info[] = {
- { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
- 0 },
- { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
- 0 },
- { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
- 0 },
- { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
- 0 },
- { 0xfffffff, "ULPTX parity error", -1, 1 },
+ static const struct intr_details t7_mc_intr_details[] = {
+ { DDRPHY_INT_CAUSE_F, "DDR PHY IP interrupts" },
+ { DDRCTL_INT_CAUSE_F, "DDR Controller IP interrupt cause" },
+ { T7_ECC_UE_INT_CAUSE_F, "Uncorrectable ECC data error(s)" },
+ { T7_ECC_CE_INT_CAUSE_F, "Correctable ECC data error(s)" },
+ { PERR_INT_CAUSE_F, "FIFO parity error" },
+ { 0 }
+ };
+ struct intr_action t7_mc_intr_actions[] = {
+ { DDRPHY_INT_CAUSE_F, i, mc_ddrphy_intr_handler },
+ { DDRCTL_INT_CAUSE_F, i, mc_ddrctl_intr_handler },
+ { T7_ECC_CE_INT_CAUSE_F, i, mc_ecc_intr_handler },
+ { T7_ECC_UE_INT_CAUSE_F, i, mc_ecc_intr_handler },
+ { PERR_INT_CAUSE_F, i, mc_perr_intr_handler },
+ { 0 }
+ };
+ struct intr_action mc_intr_actions[] = {
+ { PERR_INT_CAUSE_F, i, mc_perr_intr_handler },
{ 0 }
};
- if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
- t4_fatal_err(adapter);
+ char rname[32];
+ struct intr_info ii = {
+ .name = &rname[0],
+ .fatal = PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ bool fatal = false;
+
+ i = (idx == MEM_MC0 || idx == MEM_MC1) ? idx - 2 : idx;
+ switch (idx) {
+ case MEM_EDC1:
+ fallthrough;
+ case MEM_EDC0:
+ snprintf(rname, sizeof(rname), "EDC%u_INT_CAUSE", i);
+ if (is_t4(adap->params.chip)) {
+ ii.cause_reg = EDC_REG(EDC_INT_CAUSE_A, i);
+ ii.enable_reg = EDC_REG(EDC_INT_ENABLE_A, i);
+ ii.details = mem_intr_details;
+ count_reg = EDC_REG(EDC_ECC_STATUS_A, i);
+ } else {
+ ii.cause_reg = EDC_T5_REG(EDC_H_INT_CAUSE_A, i);
+ ii.enable_reg = EDC_T5_REG(EDC_H_INT_ENABLE_A, i);
+ ii.details = mem_intr_details;
+ count_reg = EDC_T5_REG(EDC_H_ECC_STATUS_A, i);
+ }
+ ii.skip_clear = 1;
+ fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+ break;
+ case MEM_MC1:
+ if (is_t4(adap->params.chip) || is_t6(adap->params.chip))
+ return false;
+ fallthrough;
+ case MEM_MC0:
+ snprintf(rname, sizeof(rname), "MC%u_INT_CAUSE", i);
+ if (is_t4(adap->params.chip)) {
+ ii.cause_reg = MC_INT_CAUSE_A;
+ ii.enable_reg = MC_INT_ENABLE_A;
+ ii.details = mem_intr_details;
+ ii.actions = mc_intr_actions;
+ count_reg = MC_ECC_STATUS_A;
+ } else if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7) {
+ ii.cause_reg = MC_REG(MC_P_INT_CAUSE_A, i);
+ ii.enable_reg = MC_REG(MC_P_INT_ENABLE_A, i);
+ ii.details = mem_intr_details;
+ ii.actions = mc_intr_actions;
+ count_reg = MC_REG(MC_P_ECC_STATUS_A, i);
+ } else {
+ ii.cause_reg = MC_T7_REG(T7_MC_P_INT_CAUSE_A, i);
+ ii.enable_reg = MC_T7_REG(T7_MC_P_INT_ENABLE_A, i);
+ ii.details = t7_mc_intr_details;
+ ii.fatal = PERR_INT_CAUSE_F | T7_ECC_UE_INT_CAUSE_F;
+ ii.actions = t7_mc_intr_actions;
+ }
+ ii.skip_clear = 1;
+ fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+
+ break;
+ }
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7 || idx <= MEM_EDC1) {
+ v = t4_read_reg(adap, count_reg);
+ if (v != 0) {
+ if (ECC_UECNT_G(v) != 0) {
+ dev_alert(adap->pdev_dev,
+ "%s: %u uncorrectable ECC data error(s)\n",
+ name[idx], ECC_UECNT_G(v));
+ }
+ if (ECC_CECNT_G(v) != 0) {
+ if (idx <= MEM_EDC1)
+ t4_edc_err_read(adap, idx);
+ dev_warn_ratelimited(adap->pdev_dev,
+ "%s: %u correctable ECC data error(s)\n",
+ name[idx], ECC_CECNT_G(v));
+ }
+ t4_write_reg(adap, count_reg, 0xffffffff);
+ }
+ }
+ clear_int_cause_reg(adap, &ii);
+ return fatal;
}
-/*
- * PM TX interrupt handler.
- */
-static void pmtx_intr_handler(struct adapter *adapter)
-{
- static const struct intr_info pmtx_intr_info[] = {
- { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
- { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
- { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
- { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
- { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
- { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
- { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
- -1, 1 },
- { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
- { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
- { 0 }
- };
+static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
+{
+ u32 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
+
+ dev_alert(adap->pdev_dev,
+ "MA address wrap-around error by client %u to address %#x\n",
+ MEM_WRAP_CLIENT_NUM_G(v), MEM_WRAP_ADDRESS_G(v) << 4);
+ t4_write_reg(adap, MA_INT_WRAP_STATUS_A, v);
- if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
- t4_fatal_err(adapter);
+ return false;
}
/*
- * PM RX interrupt handler.
+ * MA interrupt handler.
*/
-static void pmrx_intr_handler(struct adapter *adapter)
+static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
{
- static const struct intr_info pmrx_intr_info[] = {
- { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
- { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
- { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
- { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
- -1, 1 },
- { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
- { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
+ static const struct intr_action ma_intr_actions[] = {
+ { MEM_WRAP_INT_CAUSE_F, 0, ma_wrap_status },
+ { 0 },
+ };
+ static const struct intr_details ma_int_cause_details[] = {
+ { MEM_TO_INT_CAUSE_F, " MA Timeout Error Interrupt Cause status"},
+ { MEM_PERR_INT_CAUSE_F, " MA Address PARITY Error Interrupt Cause status" },
+ { MEM_WRAP_INT_CAUSE_F, "MA Address WRAP Around Interrupt Cause status" },
+ { 0 }
+ };
+ static const struct intr_info ma_intr_info = {
+ .name = "MA_INT_CAUSE",
+ .cause_reg = MA_INT_CAUSE_A,
+ .enable_reg = MA_INT_ENABLE_A,
+ .fatal = MEM_WRAP_INT_CAUSE_F | MEM_PERR_INT_CAUSE_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .skip_clear = 1,
+ .details = ma_int_cause_details,
+ .actions = ma_intr_actions,
+ };
+ static const struct intr_details t7_ma_parity_error_status1_details[] = {
+ { 0x00000f80, "Arbiter Write data queue parity error" },
+ { 0x0000007c, "Arbiter Read data queue parity error" },
+ { T7_TP_DMARBT_PAR_ERROR_F, "TP DMARBT Command, Tag logic queue parity error" },
+ { T7_LOGIC_FIFO_PAR_ERROR_F, "Command, Tag logic queue parity error" },
+ { 0 }
+ };
+ static const struct intr_details t6_ma_parity_error_status1_details[] = {
+ { TP_DMARBT_PAR_ERROR_F, "TP DMARBT Command, Tag logic queue parity error" },
+ { LOGIC_FIFO_PAR_ERROR_F, "Command, Tag logic queue parity error" },
+ { 0x3c000000, "Arbiter Write data queue parity error" },
+ { 0x03c00000, "Arbiter Read data queue parity error" },
+ { 0x003ff800, "Client Write data queue parity error" },
+ { 0x000007ff, "Client Read data queue parity error" },
+ { 0 }
+ };
+ struct intr_info ma_perr_status1 = {
+ .name = "MA_PARITY_ERROR_STATUS1",
+ .cause_reg = MA_PARITY_ERROR_STATUS1_A,
+ .enable_reg = MA_PARITY_ERROR_ENABLE1_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_ma_parity_error_status2_details[] = {
+ { 0x00007fff, "Client Write data queue parity error" },
+ { 0 }
+ };
+ static const struct intr_details ma_parity_error_status2_details[] = {
+ { ARB4_PAR_WRQUEUE_ERROR_F, "ARB3 Write data queue parity error" },
+ { ARB4_PAR_RDQUEUE_ERROR_F, "ARB3 Read data queue parity error" },
+ { 0 }
+ };
+ static struct intr_info ma_perr_status2 = {
+ .name = "MA_PARITY_ERROR_STATUS2",
+ .cause_reg = MA_PARITY_ERROR_STATUS2_A,
+ .enable_reg = MA_PARITY_ERROR_ENABLE2_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_ma_parity_error_status3_details[] = {
+ { 0x00007fff, "Client Write data queue parity error" },
{ 0 }
};
+ static struct intr_info ma_perr_status3 = {
+ .name = "MA_PARITY_ERROR_STATUS3",
+ .cause_reg = MA_PARITY_ERROR_STATUS3_A,
+ .enable_reg = MA_PARITY_ERROR_ENABLE3_A,
+ .fatal = 0xffffffff,
+ .flags = 0,
+ .details = t7_ma_parity_error_status3_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ma_write_error_details[] = {
+ { 0xffff0000, "Client write command timeout error" },
+ { 0x00007fff, "Client write data queue timeout error" },
+ { 0 }
+ };
+ static struct intr_info ma_write_error_info = {
+ .name = "MA_WRITE_TIMEOUT_ERROR_STATUS",
+ .cause_reg = MA_WRITE_TIMEOUT_ERROR_STATUS_A,
+ .enable_reg = MA_WRITE_TIMEOUT_ERROR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ma_write_error_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ma_read_error_details[] = {
+ { 0xffff0000, "Client read command timeout error" },
+ { 0x00007fff, "Client read data queue timeout error" },
+ { 0 }
+ };
+ static struct intr_info ma_read_error_info = {
+ .name = "MA_READ_TIMEOUT_ERROR_STATUS",
+ .cause_reg = MA_READ_TIMEOUT_ERROR_STATUS_A,
+ .enable_reg = MA_READ_TIMEOUT_ERROR_ENABLE_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = ma_read_error_details,
+ .actions = NULL,
+ };
+
+ bool fatal;
- if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
- t4_fatal_err(adapter);
+ fatal = false;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ ma_perr_status1.details = t7_ma_parity_error_status1_details;
+ ma_perr_status2.details = t7_ma_parity_error_status2_details;
+ } else {
+ ma_perr_status1.details = t6_ma_parity_error_status1_details;
+ ma_perr_status2.details = ma_parity_error_status2_details;
+ }
+
+ fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T6)
+ fatal |= t4_handle_intr(adap, &ma_perr_status3, 0, verbose);
+ else if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T4)
+ fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ma_write_error_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ma_read_error_info, 0, verbose);
+
+ clear_int_cause_reg(adap, &ma_intr_info);
+ return fatal;
}
/*
- * CPL switch interrupt handler.
+ * SMB interrupt handler.
*/
-static void cplsw_intr_handler(struct adapter *adapter)
-{
- static const struct intr_info cplsw_intr_info[] = {
- { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
- { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
- { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
- { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
- { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
- { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
+static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
+{
+ static const struct intr_details smb_int_cause_details[] = {
+ { MSTTXFIFOPARINT_F, "Master has Parity Error in Tx Fifo" },
+ { MSTRXFIFOPARINT_F, "Master has Parity Error in Rx Fifo" },
+ { SLVFIFOPARINT_F, "Slave has Parity Error in Fifo" },
+ { SLVUNEXPBUSSTOPINT_F, "Slave get Unexpected BusStop" },
+ { SLVUNEXPBUSSTARTINT_F, "Slave get Unexpected BusStart" },
+ { SLVCOMMANDCODEINVINT_F, "Slave get Invalid Command Code" },
+ { SLVBYTECNTERRINT_F, "Slave get Erroneous ByteCount value" },
+ { SLVUNEXPACKMSTINT_F, "Slave get Unexpected Ack from Master" },
+ { SLVUNEXPNACKMSTINT_F, "Slave get Unexpected Nack from Master" },
+ { SLVNOBUSSTOPINT_F, "Slave did not get Bus Stop" },
+ { SLVNOREPSTARTINT_F, "Slave has no Repeated Start" },
+ { SLVRXADDRINT_F, "Slave has Address Error" },
+ { SLVRXPECERRINT_F, "Slave has Pec Error" },
+ { SLVPREPTOARPINT_F, "PL has invalid request" },
+ { SLVTIMEOUTINT_F, "Slave has timed out" },
+ { SLVERRINT_F, "Slave detected error during the current transfer" },
+ { SLVDONEINT_F, "Slave has completed the current transaction" },
+ { SLVRXRDYINT_F, "Slave has received bytes to be processed by uP" },
+ { MSTTIMEOUTINT_F, "Master has timed out" },
+ { MSTNACKINT_F, "Master has detected a NAck on the transfer" },
+ { MSTLOSTARBINT_F, "Master has lost arbitration all the timeline" },
+ { MSTDONEINT_F, "Master has completed the current transaction" },
{ 0 }
};
+ static const struct intr_info smb_int_cause = {
+ .name = "SMB_INT_CAUSE",
+ .cause_reg = SMB_INT_CAUSE_A,
+ .enable_reg = SMB_INT_ENABLE_A,
+ .fatal = SLVFIFOPARINT_F | MSTRXFIFOPARINT_F | MSTTXFIFOPARINT_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = smb_int_cause_details,
+ .actions = NULL,
+ };
- if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
- t4_fatal_err(adapter);
+ return t4_handle_intr(adap, &smb_int_cause, 0, verbose);
}
/*
- * LE interrupt handler.
+ * NC-SI interrupt handler.
*/
-static void le_intr_handler(struct adapter *adap)
+static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
{
- enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
- static const struct intr_info le_intr_info[] = {
- { LIPMISS_F, "LE LIP miss", -1, 0 },
- { LIP0_F, "LE 0 LIP error", -1, 0 },
- { PARITYERR_F, "LE parity error", -1, 1 },
- { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
- { REQQPARERR_F, "LE request queue parity error", -1, 1 },
+ static const struct intr_details ncsi_int_cause_fields[] = {
+ /* t7+ */
+ { CIM2NC_PERR_F, " CIM to NC parity error" },
+ /* t6+ */
+ { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error" },
+ { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error" },
+ { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error" },
+ { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error" },
{ 0 }
};
-
- static struct intr_info t6_le_intr_info[] = {
- { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
- { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
- { CMDTIDERR_F, "LE cmd tid error", -1, 1 },
- { TCAMINTPERR_F, "LE parity error", -1, 1 },
- { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
- { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
- { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
+ static const struct intr_info ncsi_int_cause = {
+ .name = "NCSI_INT_CAUSE",
+ .cause_reg = NCSI_INT_CAUSE_A,
+ .enable_reg = NCSI_INT_ENABLE_A,
+ .fatal = RXFIFO_PRTY_ERR_F | TXFIFO_PRTY_ERR_F |
+ MPS_DM_PRTY_ERR_F | CIM_DM_PRTY_ERR_F |
+ CIM2NC_PERR_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ncsi_int_cause_fields,
+ .actions = NULL,
+ };
+ static const struct intr_details ncsi_xgmac0_int_cause_details[] = {
+ { XAUIPCSDECERR_F, "RGMII PCS DEC Error" },
+ { RGMIIRXFIFOOVERFLOW_F, "RGMII receive FIFO over flow" },
+ { RGMIIRXFIFOUNDERFLOW_F, "RGMII receive FIFO under flow" },
+ { RXPKTSIZEERROR_F, "Receive over size packet" },
+ { WOLPATDETECTED_F, "WOL pattern detected" },
+ { 0x000e0000, "Tx FIFO parity error" },
+ { 0x0001c000, "Rx FIFO parity error" },
+ { TXFIFO_UNDERRUN_F, "Tx FIFO underrun" },
+ { RXFIFO_OVERFLOW_F, "Rx FIFO overflow" },
+ { 0x00000f00, "XAUI SERDES BIST error" },
+ { 0x000000f0, "XAUI SERDES receive low signal change" },
+ { XAUIPCSCTCERR_F, "XAUI PCS CTC FIFO error" },
+ { XAUIPCSALIGNCHANGE_F, "XAUI PCS alignment change" },
+ { RGMIILINKSTSCHANGE_F, "RGMII link status change" },
+ { XGM_INT_F, "XGM Core embedded interrupt (2nd level)" },
{ 0 }
};
+ static const struct intr_info ncsi_xgmac0_int_cause = {
+ .name = "NCSI_XGMAC0_INT_CAUSE",
+ .cause_reg = NCSI_XGMAC0_INT_CAUSE_A,
+ .enable_reg = NCSI_XGMAC0_INT_ENABLE_A,
+ .fatal = 0x000fc00,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = ncsi_xgmac0_int_cause_details,
+ .actions = NULL,
+ };
+ bool fatal = false;
- if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
- (chip <= CHELSIO_T5) ?
- le_intr_info : t6_le_intr_info))
- t4_fatal_err(adap);
+ fatal |= t4_handle_intr(adap, &ncsi_int_cause, 0, verbose);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T6)
+ fatal |= t4_handle_intr(adap, &ncsi_xgmac0_int_cause, 0, verbose);
+ return fatal;
}
/*
- * MPS interrupt handler.
- */
-static void mps_intr_handler(struct adapter *adapter)
-{
- static const struct intr_info mps_rx_intr_info[] = {
- { 0xffffff, "MPS Rx parity error", -1, 1 },
+ * MAC interrupt handler.
+ */
+static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
+{
+ static const struct intr_details mac_int_cause_cmn_details[] = {
+ { 0x3fffc0, "HSS PLL lock error " },
+ { FLOCK_ASSERTED_F, "frequency lock coming out of DPLL sub-block is asserted" },
+ { FLOCK_LOST_F, "frequency lock coming out of DPLL sub-blocki is lost." },
+ { PHASE_LOCK_ASSERTED_F, "PHASE LOCK from DPLL sub-block is asserted" },
+ { PHASE_LOCK_LOST_F, "PHASE LOCK from DPLL sub-block is lost." },
+ { LOCK_ASSERTED_F, "Lock from frac_n PLL inside t7_clk module is asserted" },
+ { LOCK_LOST_F, "Lock from frac_n PLL inside t7_clk module is lost " },
{ 0 }
};
- static const struct intr_info mps_tx_intr_info[] = {
- { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
- { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
- { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
- -1, 1 },
- { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
- -1, 1 },
- { BUBBLE_F, "MPS Tx underflow", -1, 1 },
- { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
- { FRMERR_F, "MPS Tx framing error", -1, 1 },
- { 0 }
+ static const struct intr_info mac_int_cause_cmn = {
+ .name = "MAC_INT_CAUSE_CMN",
+ .cause_reg = MAC_INT_CAUSE_CMN_A,
+ .enable_reg = MAC_INT_EN_CMN_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = mac_int_cause_cmn_details,
+ .actions = NULL,
};
- static const struct intr_info t6_mps_tx_intr_info[] = {
- { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
- { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
- { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
- -1, 1 },
- { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
- -1, 1 },
- /* MPS Tx Bubble is normal for T6 */
- { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
- { FRMERR_F, "MPS Tx framing error", -1, 1 },
+ static const struct intr_details mac_perr_int_cause_mtip_details[] = {
+ { PERR_MAC0_TX_F, "MTIP MAC TX memory for MAC 0 (the 200G MAC for port 0)" },
+ { PERR_MAC1_TX_F, "MTIP MAC TX memory for MAC 1 (the 200G MAC for port 1)" },
+ { PERR_MAC2_TX_F, "MTIP MAC TX memory for MAC 2 (the 10-100G MAC for port 0)" },
+ { PERR_MAC3_TX_F, "MTIP MAC TX memory for MAC 3 (the 10-100G MAC for port 1)" },
+ { PERR_MAC4_TX_F, "MTIP MAC TX memory for MAC 4 (the 10-100G MAC for port 2)" },
+ { PERR_MAC5_TX_F, "MTIP MAC TX memory for MAC 5 (the 10-100G MAC for port 3)" },
+ { PERR_MAC0_RX_F, "MTIP MAC RX memory for MAC 0 (the 200G MAC for port 0)" },
+ { PERR_MAC1_RX_F, "MTIP MAC RX memory for MAC 1 (the 200G MAC for port 1)" },
+ { PERR_MAC2_RX_F, "MTIP MAC RX memory for MAC 2 (the 10-100G MAC for port 0)" },
+ { PERR_MAC3_RX_F, "MTIP MAC RX memory for MAC 3 (the 10-100G MAC for port 1)" },
+ { PERR_MAC4_RX_F, "MTIP MAC RX memory for MAC 4 (the 10-100G MAC for port 2)" },
+ { PERR_MAC5_RX_F, "MTIP MAC RX memory for MAC 5 (the 10-100G MAC for port 3)" },
+ { PERR_MAC_STAT_RX_F, "MTIP MAC RX statistics memory (1 for all 4 10-100G MACs)" },
+ { PERR_MAC_STAT_TX_F, "MTIP MAC TX statistics memory (1 for all 4 10-100G MACs)" },
+ { PERR_MAC_STAT_CAP_F, "MTIP MAC stat capture memory (1 for all 4 100G MACs)" },
{ 0 }
};
- static const struct intr_info mps_trc_intr_info[] = {
- { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
- { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
- -1, 1 },
- { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
+ static const struct intr_info mac_perr_cause_mtip = {
+ .name = "MAC_PERR_INT_CAUSE_MTIP",
+ .cause_reg = MAC_PERR_INT_CAUSE_MTIP_A,
+ .enable_reg = MAC_PERR_INT_EN_MTIP_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = mac_perr_int_cause_mtip_details,
+ .actions = NULL,
+ };
+ static const struct intr_details ios_intr_cause_quad0_details[] = {
+ { Q0_MAILBOX_INT_ASSERT_F, "Etopus Quad0 Mailbox interrupt cause" },
+ { 0x00f00000, "Etopus Quad0 training failure" },
+ { 0x000f0000, "Etopus Quad0 training complete" },
+ { 0x0000f000, "Etopus Quad0 AN TX interrupt" },
+ { 0x00000f00, "Etopus Quad0 signal detect assertion" },
+ { 0x000000f0, "Etopus Quad0 CDR LOL assertion" },
+ { 0x0000000f, "Etopus Quad0 LOS signal assertion" },
{ 0 }
};
- static const struct intr_info mps_stat_sram_intr_info[] = {
- { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
+ static const struct intr_details ios_intr_cause_quad1_details[] = {
+ { Q1_MAILBOX_INT_ASSERT_F, "Etopus Quad1 Mailbox interrupt cause" },
+ { 0x00f00000, "Etopus Quad1 training failure" },
+ { 0x000f0000, "Etopus Quad1 training complete" },
+ { 0x0000f000, "Etopus Quad1 AN TX interrupt" },
+ { 0x00000f00, "Etopus Quad1 signal detect assertion" },
+ { 0x000000f0, "Etopus Quad1 CDR LOL assertion" },
+ { 0x0000000f, "Etopus Quad1 LOS signal assertion" },
{ 0 }
};
- static const struct intr_info mps_stat_tx_intr_info[] = {
- { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
+ static const struct intr_info mac_ios_int_cause_quad0 = {
+ .name = "MAC_IOS_INTR_CAUSE_QUAD0",
+ .cause_reg = MAC_IOS_INTR_CAUSE_QUAD0_A,
+ .enable_reg = MAC_IOS_INTR_EN_QUAD0_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = ios_intr_cause_quad0_details,
+ .actions = NULL,
+ };
+ static const struct intr_info mac_ios_int_cause_quad1 = {
+ .name = "MAC_IOS_INTR_CAUSE_QUAD1",
+ .cause_reg = MAC_IOS_INTR_CAUSE_QUAD1_A,
+ .enable_reg = MAC_IOS_INTR_EN_QUAD1_A,
+ .fatal = 0,
+ .flags = 0,
+ .details = ios_intr_cause_quad1_details,
+ .actions = NULL,
+ };
+ static const struct intr_details mac_intr_details[] = {
+ { TXFIFO_PRTY_ERR_F, "MAC Tx FIFO parity error" },
+ { RXFIFO_PRTY_ERR_F, "MAC Rx FIFO parity error" },
{ 0 }
};
- static const struct intr_info mps_stat_rx_intr_info[] = {
- { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
+ static const struct intr_details t7_mac_int_cause_details[] = {
+ { MAC2MPS_PERR_CAUSE_F, "MPS2MAC Data parity error per port" },
+ { MAC_PPS_INT_CAUSE_F, "One second interrupt based on PTP timer" },
+ { MAC_TX_TS_AVAIL_INT_CAUSE_F,
+ "Time stamp is available for the last IEEE 1588 event frame" },
+ { MAC_PATDETWAKE_INT_CAUSE_F, "Wake up pattern match packet received" },
+ { MAC_MAGIC_WAKE_INT_CAUSE_F, "Magic packet received" },
+ { MAC_SIGDETCHG_INT_CAUSE_F, "Signal Detect Change" },
+ { MAC_PCS_LINK_GOOD_CAUSE_F, "PCS link good (xaui pcsr or 1g)" },
+ { MAC_PCS_LINK_FAIL_CAUSE_F, "PCS Failure (xaui pcsr or 1g)" },
+ { RXFIFOOVERFLOW_F, "RX Fifo Over flow error" },
+ { MAC_REM_FAULT_INT_CAUSE_F, "Remote fault received by XGMAC" },
+ { MAC_LOC_FAULT_INT_CAUSE_F, "Local fault received by XGMAC" },
+ { MAC_LINK_DOWN_INT_CAUSE_F, "Link is down" },
+ { MAC_LINK_UP_INT_CAUSE_F, "Link is up" },
+ { MAC_AN_DONE_INT_CAUSE_F, "Autonegotiation complete" },
+ { MAC_AN_PGRD_INT_CAUSE_F, "An page received" },
+ { MAC_TXFIFO_ERR_INT_CAUSE_F, "Tx FIFO parity error" },
+ { MAC_RXFIFO_ERR_INT_CAUSE_F, "Rx FIFO parity error" },
{ 0 }
};
- static const struct intr_info mps_cls_intr_info[] = {
- { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
- { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
- { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
+ static const struct intr_details mac_perr_int_cause_details[] = {
+ { T6_PERR_PKT_RAM_F, "WoL packet data memory" },
+ { T6_PERR_MASK_RAM_F, "WoL mask memory" },
+ { T6_PERR_CRC_RAM_F, "WoL CRC memory" },
{ 0 }
};
- int fat;
+ char name[32];
+ struct intr_info ii;
+ bool fatal = false;
- fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
- mps_rx_intr_info) +
- t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
- is_t6(adapter->params.chip)
- ? t6_mps_tx_intr_info
- : mps_tx_intr_info) +
- t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
- mps_trc_intr_info) +
- t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
- mps_stat_sram_intr_info) +
- t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
- mps_stat_tx_intr_info) +
- t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
- mps_stat_rx_intr_info) +
- t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
- mps_cls_intr_info);
+ if (is_t4(adap->params.chip)) {
+ snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
+ ii.name = &name[0];
+ ii.cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
+ ii.enable_reg = PORT_REG(port, XGMAC_PORT_INT_EN_A);
+ ii.fatal = MAC2MPS_PERR_CAUSE_F | TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
+ ii.flags = NONFATAL_IF_DISABLED;
+ ii.details = mac_intr_details;
+ ii.actions = NULL;
+ } else if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7) {
+ snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
+ ii.name = &name[0];
+ ii.cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
+ ii.enable_reg = T5_PORT_REG(port, MAC_PORT_INT_EN_A);
+ ii.fatal = MAC2MPS_PERR_CAUSE_F | TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
+ ii.flags = 0;
+ ii.details = mac_intr_details;
+ ii.actions = NULL;
+ } else {
+ snprintf(name, sizeof(name), "T7_MAC_PORT%u_INT_CAUSE", port);
+ ii.name = &name[0];
+ ii.cause_reg = T7_PORT_REG(port, T7_MAC_PORT_INT_CAUSE_A);
+ ii.enable_reg = T7_PORT_REG(port, T7_MAC_PORT_INT_EN_A);
+ ii.fatal = MAC2MPS_PERR_CAUSE_F | TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
+ ii.flags = NONFATAL_IF_DISABLED;
+ ii.details = t7_mac_int_cause_details;
+ ii.actions = NULL;
+ }
+ fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+ if (is_t4(adap->params.chip))
+ return fatal;
+
+ snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T6) {
+ ii.name = &name[0];
+ ii.cause_reg = T7_PORT_REG(port, T7_MAC_PORT_PERR_INT_CAUSE_A);
+ ii.enable_reg = T7_PORT_REG(port, T7_MAC_PORT_PERR_INT_EN_A);
+ ii.fatal = 0xffffffff;
+ ii.flags = NONFATAL_IF_DISABLED;
+ ii.details = mac_perr_int_cause_details;
+ ii.actions = NULL;
+ } else {
+ ii.name = &name[0];
+ ii.cause_reg = T5_PORT_REG(port, MAC_PORT_PERR_INT_CAUSE_A);
+ ii.enable_reg = T5_PORT_REG(port, MAC_PORT_PERR_INT_EN_A);
+ ii.fatal = 0xffffffff;
+ ii.flags = NONFATAL_IF_DISABLED;
+ ii.details = NULL;
+ ii.actions = NULL;
+ }
+ fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+ if (is_t5(adap->params.chip))
+ return fatal;
+
+ snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T6) {
+ ii.name = &name[0];
+ ii.cause_reg = T7_PORT_REG(port, T7_MAC_PORT_PERR_INT_CAUSE_100G_A);
+ ii.enable_reg = T7_PORT_REG(port, T7_MAC_PORT_PERR_INT_EN_100G_A);
+ ii.fatal = 0xffffffff;
+ ii.flags = NONFATAL_IF_DISABLED;
+ ii.details = NULL;
+ ii.actions = NULL;
+ } else {
+ ii.name = &name[0];
+ ii.cause_reg = T5_PORT_REG(port, MAC_PORT_PERR_INT_CAUSE_100G_A);
+ ii.enable_reg = T5_PORT_REG(port, MAC_PORT_PERR_INT_EN_100G_A);
+ ii.fatal = 0xffffffff;
+ ii.flags = NONFATAL_IF_DISABLED;
+ ii.details = NULL;
+ ii.actions = NULL;
+ }
+ fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+ if (is_t6(adap->params.chip))
+ return fatal;
+
+ fatal |= t4_handle_intr(adap, &mac_int_cause_cmn, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mac_perr_cause_mtip, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mac_ios_int_cause_quad0, 0, verbose);
+ fatal |= t4_handle_intr(adap, &mac_ios_int_cause_quad1, 0, verbose);
- t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
- t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
- if (fat)
- t4_fatal_err(adapter);
+ return fatal;
}
-#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
- ECC_UE_INT_CAUSE_F)
+static bool pl_timeout_status(struct adapter *adap, int arg, bool verbose)
+{
+ dev_alert(adap->pdev_dev, " PL_TIMEOUT_STATUS 0x%08x 0x%08x\n",
+ t4_read_reg(adap, PL_TIMEOUT_STATUS0_A),
+ t4_read_reg(adap, PL_TIMEOUT_STATUS1_A));
+
+ return false;
+}
/*
- * EDC/MC interrupt handler.
+ * PL interrupt handler.
*/
-static void mem_intr_handler(struct adapter *adapter, int idx)
+static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
{
- static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
-
- unsigned int addr, cnt_addr, v;
+ static const struct intr_details plpl_int_cause_fields[] = {
+ { FATALPERR_F, "Fatal parity error" },
+ { PERRVFID_F, "VFID_MAP parity error" },
+ { 0 }
+ };
+ static const struct intr_details t5_plpl_int_cause_fields[] = {
+ { PL_BUSPERR_F, "Bus parity error" },
+ { FATALPERR_F, "Fatal parity error" },
+ { INVALIDACCESS_F, "Global reserved memory access" },
+ { TIMEOUT_F, "Bus timeout" },
+ { PLERR_F, "Module reserved access" },
+ { 0 }
+ };
+ static const struct intr_action plpl_int_cause_actions[] = {
+ { TIMEOUT_F, 0, pl_timeout_status },
+ { 0 },
+ };
+ struct intr_info plpl_int_cause = {
+ .name = "PL_PL_INT_CAUSE",
+ .cause_reg = PL_PL_INT_CAUSE_A,
+ .enable_reg = PL_PL_INT_ENABLE_A,
+ .fatal = FATALPERR_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
- if (idx <= MEM_EDC1) {
- addr = EDC_REG(EDC_INT_CAUSE_A, idx);
- cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
- } else if (idx == MEM_MC) {
- if (is_t4(adapter->params.chip)) {
- addr = MC_INT_CAUSE_A;
- cnt_addr = MC_ECC_STATUS_A;
- } else {
- addr = MC_P_INT_CAUSE_A;
- cnt_addr = MC_P_ECC_STATUS_A;
- }
+ if (is_t4(adap->params.chip)) {
+ plpl_int_cause.fatal |= PERRVFID_F;
+ plpl_int_cause.details = plpl_int_cause_fields;
} else {
- addr = MC_REG(MC_P_INT_CAUSE_A, 1);
- cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
+ plpl_int_cause.fatal |= INVALIDACCESS_F;
+ plpl_int_cause.details = t5_plpl_int_cause_fields;
+ plpl_int_cause.actions = plpl_int_cause_actions;
}
- v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
- if (v & PERR_INT_CAUSE_F)
- dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
- name[idx]);
- if (v & ECC_CE_INT_CAUSE_F) {
- u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
-
- t4_edc_err_read(adapter, idx);
-
- t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
- if (printk_ratelimit())
- dev_warn(adapter->pdev_dev,
- "%u %s correctable ECC data error%s\n",
- cnt, name[idx], str_plural(cnt));
- }
- if (v & ECC_UE_INT_CAUSE_F)
- dev_alert(adapter->pdev_dev,
- "%s uncorrectable ECC data error\n", name[idx]);
+ return t4_handle_intr(adap, &plpl_int_cause, 0, verbose);
+}
- t4_write_reg(adapter, addr, v);
- if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
- t4_fatal_err(adapter);
+/* similar to t4_port_reg */
+static inline u32 t7_tlstx_reg(u8 instance, u8 channel, u32 reg)
+{
+ return instance * (CRYPTO_1_BASE_ADDR - CRYPTO_0_BASE_ADDR) +
+ TLS_TX_CH_REG(reg, channel);
}
/*
- * MA interrupt handler.
+ * CRYPTO (aka TLS_TX) interrupt handler.
*/
-static void ma_intr_handler(struct adapter *adap)
+static bool tlstx_intr_handler(struct adapter *adap, int idx, bool verbose)
{
- u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
+ static const struct intr_details tlstx_int_cause_fields[] = {
+ { KEX_CERR_F, "KEX SRAM Correctable error" },
+ { KEYLENERR_F, "IPsec Key length error" },
+ { INTF1_PERR_F, "Input Interface1 parity error" },
+ { INTF0_PERR_F, "Input Interface0 parity error" },
+ { KEX_PERR_F, "KEX SRAM Parity error" },
+ { 0 }
+ };
+ struct intr_info ii = {
+ .fatal = KEX_PERR_F | INTF0_PERR_F | INTF1_PERR_F | KEYLENERR_F,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = tlstx_int_cause_fields,
+ .actions = NULL,
+ };
+ char name[32];
+ int ch;
+ bool fatal = false;
- if (status & MEM_PERR_INT_CAUSE_F) {
- dev_alert(adap->pdev_dev,
- "MA parity error, parity status %#x\n",
- t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
- if (is_t5(adap->params.chip))
- dev_alert(adap->pdev_dev,
- "MA parity error, parity status %#x\n",
- t4_read_reg(adap,
- MA_PARITY_ERROR_STATUS2_A));
- }
- if (status & MEM_WRAP_INT_CAUSE_F) {
- v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
- dev_alert(adap->pdev_dev, "MA address wrap-around error by "
- "client %u to address %#x\n",
- MEM_WRAP_CLIENT_NUM_G(v),
- MEM_WRAP_ADDRESS_G(v) << 4);
- }
- t4_write_reg(adap, MA_INT_CAUSE_A, status);
- t4_fatal_err(adap);
+ for (ch = 0; ch < NUM_TLS_TX_CH_INSTANCES; ch++) {
+ snprintf(name, sizeof(name), "tlstx%u_ch%u_int_cause", idx, ch);
+ ii.name = &name[0];
+ ii.cause_reg = t7_tlstx_reg(idx, ch, TLS_TX_CH_INT_CAUSE_A);
+ ii.enable_reg = t7_tlstx_reg(idx, ch, TLS_TX_CH_INT_ENABLE_A);
+ fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+ }
+
+ return fatal;
}
/*
- * SMB interrupt handler.
- */
-static void smb_intr_handler(struct adapter *adap)
-{
- static const struct intr_info smb_intr_info[] = {
- { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
- { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
- { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
+ * hma interrupt handler.
+ */
+static bool hma_intr_handler(struct adapter *adap, int idx, bool verbose)
+{
+ static const struct intr_details hma_int_cause_fields[] = {
+ { GK_UF_INT_CAUSE_F, "Gatekeeper underflow" },
+ { IDTF_INT_CAUSE_F, "Invalid descriptor fault" },
+ { OTF_INT_CAUSE_F, "Offset translation fault" },
+ { RTF_INT_CAUSE_F, "Region translation fault" },
+ { PCIEMST_INT_CAUSE_F, "PCIe master access error" },
+ { MAMST_INT_CAUSE_F, "MA master access error" },
+ { PERR_INT_CAUSE_F, "FIFO parity error" },
{ 0 }
};
+ static const struct intr_info hma_int_cause = {
+ .name = "HMA_INT_CAUSE",
+ .cause_reg = HMA_INT_CAUSE_A,
+ .enable_reg = HMA_INT_ENABLE_A,
+ .fatal = 0xffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = hma_int_cause_fields,
+ .actions = NULL,
+ };
- if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
- t4_fatal_err(adap);
+ return t4_handle_intr(adap, &hma_int_cause, 0, verbose);
}
/*
- * NC-SI interrupt handler.
- */
-static void ncsi_intr_handler(struct adapter *adap)
-{
- static const struct intr_info ncsi_intr_info[] = {
- { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
- { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
- { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
- { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
+ * CRYPTO_KEY interrupt handler.
+ */
+static bool cryptokey_intr_handler(struct adapter *adap, int idx, bool verbose)
+{
+ static const struct intr_details cryptokey_int_cause_fields[] = {
+ { MA_FIFO_PERR_F, "MA arbiter FIFO parity error" },
+ { MA_RSP_PERR_F, "MA response IF parity error" },
+ { ING_CACHE_DATA_PERR_F, "Ingress key cache data parity error" },
+ { ING_CACHE_TAG_PERR_F, "Ingress key cache tag parity error" },
+ { LKP_KEY_REQ_PERR_F, "Ingress key req parity error" },
+ { LKP_CLIP_TCAM_PERR_F, "Ingress LKP CLIP TCAM parity error" },
+ { LKP_MAIN_TCAM_PERR_F, "Ingress LKP main TCAM parity error" },
+ { EGR_KEY_REQ_PERR_F, "Egress key req or FIFO3 parity error" },
+ { EGR_CACHE_DATA_PERR_F, "Egress key cache data parity error" },
+ { EGR_CACHE_TAG_PERR_F, "Egress key cache tag parity error" },
+ { CIM_PERR_F, "CIM interface parity error" },
+ { MA_INV_RSP_TAG_F, "MA invalid response tag" },
+ { ING_KEY_RANGE_ERR_F, "Ingress key range error" },
+ { ING_MFIFO_OVFL_F, "Ingress MFIFO overflow" },
+ { LKP_REQ_OVFL_F, "Ingress lookup FIFO overflow" },
+ { EOK_WAIT_ERR_F, "EOK wait error" },
+ { EGR_KEY_RANGE_ERR_F, "Egress key range error" },
+ { EGR_MFIFO_OVFL_F, "Egress MFIFO overflow" },
+ { SEQ_WRAP_HP_OVFL_F, "Sequence wrap (hi-pri)" },
+ { SEQ_WRAP_LP_OVFL_F, "Sequence wrap (lo-pri)" },
+ { EGR_SEQ_WRAP_HP_F, "Egress sequence wrap (hi-pri)" },
+ { EGR_SEQ_WRAP_LP_F, "Egress sequence wrap (lo-pri)" },
{ 0 }
};
+ static const struct intr_info cryptokey_int_cause = {
+ .name = "CRYPTO_KEY_INT_CAUSE",
+ .cause_reg = CRYPTO_KEY_INT_CAUSE_A,
+ .enable_reg = CRYPTO_KEY_INT_ENABLE_A,
+ .fatal = 0xfffffff0,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = cryptokey_int_cause_fields,
+ .actions = NULL,
+ };
- if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
- t4_fatal_err(adap);
+ return t4_handle_intr(adap, &cryptokey_int_cause, 0, verbose);
}
/*
- * XGMAC interrupt handler.
- */
-static void xgmac_intr_handler(struct adapter *adap, int port)
-{
- u32 v, int_cause_reg;
+ * GCACHE interrupt handler.
+ */
+static bool gcache_intr_handler(struct adapter *adap, int idx, bool verbose)
+{
+ static const struct intr_details gcache_int_cause_fields[] = {
+ { GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE_F, "GC1 SRAM rsp dataq perr" },
+ { GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE_F, "GC0 SRAM rsp dataq perr" },
+ { GC1_WQDATA_FIFO_PERR_INT_CAUSE_F, "GC1 wqdata FIFO perr" },
+ { GC0_WQDATA_FIFO_PERR_INT_CAUSE_F, "GC0 wqdata FIFO perr" },
+ { GC1_RDTAG_QUEUE_PERR_INT_CAUSE_F, "GC1 rdtag queue perr" },
+ { GC0_RDTAG_QUEUE_PERR_INT_CAUSE_F, "GC0 rdtag queue perr" },
+ { GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_F, "GC1 SRAM rdtag queue perr" },
+ { GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE_F, "GC0 SRAM rdtag queue perr" },
+ { GC1_RSP_PERR_INT_CAUSE_F, "GC1 rsp perr" },
+ { GC0_RSP_PERR_INT_CAUSE_F, "GC0 rsp perr" },
+ { GC1_LRU_UERR_INT_CAUSE_F, "GC1 lru uerr" },
+ { GC0_LRU_UERR_INT_CAUSE_F, "GC0 lru uerr" },
+ { GC1_TAG_UERR_INT_CAUSE_F, "GC1 tag uerr" },
+ { GC0_TAG_UERR_INT_CAUSE_F, "GC0 tag uerr" },
+ { GC1_LRU_CERR_INT_CAUSE_F, "GC1 lru cerr" },
+ { GC0_LRU_CERR_INT_CAUSE_F, "GC0 lru cerr" },
+ { GC1_TAG_CERR_INT_CAUSE_F, "GC1 tag cerr" },
+ { GC0_TAG_CERR_INT_CAUSE_F, "GC0 tag cerr" },
+ { GC1_CE_INT_CAUSE_F, "GC1 correctable error" },
+ { GC0_CE_INT_CAUSE_F, "GC0 correctable error" },
+ { GC1_UE_INT_CAUSE_F, "GC1 uncorrectable error" },
+ { GC0_UE_INT_CAUSE_F, "GC0 uncorrectable error" },
+ { GC1_CMD_PAR_INT_CAUSE_F, "GC1 cmd perr" },
+ { GC1_DATA_PAR_INT_CAUSE_F, "GC1 data perr" },
+ { GC0_CMD_PAR_INT_CAUSE_F, "GC0 cmd perr" },
+ { GC0_DATA_PAR_INT_CAUSE_F, "GC0 data perr" },
+ { ILLADDRACCESS1_INT_CAUSE_F, "GC1 illegal address access" },
+ { ILLADDRACCESS0_INT_CAUSE_F, "GC0 illegal address access" },
+ { 0 }
+ };
+ static const struct intr_info gcache_int_cause = {
+ .name = "GCACHE_INT_CAUSE",
+ .cause_reg = GCACHE_INT_CAUSE_A,
+ .enable_reg = GCACHE_INT_ENABLE_A,
+ .fatal = 0xffffc0ff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = gcache_int_cause_fields,
+ .actions = NULL,
+ };
+ bool fatal = false;
- if (is_t4(adap->params.chip))
- int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
- else
- int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
+ fatal |= t4_handle_intr(adap, &gcache_int_cause, 0, verbose);
- v = t4_read_reg(adap, int_cause_reg);
+ return fatal;
+}
- v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
- if (!v)
- return;
+static inline uint32_t
+get_perr_ucause(struct adapter *sc, const struct intr_info *ii)
+{
+ u32 cause;
- if (v & TXFIFO_PRTY_ERR_F)
- dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
- port);
- if (v & RXFIFO_PRTY_ERR_F)
- dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
- port);
- t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
- t4_fatal_err(adap);
+ cause = t4_read_reg(sc, ii->cause_reg);
+ cause &= t4_read_reg(sc, ii->enable_reg);
+ return cause;
}
-/*
- * PL interrupt handler.
- */
-static void pl_intr_handler(struct adapter *adap)
+static uint32_t
+t4_perr_to_ic(struct adapter *adap, uint32_t perr)
{
- static const struct intr_info pl_intr_info[] = {
- { FATALPERR_F, "T4 fatal parity error", -1, 1 },
- { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
- { 0 }
- };
+ u32 mask;
- if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
- t4_fatal_err(adap);
+ if (adap->params.arch.nchan > 2)
+ mask = MAC0_F | MAC1_F | MAC2_F | MAC3_F;
+ else
+ mask = MAC0_F | MAC1_F;
+ return (perr & mask ? perr | mask : perr);
+}
+
+static uint32_t t7_perr_to_ic1(uint32_t perr)
+{
+ u32 cause = 0;
+
+ if (perr & T7_PL_PERR_ULP_TX_F)
+ cause |= T7_ULP_TX_F;
+ if (perr & T7_PL_PERR_SGE_F)
+ cause |= T7_SGE_F;
+ if (perr & T7_PL_PERR_HMA_F)
+ cause |= T7_HMA_F;
+ if (perr & T7_PL_PERR_CPL_SWITCH_F)
+ cause |= T7_CPL_SWITCH_F;
+ if (perr & T7_PL_PERR_ULP_RX_F)
+ cause |= T7_ULP_RX_F;
+ if (perr & T7_PL_PERR_PM_RX_F)
+ cause |= T7_PM_RX_F;
+ if (perr & T7_PL_PERR_PM_TX_F)
+ cause |= T7_PM_TX_F;
+ if (perr & T7_PL_PERR_MA_F)
+ cause |= T7_MA_F;
+ if (perr & T7_PL_PERR_TP_F)
+ cause |= T7_TP_F;
+ if (perr & T7_PL_PERR_LE_F)
+ cause |= T7_LE_F;
+ if (perr & T7_PL_PERR_EDC1_F)
+ cause |= T7_EDC1_F;
+ if (perr & T7_PL_PERR_EDC0_F)
+ cause |= T7_EDC0_F;
+ if (perr & T7_PL_PERR_MC1_F)
+ cause |= T7_MC1_F;
+ if (perr & T7_PL_PERR_MC0_F)
+ cause |= T7_MC0_F;
+ if (perr & T7_PL_PERR_PCIE_F)
+ cause |= T7_PCIE_F;
+ if (perr & T7_PL_PERR_UART_F)
+ cause |= T7_UART_F;
+ if (perr & T7_PL_PERR_PMU_F)
+ cause |= PMU_F;
+ if (perr & T7_PL_PERR_MAC_F)
+ cause |= MAC0_F | MAC1_F | MAC2_F | MAC3_F;
+ if (perr & T7_PL_PERR_SMB_F)
+ cause |= SMB_F;
+ if (perr & T7_PL_PERR_SF_F)
+ cause |= SF_F;
+ if (perr & T7_PL_PERR_PL_F)
+ cause |= PL_F;
+ if (perr & T7_PL_PERR_NCSI_F)
+ cause |= NCSI_F;
+ if (perr & T7_PL_PERR_MPS_F)
+ cause |= MPS_F;
+ if (perr & T7_PL_PERR_MI_F)
+ cause |= MI_F;
+ if (perr & T7_PL_PERR_DBG_F)
+ cause |= DBG_F;
+ if (perr & T7_PL_PERR_I2CM_F)
+ cause |= I2CM_F;
+ if (perr & T7_PL_PERR_CIM_F)
+ cause |= CIM_F;
+
+ return cause;
+}
+
+static uint32_t t7_perr_to_ic2(uint32_t perr)
+{
+ u32 cause = 0;
+
+ if (perr & T7_PL_PERR_CRYPTO_KEY_F)
+ cause |= CRYPTO_KEY_F;
+ if (perr & T7_PL_PERR_CRYPTO1_F)
+ cause |= CRYPTO1_F;
+ if (perr & T7_PL_PERR_CRYPTO0_F)
+ cause |= CRYPTO0_F;
+ if (perr & T7_PL_PERR_GCACHE_F)
+ cause |= GCACHE_F;
+
+ return cause;
}
-#define PF_INTR_MASK (PFSW_F)
-#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
- EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
- CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
-
/**
* t4_slow_intr_handler - control path interrupt handler
* @adapter: the adapter
+ * @verbose: increased verbosity, for debug
*
* T4 interrupt handler for non-data global interrupt events, e.g., errors.
* The designation 'slow' is because it involves register reads, while
* data interrupts typically don't involve any MMIOs.
*/
-int t4_slow_intr_handler(struct adapter *adapter)
-{
- /* There are rare cases where a PL_INT_CAUSE bit may end up getting
- * set when the corresponding PL_INT_ENABLE bit isn't set. It's
- * easiest just to mask that case here.
- */
- u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
- u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
- u32 cause = raw_cause & enable;
+int t4_slow_intr_handler(struct adapter *adap, bool verbose)
+{
+ static const struct intr_details pl_int_cause_fields[] = {
+ { MC1_F, "MC1" },
+ { UART_F, "UART" },
+ { ULP_TX_F, "ULP TX" },
+ { SGE_F, "SGE" },
+ { HMA_F, "HMA" },
+ { CPL_SWITCH_F, "CPL Switch" },
+ { ULP_RX_F, "ULP RX" },
+ { PM_RX_F, "PM RX" },
+ { PM_TX_F, "PM TX" },
+ { MA_F, "MA" },
+ { TP_F, "TP" },
+ { LE_F, "LE" },
+ { EDC1_F, "EDC1" },
+ { EDC0_F, "EDC0" },
+ { MC_F, "MC0" },
+ { PCIE_F, "PCIE" },
+ { PMU_F, "PMU" },
+ { MAC3_F, "MAC3" },
+ { MAC2_F, "MAC2" },
+ { MAC1_F, "MAC1" },
+ { MAC0_F, "MAC0" },
+ { SMB_F, "SMB" },
+ { SF_F, "SF" },
+ { PL_F, "PL" },
+ { NCSI_F, "NC-SI" },
+ { MPS_F, "MPS" },
+ { MI_F, "MI" },
+ { DBG_F, "DBG" },
+ { I2CM_F, "I2CM" },
+ { CIM_F, "CIM" },
+ { 0 }
+ };
+ static const struct intr_action pl_int_cause_actions[] = {
+ { ULP_TX_F, -1, ulptx_intr_handler },
+ { SGE_F, -1, sge_intr_handler },
+ { CPL_SWITCH_F, -1, cplsw_intr_handler },
+ { ULP_RX_F, -1, ulprx_intr_handler },
+ { PM_RX_F, -1, pmrx_intr_handler },
+ { PM_TX_F, -1, pmtx_intr_handler },
+ { MA_F, -1, ma_intr_handler },
+ { TP_F, -1, tp_intr_handler },
+ { LE_F, -1, le_intr_handler },
+ { EDC0_F, MEM_EDC0, mem_intr_handler },
+ { EDC1_F, MEM_EDC1, mem_intr_handler },
+ { MC0_F, MEM_MC0, mem_intr_handler },
+ { MC1_F, MEM_MC1, mem_intr_handler },
+ { PCIE_F, -1, pcie_intr_handler },
+ { MAC0_F, 0, mac_intr_handler },
+ { MAC1_F, 1, mac_intr_handler },
+ { MAC2_F, 2, mac_intr_handler },
+ { MAC3_F, 3, mac_intr_handler },
+ { SMB_F, -1, smb_intr_handler },
+ { PL_F, -1, plpl_intr_handler },
+ { NCSI_F, -1, ncsi_intr_handler },
+ { MPS_F, -1, mps_intr_handler },
+ { CIM_F, -1, cim_intr_handler },
+ { 0 }
+ };
+ static const struct intr_info pl_int_cause = {
+ .name = "PL_INT_CAUSE",
+ .cause_reg = PL_INT_CAUSE_A,
+ .enable_reg = PL_INT_ENABLE_A,
+ .fatal = 0,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = pl_int_cause_fields,
+ .actions = pl_int_cause_actions,
+ };
+ static const struct intr_info pl_perr_cause = {
+ .name = "PL_PERR_CAUSE",
+ .cause_reg = PL_PERR_CAUSE_A,
+ .enable_reg = PL_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = pl_int_cause_fields,
+ .actions = NULL,
+ };
+ static const struct intr_details t7_pl_int_cause_fields[] = {
+ { T7_FLR_F, "FLR" },
+ { T7_SW_CIM_F, "SW CIM" },
+ { T7_ULP_TX_F, "ULP TX" },
+ { T7_SGE_F, "SGE" },
+ { T7_HMA_F, "HMA" },
+ { T7_CPL_SWITCH_F, "CPL Switch" },
+ { T7_ULP_RX_F, "ULP RX" },
+ { T7_PM_RX_F, "PM RX" },
+ { T7_PM_TX_F, "PM TX" },
+ { T7_MA_F, "MA" },
+ { T7_TP_F, "TP" },
+ { T7_LE_F, "LE" },
+ { T7_EDC1_F, "EDC1" },
+ { T7_EDC0_F, "EDC0" },
+ { T7_MC1_F, "MC1" },
+ { T7_MC0_F, "MC0" },
+ { T7_PCIE_F, "PCIE" },
+ { T7_UART_F, "UART" },
+ { PMU_F, "PMU" },
+ { MAC3_F, "MAC3" },
+ { MAC2_F, "MAC2" },
+ { MAC1_F, "MAC1" },
+ { MAC0_F, "MAC0" },
+ { SMB_F, "SMB" },
+ { SF_F, "SF" },
+ { PL_F, "PL" },
+ { NCSI_F, "NC-SI" },
+ { MPS_F, "MPS" },
+ { MI_F, "MI" },
+ { DBG_F, "DBG" },
+ { I2CM_F, "I2CM" },
+ { CIM_F, "CIM" },
+ { 0 }
+ };
+ static const struct intr_action t7_pl_int_cause_actions[] = {
+ { T7_ULP_TX_F, -1, ulptx_intr_handler },
+ { T7_SGE_F, -1, sge_intr_handler },
+ { T7_HMA_F, -1, hma_intr_handler },
+ { T7_CPL_SWITCH_F, -1, cplsw_intr_handler },
+ { T7_ULP_RX_F, -1, ulprx_intr_handler },
+ { T7_PM_RX_F, -1, pmrx_intr_handler},
+ { T7_PM_TX_F, -1, pmtx_intr_handler},
+ { T7_MA_F, -1, ma_intr_handler },
+ { T7_TP_F, -1, tp_intr_handler },
+ { T7_LE_F, -1, le_intr_handler },
+ { T7_EDC0_F, MEM_EDC0, mem_intr_handler },
+ { T7_EDC1_F, MEM_EDC1, mem_intr_handler },
+ { T7_MC0_F, MEM_MC0, mem_intr_handler },
+ { T7_MC1_F, MEM_MC1, mem_intr_handler },
+ { T7_PCIE_F, -1, pcie_intr_handler },
+ { MAC0_F, 0, mac_intr_handler},
+ { MAC1_F, 1, mac_intr_handler},
+ { MAC2_F, 2, mac_intr_handler},
+ { MAC3_F, 3, mac_intr_handler},
+ { SMB_F, -1, smb_intr_handler},
+ { PL_F, -1, plpl_intr_handler },
+ { NCSI_F, -1, ncsi_intr_handler},
+ { MPS_F, -1, mps_intr_handler },
+ { CIM_F, -1, cim_intr_handler },
+ { 0 }
+ };
+ static const struct intr_info t7_pl_int_cause = {
+ .name = "PL_INT_CAUSE",
+ .cause_reg = PL_INT_CAUSE_A,
+ .enable_reg = PL_INT_ENABLE_A,
+ .fatal = 0,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = t7_pl_int_cause_fields,
+ .actions = t7_pl_int_cause_actions,
+ };
+ static const struct intr_details t7_pl_int_cause2_fields[] = {
+ { CRYPTO_KEY_F, "CRYPTO KEY" },
+ { CRYPTO1_F, "CRYPTO1" },
+ { CRYPTO0_F, "CRYPTO0" },
+ { GCACHE_F, "GCACHE" },
+ { 0 }
+ };
+ static const struct intr_action t7_pl_int_cause2_actions[] = {
+ { CRYPTO_KEY_F, -1, cryptokey_intr_handler },
+ { CRYPTO1_F, 1, tlstx_intr_handler },
+ { CRYPTO0_F, 0, tlstx_intr_handler },
+ { GCACHE_F, -1, gcache_intr_handler },
+ { 0 }
+ };
+ static const struct intr_info t7_pl_int_cause2 = {
+ .name = "PL_INT_CAUSE2",
+ .cause_reg = PL_INT_CAUSE2_A,
+ .enable_reg = PL_INT_ENABLE2_A,
+ .fatal = 0,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = t7_pl_int_cause2_fields,
+ .actions = t7_pl_int_cause2_actions,
+ };
+ static const struct intr_details t7_pl_perr_cause_fields[] = {
+ { T7_PL_PERR_CRYPTO_KEY_F, "CRYPTO KEY" },
+ { T7_PL_PERR_CRYPTO1_F, "CRYPTO1" },
+ { T7_PL_PERR_CRYPTO0_F, "CRYPTO0" },
+ { T7_PL_PERR_GCACHE_F, "GCACHE" },
+ { T7_PL_PERR_ULP_TX_F, "ULP TX" },
+ { T7_PL_PERR_SGE_F, "SGE" },
+ { T7_PL_PERR_HMA_F, "HMA" },
+ { T7_PL_PERR_CPL_SWITCH_F, "CPL Switch" },
+ { T7_PL_PERR_ULP_RX_F, "ULP RX" },
+ { T7_PL_PERR_PM_RX_F, "PM RX" },
+ { T7_PL_PERR_PM_TX_F, "PM TX" },
+ { T7_PL_PERR_MA_F, "MA" },
+ { T7_PL_PERR_TP_F, "TP" },
+ { T7_PL_PERR_LE_F, "LE" },
+ { T7_PL_PERR_EDC1_F, "EDC1" },
+ { T7_PL_PERR_EDC0_F, "EDC0" },
+ { T7_PL_PERR_MC1_F, "MC1" },
+ { T7_PL_PERR_MC0_F, "MC0" },
+ { T7_PL_PERR_PCIE_F, "PCIE" },
+ { T7_PL_PERR_UART_F, "UART" },
+ { T7_PL_PERR_PMU_F, "PMU" },
+ { T7_PL_PERR_MAC_F, "MAC" },
+ { T7_PL_PERR_SMB_F, "SMB" },
+ { T7_PL_PERR_SF_F, "SF" },
+ { T7_PL_PERR_PL_F, "PL" },
+ { T7_PL_PERR_NCSI_F, "NC-SI" },
+ { T7_PL_PERR_MPS_F, "MPS" },
+ { T7_PL_PERR_MI_F, "MI" },
+ { T7_PL_PERR_DBG_F, "DBG" },
+ { T7_PL_PERR_I2CM_F, "I2CM" },
+ { T7_PL_PERR_CIM_F, "CIM" },
+ { 0 }
+ };
+ static const struct intr_info t7_pl_perr_cause = {
+ .name = "PL_PERR_CAUSE",
+ .cause_reg = PL_PERR_CAUSE_A,
+ .enable_reg = PL_PERR_ENABLE_A,
+ .fatal = 0xffffffff,
+ .flags = NONFATAL_IF_DISABLED,
+ .details = t7_pl_perr_cause_fields,
+ .actions = NULL,
+ };
+ bool fatal = false;
+ u32 perr;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7) {
+ perr = get_perr_ucause(adap, &pl_perr_cause);
+ fatal |= t4_handle_intr(adap, &pl_perr_cause, 0, verbose);
+ fatal |= t4_handle_intr(adap, &pl_int_cause,
+ t4_perr_to_ic(adap, perr), verbose);
+ t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
+ (void)t4_read_reg(adap, pl_perr_cause.cause_reg);
+ } else {
+ perr = get_perr_ucause(adap, &t7_pl_perr_cause);
+ fatal |= t4_handle_intr(adap, &t7_pl_perr_cause, 0, verbose);
+ fatal |= t4_handle_intr(adap, &t7_pl_int_cause,
+ t7_perr_to_ic1(perr), verbose);
+ fatal |= t4_handle_intr(adap, &t7_pl_int_cause2,
+ t7_perr_to_ic2(perr), verbose);
+ t4_write_reg(adap, t7_pl_perr_cause.cause_reg, perr);
+ (void)t4_read_reg(adap, t7_pl_perr_cause.cause_reg);
+ }
- if (!(cause & GLBL_INTR_MASK))
- return 0;
- if (cause & CIM_F)
- cim_intr_handler(adapter);
- if (cause & MPS_F)
- mps_intr_handler(adapter);
- if (cause & NCSI_F)
- ncsi_intr_handler(adapter);
- if (cause & PL_F)
- pl_intr_handler(adapter);
- if (cause & SMB_F)
- smb_intr_handler(adapter);
- if (cause & XGMAC0_F)
- xgmac_intr_handler(adapter, 0);
- if (cause & XGMAC1_F)
- xgmac_intr_handler(adapter, 1);
- if (cause & XGMAC_KR0_F)
- xgmac_intr_handler(adapter, 2);
- if (cause & XGMAC_KR1_F)
- xgmac_intr_handler(adapter, 3);
- if (cause & PCIE_F)
- pcie_intr_handler(adapter);
- if (cause & MC_F)
- mem_intr_handler(adapter, MEM_MC);
- if (is_t5(adapter->params.chip) && (cause & MC1_F))
- mem_intr_handler(adapter, MEM_MC1);
- if (cause & EDC0_F)
- mem_intr_handler(adapter, MEM_EDC0);
- if (cause & EDC1_F)
- mem_intr_handler(adapter, MEM_EDC1);
- if (cause & LE_F)
- le_intr_handler(adapter);
- if (cause & TP_F)
- tp_intr_handler(adapter);
- if (cause & MA_F)
- ma_intr_handler(adapter);
- if (cause & PM_TX_F)
- pmtx_intr_handler(adapter);
- if (cause & PM_RX_F)
- pmrx_intr_handler(adapter);
- if (cause & ULP_RX_F)
- ulprx_intr_handler(adapter);
- if (cause & CPL_SWITCH_F)
- cplsw_intr_handler(adapter);
- if (cause & SGE_F)
- sge_intr_handler(adapter);
- if (cause & ULP_TX_F)
- ulptx_intr_handler(adapter);
-
- /* Clear the interrupts just processed for which we are the master. */
- t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
- (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
- return 1;
+ return fatal;
}
/**
@@ -5074,24 +8206,33 @@ int t4_slow_intr_handler(struct adapter *adapter)
* non PF-specific interrupts from the various HW modules. Only one PCI
* function at a time should be doing this.
*/
-void t4_intr_enable(struct adapter *adapter)
+void t4_intr_enable(struct adapter *adap)
{
u32 val = 0;
- u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
- u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
- SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
+ u32 whoami = t4_read_reg(adap, PL_WHOAMI_A);
+ u32 pf = (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5
+ ? SOURCEPF_G(whoami)
+ : T6_SOURCEPF_G(whoami));
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
- t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
- ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
- ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
- ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
- ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
- ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
- DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
- t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
- t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
+ else
+ val = ERR_PCIE_ERROR0_F | ERR_PCIE_ERROR1_F | FATAL_WRE_LEN_F;
+
+ val |= ERR_CPL_EXCEED_IQE_SIZE_F |
+ ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
+ ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
+ ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
+ ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
+ ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
+ DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F;
+
+ t4_write_reg(adap, SGE_INT_ENABLE3_A, val);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ t4_write_reg(adap, SGE_INT_ENABLE4_A, 0xffffffff);
+ t4_write_reg(adap, MYPF_REG(PL_PF_INT_ENABLE_A), PFSW_F | PFCIM_F);
+ t4_set_reg_field(adap, PL_INT_ENABLE_A, SF_F | I2CM_F, 0);
+ t4_set_reg_field(adap, PL_INT_MAP0_A, 0, 1 << pf);
}
/**
@@ -5106,9 +8247,6 @@ void t4_intr_disable(struct adapter *adapter)
{
u32 whoami, pf;
- if (pci_channel_offline(adapter->pdev))
- return;
-
whoami = t4_read_reg(adapter, PL_WHOAMI_A);
pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH net-next v3 02/12] cxgb4: rework the interrupt handling framework
2026-10-05 22:48 ` [PATCH net-next v3 02/12] cxgb4: rework the interrupt handling framework Potnuri Bharat Teja
@ 2026-10-09 13:56 ` Simon Horman
0 siblings, 0 replies; 14+ messages in thread
From: Simon Horman @ 2026-10-09 13:56 UTC (permalink / raw)
To: Potnuri Bharat Teja; +Cc: netdev, davem, kuba, edumazet, pabeni, andrew+netdev
On Mon, Oct 05, 2026 at 06:48:20PM -0400, Potnuri Bharat Teja wrote:
> The slow interrupt path used a per module handler that walked a table
> of (mask, message) pairs with t4_handle_intr_status() and printed a
> message for every bit it found set. Each module handler open coded
> the read, report and clear sequence, and there was no way to express
> that a cause bit should be handled by inspecting a sub-register, or
> that a bit is only fatal when it is also enabled.
>
> Replace it with a data driven framework:
>
> struct intr_info describes one cause register: its name, the cause
> and enable register offsets, the mask of fatal bits, a table of
> struct intr_details for decoding individual bits, and an optional
> table of struct intr_action entries naming a function to call for a
> given cause bit.
>
> t4_handle_intr() implements the common read, report, dispatch and
> clear sequence once, so a module handler reduces to describing its
> registers and any nested cause registers it owns.
>
> The module interrupt handlers now return bool rather than void so a
> fatal condition propagates back to t4_slow_intr_handler() instead of
> being signalled out of band, and t4_slow_intr_handler() takes a
> verbose flag controlling whether individual cause bits are decoded
> and logged.
>
> This changes the interrupt path for all supported adapters. No
> functional change is intended for T4, T5 or T6 beyond the wording of
> the messages emitted.
>
> Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
Hi Potnuri,
Thanks for your patch.
x86_64 allmodconfig W=1 builds with clang 22.1.8 warn that:
.../t4_hw.c:6959:3: warning: variable 'fatal' is uninitialized when used here [-Wuninitialized]
6959 | fatal |= t4_handle_intr(adap, &ii, 0, verbose);
| ^~~~~
.../t4_hw.c:6945:12: note: initialize the variable 'fatal' to silence this warning
6945 | bool fatal;
| ^
| = 0
1 warning generated.
Warning: .../t4_hw.c:7956 function parameter 'adap' not described in 't4_slow_intr_handler'
Warning: .../t4_hw.c:7956 Excess function parameter 'adapter' description in 't4_slow_intr_handler' (did you mean one of: 'adap')
Warning: .../t4_hw.c:8209 function parameter 'adap' not described in 't4_intr_enable'
Warning: .../t4_hw.c:8209 Excess function parameter 'adapter' description in 't4_intr_enable' (did you mean one of: 'adap')
Warning: .../t4_hw.c:7956 function parameter 'adap' not described in 't4_slow_intr_handler'
Warning: .../t4_hw.c:7956 Excess function parameter 'adapter' description in 't4_slow_intr_handler' (did you mean one of: 'adap')
Warning: .../t4_hw.c:8209 function parameter 'adap' not described in 't4_intr_enable'
Warning: .../t4_hw.c:8209 Excess function parameter 'adapter' description in 't4_intr_enable' (did you mean one of: 'adap')
Similarly building patch 3/12, 5/12, 10/12, and 11/12,
seem to add new warnings reported by gcc 16.2.1 or clang.
Please make sure your patch compiles for x86_64 allmodconfig W=1
with out new warnings emitted by either gcc or clang.
The following functions added in .c files use the inline keyword.
static inline char intr_alert_char(u32 cause, u32 enable, u32 fatal)
static inline u32 t7_tlstx_reg(u8 instance, u8 channel, u32 reg)
static inline uint32_t
Please don't use inline like that, instead please let the compiler
choose to inline functions (or not).
inline functions in .h files are of course fine.
And checkpatch reports the following errors for patch 4/12.
ERROR: missing sentinel in ID array
#1734: FILE: drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c:289:
+static const struct pci_device_id cxgb4_pci_tbl[] = {
#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
#define CH_PCI_ID_TABLE_ENTRY(devid) \
{ PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF }
#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
{ 0, } \
}
ERROR: Macros with complex values should be enclosed in parentheses
#1741: FILE: drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c:296:
+#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
+ { 0, } \
+}
Please make sure the patchset does not add checkpatch errors.
...
--
pw-bot: changes-requested
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH net-next v3 03/12] cxgb4: add T7 hardware management support
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 01/12] cxgb4: add T7 hardware definitions and firmware interfaces Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 02/12] cxgb4: rework the interrupt handling framework Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 04/12] cxgb4: move PCI device management into cxgb4_pci.c and rework driver helpers Potnuri Bharat Teja
` (8 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Extend the cxgb4 hardware management layer to support T7 adapters.
Add T7 handling to hardware resource and topology discovery. The TP
load balancer mode and the firmware supplied TP channel map are read
into adapter_params, and t4_get_mps_bg_map() and t4_get_tp_ch_map()
account for the T7 channel layout. The load balancer mode distributes
the four TP channels across the active ports as four ports of one
channel, two ports of two channels, or one port of four channels.
t4_get_chip_type() moves from cxgb4_main.c into t4_hw.c so that chip
identification lives with the rest of the hardware layer, and learns
the T7 chip version.
Add T7 flash support. The flash layout is described by a table
indexed by flash location rather than by fixed FLASH_*_START_SEC and
FLASH_*_NSECS constants, with t4_flash_location_start_sec(),
t4_flash_location_nsecs(), t4_flash_location_start() and
t4_flash_location_size() returning the bounds of a region.
t4_flash_cfg_addr() now returns int so that it can report a region
that does not exist on the running adapter. t4_get_flash_params()
learns the flash parts used on T7 and a four byte address serial
flash interface, which is required for parts larger than 16MB.
Add the T7 register ranges to t4_get_regs(), the T7 PCIE memory window
registers, and T7 support to the CIM ingress and egress queue, CIM LA,
SGE context, MPS trace filter, PM statistics, scheduler and I2C
accessors.
T7 implements multiple uP cores. The number of enabled cores is read
during device log initialisation and the per core device log
parameters are kept in an array, so that the device log and the CIM
queue accessors can address a specific core.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/cudbg_lib.c | 4 +-
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 89 +-
.../ethernet/chelsio/cxgb4/cxgb4_debugfs.c | 2 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 -
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 2200 ++++++++++++++---
drivers/net/ethernet/chelsio/cxgb4/t4_hw.h | 139 +-
6 files changed, 2022 insertions(+), 429 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
index 557c591a6ce3..4bae323351f7 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
@@ -198,7 +198,7 @@ u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
}
break;
case CUDBG_DEV_LOG:
- len = adap->params.devlog.size;
+ len = adap->params.devlogs.size;
break;
case CUDBG_CIM_LA:
if (is_t6(adap->params.chip)) {
@@ -847,7 +847,7 @@ int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
return rc;
}
- dparams = &padap->params.devlog;
+ dparams = &padap->params.devlogs;
rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
if (rc)
return rc;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index c3dcb7ea83ab..43728dbb4742 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -56,6 +56,18 @@
#include <linux/thermal.h>
#include <asm/io.h>
#include "t4_chip_type.h"
+
+struct adapter;
+enum dev_state {
+ DEV_STATE_UNINIT,
+ DEV_STATE_INIT,
+ DEV_STATE_ERR
+};
+
+/* Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
+ */
+#define CXGB4_MAX_ATIDS 8192U
+
#include "cxgb4_uld.h"
#include "t4fw_api.h"
@@ -92,6 +104,7 @@ enum {
enum {
T4_REGMAP_SIZE = (160 * 1024),
T5_REGMAP_SIZE = (332 * 1024),
+ T7_REGMAP_SIZE = (360 * 1024),
};
enum {
@@ -121,12 +134,6 @@ enum dev_master {
MASTER_MUST
};
-enum dev_state {
- DEV_STATE_UNINIT,
- DEV_STATE_INIT,
- DEV_STATE_ERR
-};
-
enum cc_pause {
PAUSE_RX = 1 << 0,
PAUSE_TX = 1 << 1,
@@ -136,7 +143,8 @@ enum cc_pause {
enum cc_fec {
FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
FEC_RS = 1 << 1, /* Reed-Solomon */
- FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
+ FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
+ FEC_FORCE = 1 << 3 /* Forcefully set FEC */
};
enum {
@@ -385,6 +393,10 @@ struct tp_params {
int matchtype_shift;
int frag_shift;
+ u8 lb_mode; /* Load Balancer Mode */
+ u8 nports; /* # of ports activated by FW */
+ u32 channel_map[NCHAN]; /* saved TP Channel Map from FW */
+
u64 hash_filter_mask;
};
@@ -412,6 +424,8 @@ struct pf_resources {
};
struct pci_params {
+ u16 vendor_id;
+ u16 device_id;
unsigned char speed;
unsigned char width;
};
@@ -439,7 +453,8 @@ struct adapter_params {
struct vpd_params vpd;
struct pf_resources pfres;
struct pci_params pci;
- struct devlog_params devlog;
+ struct devlog_params devlogs;
+ struct devlog_params devlog[MAX_UP_CORES];
enum pcie_memwin drv_memwin;
unsigned int cim_la_size;
@@ -463,7 +478,7 @@ struct adapter_params {
unsigned char portvec;
enum chip_type chip; /* chip code */
struct arch_specific_params arch; /* chip specific params */
- unsigned char offload;
+ unsigned int offload;
unsigned char crypto; /* HW capability for crypto */
unsigned char ethofld; /* QoS support */
@@ -487,6 +502,10 @@ struct adapter_params {
u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
bool write_cmpl_support; /* FW supports WRITE_CMPL */
+
+ u8 num_up_cores; /* # of enabled uP cores */
+ u32 tid_qid_sel_mask; /* TID based QID selection mask for uP cores */
+ u8 tid_qid_sel_shift; /* TID based QID selection shift for uP cores */
};
/* State needed to monitor the forward progress of SGE Ingress DMA activities
@@ -605,7 +624,7 @@ struct link_config {
enum {
MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
- MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
+ MAX_CTRL_QUEUES = NCHAN * MAX_UP_CORES, /* # of control Tx queues */
};
enum {
@@ -641,7 +660,6 @@ enum {
#define PRIV_FLAGS_ADAP 0
#define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
-struct adapter;
struct sge_rspq;
#include "cxgb4_dcb.h"
@@ -874,6 +892,7 @@ struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
unsigned long tx_cso; /* # of Tx checksum offloads */
unsigned long vlan_ins; /* # of Tx VLAN insertions */
unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
+ u8 group_id;
} ____cacheline_aligned_in_smp;
struct sge_uld_txq { /* state for an SGE offload Tx queue */
@@ -892,6 +911,7 @@ struct sge_ctrl_txq { /* state for an SGE control Tx queue */
struct sk_buff_head sendq; /* list of backpressured packets */
struct tasklet_struct qresume_tsk; /* restarts the queue */
u8 full; /* the Tx ring is full */
+ u8 tid_qid_group_id;
} ____cacheline_aligned_in_smp;
struct sge_uld_rxq_info {
@@ -962,6 +982,9 @@ struct sge_eohw_txq {
};
struct sge {
+ void __iomem *tx_db_addr; /* Tx doorbell */
+ void __iomem *rx_db_addr; /* Rx doorbell */
+
struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
struct sge_eth_txq ptptxq;
struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
@@ -1109,7 +1132,9 @@ struct adapter {
struct device *pdev_dev;
const char *name;
unsigned int mbox;
+ struct mbox_chan *mbox_chan;
unsigned int pf;
+ u8 primary_pf;
unsigned int flags;
unsigned int adap_idx;
enum chip_type chip;
@@ -1146,8 +1171,10 @@ struct adapter {
unsigned int rawf_start;
unsigned int rawf_cnt;
struct smt_data *smt;
+
struct cxgb4_uld_info *uld;
void *uld_handle[CXGB4_ULD_MAX];
+
unsigned int num_uld;
unsigned int num_ofld_uld;
struct list_head list_node;
@@ -1179,6 +1206,7 @@ struct adapter {
struct mutex uld_mutex;
struct dentry *debugfs_root;
+ struct dentry *debugfs_multicore[MAX_UP_CORES];
bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
bool trace_rss; /* 1 implies that different RSS flit per filter is
* used per filter else if 0 default RSS flit is
@@ -1731,6 +1759,10 @@ static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
}
+unsigned int t4_pcie_mem_access_base_win_reg(struct adapter *adap, int win);
+unsigned int t4_pcie_mem_access_offset_reg(struct adapter *adap, int win);
+void t4_pcie_mem_access_offset_write(struct adapter *adap, u64 off, int win,
+ u32 pf);
/**
* hash_mac_addr - return the hash value of a MAC address
* @addr: the 48-bit Ethernet MAC address
@@ -1852,7 +1884,7 @@ int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
const u8 *fw_data, unsigned int size, int force);
int t4_fl_pkt_align(struct adapter *adap);
-unsigned int t4_flash_cfg_addr(struct adapter *adapter);
+int t4_flash_cfg_addr(struct adapter *adapter);
int t4_check_fw_version(struct adapter *adap);
int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
int t4_get_fw_version(struct adapter *adapter, u32 *vers);
@@ -1866,6 +1898,7 @@ void t4_dump_version_info(struct adapter *adapter);
int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
const u8 *fw_data, unsigned int fw_size,
struct fw_hdr *card_fw, enum dev_state state, int *reset);
+enum chip_type t4_get_chip_type(struct adapter *adap, int ver);
int t4_prep_adapter(struct adapter *adapter);
int t4_shutdown_adapter(struct adapter *adapter);
@@ -1881,6 +1914,7 @@ unsigned int qtimer_val(const struct adapter *adap,
const struct sge_rspq *q);
int t4_init_devlog_params(struct adapter *adapter);
+unsigned int t4_sge_get_qpp(struct adapter *adap, unsigned int qtype);
int t4_init_sge_params(struct adapter *adapter);
int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
@@ -1909,24 +1943,41 @@ void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
+u8 t4_get_tp_port_chan(struct adapter *adap, u8 pidx);
unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
+void t4_pmrx_cache_get_stats(struct adapter *adap, u32 stats[]);
+u8 t4_cim_num_ibq(struct adapter *adap);
+u8 t4_cim_num_obq(struct adapter *adap);
+void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
+ u16 *size, u16 *thres);
int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
size_t n);
+int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n);
int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
size_t n);
+int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n, unsigned int *valp);
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
unsigned int *valp);
+int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n,
+ const unsigned int *valp);
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
const unsigned int *valp);
+int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
+ u32 *wrptr);
int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
unsigned int *pif_req_wrptr,
unsigned int *pif_rsp_wrptr);
void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
+int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n);
const char *t4_get_port_type_description(enum fw_port_type port_type);
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
void t4_get_port_stats_offset(struct adapter *adap, int idx,
@@ -2057,6 +2108,7 @@ int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
int filter_index, int enable);
void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
int filter_index, int *enabled);
+void t4_set_trace_rss_control(struct adapter *adap, u8 chan, u16 qid);
int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
u32 addr, u32 val);
void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
@@ -2089,9 +2141,15 @@ void t4_uld_mem_free(struct adapter *adap);
int t4_uld_mem_alloc(struct adapter *adap);
void t4_uld_clean_up(struct adapter *adap);
void t4_register_netevent_notifier(void);
+int t4_i2c_io(struct adapter *adap, unsigned int mbox, int port,
+ unsigned int devid, unsigned int offset,
+ unsigned int len, u8 *buf, bool write);
int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
unsigned int devid, unsigned int offset,
unsigned int len, u8 *buf);
+int t4_i2c_wr(struct adapter *adap, unsigned int mbox, int port,
+ unsigned int devid, unsigned int offset,
+ unsigned int len, u8 *buf);
int t4_load_boot(struct adapter *adap, u8 *boot_data,
unsigned int boot_addr, unsigned int size);
int t4_load_bootcfg(struct adapter *adap,
@@ -2121,6 +2179,12 @@ void cxgb4_write_partial_sgl(const struct sk_buff *skb, struct sge_txq *q,
void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
u16 vlan);
+
+/* Flash Layout helpers */
+int t4_flash_location_start_sec(struct adapter *adap, enum t4_flash_loc loc);
+int t4_flash_location_nsecs(struct adapter *adap, enum t4_flash_loc loc);
+int t4_flash_location_start(struct adapter *adap, enum t4_flash_loc loc);
+int t4_flash_location_size(struct adapter *adap, enum t4_flash_loc loc);
int cxgb4_dcb_enabled(const struct net_device *dev);
int cxgb4_thermal_init(struct adapter *adap);
@@ -2153,4 +2217,5 @@ void cxgb4_port_mirror_free(struct net_device *dev);
#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
int cxgb4_set_ktls_feature(struct adapter *adap, bool enable);
#endif
+bool cxgb4_pcie_relaxed_ordering_enabled(struct adapter *adap);
#endif /* __CXGB4_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
index f521737d1275..e0b4b04d4aac 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
@@ -1081,7 +1081,7 @@ static const struct seq_operations devlog_seq_ops = {
static int devlog_open(struct inode *inode, struct file *file)
{
struct adapter *adap = inode->i_private;
- struct devlog_params *dparams = &adap->params.devlog;
+ struct devlog_params *dparams = &adap->params.devlogs;
struct devlog_info *dinfo;
unsigned int index;
u32 fseqno;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 5189016c3ef6..b7f0df9704a2 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -6199,23 +6199,6 @@ static void free_some_resources(struct adapter *adapter)
NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
#define SEGMENT_SIZE 128
-static int t4_get_chip_type(struct adapter *adap, int ver)
-{
- u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
-
- switch (ver) {
- case CHELSIO_T4:
- return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
- case CHELSIO_T5:
- return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
- case CHELSIO_T6:
- return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
- default:
- break;
- }
- return -EINVAL;
-}
-
#ifdef CONFIG_PCI_IOV
static void cxgb4_mgmt_setup(struct net_device *dev)
{
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index f761fc64c86e..e2437aabc75c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -39,6 +39,7 @@
#include "t4_values.h"
#include "t4fw_api.h"
#include "t4fw_version.h"
+#include <linux/kernel.h>
/**
* t4_wait_op_done_val - wait until an operation is completed
@@ -484,6 +485,39 @@ static int t4_edc_err_read(struct adapter *adap, int idx)
return 0;
}
+unsigned int t4_pcie_mem_access_base_win_reg(struct adapter *adap, int win)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return T7_PCIE_MEM_ACCESS_REG(T7_PCIE_MEM_ACCESS_BASE_WIN_A,
+ win);
+ return PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win);
+}
+
+unsigned int t4_pcie_mem_access_offset_reg(struct adapter *adap, int win)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return T7_PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET0_A,
+ win);
+
+ return PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win);
+}
+
+void t4_pcie_mem_access_offset_write(struct adapter *adap, u64 off, int win,
+ u32 pf)
+{
+ u32 reg = t4_pcie_mem_access_offset_reg(adap, win);
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ off >>= T7_MEMOFST_SHIFT_X;
+ t4_write_reg64(adap, reg, off | pf);
+ t4_read_reg64(adap, reg); /* Flush */
+ return;
+ }
+
+ t4_write_reg(adap, reg, off | pf);
+ t4_read_reg(adap, reg); /* Flush */
+}
+
/**
* t4_memory_rw_init - Get memory window relative offset, base, and size.
* @adap: the adapter
@@ -498,7 +532,7 @@ static int t4_edc_err_read(struct adapter *adap, int idx)
int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
u32 *mem_base, u32 *mem_aperture)
{
- u32 edc_size, mc_size, mem_reg;
+ u64 edc_size, mc_size, mem_reg;
/* Offset into the region of memory which is being accessed
* MEM_EDC0 = 0
@@ -507,15 +541,21 @@ int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
* MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
* MEM_HMA = 4
*/
- edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ edc_size = T7_EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
+ else
+ edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
+
if (mtype == MEM_HMA) {
*mem_off = 2 * (edc_size * 1024 * 1024);
} else if (mtype != MEM_MC1) {
*mem_off = (mtype * (edc_size * 1024 * 1024));
} else {
- mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
- MA_EXT_MEMORY0_BAR_A));
- *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ mc_size = T7_EXT_MEM0_SIZE_G(t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A));
+ else
+ mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A));
+ *mem_off = ((u64)(MEM_MC0 * edc_size + mc_size)) * 1024 * 1024;
}
/* Each PCI-E Memory Window is programmed with a window size -- or
@@ -526,14 +566,13 @@ int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
* space. For T4 this is an absolute PCI-E Bus Address. For T5
* the address is relative to BAR0.
*/
- mem_reg = t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
- win));
+ mem_reg = t4_read_reg(adap, t4_pcie_mem_access_base_win_reg(adap, win));
+
/* a dead adapter will return 0xffffffff for PIO reads */
if (mem_reg == 0xffffffff)
return -ENXIO;
- *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
+ *mem_aperture = 1ULL << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
*mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
if (is_t4(adap->params.chip))
*mem_base -= adap->t4_bar0;
@@ -615,9 +654,10 @@ void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
u32 len, void *hbuf, int dir)
{
- u32 pos, offset, resid, memoffset;
+ u32 offset, resid, memoffset;
u32 win_pf, mem_aperture, mem_base;
u32 *buf;
+ u64 pos;
int ret;
/* Argument sanity checks ...
@@ -653,7 +693,7 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
/* Set up initial PCI-E Memory Window to cover the start of our
* transfer.
*/
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
/* Transfer data to/from the adapter as long as there's an integral
* number of 32-bit transfers to complete.
@@ -708,7 +748,7 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
if (offset == mem_aperture) {
pos += mem_aperture;
offset = 0;
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
}
}
@@ -812,12 +852,10 @@ u32 t4_get_util_window(struct adapter *adap)
*/
void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
{
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
+ t4_write_reg(adap, t4_pcie_mem_access_base_win_reg(adap, window),
memwin_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
- t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
+ t4_read_reg(adap, t4_pcie_mem_access_base_win_reg(adap, window));
}
/**
@@ -837,6 +875,8 @@ unsigned int t4_get_regs_len(struct adapter *adapter)
case CHELSIO_T5:
case CHELSIO_T6:
return T5_REGMAP_SIZE;
+ case CHELSIO_T7:
+ return T7_REGMAP_SIZE;
}
dev_err(adapter->pdev_dev,
@@ -2638,6 +2678,648 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
0x51300, 0x51324,
};
+ static const unsigned int t7_reg_ranges[] = {
+ 0x1008, 0x101c,
+ 0x1024, 0x10a8,
+ 0x10b4, 0x10f8,
+ 0x1100, 0x1114,
+ 0x111c, 0x112c,
+ 0x1138, 0x113c,
+ 0x1144, 0x115c,
+ 0x1180, 0x1184,
+ 0x1190, 0x1194,
+ 0x11a0, 0x11a4,
+ 0x11b0, 0x11d0,
+ 0x11fc, 0x1278,
+ 0x1280, 0x1368,
+ 0x1700, 0x172c,
+ 0x173c, 0x1760,
+ 0x1800, 0x18fc,
+ 0x3000, 0x3044,
+ 0x30a4, 0x30b0,
+ 0x30b8, 0x30d8,
+ 0x30e0, 0x30e8,
+ 0x3140, 0x357c,
+ 0x35a8, 0x35cc,
+ 0x35e0, 0x35ec,
+ 0x3600, 0x37fc,
+ 0x3804, 0x3818,
+ 0x3880, 0x388c,
+ 0x3900, 0x3904,
+ 0x3910, 0x3978,
+ 0x3980, 0x399c,
+ 0x4700, 0x4720,
+ 0x4728, 0x475c,
+ 0x480c, 0x4814,
+ 0x4890, 0x489c,
+ 0x48a4, 0x48ac,
+ 0x48b8, 0x48bc,
+ 0x4900, 0x4924,
+ 0x4ffc, 0x4ffc,
+ 0x5500, 0x5624,
+ 0x56c4, 0x56ec,
+ 0x56f4, 0x5720,
+ 0x5728, 0x575c,
+ 0x580c, 0x5814,
+ 0x5890, 0x589c,
+ 0x58a4, 0x58ac,
+ 0x58b8, 0x58bc,
+ 0x5940, 0x598c,
+ 0x59b0, 0x59c8,
+ 0x59d0, 0x59dc,
+ 0x59fc, 0x5a18,
+ 0x5a60, 0x5a6c,
+ 0x5a80, 0x5a8c,
+ 0x5a94, 0x5a9c,
+ 0x5b94, 0x5bec,
+ 0x5bf8, 0x5bfc,
+ 0x5c10, 0x5c40,
+ 0x5c4c, 0x5e48,
+ 0x5e50, 0x5e94,
+ 0x5ea0, 0x5eb0,
+ 0x5ec0, 0x5ec0,
+ 0x5ec8, 0x5ed0,
+ 0x5ee0, 0x5ee0,
+ 0x5ef0, 0x5ef0,
+ 0x5f00, 0x5f04,
+ 0x5f0c, 0x5f10,
+ 0x5f20, 0x5f78,
+ 0x5f84, 0x5f88,
+ 0x5f90, 0x5fd8,
+ 0x6000, 0x6020,
+ 0x6028, 0x6030,
+ 0x6044, 0x609c,
+ 0x60a8, 0x60ac,
+ 0x60b8, 0x60ec,
+ 0x6100, 0x6104,
+ 0x6118, 0x611c,
+ 0x6150, 0x6150,
+ 0x6180, 0x61b8,
+ 0x7700, 0x77a8,
+ 0x77b0, 0x7888,
+ 0x78cc, 0x7970,
+ 0x7b00, 0x7b00,
+ 0x7b08, 0x7b0c,
+ 0x7b24, 0x7b84,
+ 0x7b8c, 0x7c2c,
+ 0x7c34, 0x7c40,
+ 0x7c48, 0x7c68,
+ 0x7c70, 0x7c7c,
+ 0x7d00, 0x7ddc,
+ 0x7de4, 0x7e38,
+ 0x7e40, 0x7e44,
+ 0x7e4c, 0x7e74,
+ 0x7e80, 0x7ee0,
+ 0x7ee8, 0x7f0c,
+ 0x7f20, 0x7f5c,
+ 0x8dc0, 0x8de8,
+ 0x8df8, 0x8e04,
+ 0x8e10, 0x8e30,
+ 0x8e7c, 0x8ee8,
+ 0x8f88, 0x8f88,
+ 0x8f90, 0x8fb0,
+ 0x8fb8, 0x9058,
+ 0x9074, 0x90f8,
+ 0x9100, 0x912c,
+ 0x9138, 0x9188,
+ 0x9400, 0x9414,
+ 0x9430, 0x9440,
+ 0x9454, 0x9454,
+ 0x945c, 0x947c,
+ 0x9498, 0x94b8,
+ 0x9600, 0x9600,
+ 0x9608, 0x9638,
+ 0x9640, 0x9704,
+ 0x9710, 0x971c,
+ 0x9800, 0x9804,
+ 0x9854, 0x9854,
+ 0x9c00, 0x9c6c,
+ 0x9c80, 0x9cec,
+ 0x9d00, 0x9d6c,
+ 0x9d80, 0x9dec,
+ 0x9e00, 0x9e6c,
+ 0x9e80, 0x9eec,
+ 0x9f00, 0x9f6c,
+ 0x9f80, 0x9fec,
+ 0xa000, 0xa06c,
+ 0xa080, 0xa0ec,
+ 0xa100, 0xa16c,
+ 0xa180, 0xa1ec,
+ 0xa200, 0xa26c,
+ 0xa280, 0xa2ec,
+ 0xa300, 0xa36c,
+ 0xa380, 0xa458,
+ 0xa460, 0xa4f8,
+ 0xd000, 0xd03c,
+ 0xd100, 0xd134,
+ 0xd200, 0xd214,
+ 0xd220, 0xd234,
+ 0xd240, 0xd254,
+ 0xd260, 0xd274,
+ 0xd280, 0xd294,
+ 0xd2a0, 0xd2b4,
+ 0xd2c0, 0xd2d4,
+ 0xd2e0, 0xd2f4,
+ 0xd300, 0xd31c,
+ 0xdfc0, 0xdfe0,
+ 0xe000, 0xe00c,
+ 0xf000, 0xf008,
+ 0xf010, 0xf06c,
+ 0x11000, 0x11014,
+ 0x11048, 0x11120,
+ 0x11130, 0x11144,
+ 0x11174, 0x11178,
+ 0x11190, 0x111a0,
+ 0x111e4, 0x112f0,
+ 0x11300, 0x1133c,
+ 0x11408, 0x1146c,
+ 0x12000, 0x12004,
+ 0x12060, 0x122c4,
+ 0x19040, 0x1906c,
+ 0x19078, 0x19080,
+ 0x1908c, 0x190e8,
+ 0x190f0, 0x190f8,
+ 0x19100, 0x19110,
+ 0x19120, 0x19124,
+ 0x19150, 0x19194,
+ 0x1919c, 0x191a0,
+ 0x191ac, 0x191c8,
+ 0x191d0, 0x191e4,
+ 0x19250, 0x19250,
+ 0x19258, 0x19268,
+ 0x19278, 0x19278,
+ 0x19280, 0x192b0,
+ 0x192bc, 0x192f0,
+ 0x19300, 0x19308,
+ 0x19310, 0x19318,
+ 0x19320, 0x19328,
+ 0x19330, 0x19330,
+ 0x19348, 0x1934c,
+ 0x193f8, 0x19428,
+ 0x19430, 0x19444,
+ 0x1944c, 0x1946c,
+ 0x19474, 0x1947c,
+ 0x19488, 0x194cc,
+ 0x194f0, 0x194f8,
+ 0x19c00, 0x19c48,
+ 0x19c50, 0x19c80,
+ 0x19c94, 0x19c98,
+ 0x19ca0, 0x19cdc,
+ 0x19ce4, 0x19cf8,
+ 0x19d00, 0x19d30,
+ 0x19d50, 0x19d80,
+ 0x19d94, 0x19d98,
+ 0x19da0, 0x19de0,
+ 0x19df0, 0x19e10,
+ 0x19e50, 0x19e6c,
+ 0x19ea0, 0x19ebc,
+ 0x19ec4, 0x19ef4,
+ 0x19f04, 0x19f2c,
+ 0x19f34, 0x19f34,
+ 0x19f40, 0x19f50,
+ 0x19f90, 0x19fb4,
+ 0x19fbc, 0x19fbc,
+ 0x19fc4, 0x19fc8,
+ 0x19fd0, 0x19fe4,
+ 0x1a000, 0x1a004,
+ 0x1a010, 0x1a06c,
+ 0x1a0b0, 0x1a0e4,
+ 0x1a0ec, 0x1a108,
+ 0x1a114, 0x1a130,
+ 0x1a138, 0x1a1c4,
+ 0x1a1fc, 0x1a29c,
+ 0x1a2a8, 0x1a2b8,
+ 0x1a2c0, 0x1a388,
+ 0x1a398, 0x1a3ac,
+ 0x1e008, 0x1e00c,
+ 0x1e040, 0x1e044,
+ 0x1e04c, 0x1e04c,
+ 0x1e284, 0x1e290,
+ 0x1e2c0, 0x1e2c0,
+ 0x1e2e0, 0x1e2e4,
+ 0x1e300, 0x1e384,
+ 0x1e3c0, 0x1e3c8,
+ 0x1e408, 0x1e40c,
+ 0x1e440, 0x1e444,
+ 0x1e44c, 0x1e44c,
+ 0x1e684, 0x1e690,
+ 0x1e6c0, 0x1e6c0,
+ 0x1e6e0, 0x1e6e4,
+ 0x1e700, 0x1e784,
+ 0x1e7c0, 0x1e7c8,
+ 0x1e808, 0x1e80c,
+ 0x1e840, 0x1e844,
+ 0x1e84c, 0x1e84c,
+ 0x1ea84, 0x1ea90,
+ 0x1eac0, 0x1eac0,
+ 0x1eae0, 0x1eae4,
+ 0x1eb00, 0x1eb84,
+ 0x1ebc0, 0x1ebc8,
+ 0x1ec08, 0x1ec0c,
+ 0x1ec40, 0x1ec44,
+ 0x1ec4c, 0x1ec4c,
+ 0x1ee84, 0x1ee90,
+ 0x1eec0, 0x1eec0,
+ 0x1eee0, 0x1eee4,
+ 0x1ef00, 0x1ef84,
+ 0x1efc0, 0x1efc8,
+ 0x1f008, 0x1f00c,
+ 0x1f040, 0x1f044,
+ 0x1f04c, 0x1f04c,
+ 0x1f284, 0x1f290,
+ 0x1f2c0, 0x1f2c0,
+ 0x1f2e0, 0x1f2e4,
+ 0x1f300, 0x1f384,
+ 0x1f3c0, 0x1f3c8,
+ 0x1f408, 0x1f40c,
+ 0x1f440, 0x1f444,
+ 0x1f44c, 0x1f44c,
+ 0x1f684, 0x1f690,
+ 0x1f6c0, 0x1f6c0,
+ 0x1f6e0, 0x1f6e4,
+ 0x1f700, 0x1f784,
+ 0x1f7c0, 0x1f7c8,
+ 0x1f808, 0x1f80c,
+ 0x1f840, 0x1f844,
+ 0x1f84c, 0x1f84c,
+ 0x1fa84, 0x1fa90,
+ 0x1fac0, 0x1fac0,
+ 0x1fae0, 0x1fae4,
+ 0x1fb00, 0x1fb84,
+ 0x1fbc0, 0x1fbc8,
+ 0x1fc08, 0x1fc0c,
+ 0x1fc40, 0x1fc44,
+ 0x1fc4c, 0x1fc4c,
+ 0x1fe84, 0x1fe90,
+ 0x1fec0, 0x1fec0,
+ 0x1fee0, 0x1fee4,
+ 0x1ff00, 0x1ff84,
+ 0x1ffc0, 0x1ffc8,
+ 0x30000, 0x30038,
+ 0x30100, 0x3017c,
+ 0x30190, 0x301a0,
+ 0x301a8, 0x301b8,
+ 0x301c4, 0x301c8,
+ 0x301d0, 0x301e0,
+ 0x30200, 0x30344,
+ 0x30400, 0x304b4,
+ 0x304c0, 0x3052c,
+ 0x30540, 0x3065c,
+ 0x30800, 0x30848,
+ 0x30850, 0x308a8,
+ 0x308b8, 0x308c0,
+ 0x308cc, 0x308dc,
+ 0x30900, 0x30904,
+ 0x3090c, 0x30914,
+ 0x3091c, 0x30928,
+ 0x30930, 0x3093c,
+ 0x30944, 0x30948,
+ 0x30954, 0x30974,
+ 0x3097c, 0x30980,
+ 0x30a00, 0x30a20,
+ 0x30a38, 0x30a3c,
+ 0x30a50, 0x30a50,
+ 0x30a80, 0x30a80,
+ 0x30a88, 0x30aa8,
+ 0x30ab0, 0x30ab4,
+ 0x30ac8, 0x30ad4,
+ 0x30b28, 0x30b84,
+ 0x30b98, 0x30bb8,
+ 0x30c98, 0x30d14,
+ 0x31000, 0x31020,
+ 0x31038, 0x3103c,
+ 0x31050, 0x31050,
+ 0x31080, 0x31080,
+ 0x31088, 0x310a8,
+ 0x310b0, 0x310b4,
+ 0x310c8, 0x310d4,
+ 0x31128, 0x31184,
+ 0x31198, 0x311b8,
+ 0x32000, 0x32038,
+ 0x32100, 0x3217c,
+ 0x32190, 0x321a0,
+ 0x321a8, 0x321b8,
+ 0x321c4, 0x321c8,
+ 0x321d0, 0x321e0,
+ 0x32200, 0x32344,
+ 0x32400, 0x324b4,
+ 0x324c0, 0x3252c,
+ 0x32540, 0x3265c,
+ 0x32800, 0x32848,
+ 0x32850, 0x328a8,
+ 0x328b8, 0x328c0,
+ 0x328cc, 0x328dc,
+ 0x32900, 0x32904,
+ 0x3290c, 0x32914,
+ 0x3291c, 0x32928,
+ 0x32930, 0x3293c,
+ 0x32944, 0x32948,
+ 0x32954, 0x32974,
+ 0x3297c, 0x32980,
+ 0x32a00, 0x32a20,
+ 0x32a38, 0x32a3c,
+ 0x32a50, 0x32a50,
+ 0x32a80, 0x32a80,
+ 0x32a88, 0x32aa8,
+ 0x32ab0, 0x32ab4,
+ 0x32ac8, 0x32ad4,
+ 0x32b28, 0x32b84,
+ 0x32b98, 0x32bb8,
+ 0x32c98, 0x32d14,
+ 0x33000, 0x33020,
+ 0x33038, 0x3303c,
+ 0x33050, 0x33050,
+ 0x33080, 0x33080,
+ 0x33088, 0x330a8,
+ 0x330b0, 0x330b4,
+ 0x330c8, 0x330d4,
+ 0x33128, 0x33184,
+ 0x33198, 0x331b8,
+ 0x34000, 0x34038,
+ 0x34100, 0x3417c,
+ 0x34190, 0x341a0,
+ 0x341a8, 0x341b8,
+ 0x341c4, 0x341c8,
+ 0x341d0, 0x341e0,
+ 0x34200, 0x34344,
+ 0x34400, 0x344b4,
+ 0x344c0, 0x3452c,
+ 0x34540, 0x3465c,
+ 0x34800, 0x34848,
+ 0x34850, 0x348a8,
+ 0x348b8, 0x348c0,
+ 0x348cc, 0x348dc,
+ 0x34900, 0x34904,
+ 0x3490c, 0x34914,
+ 0x3491c, 0x34928,
+ 0x34930, 0x3493c,
+ 0x34944, 0x34948,
+ 0x34954, 0x34974,
+ 0x3497c, 0x34980,
+ 0x34a00, 0x34a20,
+ 0x34a38, 0x34a3c,
+ 0x34a50, 0x34a50,
+ 0x34a80, 0x34a80,
+ 0x34a88, 0x34aa8,
+ 0x34ab0, 0x34ab4,
+ 0x34ac8, 0x34ad4,
+ 0x34b28, 0x34b84,
+ 0x34b98, 0x34bb8,
+ 0x34c98, 0x34d14,
+ 0x35000, 0x35020,
+ 0x35038, 0x3503c,
+ 0x35050, 0x35050,
+ 0x35080, 0x35080,
+ 0x35088, 0x350a8,
+ 0x350b0, 0x350b4,
+ 0x350c8, 0x350d4,
+ 0x35128, 0x35184,
+ 0x35198, 0x351b8,
+ 0x36000, 0x36038,
+ 0x36100, 0x3617c,
+ 0x36190, 0x361a0,
+ 0x361a8, 0x361b8,
+ 0x361c4, 0x361c8,
+ 0x361d0, 0x361e0,
+ 0x36200, 0x36344,
+ 0x36400, 0x364b4,
+ 0x364c0, 0x3652c,
+ 0x36540, 0x3665c,
+ 0x36800, 0x36848,
+ 0x36850, 0x368a8,
+ 0x368b8, 0x368c0,
+ 0x368cc, 0x368dc,
+ 0x36900, 0x36904,
+ 0x3690c, 0x36914,
+ 0x3691c, 0x36928,
+ 0x36930, 0x3693c,
+ 0x36944, 0x36948,
+ 0x36954, 0x36974,
+ 0x3697c, 0x36980,
+ 0x36a00, 0x36a20,
+ 0x36a38, 0x36a3c,
+ 0x36a50, 0x36a50,
+ 0x36a80, 0x36a80,
+ 0x36a88, 0x36aa8,
+ 0x36ab0, 0x36ab4,
+ 0x36ac8, 0x36ad4,
+ 0x36b28, 0x36b84,
+ 0x36b98, 0x36bb8,
+ 0x36c98, 0x36d14,
+ 0x37000, 0x37020,
+ 0x37038, 0x3703c,
+ 0x37050, 0x37050,
+ 0x37080, 0x37080,
+ 0x37088, 0x370a8,
+ 0x370b0, 0x370b4,
+ 0x370c8, 0x370d4,
+ 0x37128, 0x37184,
+ 0x37198, 0x371b8,
+ 0x38000, 0x380b0,
+ 0x380b8, 0x38130,
+ 0x38140, 0x38140,
+ 0x38150, 0x38154,
+ 0x38160, 0x381c4,
+ 0x381d0, 0x38204,
+ 0x3820c, 0x38214,
+ 0x3821c, 0x3822c,
+ 0x38244, 0x38244,
+ 0x38254, 0x38274,
+ 0x3827c, 0x38280,
+ 0x38300, 0x38304,
+ 0x3830c, 0x38314,
+ 0x3831c, 0x3832c,
+ 0x38344, 0x38344,
+ 0x38354, 0x38374,
+ 0x3837c, 0x38380,
+ 0x38400, 0x38424,
+ 0x38438, 0x3843c,
+ 0x38480, 0x38480,
+ 0x384a8, 0x384a8,
+ 0x384b0, 0x384b4,
+ 0x384c8, 0x38514,
+ 0x38600, 0x3860c,
+ 0x3861c, 0x38624,
+ 0x38900, 0x38924,
+ 0x38938, 0x3893c,
+ 0x38980, 0x38980,
+ 0x389a8, 0x389a8,
+ 0x389b0, 0x389b4,
+ 0x389c8, 0x38a14,
+ 0x38b00, 0x38b0c,
+ 0x38b1c, 0x38b24,
+ 0x38e00, 0x38e00,
+ 0x38e18, 0x38e20,
+ 0x38e38, 0x38e40,
+ 0x38e58, 0x38e60,
+ 0x38e78, 0x38e80,
+ 0x38e98, 0x38ea0,
+ 0x38eb8, 0x38ec0,
+ 0x38ed8, 0x38ee0,
+ 0x38ef8, 0x38f08,
+ 0x38f10, 0x38f2c,
+ 0x38f80, 0x38ffc,
+ 0x39080, 0x39080,
+ 0x39088, 0x39090,
+ 0x39100, 0x39108,
+ 0x39120, 0x39128,
+ 0x39140, 0x39148,
+ 0x39160, 0x39168,
+ 0x39180, 0x39188,
+ 0x391a0, 0x391a8,
+ 0x391c0, 0x391c8,
+ 0x391e0, 0x391e8,
+ 0x39200, 0x39200,
+ 0x39208, 0x39240,
+ 0x39300, 0x39300,
+ 0x39308, 0x39340,
+ 0x39400, 0x39400,
+ 0x39408, 0x39440,
+ 0x39500, 0x39500,
+ 0x39508, 0x39540,
+ 0x39600, 0x39600,
+ 0x39608, 0x39640,
+ 0x39700, 0x39700,
+ 0x39708, 0x39740,
+ 0x39800, 0x39800,
+ 0x39808, 0x39840,
+ 0x39900, 0x39900,
+ 0x39908, 0x39940,
+ 0x39a00, 0x39a04,
+ 0x39a10, 0x39a14,
+ 0x39a1c, 0x39aa8,
+ 0x39b00, 0x39ecc,
+ 0x3a000, 0x3a004,
+ 0x3a050, 0x3a084,
+ 0x3a090, 0x3a09c,
+ 0x3a93c, 0x3a93c,
+ 0x3b93c, 0x3b93c,
+ 0x3c93c, 0x3c93c,
+ 0x3d93c, 0x3d93c,
+ 0x3e000, 0x3e020,
+ 0x3e03c, 0x3e05c,
+ 0x3e100, 0x3e120,
+ 0x3e13c, 0x3e15c,
+ 0x3e200, 0x3e220,
+ 0x3e23c, 0x3e25c,
+ 0x3e300, 0x3e320,
+ 0x3e33c, 0x3e35c,
+ 0x3f000, 0x3f034,
+ 0x3f100, 0x3f130,
+ 0x3f200, 0x3f218,
+ 0x44000, 0x44014,
+ 0x44020, 0x44028,
+ 0x44030, 0x44030,
+ 0x44100, 0x44114,
+ 0x44120, 0x44128,
+ 0x44130, 0x44130,
+ 0x44200, 0x44214,
+ 0x44220, 0x44228,
+ 0x44230, 0x44230,
+ 0x44300, 0x44314,
+ 0x44320, 0x44328,
+ 0x44330, 0x44330,
+ 0x44400, 0x44414,
+ 0x44420, 0x44428,
+ 0x44430, 0x44430,
+ 0x44500, 0x44514,
+ 0x44520, 0x44528,
+ 0x44530, 0x44530,
+ 0x44714, 0x44718,
+ 0x44730, 0x44730,
+ 0x447c0, 0x447c0,
+ 0x447f0, 0x447f0,
+ 0x447f8, 0x447fc,
+ 0x45000, 0x45014,
+ 0x45020, 0x45028,
+ 0x45030, 0x45030,
+ 0x45100, 0x45114,
+ 0x45120, 0x45128,
+ 0x45130, 0x45130,
+ 0x45200, 0x45214,
+ 0x45220, 0x45228,
+ 0x45230, 0x45230,
+ 0x45300, 0x45314,
+ 0x45320, 0x45328,
+ 0x45330, 0x45330,
+ 0x45400, 0x45414,
+ 0x45420, 0x45428,
+ 0x45430, 0x45430,
+ 0x45500, 0x45514,
+ 0x45520, 0x45528,
+ 0x45530, 0x45530,
+ 0x45714, 0x45718,
+ 0x45730, 0x45730,
+ 0x457c0, 0x457c0,
+ 0x457f0, 0x457f0,
+ 0x457f8, 0x457fc,
+ 0x46000, 0x46010,
+ 0x46020, 0x46034,
+ 0x46040, 0x46050,
+ 0x46060, 0x46088,
+ 0x47000, 0x4709c,
+ 0x470c0, 0x470d4,
+ 0x47100, 0x471a8,
+ 0x471b0, 0x471e8,
+ 0x47200, 0x47210,
+ 0x4721c, 0x47230,
+ 0x47238, 0x47238,
+ 0x47240, 0x472ac,
+ 0x472d0, 0x472f4,
+ 0x47300, 0x47310,
+ 0x47318, 0x47348,
+ 0x47350, 0x47354,
+ 0x47380, 0x47388,
+ 0x47390, 0x47394,
+ 0x47400, 0x47448,
+ 0x47450, 0x47458,
+ 0x47500, 0x4751c,
+ 0x47530, 0x4754c,
+ 0x47560, 0x4757c,
+ 0x47590, 0x475ac,
+ 0x47600, 0x47630,
+ 0x47640, 0x47644,
+ 0x47660, 0x4769c,
+ 0x47700, 0x47710,
+ 0x47740, 0x47750,
+ 0x4775c, 0x4779c,
+ 0x477b0, 0x477bc,
+ 0x477c4, 0x477c8,
+ 0x477d4, 0x477fc,
+ 0x48000, 0x48004,
+ 0x48018, 0x4801c,
+ 0x49304, 0x49320,
+ 0x4932c, 0x4932c,
+ 0x49334, 0x493f0,
+ 0x49400, 0x49410,
+ 0x49460, 0x494f4,
+ 0x50000, 0x50084,
+ 0x50090, 0x500cc,
+ 0x50300, 0x50384,
+ 0x50400, 0x50404,
+ 0x50800, 0x50884,
+ 0x50890, 0x508cc,
+ 0x50b00, 0x50b84,
+ 0x50c00, 0x50c04,
+ 0x51000, 0x51020,
+ 0x51028, 0x510c4,
+ 0x51104, 0x51108,
+ 0x51200, 0x51274,
+ 0x51300, 0x51324,
+ 0x51400, 0x51548,
+ 0x51550, 0x51554,
+ 0x5155c, 0x51584,
+ 0x5158c, 0x515c8,
+ 0x515f0, 0x515f4,
+ 0x58000, 0x58004,
+ 0x58018, 0x5801c,
+ 0x59304, 0x59320,
+ 0x5932c, 0x5932c,
+ 0x59334, 0x593f0,
+ 0x59400, 0x59410,
+ 0x59460, 0x594f4,
+ };
+
u32 *buf_end = (u32 *)((char *)buf + buf_size);
const unsigned int *reg_ranges;
int reg_ranges_size, range;
@@ -2662,6 +3344,11 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
break;
+ case CHELSIO_T7:
+ reg_ranges = t7_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t7_reg_ranges);
+ break;
+
default:
dev_err(adap->pdev_dev,
"Unsupported chip version %d\n", chip_version);
@@ -2731,6 +3418,7 @@ int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
int t4_seeprom_wp(struct adapter *adapter, bool enable)
{
unsigned int v = enable ? 0xc : 0;
+
int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
return ret < 0 ? ret : 0;
}
@@ -2899,6 +3587,121 @@ int t4_get_pfres(struct adapter *adapter)
return 0;
}
+/* Flash Layout {start sector, # of sectors} for T4/T5/T6 adapters */
+static const struct t4_flash_loc_entry t4_flash_loc_arr[] = {
+ [FLASH_LOC_EXP_ROM] = { 0, 6 },
+ [FLASH_LOC_IBFT] = { 6, 1 },
+ [FLASH_LOC_BOOTCFG] = { 7, 1 },
+ [FLASH_LOC_FW] = { 8, 16 },
+ [FLASH_LOC_FWBOOTSTRAP] = { 27, 1 },
+ [FLASH_LOC_ISCSI_CRASH] = { 29, 1 },
+ [FLASH_LOC_FCOE_CRASH] = { 30, 1 },
+ [FLASH_LOC_CFG] = { 31, 1 },
+ [FLASH_LOC_CUDBG] = { 32, 32 },
+ [FLASH_LOC_BOOT_AREA] = { 0, 8 }, /* Spans complete Boot Area */
+ [FLASH_LOC_MIN_SIZE] = { 0, 32 }, /* Spans minimum required sections */
+ [FLASH_LOC_END] = { 0, 64 }, /* Spans the entire Serial Flash*/
+};
+
+/* Flash Layout {start sector, # of sectors} for T7 adapters */
+static const struct t4_flash_loc_entry t7_flash_loc_arr[] = {
+ [FLASH_LOC_VPD] = { 0, 1 },
+ [FLASH_LOC_FWBOOTSTRAP] = { 1, 1 },
+ [FLASH_LOC_FW] = { 2, 29 },
+ [FLASH_LOC_CFG] = { 31, 1 },
+ [FLASH_LOC_EXP_ROM] = { 32, 15 },
+ [FLASH_LOC_IBFT] = { 47, 1 },
+ [FLASH_LOC_BOOTCFG] = { 48, 1 },
+ [FLASH_LOC_ISCSI_CRASH] = { 62, 1 },
+ [FLASH_LOC_FCOE_CRASH] = { 63, 1 },
+ [FLASH_LOC_VPD_BACKUP] = { 64, 1 },
+ [FLASH_LOC_FWBOOTSTRAP_BACKUP] = { 65, 1 },
+ [FLASH_LOC_FW_BACKUP] = { 66, 29 },
+ [FLASH_LOC_CFG_BACK] = { 95, 1 },
+ [FLASH_LOC_CUDBG] = { 96, 48 },
+ [FLASH_LOC_CHIP_DUMP] = { 144, 48 },
+ [FLASH_LOC_BOOT_AREA] = { 32,
+ 17 }, /* Spans complete UEFI/PXE Boot Area */
+ [FLASH_LOC_MIN_SIZE] = { 0, 32 }, /* Spans minimum required sections */
+ [FLASH_LOC_END] = { 0, 256 }, /* Spans the entire Serial Flash*/
+};
+
+static const struct t4_flash_loc_entry *
+t4_flash_location_entry_get(struct adapter *adap, enum t4_flash_loc loc)
+{
+ const struct t4_flash_loc_entry *arr;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ arr = t7_flash_loc_arr;
+ else
+ arr = t4_flash_loc_arr;
+
+ return arr[loc].nsecs ? &arr[loc] : NULL;
+}
+
+int t4_flash_location_start_sec(struct adapter *adap, enum t4_flash_loc loc)
+{
+ const struct t4_flash_loc_entry *entry;
+
+ entry = t4_flash_location_entry_get(adap, loc);
+ if (!entry)
+ return -ENOENT;
+
+ return entry->start_sec;
+}
+
+int t4_flash_location_nsecs(struct adapter *adap, enum t4_flash_loc loc)
+{
+ const struct t4_flash_loc_entry *entry;
+
+ entry = t4_flash_location_entry_get(adap, loc);
+ if (!entry)
+ return -ENOENT;
+
+ return entry->nsecs;
+}
+
+int t4_flash_location_start(struct adapter *adap, enum t4_flash_loc loc)
+{
+ int ret = t4_flash_location_start_sec(adap, loc);
+
+ if (ret < 0)
+ return ret;
+
+ return FLASH_START(ret);
+}
+
+int t4_flash_location_size(struct adapter *adap, enum t4_flash_loc loc)
+{
+ int ret = t4_flash_location_nsecs(adap, loc);
+
+ if (ret < 0)
+ return ret;
+
+ return FLASH_MAX_SIZE(ret);
+}
+
+static int t4_flash_location_end(struct adapter *adap, enum t4_flash_loc loc)
+{
+ int ret = t4_flash_location_size(adap, loc);
+
+ if (ret < 0)
+ return ret;
+
+ return t4_flash_location_start(adap, loc) + ret;
+}
+
+static bool t4_flash_location_in_range(struct adapter *adap,
+ enum t4_flash_loc loc, u32 addr)
+{
+ int ret = t4_flash_location_end(adap, loc);
+
+ if (ret < 0)
+ return false;
+
+ return addr >= t4_flash_location_start(adap, loc) && addr < ret;
+}
+
/* serial flash and firmware constants */
enum {
SF_ATTEMPTS = 10, /* max retries for SF operations */
@@ -2934,8 +3737,15 @@ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
return -EINVAL;
if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
return -EBUSY;
- t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
- SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
+ if (is_t7(adapter->params.chip))
+ t4_write_reg(adapter, SF_OP_A, QUADREADDISABLE_F |
+ SF_LOCK_V(lock) | SF_CONT_V(cont) |
+ BYTECNT_V(byte_cnt - 1));
+ else
+ t4_write_reg(adapter, SF_OP_A,
+ SF_LOCK_V(lock) | SF_CONT_V(cont) |
+ BYTECNT_V(byte_cnt - 1));
+
ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
if (!ret)
*valp = t4_read_reg(adapter, SF_DATA_A);
@@ -3108,8 +3918,12 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
*/
int t4_get_fw_version(struct adapter *adapter, u32 *vers)
{
- return t4_read_flash(adapter, FLASH_FW_START +
- offsetof(struct fw_hdr, fw_ver), 1,
+ int ret = t4_flash_location_start(adapter, FLASH_LOC_FW);
+
+ if (ret < 0)
+ return ret;
+
+ return t4_read_flash(adapter, ret + offsetof(struct fw_hdr, fw_ver), 1,
vers, 0);
}
@@ -3122,8 +3936,12 @@ int t4_get_fw_version(struct adapter *adapter, u32 *vers)
*/
int t4_get_bs_version(struct adapter *adapter, u32 *vers)
{
- return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
- offsetof(struct fw_hdr, fw_ver), 1,
+ int ret = t4_flash_location_start(adapter, FLASH_LOC_FWBOOTSTRAP);
+
+ if (ret < 0)
+ return ret;
+
+ return t4_read_flash(adapter, ret + offsetof(struct fw_hdr, fw_ver), 1,
vers, 0);
}
@@ -3136,10 +3954,15 @@ int t4_get_bs_version(struct adapter *adapter, u32 *vers)
*/
int t4_get_tp_version(struct adapter *adapter, u32 *vers)
{
- return t4_read_flash(adapter, FLASH_FW_START +
- offsetof(struct fw_hdr, tp_microcode_ver),
- 1, vers, 0);
-}
+ int ret = t4_flash_location_start(adapter, FLASH_LOC_FW);
+
+ if (ret < 0)
+ return ret;
+
+ return t4_read_flash(adapter,
+ ret + offsetof(struct fw_hdr, tp_microcode_ver), 1,
+ vers, 0);
+}
/**
* t4_get_exprom_version - return the Expansion ROM version (if any)
@@ -3161,9 +3984,13 @@ int t4_get_exprom_version(struct adapter *adap, u32 *vers)
sizeof(u32))];
int ret;
- ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
- ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
- 0);
+ ret = t4_flash_location_start(adap, FLASH_LOC_EXP_ROM);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_read_flash(adap, ret, ARRAY_SIZE(exprom_header_buf),
+ exprom_header_buf, 0);
+
if (ret)
return ret;
@@ -3361,9 +4188,9 @@ void t4_dump_version_info(struct adapter *adapter)
*/
int t4_check_fw_version(struct adapter *adap)
{
- int i, ret, major, minor, micro;
- int exp_major, exp_minor, exp_micro;
unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
+ int exp_major, exp_minor, exp_micro;
+ int i, ret, major, minor, micro;
ret = t4_get_fw_version(adap, &adap->params.fw_vers);
/* Try multiple times before returning error */
@@ -3393,6 +4220,11 @@ int t4_check_fw_version(struct adapter *adap)
exp_minor = T6FW_MIN_VERSION_MINOR;
exp_micro = T6FW_MIN_VERSION_MICRO;
break;
+ case CHELSIO_T7:
+ exp_major = T7FW_MIN_VERSION_MAJOR;
+ exp_minor = T7FW_MIN_VERSION_MINOR;
+ exp_micro = T7FW_MIN_VERSION_MICRO;
+ break;
default:
dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
adap->chip);
@@ -3471,10 +4303,12 @@ int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
const struct fw_hdr *drv_fw;
drv_fw = &fw_info->fw_hdr;
+ ret = t4_flash_location_start(adap, FLASH_LOC_FW);
+ if (ret < 0)
+ return ret;
/* Read the header of the firmware on the card */
- ret = t4_read_flash(adap, FLASH_FW_START,
- sizeof(*card_fw) / sizeof(uint32_t),
+ ret = t4_read_flash(adap, ret, sizeof(*card_fw) / sizeof(uint32_t),
(uint32_t *)card_fw, 1);
if (ret == 0) {
card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
@@ -3584,12 +4418,18 @@ static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
* Return the address within the flash where the Firmware Configuration
* File is stored.
*/
-unsigned int t4_flash_cfg_addr(struct adapter *adapter)
+int t4_flash_cfg_addr(struct adapter *adapter)
{
- if (adapter->params.sf_size == 0x100000)
- return FLASH_FPGA_CFG_START;
+ int ret = t4_flash_location_end(adapter, FLASH_LOC_CFG);
+
+ /*
+ * If the device FLASH isn't large enough to hold a Firmware
+ * Configuration File, return an error.
+ */
+ if (ret < 0 || adapter->params.sf_size < ret)
+ return -ENOSPC;
else
- return FLASH_CFG_START;
+ return t4_flash_location_start(adapter, FLASH_LOC_CFG);
}
/* Return TRUE if the specified firmware matches the adapter. I.e. T4
@@ -3605,7 +4445,9 @@ static bool t4_fw_matches_chip(const struct adapter *adap,
*/
if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
(is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
- (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
+ (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6) ||
+ (is_t7(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T7))
+
return true;
dev_err(adap->pdev_dev,
@@ -3624,16 +4466,17 @@ static bool t4_fw_matches_chip(const struct adapter *adap,
*/
int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
{
- u32 csum;
- int ret, addr;
- unsigned int i;
- u8 first_page[SF_PAGE_SIZE];
- const __be32 *p = (const __be32 *)fw_data;
- const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
- unsigned int fw_start_sec = FLASH_FW_START_SEC;
- unsigned int fw_size = FLASH_FW_MAX_SIZE;
- unsigned int fw_start = FLASH_FW_START;
+ const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
+ const __be32 *p = (const __be32 *)fw_data;
+ u8 first_page[SF_PAGE_SIZE];
+ unsigned int fw_start_sec;
+ enum t4_flash_loc loc;
+ unsigned int fw_start;
+ unsigned int fw_size;
+ unsigned int i;
+ int ret, addr;
+ u32 csum;
if (!size) {
dev_err(adap->pdev_dev, "FW image has no data\n");
@@ -3649,6 +4492,20 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
"FW image size differs from size in FW header\n");
return -EINVAL;
}
+
+ loc = FLASH_LOC_FW;
+ ret = t4_flash_location_size(adap, loc);
+ if (ret < 0) {
+ dev_err(adap->pdev_dev,
+ "Error finding Flash location (%u). ret: %d\n", loc,
+ ret);
+ return ret;
+ }
+
+ fw_size = ret;
+ fw_start_sec = t4_flash_location_start_sec(adap, loc);
+ fw_start = t4_flash_location_start(adap, loc);
+
if (size > fw_size) {
dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
fw_size);
@@ -5684,7 +6541,7 @@ static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
ulprx_intr_info.details = ulprx_intr_details;
else if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T6)
- ulprx_intr_info.details = t6_ulprx_int_cause_details;
+ ulprx_intr_info.details = t6_ulprx_int_cause_details;
else
ulprx_intr_info.details = t7_ulprx_int_cause_details;
@@ -7415,6 +8272,17 @@ static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
return fatal;
}
+static u32 t4_port_reg(struct adapter *adap, u8 port, u32 reg)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return T7_PORT_REG(port, reg);
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T4)
+ return T5_PORT_REG(port, reg);
+
+ return PORT_REG(port, reg);
+}
+
/*
* MAC interrupt handler.
*/
@@ -8384,12 +9252,55 @@ int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
}
+/**
+ * t7_wait_sram_done - wait until an operation is completed
+ * @adapter: the adapter performing the operation
+ * @reg: the register to check for completion
+ * @result_reg: register that holds the result value
+ * @attempts: number of check iterations
+ * @delay: delay in usecs between iterations
+ * @valp: where to store the value of the result register at completion time
+ *
+ * Waits until a specific bit in @reg is cleared, checking up to
+ * @attempts times.Once the bit is cleared, reads from @result_reg
+ * and stores the value in @valp if it is not NULL. Returns 0 if the
+ * operation completes successfully and -EAGAIN if it times out.
+ */
+static int t7_wait_sram_done(struct adapter *adap, int reg, int result_reg,
+ int attempts, int delay, u32 *valp)
+{
+ while (1) {
+ u32 val = t4_read_reg(adap, reg);
+
+ /* Check if SramStart (bit 19) is cleared */
+ if (!(val & (1 << 19))) {
+ if (valp)
+ *valp = t4_read_reg(adap, result_reg);
+ return 0;
+ }
+
+ if (--attempts == 0)
+ return -EAGAIN;
+
+ if (delay)
+ udelay(delay);
+ }
+}
+
/* Read an RSS table row */
static int rd_rss_row(struct adapter *adap, int row, u32 *val)
{
- t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
- return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
- 5, 0, val);
+ int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ if (chip_ver < CHELSIO_T7) {
+ t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
+ return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A,
+ LKPTBLROWVLD_F, 1, 5, 0, val);
+ } else {
+ t4_write_reg(adap, TP_RSS_CONFIG_SRAM_A, 0xB0000 | row);
+ return t7_wait_sram_done(adap, TP_RSS_CONFIG_SRAM_A,
+ TP_RSS_LKP_TABLE_A, 5, 0, val);
+ }
}
/**
@@ -8819,6 +9730,7 @@ void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
{
t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
sleep_ok);
+
}
/**
@@ -9078,11 +9990,21 @@ void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
int idx, int enable)
{
- int i, ofst = idx * 4;
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ u32 match_ctl_a, match_ctl_b;
u32 data_reg, mask_reg, cfg;
+ int i, ofst = idx;
+
+ if (chip >= CHELSIO_T7) {
+ match_ctl_a = T7_MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = T7_MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ } else {
+ match_ctl_a = MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ }
if (!enable) {
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
+ t4_write_reg(adap, match_ctl_a, 0);
return 0;
}
@@ -9109,20 +10031,20 @@ int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
return -EINVAL;
/* stop the tracer we'll be changing */
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
+ t4_write_reg(adap, match_ctl_a, 0);
- idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
- data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
- mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
+ ofst *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
+ data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
+ mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
t4_write_reg(adap, data_reg, tp->data[i]);
t4_write_reg(adap, mask_reg, ~tp->mask[i]);
}
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
+ t4_write_reg(adap, match_ctl_b,
TFCAPTUREMAX_V(tp->snap_len) |
TFMINPKTSIZE_V(tp->min_len));
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
+ t4_write_reg(adap, match_ctl_b,
TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
(is_t4(adap->params.chip) ?
TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
@@ -9144,12 +10066,21 @@ int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
int *enabled)
{
- u32 ctla, ctlb;
- int i, ofst = idx * 4;
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ u32 match_ctl_a, match_ctl_b, ctla, ctlb;
u32 data_reg, mask_reg;
+ int i, ofst = idx;
+
+ if (chip >= CHELSIO_T7) {
+ match_ctl_a = T7_MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = T7_MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ } else {
+ match_ctl_a = MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ }
- ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
- ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
+ ctla = t4_read_reg(adap, match_ctl_a);
+ ctlb = t4_read_reg(adap, match_ctl_b);
if (is_t4(adap->params.chip)) {
*enabled = !!(ctla & TFEN_F);
@@ -9165,7 +10096,7 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
tp->skip_ofst = TFOFFSET_G(ctla);
tp->skip_len = TFLENGTH_G(ctla);
- ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
+ ofst *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
@@ -9175,6 +10106,37 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
}
}
+/**
+ * t4_set_trace_rss_control - configure the trace rss control register
+ * @adap: the adapter
+ * @chan: the channel number for RSS control
+ * @qid: queue number
+ *
+ * Configures the MPS tracing RSS control parameter for specified
+ * @chan channel and @qid queue number.
+ */
+void t4_set_trace_rss_control(struct adapter *adap, u8 chan, u16 qid)
+{
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ u32 mps_trc_rss_control;
+
+ switch (chip) {
+ case CHELSIO_T4:
+ mps_trc_rss_control = MPS_TRC_RSS_CONTROL_A;
+ break;
+ case CHELSIO_T5:
+ case CHELSIO_T6:
+ mps_trc_rss_control = MPS_T5_TRC_RSS_CONTROL_A;
+ break;
+ case CHELSIO_T7:
+ mps_trc_rss_control = T7_MPS_T5_TRC_RSS_CONTROL_A;
+ break;
+ }
+
+ t4_write_reg(adap, mps_trc_rss_control,
+ RSSCONTROL_V(chan) | QUEUENUMBER_V(qid));
+}
+
/**
* t4_pmtx_get_stats - returns the HW stats from PMTX
* @adap: the adapter
@@ -9185,8 +10147,9 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
*/
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
{
- int i;
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
u32 data[2];
+ int i;
for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
@@ -9196,7 +10159,9 @@ void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
} else {
t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
PM_TX_DBG_DATA_A, data, 2,
- PM_TX_DBG_STAT_MSB_A);
+ chip >= CHELSIO_T7 ?
+ T7_PM_TX_DBG_STAT_MSB_A :
+ PM_TX_DBG_STAT_MSB_A);
cycles[i] = (((u64)data[0] << 32) | data[1]);
}
}
@@ -9229,6 +10194,25 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
}
}
+/**
+ * t4_pmrx_cache_get_stats - returns the HW PMRX cache stats
+ * @adap: the adapter
+ * @stats: where to store the statistics
+ *
+ * Returns performance statistics of PMRX cache.
+ */
+void t4_pmrx_cache_get_stats(struct adapter *adap, u32 stats[])
+{
+ u8 i, j;
+
+ for (i = 0, j = 0; i < T7_PM_RX_CACHE_NSTATS / 3; i++, j += 3) {
+ t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0x100 + i);
+ stats[j] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
+ t4_read_indirect(adap, PM_RX_DBG_CTRL_A, PM_RX_DBG_DATA_A,
+ &stats[j + 1], 2, PM_RX_DBG_STAT_MSB_A);
+ }
+}
+
/**
* compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
* @adapter: the adapter
@@ -9251,8 +10235,10 @@ static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
case CHELSIO_T5:
switch (nports) {
case 1: return 0xf;
- case 2: return 3 << (2 * pidx);
- case 4: return 1 << pidx;
+ case 2:
+ return 3 << (2 * pidx);
+ case 4:
+ return 1 << pidx;
}
break;
@@ -9261,6 +10247,14 @@ static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
case 2: return 1 << (2 * pidx);
}
break;
+ case CHELSIO_T7:
+ switch (nports) {
+ case 1:
+ case 2:
+ case 4:
+ return 1 << pidx;
+ }
+ break;
}
dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
@@ -9336,36 +10330,87 @@ unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
}
/**
- * t4_get_tp_e2c_map - return the E2C channel map associated with a port
- * @adapter: the adapter
- * @pidx: the port index
+ * t4_get_num_ports - Save the FW initialized # of active ports from registers.
+ * @adap: the adapter
+ *
+ * Save the number of FW initialized active ports from hardware registers.
+ * For <= T6, the number of active ports is same as available from MPS.
+ * For > T6, the number of active ports is based on configured TP Load
+ * Balancer Mode. This function must be called after FW is initialized
+ * to ensure the TP Load Balancer Mode had been configured for > T6.
*/
-static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
+static void t4_get_tp_num_ports(struct adapter *adap)
{
- unsigned int nports;
- u32 param, val = 0;
- int ret;
+ u32 val = 0;
- nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
- if (pidx >= nports) {
- CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
- pidx, nports);
- return 0;
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ t4_tp_pio_read(adap, &val, 1, TP_CHANNEL_MAP_A, false);
+ adap->params.tp.lb_mode = T7_LB_MODE_G(val);
+
+ switch (adap->params.tp.lb_mode) {
+ case 0:
+ adap->params.tp.nports = 4;
+ break;
+ case 2:
+ adap->params.tp.nports = 2;
+ break;
+ default:
+ adap->params.tp.nports = 1;
+ break;
+ }
+ } else {
+ val = t4_read_reg(adap, MPS_CMN_CTL_A);
+ adap->params.tp.lb_mode = 0;
+ adap->params.tp.nports = 1 << NUMPORTS_G(val);
}
+}
- /* FW version >= 1.16.44.0 can determine E2C channel map using
- * FW_PARAMS_PARAM_DEV_TPCHMAP API.
- */
- param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
- FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
- ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
- 0, 1, ¶m, &val);
+/**
+ * t4_get_tp_channel_map - fetch and save the configured TP Channel Map
+ * @adap: the adapter
+ *
+ * Fetch and save the configured TP Channel Map.
+ */
+static void t4_get_tp_channel_map(struct adapter *adap)
+{
+ u32 param, val = 0;
+ int ret;
+ u8 i;
+
+ param = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
+ FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP);
+ ret = t4_query_params_ns(adap, adap->mbox, adap->pf, 0, 1, ¶m,
+ &val);
if (!ret)
- return (val >> (8 * pidx)) & 0xff;
+ for (i = 0; i < NCHAN; i++)
+ adap->params.tp.channel_map[i] = (val >> (8 * i)) &
+ 0xff;
+}
- return 0;
+/**
+ * t4_get_tp_port_chan - Get the associated TP channel for the port
+ * @adap: the adapter
+ * @pidx: the port ID for which to get the TP channel
+ *
+ * Get the associated TP channel for the port.
+ */
+u8 t4_get_tp_port_chan(struct adapter *adap, u8 pidx)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T6)
+ return pidx;
+
+ return adap->params.tp.channel_map[pidx];
}
+/**
+ * t4_get_tp_e2c_map - return the E2C channel map associated with a port
+ * @adapter: the adapter
+ * @pidx: the port index
+ */
+static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
+{
+ return adapter->params.tp.channel_map[pidx];
+}
/**
* t4_get_tp_ch_map - return TP ingress channels associated with a port
* @adap: the adapter
@@ -9378,13 +10423,7 @@ static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
{
unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
- unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
-
- if (pidx >= nports) {
- dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
- pidx, nports);
- return 0;
- }
+ u8 nports = adap->params.tp.nports;
switch (chip_version) {
case CHELSIO_T4:
@@ -9395,8 +10434,10 @@ unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
*/
switch (nports) {
case 1: return 0xf;
- case 2: return 3 << (2 * pidx);
- case 4: return 1 << pidx;
+ case 2:
+ return 3 << (2 * pidx);
+ case 4:
+ return 1 << pidx;
}
break;
@@ -9406,6 +10447,14 @@ unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
case 2: return 1 << pidx;
}
break;
+ case CHELSIO_T7:
+ switch (nports) {
+ case 1:
+ case 2:
+ case 4:
+ return 1 << pidx;
+ }
+ break;
}
dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
@@ -9419,37 +10468,76 @@ unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
*/
const char *t4_get_port_type_description(enum fw_port_type port_type)
{
- static const char *const port_type_description[] = {
- "Fiber_XFI",
- "Fiber_XAUI",
- "BT_SGMII",
- "BT_XFI",
- "BT_XAUI",
- "KX4",
- "CX4",
- "KX",
- "KR",
- "SFP",
- "BP_AP",
- "BP4_AP",
- "QSFP_10G",
- "QSA",
- "QSFP",
- "BP40_BA",
- "KR4_100G",
- "CR4_QSFP",
- "CR_QSFP",
- "CR2_QSFP",
- "SFP28",
- "KR_SFP28",
- "KR_XLAUI"
- };
+ static const char *const port_type_description[] = { "Fiber_XFI",
+ "Fiber_XAUI",
+ "BT_SGMII",
+ "BT_XFI",
+ "BT_XAUI",
+ "KX4",
+ "CX4",
+ "KX",
+ "KR",
+ "SFP",
+ "BP_AP",
+ "BP4_AP",
+ "QSFP_10G",
+ "QSA",
+ "QSFP",
+ "BP40_BA",
+ "KR4_100G",
+ "CR4_QSFP",
+ "CR_QSFP",
+ "CR2_QSFP",
+ "SFP28",
+ "KR_SFP28",
+ "KR_XLAUI",
+ "BARE_LINK_50G",
+ "BARE_LINK_100G",
+ "BARE_LINK_200G",
+ "SFP56",
+ "QSFP56",
+ "QSFP56_4_50G",
+ "KR_50G",
+ "KR2_100G",
+ "KR4_200G",
+ "QSFP56_2_50G",
+ "OSFP",
+ "QSFPDD",
+ "OSFP_2_200G",
+ "QSFP_4_100G",
+ "QSFPDD_2_200G",
+ "KR8_400G" };
if (port_type < ARRAY_SIZE(port_type_description))
return port_type_description[port_type];
return "UNKNOWN";
}
+static u64 t4_get_port_stats_lb_mode(struct adapter *adap, int idx, u32 reg)
+{
+ u8 i, n, start;
+ u64 s = 0;
+
+ start = t4_get_tp_port_chan(adap, idx);
+
+ switch (adap->params.tp.lb_mode) {
+ case 0:
+ n = 1;
+ break;
+ case 2:
+ n = 2;
+ break;
+ default:
+ n = 4;
+ break;
+ }
+
+ for (i = 0; i < n; i++)
+ s += t4_read_reg64(adap, t4_port_reg(adap, start + i, reg));
+
+ return s;
+}
+
/**
* t4_get_port_stats_offset - collect port stats relative to a previous
* snapshot
@@ -9482,13 +10570,11 @@ void t4_get_port_stats_offset(struct adapter *adap, int idx,
*/
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
{
- u32 bgmap = t4_get_mps_bg_map(adap, idx);
u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
+ u32 bgmap = t4_get_mps_bg_map(adap, idx);
#define GET_STAT(name) \
- t4_read_reg64(adap, \
- (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
- T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
+ t4_get_port_stats_lb_mode(adap, idx, MPS_PORT_STAT_##name##_L);
#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
p->tx_octets = GET_STAT(TX_PORT_BYTES);
@@ -9582,10 +10668,7 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
u32 bgmap = t4_get_mps_bg_map(adap, idx);
#define GET_STAT(name) \
- t4_read_reg64(adap, \
- (is_t4(adap->params.chip) ? \
- PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
- T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
+ t4_get_port_stats_lb_mode(adap, idx, MPS_PORT_STAT_LB_PORT_##name##_L);
#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
p->octets = GET_STAT(BYTES);
@@ -9866,6 +10949,7 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state)
break;
case CHELSIO_T6:
+ case CHELSIO_T7:
sge_idma_decode = (const char **)t6_decode;
sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
break;
@@ -11185,18 +12269,23 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
*
* Returns a negative error number or the number of filters freed.
*/
-int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
- unsigned int viid, unsigned int naddr,
- const u8 **addr, bool sleep_ok)
+int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
+ unsigned int naddr, const u8 **addr, bool sleep_ok)
{
int offset, ret = 0;
struct fw_vi_mac_cmd c;
unsigned int nfilters = 0;
- unsigned int max_naddr = is_t4(adap->params.chip) ?
- NUM_MPS_CLS_SRAM_L_INSTANCES :
- NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+ unsigned int max_naddr = 0;
unsigned int rem = naddr;
+ if (is_t4(adap->params.chip))
+ max_naddr = NUM_MPS_CLS_SRAM_L_INSTANCES;
+ else if (is_t7(adap->params.chip))
+ /* In T7 there 3 TCAM each of 512 size*/
+ max_naddr = NUM_MPS_T5_CLS_SRAM_L_INSTANCES * 3;
+ else
+ max_naddr = NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+
if (naddr > max_naddr)
return -EINVAL;
@@ -11812,7 +12901,7 @@ void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
lc->link_down_rc = linkdnrc;
dev_warn_ratelimited(adapter->pdev_dev,
"Port %d link down, reason: %s\n",
- pi->tx_chan,
+ pi->lport,
t4_link_down_rc_str(linkdnrc));
}
lc->link_ok = link_ok;
@@ -11888,7 +12977,7 @@ int t4_update_port_info(struct port_info *pi)
memset(&port_cmd, 0, sizeof(port_cmd));
port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F |
- FW_PORT_CMD_PORTID_V(pi->tx_chan));
+ FW_PORT_CMD_PORTID_V(pi->lport));
port_cmd.action_to_len16 = cpu_to_be32(
FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
? FW_PORT_ACTION_GET_PORT_INFO
@@ -11926,7 +13015,7 @@ int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
memset(&port_cmd, 0, sizeof(port_cmd));
port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F |
- FW_PORT_CMD_PORTID_V(pi->tx_chan));
+ FW_PORT_CMD_PORTID_V(pi->lport));
action = (fw_caps == FW_CAPS16
? FW_PORT_ACTION_GET_PORT_INFO
: FW_PORT_ACTION_GET_PORT_INFO32);
@@ -12091,9 +13180,12 @@ static int t4_get_flash_params(struct adapter *adap)
unsigned int part, manufacturer;
unsigned int density, size = 0;
+ int ret, min_size;
u32 flashid = 0;
- int ret;
+ min_size = t4_flash_location_end(adap, FLASH_LOC_MIN_SIZE);
+ if (min_size < 0)
+ return min_size;
/* Issue a Read ID Command to the Flash part. We decode supported
* Flash parts and their sizes from this. There's a newer Query
* Command which can retrieve detailed geometry information but many
@@ -12227,12 +13319,36 @@ static int t4_get_flash_params(struct adapter *adap)
adap->params.sf_nsec = size / SF_SEC_SIZE;
found:
- if (adap->params.sf_size < FLASH_MIN_SIZE)
+ if (adap->params.sf_size < min_size)
dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
- flashid, adap->params.sf_size, FLASH_MIN_SIZE);
+ flashid, adap->params.sf_size, min_size);
return 0;
}
+/**
+ * t4_get_chip_type - Determine chip type from device ID
+ * @adap: the adapter
+ * @ver: adapter version
+ */
+enum chip_type t4_get_chip_type(struct adapter *adap, int ver)
+{
+ u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
+
+ switch (ver) {
+ case CHELSIO_T4:
+ return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
+ case CHELSIO_T5:
+ return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
+ case CHELSIO_T6:
+ return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
+ case CHELSIO_T7:
+ return CHELSIO_CHIP_CODE(CHELSIO_T7, pl_rev);
+ default:
+ break;
+ }
+ return -EINVAL;
+}
+
/**
* t4_prep_adapter - prepare SW and HW for operation
* @adapter: the adapter
@@ -12244,26 +13360,22 @@ static int t4_get_flash_params(struct adapter *adap)
int t4_prep_adapter(struct adapter *adapter)
{
int ret, ver;
- uint16_t device_id;
- u32 pl_rev;
get_pci_mode(adapter, &adapter->params.pci);
- pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
-
ret = t4_get_flash_params(adapter);
if (ret < 0) {
dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
return ret;
}
-
/* Retrieve adapter's device ID
*/
- pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
- ver = device_id >> 12;
- adapter->params.chip = 0;
+ pci_read_config_word(adapter->pdev, PCI_DEVICE_ID,
+ &adapter->params.pci.device_id);
+ pci_read_config_word(adapter->pdev, PCI_VENDOR_ID,
+ &adapter->params.pci.vendor_id);
+ ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
switch (ver) {
case CHELSIO_T4:
- adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
adapter->params.arch.sge_fl_db = DBPRIO_F;
adapter->params.arch.mps_tcam_size =
NUM_MPS_CLS_SRAM_L_INSTANCES;
@@ -12275,9 +13387,9 @@ int t4_prep_adapter(struct adapter *adapter)
* MPS can have 4 priority per port.
*/
adapter->params.arch.cng_ch_bits_log = 2;
+ adapter->params.cim_la_size = CIMLA_SIZE;
break;
case CHELSIO_T5:
- adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
adapter->params.arch.mps_tcam_size =
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
@@ -12286,9 +13398,9 @@ int t4_prep_adapter(struct adapter *adapter)
adapter->params.arch.pm_stats_cnt = PM_NSTATS;
adapter->params.arch.vfcount = 128;
adapter->params.arch.cng_ch_bits_log = 2;
+ adapter->params.cim_la_size = CIMLA_SIZE;
break;
case CHELSIO_T6:
- adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
adapter->params.arch.sge_fl_db = 0;
adapter->params.arch.mps_tcam_size =
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
@@ -12300,14 +13412,29 @@ int t4_prep_adapter(struct adapter *adapter)
* MPS can have 8 priority per port.
*/
adapter->params.arch.cng_ch_bits_log = 3;
+ adapter->params.cim_la_size = CIMLA_SIZE_T6;
+ break;
+ case CHELSIO_T7:
+ adapter->params.arch.sge_fl_db = 0;
+ /* In T7 there 3 TCAM each of 512 size*/
+ adapter->params.arch.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES * 3;
+ adapter->params.arch.mps_rplc_size = 256;
+ adapter->params.arch.nchan = NCHAN;
+ adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
+ adapter->params.arch.vfcount = 256;
+ /*
+ * Congestion map will be for 4 channels so that
+ * MPS can have 4 priority per port.
+ */
+ adapter->params.arch.cng_ch_bits_log = 2;
+ adapter->params.cim_la_size = CIMLA_SIZE_T6;
break;
default:
dev_err(adapter->pdev_dev, "Device %d is not supported\n",
- device_id);
+ adapter->params.pci.device_id);
return -EINVAL;
}
- adapter->params.cim_la_size = CIMLA_SIZE;
init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
/*
@@ -12317,9 +13444,6 @@ int t4_prep_adapter(struct adapter *adapter)
adapter->params.portvec = 1;
adapter->params.vpd.cclk = 50000;
- /* Set PCIe completion timeout to 4 seconds. */
- pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
- PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
return 0;
}
@@ -12342,9 +13466,12 @@ int t4_shutdown_adapter(struct adapter *adapter)
t4_intr_disable(adapter);
t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
for_each_port(adapter, port) {
- u32 a_port_cfg = is_t4(adapter->params.chip) ?
- PORT_REG(port, XGMAC_PORT_CFG_A) :
- T5_PORT_REG(port, MAC_PORT_CFG_A);
+ u32 a_port_cfg;
+
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T4)
+ a_port_cfg = t4_port_reg(adapter, port, MAC_PORT_CFG_A);
+ else
+ a_port_cfg = PORT_REG(port, XGMAC_PORT_CFG_A);
t4_write_reg(adapter, a_port_cfg,
t4_read_reg(adapter, a_port_cfg)
@@ -12454,10 +13581,10 @@ int t4_bar2_sge_qregs(struct adapter *adapter,
*/
int t4_init_devlog_params(struct adapter *adap)
{
- struct devlog_params *dparams = &adap->params.devlog;
- u32 pf_dparams;
- unsigned int devlog_meminfo;
+ struct devlog_params *dparams = adap->params.devlog;
+ u32 nentries128, size, start, pf_dparams;
struct fw_devlog_cmd devlog_cmd;
+ u8 i, memtype, ncount;
int ret;
/* If we're dealing with newer firmware, the Device Log Parameters
@@ -12467,16 +13594,13 @@ int t4_init_devlog_params(struct adapter *adap)
pf_dparams =
t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
if (pf_dparams) {
- unsigned int nentries, nentries128;
-
- dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
- dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
-
+ ncount = ((PCIE_FW_PF_DEVLOG_COUNT_MSB_G(pf_dparams) << 1) |
+ PCIE_FW_PF_DEVLOG_COUNT_LSB_G(pf_dparams));
+ memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
+ start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
- nentries = (nentries128 + 1) * 128;
- dparams->size = nentries * sizeof(struct fw_devlog_e);
-
- return 0;
+ size = (nentries128 + 1) * 128 * sizeof(struct fw_devlog_e);
+ goto out_copy;
}
/* Otherwise, ask the firmware for its Device Log Parameters.
@@ -12490,15 +13614,41 @@ int t4_init_devlog_params(struct adapter *adap)
if (ret)
return ret;
- devlog_meminfo =
- be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
- dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
- dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
- dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
+ pf_dparams = be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
+ memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(pf_dparams);
+ start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(pf_dparams) << 4;
+ size = be32_to_cpu(devlog_cmd.memsize_devlog);
+ ncount = 0;
+
+out_copy:
+ adap->params.num_up_cores = 1 << ncount;
+ for (i = 0; i < adap->params.num_up_cores; i++) {
+ dparams[i].memtype = memtype;
+ dparams[i].start = start;
+ dparams[i].size = size / adap->params.num_up_cores;
+ start += dparams[i].size;
+ }
return 0;
}
+/**
+ * t4_sge_get_qpp - get the number of Egress or Ingress queues per page
+ * @adap: the adapter
+ * @qtype: Egress or Ingress queue map register to read
+ *
+ * Fetches the number of Egress or Ingress queues per page.
+ */
+unsigned int t4_sge_get_qpp(struct adapter *adap, unsigned int qtype)
+{
+ unsigned int s_qpp, qpp;
+
+ s_qpp = (QUEUESPERPAGEPF0_S +
+ (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adap->pf);
+ qpp = t4_read_reg(adap, qtype);
+ return ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
+}
+
/**
* t4_init_sge_params - initialize adap->params.sge
* @adapter: the adapter
@@ -12508,8 +13658,7 @@ int t4_init_devlog_params(struct adapter *adap)
int t4_init_sge_params(struct adapter *adapter)
{
struct sge_params *sge_params = &adapter->params.sge;
- u32 hps, qpp;
- unsigned int s_hps, s_qpp;
+ u32 hps, s_hps;
/* Extract the SGE Page Size for our PF.
*/
@@ -12520,13 +13669,10 @@ int t4_init_sge_params(struct adapter *adapter)
/* Extract the SGE Egress and Ingess Queues Per Page for our PF.
*/
- s_qpp = (QUEUESPERPAGEPF0_S +
- (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
- qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
- sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
- qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
- sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
-
+ sge_params->eq_qpp =
+ t4_sge_get_qpp(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
+ sge_params->iq_qpp =
+ t4_sge_get_qpp(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
return 0;
}
@@ -12542,7 +13688,6 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
u32 param, val, v;
int chan, ret;
-
v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
adap->params.tp.tre = TIMERRESOLUTION_G(v);
adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
@@ -12551,6 +13696,12 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
for (chan = 0; chan < NCHAN; chan++)
adap->params.tp.tx_modq[chan] = chan;
+ /* Save the number of ports activated by FW */
+ t4_get_tp_num_ports(adap);
+
+ /* Save the TP Channel Map from FW */
+ t4_get_tp_channel_map(adap);
+
/* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
* Configuration.
*/
@@ -12607,21 +13758,48 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
* shift positions of several elements of the Compressed Filter Tuple
* for this adapter which we need frequently ...
*/
- adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
- adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
- adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
- adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
- adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
- adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
- PROTOCOL_F);
- adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
- ETHERTYPE_F);
- adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
- MACMATCH_F);
- adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
- MPSHITTYPE_F);
- adap->params.tp.frag_shift = t4_filter_field_shift(adap,
- FRAGMENTATION_F);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ adap->params.tp.fcoe_shift =
+ t4_filter_field_shift(adap, T7_FCOE_F);
+ adap->params.tp.port_shift =
+ t4_filter_field_shift(adap, T7_PORT_F);
+ adap->params.tp.vnic_shift =
+ t4_filter_field_shift(adap, T7_VNIC_ID_F);
+ adap->params.tp.vlan_shift =
+ t4_filter_field_shift(adap, T7_VLAN_F);
+ adap->params.tp.tos_shift =
+ t4_filter_field_shift(adap, T7_TOS_F);
+ adap->params.tp.protocol_shift =
+ t4_filter_field_shift(adap, T7_PROTOCOL_F);
+ adap->params.tp.ethertype_shift =
+ t4_filter_field_shift(adap, T7_ETHERTYPE_F);
+ adap->params.tp.macmatch_shift =
+ t4_filter_field_shift(adap, T7_MACMATCH_F);
+ adap->params.tp.matchtype_shift =
+ t4_filter_field_shift(adap, T7_MPSHITTYPE_F);
+ adap->params.tp.frag_shift =
+ t4_filter_field_shift(adap, T7_FRAGMENTATION_F);
+ } else {
+ adap->params.tp.fcoe_shift =
+ t4_filter_field_shift(adap, FCOE_F);
+ adap->params.tp.port_shift =
+ t4_filter_field_shift(adap, PORT_F);
+ adap->params.tp.vnic_shift =
+ t4_filter_field_shift(adap, VNIC_ID_F);
+ adap->params.tp.vlan_shift =
+ t4_filter_field_shift(adap, VLAN_F);
+ adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
+ adap->params.tp.protocol_shift =
+ t4_filter_field_shift(adap, PROTOCOL_F);
+ adap->params.tp.ethertype_shift =
+ t4_filter_field_shift(adap, ETHERTYPE_F);
+ adap->params.tp.macmatch_shift =
+ t4_filter_field_shift(adap, MACMATCH_F);
+ adap->params.tp.matchtype_shift =
+ t4_filter_field_shift(adap, MPSHITTYPE_F);
+ adap->params.tp.frag_shift =
+ t4_filter_field_shift(adap, FRAGMENTATION_F);
+ }
/* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
* represents the presence of an Outer VLAN instead of a VNIC ID.
@@ -12643,7 +13821,7 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
*
* Return the shift position of a filter field within the Compressed
* Filter Tuple. The filter field is specified via its selection bit
- * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
+ * within TP_VLAN_PRI_MAL (filter mode). E.g. VLAN_F.
*/
int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
{
@@ -12654,6 +13832,54 @@ int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
if ((filter_mode & filter_sel) == 0)
return -1;
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
+ switch (filter_mode & sel) {
+ case IPSECIDX_F:
+ field_shift += FT_IPSECIDX_W;
+ break;
+ case T7_FCOE_F:
+ field_shift += FT_FCOE_W;
+ break;
+ case T7_PORT_F:
+ field_shift += FT_PORT_W;
+ break;
+ case T7_VNIC_ID_F:
+ field_shift += FT_VNIC_ID_W;
+ break;
+ case T7_VLAN_F:
+ field_shift += FT_VLAN_W;
+ break;
+ case T7_TOS_F:
+ field_shift += FT_TOS_W;
+ break;
+ case T7_PROTOCOL_F:
+ field_shift += FT_PROTOCOL_W;
+ break;
+ case T7_ETHERTYPE_F:
+ field_shift += FT_ETHERTYPE_W;
+ break;
+ case T7_MACMATCH_F:
+ field_shift += FT_MACMATCH_W;
+ break;
+ case T7_MPSHITTYPE_F:
+ field_shift += FT_MPSHITTYPE_W;
+ break;
+ case T7_FRAGMENTATION_F:
+ field_shift += FT_FRAGMENTATION_W;
+ break;
+ case SYNONLY_F:
+ field_shift += FT_SYNONLY_W;
+ break;
+ case TCPFLAGS_F:
+ field_shift += FT_TCPFLAGS_W;
+ break;
+ }
+ }
+
+ goto out;
+ }
+
for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
switch (filter_mode & sel) {
case FCOE_F:
@@ -12688,6 +13914,8 @@ int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
break;
}
}
+
+out:
return field_shift;
}
@@ -12799,7 +14027,7 @@ int t4_init_portinfo(struct port_info *pi, int mbox,
return ret;
pi->viid = ret;
- pi->tx_chan = port;
+ pi->tx_chan = t4_get_tp_port_chan(pi->adapter, port);
pi->lport = port;
pi->rss_size = rss_size;
pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
@@ -12845,6 +14073,101 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
return 0;
}
+u8 t4_cim_num_ibq(struct adapter *adap)
+{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ return chip_ver >= CHELSIO_T7 ? CIM_NUM_IBQ_T7 : CIM_NUM_IBQ;
+}
+
+u8 t4_cim_num_obq(struct adapter *adap)
+{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ if (chip_ver >= CHELSIO_T7)
+ return CIM_NUM_OBQ_T7;
+
+ if (chip_ver > CHELSIO_T4)
+ return CIM_NUM_OBQ_T5;
+
+ return CIM_NUM_OBQ;
+}
+
+static void t4_read_cimq_cfg_ibq_core(struct adapter *adap, u8 coreid, u32 qid,
+ u16 *base, u16 *size, u16 *thres)
+{
+ unsigned int v, m;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ v = T7_IBQSELECT_F | T7_QUENUMSELECT_V(qid) |
+ CORESELECT_V(coreid);
+ /* value is in 512-byte units */
+ m = 512;
+ } else {
+ v = IBQSELECT_F | QUENUMSELECT_V(qid);
+ /* value is in 256-byte units */
+ m = 256;
+ }
+
+ t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, v);
+ v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
+ if (base)
+ *base = CIMQBASE_G(v) * m;
+ if (size)
+ *size = CIMQSIZE_G(v) * m;
+ if (thres)
+ *thres = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
+}
+
+static void t4_read_cimq_cfg_obq_core(struct adapter *adap, u8 coreid, u32 qid,
+ u16 *base, u16 *size)
+{
+ unsigned int v, m;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ v = T7_OBQSELECT_F | T7_QUENUMSELECT_V(qid) |
+ CORESELECT_V(coreid);
+ /* value is in 512-byte units */
+ m = 512;
+ } else {
+ v = OBQSELECT_F | QUENUMSELECT_V(qid);
+ /* value is in 256-byte units */
+ m = 256;
+ }
+
+ t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, v);
+ v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
+ if (base)
+ *base = CIMQBASE_G(v) * m;
+ if (size)
+ *size = CIMQSIZE_G(v) * m;
+}
+
+/**
+ * t4_read_cimq_cfg_core - read CIM queue configuration on specific core
+ * @adap: the adapter
+ * @coreid: the uP coreid
+ * @base: holds the queue base addresses in bytes
+ * @size: holds the queue sizes in bytes
+ * @thres: holds the queue full thresholds in bytes
+ *
+ * Returns the current configuration of the CIM queues, starting with
+ * the IBQs, then the OBQs, on a specific @coreid.
+ */
+void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
+ u16 *size, u16 *thres)
+{
+ unsigned int cim_num_ibq = t4_cim_num_ibq(adap);
+ unsigned int cim_num_obq = t4_cim_num_obq(adap);
+ unsigned int i;
+
+ for (i = 0; i < cim_num_ibq; i++, base++, size++, thres++)
+ t4_read_cimq_cfg_ibq_core(adap, coreid, i, base, size, thres);
+
+ for (i = 0; i < cim_num_obq; i++, base++, size++)
+ t4_read_cimq_cfg_obq_core(adap, coreid, i, base, size);
+}
+
int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
u16 *mirror_viid)
{
@@ -12873,73 +14196,78 @@ int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
*/
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
{
- unsigned int i, v;
- int cim_num_obq = is_t4(adap->params.chip) ?
- CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
+ t4_read_cimq_cfg_core(adap, 0, base, size, thres);
+}
- for (i = 0; i < CIM_NUM_IBQ; i++) {
- t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
- QUENUMSELECT_V(i));
- v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
- /* value is in 256-byte units */
- *base++ = CIMQBASE_G(v) * 256;
- *size++ = CIMQSIZE_G(v) * 256;
- *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
- }
- for (i = 0; i < cim_num_obq; i++) {
- t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
- QUENUMSELECT_V(i));
- v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
- /* value is in 256-byte units */
- *base++ = CIMQBASE_G(v) * 256;
- *size++ = CIMQSIZE_G(v) * 256;
- }
+static int t4_read_cim_ibq_data_core(struct adapter *adap, u8 coreid, u32 addr,
+ u32 *data)
+{
+ int ret, attempts;
+ unsigned int v;
+
+ /*
+ * It might take 3-10ms before the IBQ debug read access is allowed.
+ * Wait for 1 Sec with a delay of 1 usec.
+ */
+ attempts = 1000000;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ v = T7_IBQDBGADDR_V(addr) | IBQDBGCORE_V(coreid);
+ else
+ v = IBQDBGADDR_V(addr);
+
+ t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, v | IBQDBGEN_F);
+ ret = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
+ attempts, 1);
+ if (ret)
+ return ret;
+
+ *data = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
+ return 0;
}
/**
- * t4_read_cim_ibq - read the contents of a CIM inbound queue
+ * t4_read_cim_ibq_core - read the contents of a CIM inbound queue on
+ * specific core
* @adap: the adapter
+ * @coreid: the uP coreid
* @qid: the queue index
* @data: where to store the queue contents
* @n: capacity of @data in 32-bit words
*
* Reads the contents of the selected CIM queue starting at address 0 up
- * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
- * error and the number of 32-bit words actually read on success.
+ * to the capacity of @data on a specific @coreid. @n must be a multiple
+ * of 4. Returns < 0 on error and the number of 32-bit words actually
+ * read on success.
*/
-int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n)
{
- int i, err, attempts;
- unsigned int addr;
- const unsigned int nwords = CIM_IBQ_SIZE * 4;
+ unsigned int cim_num_ibq = t4_cim_num_ibq(adap);
+ u16 i, addr, nwords;
+ int ret;
- if (qid > 5 || (n & 3))
+ if (qid > (cim_num_ibq - 1) || (n & 3))
return -EINVAL;
- addr = qid * nwords;
+ t4_read_cimq_cfg_ibq_core(adap, coreid, qid, &addr, &nwords, NULL);
+ addr >>= sizeof(u16);
+ nwords >>= sizeof(u16);
if (n > nwords)
n = nwords;
- /* It might take 3-10ms before the IBQ debug read access is allowed.
- * Wait for 1 Sec with a delay of 1 usec.
- */
- attempts = 1000000;
-
- for (i = 0; i < n; i++, addr++) {
- t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
- IBQDBGEN_F);
- err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
- attempts, 1);
- if (err)
- return err;
- *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
+ for (i = 0; i < n; i++, addr++, data++) {
+ ret = t4_read_cim_ibq_data_core(adap, coreid, addr, data);
+ if (ret < 0)
+ return ret;
}
+
t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
return i;
}
-/**
- * t4_read_cim_obq - read the contents of a CIM outbound queue
+/*
+ * t4_read_cim_ibq - read the contents of a CIM inbound queue
* @adap: the adapter
* @qid: the queue index
* @data: where to store the queue contents
@@ -12949,38 +14277,126 @@ int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
* to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
* error and the number of 32-bit words actually read on success.
*/
-int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+{
+ return t4_read_cim_ibq_core(adap, 0, qid, data, n);
+}
+
+static int t4_read_cim_obq_data_core(struct adapter *adap, u8 coreid, u32 addr,
+ u32 *data)
+{
+ unsigned int v;
+ int ret;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ v = T7_OBQDBGADDR_V(addr) | OBQDBGCORE_V(coreid);
+ else
+ v = OBQDBGADDR_V(addr);
+
+ t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, v | OBQDBGEN_F);
+ ret = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, 2, 1);
+ if (ret)
+ return ret;
+
+ *data = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
+ return 0;
+}
+
+/**
+ * t4_read_cim_obq_core - read the contents of a CIM outbound queue on
+ * specific core
+ * @adap: the adapter
+ * @coreid: the uP coreid
+ * @qid: the queue index
+ * @data: where to store the queue contents
+ * @n: capacity of @data in 32-bit words
+ *
+ * Reads the contents of the selected CIM queue starting at address 0 up
+ * to the capacity of @data on specific @coreid. @n must be a multiple
+ * of 4. Returns < 0 on error and the number of 32-bit words actually
+ * read on success.
+ */
+int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n)
{
- int i, err;
- unsigned int addr, v, nwords;
- int cim_num_obq = is_t4(adap->params.chip) ?
- CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
+ unsigned int cim_num_obq = t4_cim_num_obq(adap);
+ u16 i, addr, nwords;
+ int ret;
if ((qid > (cim_num_obq - 1)) || (n & 3))
return -EINVAL;
- t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
- QUENUMSELECT_V(qid));
- v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
-
- addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
- nwords = CIMQSIZE_G(v) * 64; /* same */
+ t4_read_cimq_cfg_obq_core(adap, coreid, qid, &addr, &nwords);
+ addr >>= sizeof(u16);
+ nwords >>= sizeof(u16);
if (n > nwords)
n = nwords;
-
- for (i = 0; i < n; i++, addr++) {
- t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
- OBQDBGEN_F);
- err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
- 2, 1);
- if (err)
- return err;
- *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
+ for (i = 0; i < n; i++, addr++, data++) {
+ ret = t4_read_cim_obq_data_core(adap, coreid, addr, data);
+ if (ret < 0)
+ return ret;
}
+
t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
return i;
}
+/*
+ * t4_read_cim_obq - read the contents of a CIM outbound queue
+ * @adap: the adapter
+ * @qid: the queue index
+ * @data: where to store the queue contents
+ * @n: capacity of @data in 32-bit words
+ *
+ * Reads the contents of the selected CIM queue starting at address 0 up
+ * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
+ * error and the number of 32-bit words actually read on success.
+ */
+int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+{
+ return t4_read_cim_obq_core(adap, 0, qid, data, n);
+}
+
+/**
+ * t4_cim_read_core - read a block from CIM internal address space
+ * of a control register group on specific core.
+ * @adap: the adapter
+ * @group: the control register group to select for read
+ * @coreid: the uP coreid
+ * @addr: the start address within the CIM address space
+ * @n: number of words to read
+ * @valp: where to store the result
+ *
+ * Reads a block of 4-byte words from the CIM intenal address space
+ * of a control register @group on a specific @coreid.
+ */
+int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n, unsigned int *valp)
+{
+ unsigned int hostbusy, v = 0;
+ int ret = 0;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ hostbusy = T7_HOSTBUSY_F;
+ v = HOSTGRPSEL_V(group) | HOSTCORESEL_V(coreid);
+ } else {
+ hostbusy = HOSTBUSY_F;
+ }
+
+ if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & hostbusy)
+ return -EBUSY;
+
+ for (; !ret && n--; addr += 4) {
+ t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | v);
+ ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, hostbusy, 0, 5,
+ 2);
+ if (!ret)
+ *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
+ }
+
+ return ret;
+}
+
/**
* t4_cim_read - read a block from CIM internal address space
* @adap: the adapter
@@ -12993,18 +14409,48 @@ int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
unsigned int *valp)
{
+ return t4_cim_read_core(adap, 0, 0, addr, n, valp);
+}
+
+/**
+ * t4_cim_write_core - write a block into CIM internal address space
+ * of a control register group on specific core.
+ * @adap: the adapter
+ * @group: the control register group to select for write
+ * @coreid: the uP coreid
+ * @addr: the start address within the CIM address space
+ * @n: number of words to write
+ * @valp: set of values to write
+ *
+ * Writes a block of 4-byte words into the CIM intenal address space
+ * of a control register @group on a specific @coreid.
+ */
+int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n,
+ const unsigned int *valp)
+{
+ unsigned int hostbusy, v;
int ret = 0;
- if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ hostbusy = T7_HOSTBUSY_F;
+ v = T7_HOSTWRITE_F | HOSTGRPSEL_V(group) |
+ HOSTCORESEL_V(coreid);
+ } else {
+ hostbusy = HOSTBUSY_F;
+ v = HOSTWRITE_F;
+ }
+
+ if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & hostbusy)
return -EBUSY;
for ( ; !ret && n--; addr += 4) {
- t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
- ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
- 0, 5, 2);
- if (!ret)
- *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
+ t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
+ t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | v);
+ ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, hostbusy, 0, 5,
+ 2);
}
+
return ret;
}
@@ -13020,52 +14466,40 @@ int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
const unsigned int *valp)
{
- int ret = 0;
-
- if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
- return -EBUSY;
-
- for ( ; !ret && n--; addr += 4) {
- t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
- t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
- ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
- 0, 5, 2);
- }
- return ret;
-}
-
-static int t4_cim_write1(struct adapter *adap, unsigned int addr,
- unsigned int val)
-{
- return t4_cim_write(adap, addr, 1, &val);
+ return t4_cim_write_core(adap, 0, 0, addr, n, valp);
}
/**
- * t4_cim_read_la - read CIM LA capture buffer
+ * t4_cim_read_la_core - read CIM LA capture buffer on specific core
* @adap: the adapter
+ * @coreid: uP coreid
* @la_buf: where to store the LA data
- * @wrptr: the HW write pointer within the capture buffer
+ * @wrptr: the HW write pointer within the capture buffet4_init_portinfor
*
- * Reads the contents of the CIM LA buffer with the most recent entry at
- * the end of the returned data and with the entry at @wrptr first.
- * We try to leave the LA in the running state we find it in.
+ * Reads the contents of the CIM LA buffer on a specific @coreid
+ * with the most recent entry at the end of the returned data
+ * and with the entry at @wrptr first. We try to leave the LA
+ * in the running state we find it in.
*/
-int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
+int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
+ u32 *wrptr)
{
- int i, ret;
unsigned int cfg, val, idx;
+ int i, ret;
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &cfg);
if (ret)
return ret;
- if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
- ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
+ if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
+ val = 0;
+ ret = t4_cim_write_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (ret)
return ret;
}
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &val);
if (ret)
goto restart;
@@ -13074,25 +14508,29 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
*wrptr = idx;
for (i = 0; i < adap->params.cim_la_size; i++) {
- ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
- UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
+ val = UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F;
+ ret = t4_cim_write_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (ret)
break;
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (ret)
break;
if (val & UPDBGLARDEN_F) {
ret = -ETIMEDOUT;
break;
}
- ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_DATA_A, 1,
+ &la_buf[i]);
if (ret)
break;
/* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
* identify the 32-bit portion of the full 312-bit data
*/
- if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
+ if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
+ (idx & 0xf) >= 9)
idx = (idx & 0xff0) + 0x10;
else
idx++;
@@ -13101,14 +14539,33 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
}
restart:
if (cfg & UPDBGLAEN_F) {
- int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
- cfg & ~UPDBGLARDEN_F);
+ int r;
+
+ val = cfg & ~UPDBGLARDEN_F;
+ r = t4_cim_write_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (!ret)
ret = r;
}
+
return ret;
}
+/**
+ * t4_cim_read_la - read CIM LA capture buffer
+ * @adap: the adapter
+ * @la_buf: where to store the LA data
+ * @wrptr: the HW write pointer within the capture buffer
+ *
+ * Reads the contents of the CIM LA buffer with the most recent entry at
+ * the end of the returned data and with the entry at @wrptr first.
+ * We try to leave the LA in the running state we find it in.
+ */
+int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
+{
+ return t4_cim_read_la_core(adap, 0, la_buf, wrptr);
+}
+
/**
* t4_tp_read_la - read TP LA capture buffer
* @adap: the adapter
@@ -13293,10 +14750,10 @@ void t4_idma_monitor(struct adapter *adapter,
*/
int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
{
+ unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
+ unsigned int flash_cfg_start_sec, flash_cfg_size;
int ret, i, n, cfg_addr;
unsigned int addr;
- unsigned int flash_cfg_start_sec;
- unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
cfg_addr = t4_flash_cfg_addr(adap);
if (cfg_addr < 0)
@@ -13305,14 +14762,15 @@ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
addr = cfg_addr;
flash_cfg_start_sec = addr / SF_SEC_SIZE;
- if (size > FLASH_CFG_MAX_SIZE) {
+ flash_cfg_size = t4_flash_location_size(adap, FLASH_LOC_CFG);
+
+ if (size > flash_cfg_size) {
dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
- FLASH_CFG_MAX_SIZE);
+ flash_cfg_size);
return -EFBIG;
}
- i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
- sf_sec_size);
+ i = DIV_ROUND_UP(flash_cfg_size, sf_sec_size); /* # of sectors spanned */
ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
flash_cfg_start_sec + i - 1);
/* If size == 0 then we're simply erasing the FLASH sectors associated
@@ -13476,6 +14934,8 @@ int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ data[6] = be32_to_cpu(c.u.idctxt.ctxt_data6);
}
return ret;
}
@@ -13494,13 +14954,21 @@ int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
enum ctxt_type ctype, u32 *data)
{
int i, ret;
+ u32 end;
t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
- if (!ret)
- for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
- *data++ = t4_read_reg(adap, i);
- return ret;
+ if (ret)
+ return ret;
+
+ end = CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7 ?
+ SGE_CTXT_DATA6_A :
+ SGE_CTXT_DATA5_A;
+
+ for (i = SGE_CTXT_DATA0_A; i <= end; i += 4)
+ *data++ = t4_read_reg(adap, i);
+
+ return 0;
}
int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
@@ -13535,7 +15003,7 @@ int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
}
/**
- * t4_i2c_rd - read I2C data from adapter
+ * t4_i2c_io - read/write I2C data from adapter
* @adap: the adapter
* @mbox: mailbox to use for the FW command
* @port: Port number if per-port device; <0 if not
@@ -13543,29 +15011,34 @@ int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
* @offset: byte offset into device I2C space
* @len: byte length of I2C space data
* @buf: buffer in which to return I2C data
+ * @write: if true, do a write; else do a read
*
* Reads the I2C data from the indicated device and location.
*/
-int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
- unsigned int devid, unsigned int offset,
- unsigned int len, u8 *buf)
+int t4_i2c_io(struct adapter *adap, unsigned int mbox, int port,
+ unsigned int devid, unsigned int offset, unsigned int len,
+ u8 *buf, bool write)
{
struct fw_ldst_cmd ldst_cmd, ldst_rpl;
unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
int ret = 0;
- if (len > I2C_PAGE_SIZE)
+ if (len > I2C_PAGE_SIZE) {
+ dev_err(adap->pdev_dev, "Incorrect page size len %d\n", len);
return -EINVAL;
+ }
/* Dont allow reads that spans multiple pages */
- if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
+ if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) {
+ dev_err(adap->pdev_dev, "Read across the page\n");
return -EINVAL;
+ }
memset(&ldst_cmd, 0, sizeof(ldst_cmd));
ldst_cmd.op_to_addrspace =
cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
FW_CMD_REQUEST_F |
- FW_CMD_READ_F |
+ (write ? FW_CMD_WRITE_F : FW_CMD_READ_F) |
FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
@@ -13577,12 +15050,17 @@ int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
ldst_cmd.u.i2c.boffset = offset;
ldst_cmd.u.i2c.blen = i2c_len;
+ if (write)
+ memcpy(ldst_cmd.u.i2c.data, buf, i2c_len);
+
ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
- &ldst_rpl);
+ write ? NULL : &ldst_rpl);
if (ret)
break;
- memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
+ if (!write)
+ memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
+
offset += i2c_len;
buf += i2c_len;
len -= i2c_len;
@@ -13591,6 +15069,22 @@ int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
return ret;
}
+int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
+ int port, unsigned int devid,
+ unsigned int offset, unsigned int len,
+ u8 *buf)
+{
+ return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false);
+}
+
+int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
+ int port, unsigned int devid,
+ unsigned int offset, unsigned int len,
+ u8 *buf)
+{
+ return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true);
+}
+
/**
* t4_set_vlan_acl - Set a VLAN id for the specified VF
* @adap: the adapter
@@ -13712,16 +15206,17 @@ int t4_load_boot(struct adapter *adap, u8 *boot_data,
unsigned int boot_sector = (boot_addr * 1024);
struct cxgb4_pci_exp_rom_header *header;
struct cxgb4_pcir_data *pcir_header;
- int pcir_offset;
+ int pcir_offset, ret, addr;
unsigned int i;
u16 device_id;
- int ret, addr;
- /**
- * Make sure the boot image does not encroach on the firmware region
+ /*
+ * Make sure the boot image does not exceed its available space.
*/
- if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
- dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
+ if (!t4_flash_location_in_range(adap, FLASH_LOC_BOOT_AREA,
+ boot_sector + size)) {
+ dev_err(adap->pdev_dev,
+ "boot data is larger than available BOOT area\n");
return -EFBIG;
}
@@ -13763,7 +15258,9 @@ int t4_load_boot(struct adapter *adap, u8 *boot_data,
* and Boot configuration data sections. These 3 boot sections span
* sectors 0 to 7 in flash and live right before the FW image location.
*/
- i = DIV_ROUND_UP(size ? size : FLASH_FW_START, sf_sec_size);
+ i = DIV_ROUND_UP(size ? size :
+ t4_flash_location_size(adap, FLASH_LOC_BOOT_AREA),
+ sf_sec_size);
ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
(boot_sector >> 16) + i - 1);
@@ -13824,35 +15321,37 @@ int t4_load_boot(struct adapter *adap, u8 *boot_data,
*/
static int t4_flash_bootcfg_addr(struct adapter *adapter)
{
+ int ret = t4_flash_location_end(adapter, FLASH_LOC_BOOTCFG);
/**
* If the device FLASH isn't large enough to hold a Firmware
* Configuration File, return an error.
*/
- if (adapter->params.sf_size <
- FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
+ if (ret < 0 || adapter->params.sf_size < ret)
return -ENOSPC;
- return FLASH_BOOTCFG_START;
+ return t4_flash_location_start(adapter, FLASH_LOC_BOOTCFG);
}
int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
{
unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
+ unsigned int boot_cfg_start_sec, boot_cfg_size;
struct cxgb4_bootcfg_data *header;
- unsigned int flash_cfg_start_sec;
- unsigned int addr, npad;
int ret, i, n, cfg_addr;
+ unsigned int addr, npad;
cfg_addr = t4_flash_bootcfg_addr(adap);
if (cfg_addr < 0)
return cfg_addr;
addr = cfg_addr;
- flash_cfg_start_sec = addr / SF_SEC_SIZE;
+ boot_cfg_start_sec = addr / SF_SEC_SIZE;
+ boot_cfg_size = t4_flash_location_size(adap, FLASH_LOC_BOOTCFG);
- if (size > FLASH_BOOTCFG_MAX_SIZE) {
- dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
- FLASH_BOOTCFG_MAX_SIZE);
+ if (size > boot_cfg_size) {
+ dev_err(adap->pdev_dev,
+ "bootcfg file too large, max is %u bytes\n",
+ boot_cfg_size);
return -EFBIG;
}
@@ -13863,10 +15362,9 @@ int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
goto out;
}
- i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
- sf_sec_size);
- ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
- flash_cfg_start_sec + i - 1);
+ i = DIV_ROUND_UP(boot_cfg_size, sf_sec_size); /* # of sectors spanned */
+ ret = t4_flash_erase_sectors(adap, boot_cfg_start_sec,
+ boot_cfg_start_sec + i - 1);
/**
* If size == 0 then we're simply erasing the FLASH sectors associated
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
index 63bc956d2037..13c56fedfc5c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
@@ -54,13 +54,18 @@ enum {
MBOX_LEN = 64, /* mailbox size in bytes */
TRACE_LEN = 112, /* length of trace data and mask */
FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
+ T7_PM_RX_CACHE_NSTATS = 27, /* # of PM Rx Cache stats in T7 */
+ MAX_UP_CORES = 8, /* Max # of uP cores that can be enabled */
};
enum {
CIM_NUM_IBQ = 6, /* # of CIM IBQs */
+ CIM_NUM_IBQ_T7 = 16, /* # of CIM IBQs for T7 */
CIM_NUM_OBQ = 6, /* # of CIM OBQs */
CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
- CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
+ CIM_NUM_OBQ_T7 = 16, /* # of CIM OBQs for T7 adapter */
+ CIMLA_SIZE = (256 * 8), /* 256 rows * ceil(235/32) 32-bit words */
+ CIMLA_SIZE_T6 = (256 * 10), /* 256 rows * ceil(311/32) 32-bit words */
CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
@@ -89,6 +94,7 @@ enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
enum {
SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
SGE_CTXT_SIZE = 24, /* size of SGE context */
+ SGE_CTXT_SIZE_T7 = 28, /* size of SGE context for T7 */
SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */
@@ -199,89 +205,130 @@ struct rsp_ctrl {
#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
enum {
+ FLASH_FW_START_SEC = 8,
+ FLASH_FW_NSECS = 16,
+ FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
+ FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+
+ FLASH_CFG_START_SEC = 31,
+ FLASH_CFG_NSECS = 1,
+ FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
+ FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+
+ FLASH_EXP_ROM_START_SEC = 0,
+ FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
+
+ FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
+};
+
+enum t4_flash_loc {
/*
* Various Expansion-ROM boot images, etc.
*/
- FLASH_EXP_ROM_START_SEC = 0,
- FLASH_EXP_ROM_NSECS = 6,
- FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
- FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
+ FLASH_LOC_EXP_ROM = 0,
/*
* iSCSI Boot Firmware Table (iBFT) and other driver-related
* parameters ...
*/
- FLASH_IBFT_START_SEC = 6,
- FLASH_IBFT_NSECS = 1,
- FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
- FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
+ FLASH_LOC_IBFT,
/*
* Boot configuration data.
*/
- FLASH_BOOTCFG_START_SEC = 7,
- FLASH_BOOTCFG_NSECS = 1,
- FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
- FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
+ FLASH_LOC_BOOTCFG,
/*
* Location of firmware image in FLASH.
*/
- FLASH_FW_START_SEC = 8,
- FLASH_FW_NSECS = 16,
- FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
- FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+ FLASH_LOC_FW,
/* Location of bootstrap firmware image in FLASH.
*/
- FLASH_FWBOOTSTRAP_START_SEC = 27,
- FLASH_FWBOOTSTRAP_NSECS = 1,
- FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
- FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
+ FLASH_LOC_FWBOOTSTRAP,
/*
* iSCSI persistent/crash information.
*/
- FLASH_ISCSI_CRASH_START_SEC = 29,
- FLASH_ISCSI_CRASH_NSECS = 1,
- FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
- FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
+ FLASH_LOC_ISCSI_CRASH,
/*
* FCoE persistent/crash information.
*/
- FLASH_FCOE_CRASH_START_SEC = 30,
- FLASH_FCOE_CRASH_NSECS = 1,
- FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
- FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
+ FLASH_LOC_FCOE_CRASH,
/*
- * Location of Firmware Configuration File in FLASH. Since the FPGA
- * "FLASH" is smaller we need to store the Configuration File in a
- * different location -- which will overlap the end of the firmware
- * image if firmware ever gets that large ...
+ * Location of Firmware Configuration File in FLASH.
*/
- FLASH_CFG_START_SEC = 31,
- FLASH_CFG_NSECS = 1,
- FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
- FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+ FLASH_LOC_CFG,
- /* We don't support FLASH devices which can't support the full
- * standard set of sections which we need for normal
- * operations.
+ /*
+ * CUDBG chip dump.
*/
- FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
+ FLASH_LOC_CUDBG,
+
+ /*
+ * FW chip dump.
+ */
+ FLASH_LOC_CHIP_DUMP,
+
+ /*
+ * DPU boot information store.
+ */
+ FLASH_LOC_DPU_BOOT,
- FLASH_FPGA_CFG_START_SEC = 15,
- FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
+ /*
+ * DPU persistent information store.
+ */
+ FLASH_LOC_DPU_AREA,
/*
- * Sectors 32-63 are reserved for FLASH failover.
+ * VPD location.
*/
+ FLASH_LOC_VPD,
+
+ /*
+ * Backup init/vpd.
+ */
+ FLASH_LOC_VPD_BACKUP,
+
+ /*
+ * Sectors 32-63 for CUDBG.
+ * Backup firmware image.
+ */
+ FLASH_LOC_FW_BACKUP,
+
+ /*
+ * Backup bootstrap firmware image.
+ */
+ FLASH_LOC_FWBOOTSTRAP_BACKUP,
+
+ /*
+ * Backup Location of Firmware Configuration File in FLASH.
+ */
+ FLASH_LOC_CFG_BACK,
+
+ /*
+ * Helper to retrieve info that spans the entire Boot related area.
+ */
+ FLASH_LOC_BOOT_AREA,
+
+ /*
+ * Helper to determine minimum standard set of sections needed for
+ * normal operations.
+ */
+ FLASH_LOC_MIN_SIZE,
+
+ /*
+ * End of FLASH regions.
+ */
+ FLASH_LOC_END
};
-#undef FLASH_START
-#undef FLASH_MAX_SIZE
+struct t4_flash_loc_entry {
+ u16 start_sec;
+ u16 nsecs;
+};
#define SGE_TIMESTAMP_S 0
#define SGE_TIMESTAMP_M 0xfffffffffffffffULL
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 04/12] cxgb4: move PCI device management into cxgb4_pci.c and rework driver helpers
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (2 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 03/12] cxgb4: add T7 hardware management support Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 05/12] cxgb4: add T7 support to the main driver Potnuri Bharat Teja
` (7 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
cxgb4_main.c has accumulated all of the PCI bus glue - the device ID
table, probe, remove, shutdown and the EEH error handlers - alongside
the actual network driver. Split the bus-facing half out into a new
cxgb4_pci.c so that adding a new chip generation does not require
touching PCI enumeration code, and so that the probe path can be read
as a sequence of named steps rather than one 400 line function.
init_one() becomes cxgb4_pci_init_one() (bus side) plus
cxgb4_adap_probe() (driver side); remove_one() and shutdown_one() are
split the same way. Resource acquisition, chip identification, memory
window setup and the firmware handshake move into
cxgb4_pci_resource_init(), cxgb4_pci_chip_init(),
cxgb4_pci_setup_memwin{,_rdma}() and cxgb4_pci_fw_init(). The EEH
handlers are renamed cxgb4_pci_eeh_* and exported so the
pci_error_handlers table can live next to the pci_driver.
Because the pci_driver structure is no longer in cxgb4_main.c, the two
places that identified a cxgb4 netdevice by comparing its parent
device driver now compare netdev_ops against cxgb4_netdev_ops instead.
Several helpers are reworked while the code is being moved:
- cxgb4_work_queue()/cxgb4_work_cancel() and
cxgb4_workqueues_{create,destroy}() replace the open coded
workqueue calls.
- cxgb4_pci_msi{x,}_enabled() replace direct tests of
CXGB4_USING_MSI/CXGB4_USING_MSIX, and enable_msix() now records
which interrupt mode was actually selected.
- cxgb4_port_chan_to_netdev() looks a netdevice up by channel and
returns NULL if none matches, so the DCB firmware event paths no
longer index chan_map[] blindly.
- The HMA page size calculation picks the largest power of two page
size the scatterlist actually provides instead of assuming a fixed
page order.
- SGE doorbell addresses are computed once at probe and used via
writel() rather than recomputed per doorbell ring.
Fixed while moving the code:
- CXGB4_DEV_ENABLED is now set in cxgb4_pci_resource_init()
immediately after pci_enable_device() and cleared where the VF
management PF disables the device again. Previously the flag was
set late in probe, so an early probe failure left the device
enabled.
- enable_msix() leaked the msix_entry array on its success path.
- free_some_resources() passed adapter->pf to t4_fw_bye() where the
mailbox number is wanted.
- cxgb_udp_tunnel_set_port() now unwinds the MAC filters it
allocated if a later port fails, and only programs the MPS
register once every filter is in place.
No functional change is intended for T4/T5/T6 beyond the fixes listed
above.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/Makefile | 2 +-
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 18 +
.../net/ethernet/chelsio/cxgb4/cxgb4_dcb.c | 19 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 647 ++++++++----------
.../net/ethernet/chelsio/cxgb4/cxgb4_pci.c | 332 +++++++++
.../net/ethernet/chelsio/cxgb4/cxgb4_pci.h | 23 +
drivers/net/ethernet/chelsio/cxgb4/sge.c | 96 +--
7 files changed, 715 insertions(+), 422 deletions(-)
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h
diff --git a/drivers/net/ethernet/chelsio/cxgb4/Makefile b/drivers/net/ethernet/chelsio/cxgb4/Makefile
index a4b4d475abf8..08aef803a14a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/Makefile
+++ b/drivers/net/ethernet/chelsio/cxgb4/Makefile
@@ -9,7 +9,7 @@ cxgb4-objs := cxgb4_main.o l2t.o smt.o t4_hw.o sge.o clip_tbl.o cxgb4_ethtool.o
cxgb4_uld.o srq.o sched.o cxgb4_filter.o cxgb4_tc_u32.o \
cxgb4_ptp.o cxgb4_tc_flower.o cxgb4_cudbg.o cxgb4_mps.o \
cudbg_common.o cudbg_lib.o cudbg_zlib.o cxgb4_tc_mqprio.o \
- cxgb4_tc_matchall.o
+ cxgb4_tc_matchall.o cxgb4_pci.o
cxgb4-$(CONFIG_CHELSIO_T4_DCB) += cxgb4_dcb.o
cxgb4-$(CONFIG_CHELSIO_T4_FCOE) += cxgb4_fcoe.o
cxgb4-$(CONFIG_DEBUG_FS) += cxgb4_debugfs.o
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 43728dbb4742..9cbf5bf5b555 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -70,6 +70,8 @@ enum dev_state {
#include "cxgb4_uld.h"
#include "t4fw_api.h"
+#include "t4_values.h"
+#include "cxgb4_pci.h"
#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
extern struct list_head adapter_list;
@@ -1636,6 +1638,9 @@ extern char cxgb4_driver_name[];
void t4_os_portmod_changed(struct adapter *adap, int port_id);
void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
+void cxgb4_work_queue(struct workqueue_struct *workq, struct work_struct *work);
+void cxgb4_work_cancel(struct workqueue_struct *workq, struct work_struct *work);
+struct net_device *cxgb4_port_chan_to_netdev(struct adapter *adap, u8 chan);
void t4_free_sge_resources(struct adapter *adap);
irq_handler_t t4_intr_handler(struct adapter *adap);
netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
@@ -2067,6 +2072,19 @@ int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
const u8 **addr, bool sleep_ok);
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
int idx, const u8 *addr, bool persist, u8 *smt_idx);
+int cxgb4_is_primary_pf(struct adapter *adapter);
+int cxgb4_mbox_log_init(struct adapter *adap);
+
+pci_ers_result_t cxgb4_pci_eeh_err_detected(struct pci_dev *pdev,
+ pci_channel_state_t state);
+pci_ers_result_t cxgb4_pci_eeh_slot_reset(struct pci_dev *pdev);
+void cxgb4_pci_eeh_resume(struct pci_dev *pdev);
+void cxgb4_pci_eeh_reset_prepare(struct pci_dev *pdev);
+void cxgb4_pci_eeh_reset_done(struct pci_dev *pdev);
+int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs);
+int cxgb4_adap_probe(struct adapter *adapter);
+void cxgb4_adap_remove(struct adapter *adapter);
+void cxgb4_adap_shutdown(struct adapter *adapter);
int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
bool ucast, u64 vec, bool sleep_ok);
int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.c
index 7d5204834ee2..7c5437423696 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.c
@@ -273,13 +273,24 @@ void cxgb4_dcb_state_fsm(struct net_device *dev,
void cxgb4_dcb_handle_fw_update(struct adapter *adap,
const struct fw_port_cmd *pcmd)
{
- const union fw_port_dcb *fwdcb = &pcmd->u.dcb;
int port = FW_PORT_CMD_PORTID_G(be32_to_cpu(pcmd->op_to_portid));
- struct net_device *dev = adap->port[adap->chan_map[port]];
- struct port_info *pi = netdev_priv(dev);
- struct port_dcb_info *dcb = &pi->dcb;
+ const union fw_port_dcb *fwdcb = &pcmd->u.dcb;
int dcb_type = pcmd->u.dcb.pgid.type;
+ struct port_dcb_info *dcb;
int dcb_running_version;
+ struct net_device *dev;
+ struct port_info *pi;
+
+ dev = cxgb4_port_chan_to_netdev(adap, port);
+ if (!dev) {
+ dev_warn(adap->pdev_dev,
+ "Could not get netdevice for handling DCB FW update for port: %d\n",
+ port);
+ return;
+ }
+
+ pi = netdev_priv(dev);
+ dcb = &pi->dcb;
/* Handle Firmware DCB Control messages separately since they drive
* our state machine.
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index b7f0df9704a2..05ee6c1f9923 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -98,28 +98,6 @@ char cxgb4_driver_name[] = KBUILD_MODNAME;
NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
-/* Macros needed to support the PCI Device ID Table ...
- */
-#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
- static const struct pci_device_id cxgb4_pci_tbl[] = {
-#define CXGB4_UNIFIED_PF 0x4
-
-#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
-
-/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
- * called for both.
- */
-#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
-
-#define CH_PCI_ID_TABLE_ENTRY(devid) \
- { PCI_VDEVICE(CHELSIO, (devid)), .driver_data = CXGB4_UNIFIED_PF }
-
-#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
- { } \
- }
-
-#include "t4_pci_id_tbl.h"
-
#define FW4_FNAME "cxgb4/t4fw.bin"
#define FW5_FNAME "cxgb4/t5fw.bin"
#define FW6_FNAME "cxgb4/t6fw.bin"
@@ -134,7 +112,6 @@ char cxgb4_driver_name[] = KBUILD_MODNAME;
MODULE_DESCRIPTION(DRV_DESC);
MODULE_AUTHOR("Chelsio Communications");
MODULE_LICENSE("Dual BSD/GPL");
-MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
MODULE_FIRMWARE(FW4_FNAME);
MODULE_FIRMWARE(FW5_FNAME);
MODULE_FIRMWARE(FW6_FNAME);
@@ -171,14 +148,15 @@ static int rx_dma_offset = 2;
* queue. Select between the kernel provided function (select_queue=0) or user
* cxgb_select_queue function (select_queue=1)
*
- * Default: select_queue=0
+ * Default: select_queue=1
*/
-static int select_queue;
+static int select_queue = 1;
module_param(select_queue, int, 0644);
MODULE_PARM_DESC(select_queue,
"Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
static struct dentry *cxgb4_debugfs_root;
+static const struct net_device_ops cxgb4_netdev_ops;
LIST_HEAD(adapter_list);
DEFINE_MUTEX(uld_mutex);
@@ -333,6 +311,40 @@ void t4_os_portmod_changed(struct adapter *adap, int port_id)
pi->link_cfg.redo_l1cfg = netif_running(dev);
}
+void cxgb4_work_queue(struct workqueue_struct *workq, struct work_struct *work)
+{
+ if (!workq)
+ return;
+
+ queue_work(workq, work);
+}
+
+void cxgb4_work_cancel(struct workqueue_struct *workq, struct work_struct *work)
+{
+ if (!workq)
+ return;
+
+ cancel_work_sync(work);
+}
+
+static void cxgb4_workqueues_destroy(struct adapter *adap)
+{
+ if (adap->workq) {
+ flush_workqueue(adap->workq);
+ destroy_workqueue(adap->workq);
+ adap->workq = NULL;
+ }
+}
+
+static int cxgb4_workqueues_create(struct adapter *adap)
+{
+ adap->workq = create_singlethread_workqueue("cxgb4");
+ if (!adap->workq)
+ return -ENOMEM;
+
+ return 0;
+}
+
int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
module_param(dbfifo_int_thresh, int, 0644);
MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
@@ -534,9 +546,17 @@ static int link_start(struct net_device *dev)
static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
{
int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
- struct net_device *dev = adap->port[adap->chan_map[port]];
- int old_dcb_enabled = cxgb4_dcb_enabled(dev);
- int new_dcb_enabled;
+ int old_dcb_enabled, new_dcb_enabled;
+ struct net_device *dev;
+
+ dev = cxgb4_port_chan_to_netdev(adap, port);
+ if (!dev) {
+ dev_warn(adap->pdev_dev,
+ "Could not get netdevice for handling dcb_rpl for port %d\n", port);
+ return;
+ }
+
+ old_dcb_enabled = cxgb4_dcb_enabled(dev);
cxgb4_dcb_handle_fw_update(adap, pcmd);
new_dcb_enabled = cxgb4_dcb_enabled(dev);
@@ -608,7 +628,14 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
struct net_device *dev;
int dcbxdis, state_input;
- dev = q->adap->port[q->adap->chan_map[port]];
+ dev = cxgb4_port_chan_to_netdev(q->adap, port);
+ if (!dev) {
+ dev_warn(q->adap->pdev_dev,
+ "Could not get netdevice for handling DCB event for port %d\n",
+ port);
+ goto out;
+ }
+
dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
: !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
@@ -959,7 +986,7 @@ void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q)
/* 0-increment GTS to start the timer and enable interrupts */
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
SEINTARM_V(q->intr_params) |
- INGRESSQID_V(q->cntxt_id));
+ INGRESSQID_V(q->cntxt_id) | CIDXINC_V(0));
}
/*
@@ -1286,17 +1313,6 @@ static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
return err;
}
-static int setup_debugfs(struct adapter *adap)
-{
- if (IS_ERR_OR_NULL(adap->debugfs_root))
- return -1;
-
-#ifdef CONFIG_DEBUG_FS
- t4_setup_debugfs(adap);
-#endif
- return 0;
-}
-
static void cxgb4_port_mirror_free_rxq(struct adapter *adap,
struct sge_eth_rxq *mirror_rxq)
{
@@ -2126,6 +2142,20 @@ unsigned int cxgb4_port_chan(const struct net_device *dev)
}
EXPORT_SYMBOL(cxgb4_port_chan);
+struct net_device *cxgb4_port_chan_to_netdev(struct adapter *adap, u8 chan)
+{
+ struct port_info *pi;
+ u8 i;
+
+ for_each_port(adap, i) {
+ pi = adap2pinfo(adap, i);
+ if (pi->lport == chan)
+ return adap->port[pi->port_id];
+ }
+
+ return NULL;
+}
+
/**
* cxgb4_port_e2cchan - get the HW c-channel of a port
* @dev: the net device for the port
@@ -2357,8 +2387,6 @@ int cxgb4_bar2_sge_qregs(struct net_device *dev,
}
EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
-static struct pci_driver cxgb4_driver;
-
static void check_neigh_update(struct neighbour *neigh)
{
const struct device *parent;
@@ -2367,7 +2395,7 @@ static void check_neigh_update(struct neighbour *neigh)
if (is_vlan_dev(netdev))
netdev = vlan_dev_real_dev(netdev);
parent = netdev->dev.parent;
- if (parent && parent->driver == &cxgb4_driver.driver)
+ if (parent && netdev->netdev_ops == &cxgb4_netdev_ops)
t4_l2t_update(dev_get_drvdata(parent), neigh);
}
@@ -2393,7 +2421,6 @@ static struct notifier_block cxgb4_netevent_nb = {
static void drain_db_fifo(struct adapter *adap, int usecs)
{
u32 v1, v2, lp_count, hp_count;
-
do {
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
@@ -2608,7 +2635,7 @@ void t4_db_full(struct adapter *adap)
notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
- queue_work(adap->workq, &adap->db_full_task);
+ cxgb4_work_queue(adap->workq, &adap->db_full_task);
}
}
@@ -2618,7 +2645,7 @@ void t4_db_dropped(struct adapter *adap)
disable_dbs(adap);
notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
}
- queue_work(adap->workq, &adap->db_drop_task);
+ cxgb4_work_queue(adap->workq, &adap->db_drop_task);
}
void t4_register_netevent_notifier(void)
@@ -2669,7 +2696,6 @@ static int cxgb4_inet6addr_handler(struct notifier_block *this,
{
struct inet6_ifaddr *ifa = data;
struct net_device *event_dev = ifa->idev->dev;
- const struct device *parent = NULL;
#if IS_ENABLED(CONFIG_BONDING)
struct adapter *adap;
#endif
@@ -2695,10 +2721,7 @@ static int cxgb4_inet6addr_handler(struct notifier_block *this,
}
#endif
- if (event_dev)
- parent = event_dev->dev.parent;
-
- if (parent && parent->driver == &cxgb4_driver.driver) {
+ if (event_dev && event_dev->netdev_ops == &cxgb4_netdev_ops) {
switch (event) {
case NETDEV_UP:
cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
@@ -2768,7 +2791,6 @@ static int cxgb_up(struct adapter *adap)
err = -ENOMEM;
goto irq_err;
}
-
err = request_irq(adap->msix_info[s->nd_msix_idx].vec,
t4_nondata_intr, 0,
adap->msix_info[s->nd_msix_idx].desc, adap);
@@ -2779,10 +2801,13 @@ static int cxgb_up(struct adapter *adap)
if (err)
goto irq_err_free_nd_msix;
} else {
+ unsigned long flags = 0;
+
+ if (!cxgb4_pci_msix_enabled(adap) && !cxgb4_pci_msi_enabled(adap))
+ flags = IRQF_SHARED;
+
err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
- (adap->flags & CXGB4_USING_MSI) ? 0
- : IRQF_SHARED,
- adap->port[0]->name, adap);
+ flags, adap->port[0]->name, adap);
if (err)
goto irq_err;
}
@@ -2812,9 +2837,9 @@ static int cxgb_up(struct adapter *adap)
static void cxgb_down(struct adapter *adapter)
{
- cancel_work_sync(&adapter->tid_release_task);
- cancel_work_sync(&adapter->db_full_task);
- cancel_work_sync(&adapter->db_drop_task);
+ cxgb4_work_cancel(adapter->workq, &adapter->tid_release_task);
+ cxgb4_work_cancel(adapter->workq, &adapter->db_full_task);
+ cxgb4_work_cancel(adapter->workq, &adapter->db_drop_task);
adapter->tid_release_task_busy = false;
adapter->tid_release_head = NULL;
@@ -3856,13 +3881,13 @@ static const struct net_device_ops cxgb4_netdev_ops = {
.ndo_open = cxgb_open,
.ndo_stop = cxgb_close,
.ndo_start_xmit = t4_start_xmit,
- .ndo_select_queue = cxgb_select_queue,
+ .ndo_select_queue = cxgb_select_queue,
.ndo_get_stats64 = cxgb_get_stats,
.ndo_set_rx_mode = cxgb_set_rxmode,
.ndo_set_mac_address = cxgb_set_mac_addr,
.ndo_set_features = cxgb_set_features,
.ndo_validate_addr = eth_validate_addr,
- .ndo_eth_ioctl = cxgb_ioctl,
+ .ndo_eth_ioctl = cxgb_ioctl,
.ndo_change_mtu = cxgb_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = cxgb_netpoll,
@@ -3937,35 +3962,7 @@ void t4_fatal_err(struct adapter *adap)
netif_carrier_off(dev);
}
dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
- queue_work(adap->workq, &adap->fatal_err_notify_task);
-}
-
-static void setup_memwin(struct adapter *adap)
-{
- u32 nic_win_base = t4_get_util_window(adap);
-
- t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
-}
-
-static void setup_memwin_rdma(struct adapter *adap)
-{
- if (adap->vres.ocq.size) {
- u32 start;
- unsigned int sz_kb;
-
- start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
- start &= PCI_BASE_ADDRESS_MEM_MASK;
- start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
- sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
- start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
- adap->vres.ocq.start);
- t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
- }
+ cxgb4_work_queue(adap->workq, &adap->fatal_err_notify_task);
}
/* HMA Definitions */
@@ -3975,11 +3972,13 @@ static void setup_memwin_rdma(struct adapter *adap)
#define HMA_PAGE_SIZE PAGE_SIZE
+/* HW supports max 16M page size */
+#define HMA_MAX_PAGE_SIZE (16UL << 20)
+
#define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
-#define HMA_PAGE_ORDER \
- ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
- ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
+/* Allocate pages of size page_size << page_order */
+#define HMA_PAGE_ORDER ilog2((4 << 20) / HMA_PAGE_SIZE)
/* The minimum and maximum possible HMA sizes that can be specified in the FW
* configuration(in units of MB).
@@ -4025,7 +4024,9 @@ static int adap_config_hma(struct adapter *adapter)
unsigned int i, j, k;
u32 param, hma_size;
unsigned int ncmds;
+ unsigned int nents;
size_t page_size;
+ u32 best_page_size;
u32 page_order;
int node, ret;
@@ -4076,8 +4077,8 @@ static int adap_config_hma(struct adapter *adapter)
sgl = adapter->hma.sgt->sgl;
node = dev_to_node(adapter->pdev_dev);
for_each_sg(sgl, iter, sgt->orig_nents, i) {
- newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
- __GFP_ZERO, page_order);
+ newpage = alloc_pages_node(node, __GFP_NOWARN | __GFP_ZERO |
+ GFP_KERNEL, page_order);
if (!newpage) {
dev_err(adapter->pdev_dev,
"Not enough memory for HMA page allocation\n");
@@ -4097,16 +4098,32 @@ static int adap_config_hma(struct adapter *adapter)
}
adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
- adapter->hma.phy_addr = kzalloc_objs(dma_addr_t, sgt->nents);
+ best_page_size = HMA_MAX_PAGE_SIZE;
+ for_each_sg(sgl, iter, sgt->nents, i) {
+ if (!is_power_of_2(sg_dma_len(iter))) {
+ best_page_size = min(page_size << page_order, HMA_MAX_PAGE_SIZE);
+ break;
+ }
+
+ if (sg_dma_len(iter) < best_page_size)
+ best_page_size = sg_dma_len(iter);
+ }
+
+ nents = (hma_size << 20) / best_page_size;
+ adapter->hma.phy_addr = kcalloc(nents, sizeof(dma_addr_t), GFP_KERNEL);
if (unlikely(!adapter->hma.phy_addr))
goto free_hma;
+ k = 0;
for_each_sg(sgl, iter, sgt->nents, i) {
- newpage = sg_page(iter);
- adapter->hma.phy_addr[i] = sg_dma_address(iter);
+ u32 npages = sg_dma_len(iter) / best_page_size;
+
+ for (j = 0; j < npages; j++)
+ adapter->hma.phy_addr[k++] =
+ sg_dma_address(iter) + (j * best_page_size);
}
- ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
+ ncmds = DIV_ROUND_UP(nents, HMA_MAX_ADDR_IN_CMD);
/* Pass on the addresses to firmware */
for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
struct fw_hma_cmd hma_cmd;
@@ -4121,7 +4138,7 @@ static int adap_config_hma(struct adapter *adapter)
* addresses
*/
if (i == ncmds - 1) {
- naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
+ naddr = nents % HMA_MAX_ADDR_IN_CMD;
naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
}
memset(&hma_cmd, 0, sizeof(hma_cmd));
@@ -4140,8 +4157,7 @@ static int adap_config_hma(struct adapter *adapter)
/* Total Page size specified in units of 4K */
hma_cmd.addr_size_pkd =
- htonl(FW_HMA_CMD_ADDR_SIZE_V
- ((page_size << page_order) >> 12));
+ htonl(FW_HMA_CMD_ADDR_SIZE_V(best_page_size >> 12));
/* Fill the 5 addresses */
for (j = 0; j < naddr; j++) {
@@ -4285,7 +4301,7 @@ static int adap_init0_tweaks(struct adapter *adapter)
* Process module parameters which affect early initialization.
*/
if (rx_dma_offset != 2 && rx_dma_offset != 0) {
- dev_err(&adapter->pdev->dev,
+ dev_err(adapter->pdev_dev,
"Ignoring illegal rx_dma_offset=%d, using 2\n",
rx_dma_offset);
rx_dma_offset = 2;
@@ -4356,9 +4372,9 @@ static struct info_10gbt_phy_fw {
{ 0, NULL, NULL },
};
-static struct info_10gbt_phy_fw *find_phy_info(int devid)
+static struct info_10gbt_phy_fw *find_phy_info(struct adapter *adap)
{
- int i;
+ int i, devid = adap->pdev->device;
for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
if (phy_info_array[i].phy_fw_id == devid)
@@ -4374,13 +4390,13 @@ static struct info_10gbt_phy_fw *find_phy_info(int devid)
*/
static int adap_init0_phy(struct adapter *adap)
{
+ struct info_10gbt_phy_fw *phy_info;
const struct firmware *phyf;
int ret;
- struct info_10gbt_phy_fw *phy_info;
/* Use the device ID to determine which PHY file to flash.
*/
- phy_info = find_phy_info(adap->pdev->device);
+ phy_info = find_phy_info(adap);
if (!phy_info) {
dev_warn(adap->pdev_dev,
"No PHY Firmware file found for this PHY\n");
@@ -4766,14 +4782,10 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
if (ret < 0)
return ret;
- /* Contact FW, advertising Master capability */
- ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
- is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
- if (ret < 0) {
- dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
- ret);
+ ret = cxgb4_pci_fw_init(adap, &state);
+ if (ret < 0)
return ret;
- }
+
if (ret == adap->mbox)
adap->flags |= CXGB4_MASTER_PF;
@@ -5021,7 +5033,8 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
- adap->sge.egr_map = kzalloc_objs(*adap->sge.egr_map, adap->sge.egr_sz);
+ adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
+ sizeof(*adap->sge.egr_map), GFP_KERNEL);
if (!adap->sge.egr_map) {
ret = -ENOMEM;
goto bye;
@@ -5415,8 +5428,8 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
/* EEH callbacks */
-static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
- pci_channel_state_t state)
+pci_ers_result_t cxgb4_pci_eeh_err_detected(struct pci_dev *pdev,
+ pci_channel_state_t state)
{
int i;
struct adapter *adap = pci_get_drvdata(pdev);
@@ -5448,7 +5461,7 @@ out: return state == pci_channel_io_perm_failure ?
PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
}
-static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
+pci_ers_result_t cxgb4_pci_eeh_slot_reset(struct pci_dev *pdev)
{
int i, ret;
struct fw_caps_config_cmd c;
@@ -5504,13 +5517,13 @@ static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
adap->params.b_wnd);
- setup_memwin(adap);
+ cxgb4_pci_setup_memwin(adap);
if (cxgb_up(adap))
return PCI_ERS_RESULT_DISCONNECT;
return PCI_ERS_RESULT_RECOVERED;
}
-static void eeh_resume(struct pci_dev *pdev)
+void cxgb4_pci_eeh_resume(struct pci_dev *pdev)
{
int i;
struct adapter *adap = pci_get_drvdata(pdev);
@@ -5532,7 +5545,7 @@ static void eeh_resume(struct pci_dev *pdev)
rtnl_unlock();
}
-static void eeh_reset_prepare(struct pci_dev *pdev)
+void cxgb4_pci_eeh_reset_prepare(struct pci_dev *pdev)
{
struct adapter *adapter = pci_get_drvdata(pdev);
int i;
@@ -5557,7 +5570,7 @@ static void eeh_reset_prepare(struct pci_dev *pdev)
cxgb_down(adapter);
}
-static void eeh_reset_done(struct pci_dev *pdev)
+void cxgb4_pci_eeh_reset_done(struct pci_dev *pdev)
{
struct adapter *adapter = pci_get_drvdata(pdev);
int err, i;
@@ -5572,7 +5585,7 @@ static void eeh_reset_done(struct pci_dev *pdev)
return;
}
- setup_memwin(adapter);
+ cxgb4_pci_setup_memwin(adapter);
err = adap_init0(adapter, 1);
if (err) {
@@ -5581,7 +5594,7 @@ static void eeh_reset_done(struct pci_dev *pdev)
return;
}
- setup_memwin_rdma(adapter);
+ cxgb4_pci_setup_memwin_rdma(adapter);
if (adapter->flags & CXGB4_FW_OK) {
err = t4_port_init(adapter, adapter->pf, adapter->pf, 0);
@@ -5613,14 +5626,6 @@ static void eeh_reset_done(struct pci_dev *pdev)
cxgb_open(adapter->port[i]);
}
-static const struct pci_error_handlers cxgb4_eeh = {
- .error_detected = eeh_err_detected,
- .slot_reset = eeh_slot_reset,
- .resume = eeh_resume,
- .reset_prepare = eeh_reset_prepare,
- .reset_done = eeh_reset_done,
-};
-
/* Return true if the Link Configuration supports "High Speeds" (those greater
* than 1Gb/s).
*/
@@ -5956,6 +5961,7 @@ static int enable_msix(struct adapter *adap)
goto out_free;
}
+ adap->flags |= CXGB4_USING_MSI;
dev_info(adap->pdev_dev,
"Disabling offload due to insufficient MSI-X vectors\n");
adap->params.offload = 0;
@@ -5967,6 +5973,8 @@ static int enable_msix(struct adapter *adap)
uld_need = 0;
ethofld_need = 0;
mirror_need = 0;
+ } else {
+ adap->flags |= CXGB4_USING_MSIX;
}
num_vec = allocated;
@@ -6066,16 +6074,21 @@ static int enable_msix(struct adapter *adap)
adap->msix_info[i].idx = i;
}
- dev_info(adap->pdev_dev,
- "%d MSI-X vectors allocated, nic %d eoqsets %d per uld %d mirrorqsets %d\n",
- allocated, s->max_ethqsets, s->eoqsets, s->nqs_per_uld,
- s->mirrorqsets);
+ if (cxgb4_pci_msix_enabled(adap))
+ dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, ", allocated);
+ else if (cxgb4_pci_msi_enabled(adap))
+ dev_info(adap->pdev_dev, "%d MSI vectors allocated, ", allocated);
+ else
+ dev_info(adap->pdev_dev, "%d Legacy vectors allocated, ", allocated);
+
+ dev_info(adap->pdev_dev, "nic %d eoqsets %d per uld %d mirrorqsets %d\n",
+ s->max_ethqsets, s->eoqsets, s->nqs_per_uld, s->mirrorqsets);
kfree(entries);
return 0;
out_disable_msix:
- pci_disable_msix(adap->pdev);
+ disable_msi(adap);
out_free:
kfree(entries);
@@ -6111,10 +6124,10 @@ static void print_adapter_info(struct adapter *adapter)
/* Software/Hardware configuration */
dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
- is_offload(adapter) ? "R" : "",
- ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
- (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
- is_offload(adapter) ? "Offload" : "non-Offload");
+ is_uld(adapter) ? "R" : "",
+ cxgb4_pci_msix_enabled(adapter) ? "MSI-X" :
+ (cxgb4_pci_msi_enabled(adapter) ? "MSI" : ""),
+ is_uld(adapter) ? "Offload" : "non-Offload");
}
static void print_port_info(const struct net_device *dev)
@@ -6190,7 +6203,7 @@ static void free_some_resources(struct adapter *adapter)
free_netdev(adapter->port[i]);
}
if (adapter->flags & CXGB4_FW_OK)
- t4_fw_bye(adapter, adapter->pf);
+ t4_fw_bye(adapter, adapter->mbox);
}
#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN | \
@@ -6215,7 +6228,7 @@ static void cxgb4_mgmt_setup(struct net_device *dev)
dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
}
-static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
+int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
{
struct adapter *adap = pci_get_drvdata(pdev);
int err = 0;
@@ -6551,109 +6564,71 @@ static const struct xfrmdev_ops cxgb4_xfrmdev_ops = {
#endif /* CONFIG_CHELSIO_IPSEC_INLINE */
-static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+static int cxgb4_primary_pf(struct adapter *adapter)
+{
+ return adapter->primary_pf;
+}
+
+int cxgb4_is_primary_pf(struct adapter *adapter)
+{
+ return adapter->pf == cxgb4_primary_pf(adapter);
+}
+
+int cxgb4_mbox_log_init(struct adapter *adap)
+{
+ adap->mbox_log =
+ kzalloc(sizeof(struct mbox_cmd_log) +
+ (sizeof(struct mbox_cmd) *
+ T4_OS_LOG_MBOX_CMDS), GFP_KERNEL);
+ if (!adap->mbox_log)
+ return -ENOMEM;
+
+ spin_lock_init(&adap->mbox_lock);
+ INIT_LIST_HEAD(&adap->mlist.list);
+ adap->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
+ return 0;
+}
+
+int cxgb4_adap_probe(struct adapter *adapter)
{
struct net_device *netdev;
- struct adapter *adapter;
static int adap_idx = 1;
- int s_qpp, qpp, num_seg;
struct port_info *pi;
- enum chip_type chip;
- void __iomem *regs;
- int func, chip_ver;
- u16 device_id;
+ int chip_ver;
int i, err;
- u32 whoami;
- err = pci_request_regions(pdev, KBUILD_MODNAME);
- if (err) {
- /* Just info, some other driver may have claimed the device. */
- dev_info(&pdev->dev, "cannot obtain PCI resources\n");
+ err = cxgb4_pci_resource_init(adapter);
+ if (err < 0)
return err;
- }
- err = pci_enable_device(pdev);
- if (err) {
- dev_err(&pdev->dev, "cannot enable PCI device\n");
- goto out_release_regions;
- }
-
- regs = pci_ioremap_bar(pdev, 0);
- if (!regs) {
- dev_err(&pdev->dev, "cannot map device registers\n");
- err = -ENOMEM;
- goto out_disable_device;
- }
-
- adapter = kzalloc_obj(*adapter);
- if (!adapter) {
- err = -ENOMEM;
- goto out_unmap_bar0;
- }
-
- adapter->regs = regs;
- err = t4_wait_dev_ready(regs);
+ err = t4_wait_dev_ready(adapter->regs);
if (err < 0)
- goto out_free_adapter;
-
- /* We control everything through one PF */
- whoami = t4_read_reg(adapter, PL_WHOAMI_A);
- pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
- chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
- if ((int)chip < 0) {
- dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
- err = chip;
- goto out_free_adapter;
- }
- chip_ver = CHELSIO_CHIP_VERSION(chip);
- func = chip_ver <= CHELSIO_T5 ?
- SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
+ goto out_free_resources;
- adapter->pdev = pdev;
- adapter->pdev_dev = &pdev->dev;
- adapter->name = pci_name(pdev);
- adapter->mbox = func;
- adapter->pf = func;
- adapter->params.chip = chip;
adapter->adap_idx = adap_idx;
- adapter->msg_enable = DFLT_MSG_ENABLE;
- adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
- (sizeof(struct mbox_cmd) *
- T4_OS_LOG_MBOX_CMDS),
- GFP_KERNEL);
- if (!adapter->mbox_log) {
- err = -ENOMEM;
- goto out_free_adapter;
- }
- spin_lock_init(&adapter->mbox_lock);
- INIT_LIST_HEAD(&adapter->mlist.list);
- adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
- pci_set_drvdata(pdev, adapter);
+ err = cxgb4_pci_chip_init(adapter);
+ if (err < 0)
+ goto out_free_resources;
- if (func != ent->driver_data) {
- pci_disable_device(pdev);
- pci_save_state(pdev); /* to restore SR-IOV later */
+ if (!cxgb4_is_primary_pf(adapter))
return 0;
- }
- err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
- if (err) {
- dev_err(&pdev->dev, "no usable DMA configuration\n");
- goto out_free_adapter;
- }
+ /*
+ * Everything from here down is now the Primary Physical Function!
+ */
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
- pci_set_master(pdev);
- pci_save_state(pdev);
+ memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
adap_idx++;
- adapter->workq = create_singlethread_workqueue("cxgb4");
- if (!adapter->workq) {
- err = -ENOMEM;
- goto out_free_adapter;
- }
+ /*
+ * Default message set for the interfaces. This can be changed later
+ * via "ethtool -s ethX msglvl N".
+ */
+ adapter->msg_enable = DFLT_MSG_ENABLE;
- /* PCI device has been enabled */
- adapter->flags |= CXGB4_DEV_ENABLED;
- memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
+ err = cxgb4_workqueues_create(adapter);
+ if (err < 0)
+ goto out_free_adapter;
/* If possible, we use PCIe Relaxed Ordering Attribute to deliver
* Ingress Packet Data to Free List Buffers in order to allow for
@@ -6669,7 +6644,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
* PCIe configuration space to see if it's flagged with advice against
* using Relaxed Ordering.
*/
- if (!pcie_relaxed_ordering_enabled(pdev))
+ if (!pcie_relaxed_ordering_enabled(adapter->pdev))
adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
spin_lock_init(&adapter->stats_lock);
@@ -6696,46 +6671,14 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
}
}
- if (!is_t4(adapter->params.chip)) {
- s_qpp = (QUEUESPERPAGEPF0_S +
- (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
- adapter->pf);
- qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
- SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
- num_seg = PAGE_SIZE / SEGMENT_SIZE;
-
- /* Each segment size is 128B. Write coalescing is enabled only
- * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
- * queue is less no of segments that can be accommodated in
- * a page size.
- */
- if (qpp > num_seg) {
- dev_err(&pdev->dev,
- "Incorrect number of egress queues per page\n");
- err = -EINVAL;
- goto out_free_adapter;
- }
- adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
- pci_resource_len(pdev, 2));
- if (!adapter->bar2) {
- dev_err(&pdev->dev, "cannot map device bar2 region\n");
- err = -ENOMEM;
- goto out_free_adapter;
- }
- }
-
- setup_memwin(adapter);
+ cxgb4_pci_setup_memwin(adapter);
err = adap_init0(adapter, 0);
if (err)
- goto out_unmap_bar;
-
- setup_memwin_rdma(adapter);
+ dev_err(adapter->pdev_dev,
+ "Adapter initialization failed, error %d. Continuing in debug mode\n",
+ -err);
- /* configure SGE_STAT_CFG_A to read WC stats */
- if (!is_t4(adapter->params.chip))
- t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
- (is_t5(adapter->params.chip) ? STATMODE_V(0) :
- T6_STATMODE_V(0)));
+ cxgb4_pci_setup_memwin_rdma(adapter);
/* Initialize hash mac addr list */
INIT_LIST_HEAD(&adapter->mac_hlist);
@@ -6748,20 +6691,20 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
* know the actual # of EOTIDs supported.
*/
netdev = alloc_etherdev_mq(sizeof(struct port_info),
- MAX_ETH_QSETS + MAX_ATIDS);
+ MAX_ETH_QSETS + CXGB4_MAX_ATIDS);
if (!netdev) {
err = -ENOMEM;
goto out_free_dev;
}
- SET_NETDEV_DEV(netdev, &pdev->dev);
+ SET_NETDEV_DEV(netdev, adapter->pdev_dev);
adapter->port[i] = netdev;
pi = netdev_priv(netdev);
pi->adapter = adapter;
pi->xact_addr_filt = -1;
pi->port_id = i;
- netdev->irq = pdev->irq;
+ netdev->irq = adapter->pdev->irq;
netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
@@ -6819,10 +6762,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
cxgb4_init_ethtool_dump(adapter);
- pci_set_drvdata(pdev, adapter);
-
if (adapter->flags & CXGB4_FW_OK) {
- err = t4_port_init(adapter, func, func, 0);
+ err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
if (err)
goto out_free_dev;
} else if (adapter->params.nports == 1) {
@@ -6856,13 +6797,13 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
adapter->smt = t4_init_smt();
if (!adapter->smt) {
/* We tolerate a lack of SMT, giving up some functionality */
- dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
+ dev_warn(adapter->pdev_dev, "could not allocate SMT, continuing\n");
}
adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
if (!adapter->l2t) {
/* We tolerate a lack of L2T, giving up some functionality */
- dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
+ dev_warn(adapter->pdev_dev, "could not allocate L2T, continuing\n");
adapter->params.offload = 0;
}
@@ -6872,9 +6813,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
/* CLIP functionality is not present in hardware,
* hence disable all offload features
*/
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"CLIP not enabled in hardware, continuing\n");
- adapter->params.offload = 0;
} else {
adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
adapter->clipt_end);
@@ -6882,9 +6822,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
/* We tolerate a lack of clip_table, giving up
* some functionality
*/
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not allocate Clip table, continuing\n");
- adapter->params.offload = 0;
}
}
#endif
@@ -6893,7 +6832,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
pi = adap2pinfo(adapter, i);
pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
if (!pi->sched_tbl)
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not activate scheduling on port %d\n",
i);
}
@@ -6917,49 +6856,40 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
}
if (tid_init(&adapter->tids) < 0) {
- dev_warn(&pdev->dev, "could not allocate TID table, "
+ dev_warn(adapter->pdev_dev, "could not allocate TID table, "
"continuing\n");
adapter->params.offload = 0;
} else {
adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
if (!adapter->tc_u32)
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc u32, continuing\n");
if (cxgb4_init_tc_flower(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc flower, continuing\n");
if (cxgb4_init_tc_mqprio(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc mqprio, continuing\n");
if (cxgb4_init_tc_matchall(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc matchall, continuing\n");
if (cxgb4_init_ethtool_filters(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not initialize ethtool filters, continuing\n");
}
- /* See what interrupts we'll be using */
- if (msi > 1 && enable_msix(adapter) == 0)
- adapter->flags |= CXGB4_USING_MSIX;
- else if (msi > 0 && pci_enable_msi(pdev) == 0) {
- adapter->flags |= CXGB4_USING_MSI;
- if (msi > 1)
- free_msix_info(adapter);
- }
-
- /* check for PCI Express bandwidth capabiltites */
- pcie_print_link_status(pdev);
-
- cxgb4_init_mps_ref_entries(adapter);
-
err = init_rss(adapter);
if (err)
goto out_free_dev;
+ /* See what interrupts we'll be using */
+ err = enable_msix(adapter);
+ if (err)
+ goto out_disable_interrupts;
+
err = setup_non_data_intr(adapter);
if (err) {
dev_err(adapter->pdev_dev,
@@ -6975,6 +6905,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
}
fw_attach_fail:
+ cxgb4_init_mps_ref_entries(adapter);
/*
* The card is now ready to go. If any errors occur during device
* registration we do not fail the whole card but rather proceed only
@@ -6992,26 +6923,25 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
err = register_netdev(adapter->port[i]);
if (err)
break;
+
adapter->chan_map[pi->tx_chan] = i;
print_port_info(adapter->port[i]);
}
if (i == 0) {
- dev_err(&pdev->dev, "could not register any net devices\n");
+ dev_err(adapter->pdev_dev, "could not register any net devices\n");
goto out_free_dev;
}
if (err) {
- dev_warn(&pdev->dev, "only %d net devices registered\n", i);
+ dev_warn(adapter->pdev_dev, "only %d net devices registered\n", i);
err = 0;
}
if (cxgb4_debugfs_root) {
- adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
- cxgb4_debugfs_root);
- setup_debugfs(adapter);
- }
+ const char *dir_name = pci_name(adapter->pdev);
- /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
- pdev->needs_freset = 1;
+ adapter->debugfs_root = debugfs_create_dir(dir_name, cxgb4_debugfs_root);
+ t4_setup_debugfs(adapter);
+ }
if (is_uld(adapter))
cxgb4_uld_enable(adapter);
@@ -7026,40 +6956,29 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
print_adapter_info(adapter);
return 0;
- out_free_dev:
+out_disable_interrupts:
+ disable_msi(adapter);
+
+out_free_dev:
t4_free_sge_resources(adapter);
free_some_resources(adapter);
- if (adapter->flags & CXGB4_USING_MSIX)
- free_msix_info(adapter);
if (adapter->num_uld || adapter->num_ofld_uld)
t4_uld_mem_free(adapter);
- out_unmap_bar:
- if (!is_t4(adapter->params.chip))
- iounmap(adapter->bar2);
- out_free_adapter:
- if (adapter->workq)
- destroy_workqueue(adapter->workq);
-
- kfree(adapter->mbox_log);
- kfree(adapter);
- out_unmap_bar0:
- iounmap(regs);
- out_disable_device:
- pci_disable_device(pdev);
- out_release_regions:
- pci_release_regions(pdev);
+out_free_adapter:
+ cxgb4_workqueues_destroy(adapter);
+ cxgb4_pci_chip_free(adapter);
+
+out_free_resources:
+ cxgb4_pci_resource_free(adapter);
return err;
}
-static void remove_one(struct pci_dev *pdev)
+void cxgb4_adap_remove(struct adapter *adapter)
{
- struct adapter *adapter = pci_get_drvdata(pdev);
struct hash_mac_addr *entry, *tmp;
- if (!adapter) {
- pci_release_regions(pdev);
+ if (!adapter)
return;
- }
/* If we allocated filters, free up state associated with any
* valid filters ...
@@ -7068,26 +6987,26 @@ static void remove_one(struct pci_dev *pdev)
adapter->flags |= CXGB4_SHUTTING_DOWN;
- if (adapter->pf == 4) {
+ if (cxgb4_is_primary_pf(adapter)) {
int i;
/* Tear down per-adapter Work Queue first since it can contain
* references to our adapter data structure.
*/
- destroy_workqueue(adapter->workq);
+ cxgb4_workqueues_destroy(adapter);
- detach_ulds(adapter);
+ if (is_uld(adapter)) {
+ if (!list_empty(&adapter->list_node))
+ detach_ulds(adapter);
+ t4_uld_clean_up(adapter);
+ }
+ adap_free_hma_mem(adapter);
+ disable_interrupts(adapter);
for_each_port(adapter, i)
if (adapter->port[i]->reg_state == NETREG_REGISTERED)
unregister_netdev(adapter->port[i]);
- t4_uld_clean_up(adapter);
-
- adap_free_hma_mem(adapter);
-
- disable_interrupts(adapter);
-
cxgb4_free_mps_ref_entries(adapter);
debugfs_remove_recursive(adapter->debugfs_root);
@@ -7104,6 +7023,7 @@ static void remove_one(struct pci_dev *pdev)
free_msix_info(adapter);
if (adapter->num_uld || adapter->num_ofld_uld)
t4_uld_mem_free(adapter);
+
free_some_resources(adapter);
list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
list) {
@@ -7114,23 +7034,16 @@ static void remove_one(struct pci_dev *pdev)
#if IS_ENABLED(CONFIG_IPV6)
t4_cleanup_clip_tbl(adapter);
#endif
- if (!is_t4(adapter->params.chip))
- iounmap(adapter->bar2);
}
#ifdef CONFIG_PCI_IOV
else {
cxgb4_iov_configure(adapter->pdev, 0);
}
#endif
- iounmap(adapter->regs);
- if ((adapter->flags & CXGB4_DEV_ENABLED)) {
- pci_disable_device(pdev);
- adapter->flags &= ~CXGB4_DEV_ENABLED;
- }
- pci_release_regions(pdev);
- kfree(adapter->mbox_log);
+ cxgb4_pci_chip_free(adapter);
+ cxgb4_pci_resource_free(adapter);
+ adapter->flags &= ~CXGB4_DEV_ENABLED;
synchronize_rcu();
- kfree(adapter);
}
/* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
@@ -7138,22 +7051,18 @@ static void remove_one(struct pci_dev *pdev)
* function where we do the minimal amount of work necessary to shutdown any
* further activity.
*/
-static void shutdown_one(struct pci_dev *pdev)
+void cxgb4_adap_shutdown(struct adapter *adapter)
{
- struct adapter *adapter = pci_get_drvdata(pdev);
-
/* As with remove_one() above (see extended comment), we only want do
* do cleanup on PCI Devices which went all the way through init_one()
* ...
*/
- if (!adapter) {
- pci_release_regions(pdev);
+ if (!adapter)
return;
- }
adapter->flags |= CXGB4_SHUTTING_DOWN;
- if (adapter->pf == 4) {
+ if (cxgb4_is_primary_pf(adapter)) {
int i;
for_each_port(adapter, i)
@@ -7178,33 +7087,21 @@ static void shutdown_one(struct pci_dev *pdev)
}
}
-static struct pci_driver cxgb4_driver = {
- .name = KBUILD_MODNAME,
- .id_table = cxgb4_pci_tbl,
- .probe = init_one,
- .remove = remove_one,
- .shutdown = shutdown_one,
-#ifdef CONFIG_PCI_IOV
- .sriov_configure = cxgb4_iov_configure,
-#endif
- .err_handler = &cxgb4_eeh,
-};
-
static int __init cxgb4_init_module(void)
{
int ret;
cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
- ret = pci_register_driver(&cxgb4_driver);
+ ret = cxgb4_pci_driver_register();
if (ret < 0)
- goto err_pci;
+ goto out_err;
#if IS_ENABLED(CONFIG_IPV6)
if (!inet6addr_registered) {
ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
if (ret)
- pci_unregister_driver(&cxgb4_driver);
+ cxgb4_pci_driver_unregister();
else
inet6addr_registered = true;
}
@@ -7212,10 +7109,8 @@ static int __init cxgb4_init_module(void)
if (ret == 0)
return ret;
-
-err_pci:
+out_err:
debugfs_remove(cxgb4_debugfs_root);
-
return ret;
}
@@ -7227,7 +7122,7 @@ static void __exit cxgb4_cleanup_module(void)
inet6addr_registered = false;
}
#endif
- pci_unregister_driver(&cxgb4_driver);
+ cxgb4_pci_driver_unregister();
debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
new file mode 100644
index 000000000000..356109729d56
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * This file is part of the Chelsio T4/T5/T6/T7 Ethernet driver for Linux.
+ *
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ *
+ */
+
+#include <linux/crash_dump.h>
+
+#include "cxgb4.h"
+#include "t4_regs.h"
+
+#include "cxgb4_pci.h"
+
+int cxgb4_pci_resource_init(struct adapter *adap)
+{
+ struct pci_dev *pdev = adap->pdev;
+ int ret;
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ /* Just info, some other driver may have claimed the device. */
+ dev_info(adap->pdev_dev, "cannot obtain PCI resources\n");
+ return ret;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ dev_err(adap->pdev_dev, "cannot enable PCI device\n");
+ goto out_release_regions;
+ }
+ adap->flags |= CXGB4_DEV_ENABLED;
+
+ adap->regs = pci_ioremap_bar(pdev, 0);
+ if (!adap->regs) {
+ dev_err(adap->pdev_dev, "cannot map device registers\n");
+ ret = -ENOMEM;
+ goto out_disable_device;
+ }
+
+ adap->sge.tx_db_addr = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
+ adap->sge.rx_db_addr = adap->regs + MYPF_REG(SGE_PF_GTS_A);
+
+ adap->name = pci_name(pdev);
+ adap->primary_pf = CXGB4_UNIFIED_PF;
+ return 0;
+
+out_disable_device:
+ pci_disable_device(pdev);
+
+out_release_regions:
+ pci_release_regions(pdev);
+ return ret;
+}
+
+void cxgb4_pci_resource_free(struct adapter *adap)
+{
+ struct pci_dev *pdev = adap->pdev;
+
+ iounmap(adap->regs);
+ if ((adap->flags & CXGB4_DEV_ENABLED))
+ pci_disable_device(pdev);
+ pci_release_regions(pdev);
+}
+
+int cxgb4_pci_chip_init(struct adapter *adap)
+{
+ struct pci_dev *pdev = adap->pdev;
+ u16 device_id;
+ u32 whoami;
+ u8 func;
+ int ret;
+
+ /*
+ * Note that we use the PL_WHOAMI register to figure out to which PF
+ * we're actually attached rather than PCI_FUNC(pdev->devfn). We do
+ * this because we could be operating within a Virtual Machine where,
+ * say, PF4 has been inserted via some form of "PCI Pass Through"
+ * resulting in the VM PCI Device having a completely different PCI
+ * Function Number, say, PF0. However, there are many communications
+ * with the firmware (and the hardware) where we need to use the
+ * actual Physical Function Number and we can get this from the
+ * PL_WHOAMI register ...
+ */
+ whoami = t4_read_reg(adap, PL_WHOAMI_A);
+ pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
+ ret = t4_get_chip_type(adap, CHELSIO_PCI_ID_VER(device_id));
+ if (ret < 0)
+ return ret;
+
+ adap->params.chip = ret;
+ func = CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5 ?
+ SOURCEPF_G(whoami) :
+ T6_SOURCEPF_G(whoami);
+
+ adap->mbox = func;
+ adap->pf = func;
+
+ ret = cxgb4_mbox_log_init(adap);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * If we're not the MASTER Physical Function, there's not much more
+ * we need to do.
+ */
+ if (!cxgb4_is_primary_pf(adap)) {
+ /* We must be a PCIe SR-IOV Virtual Function. We won't be
+ * doing any DMA, but we will be offering VF Management
+ * services ...
+ */
+ pci_disable_device(pdev);
+ adap->flags &= ~CXGB4_DEV_ENABLED;
+ pci_save_state(pdev); /* to restore SR-IOV later */
+ return 0;
+ }
+
+ ret = dma_set_mask_and_coherent(adap->pdev_dev, DMA_BIT_MASK(64));
+ if (ret) {
+ dev_err(adap->pdev_dev, "no usable DMA configuration\n");
+ goto out_free_mbox_log;
+ }
+
+ pci_set_master(pdev);
+ pci_save_state(pdev);
+
+ if (!is_t4(adap->params.chip)) {
+ adap->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
+ pci_resource_len(pdev, 2));
+ if (!adap->bar2) {
+ dev_err(adap->pdev_dev,
+ "cannot map device bar2 region\n");
+ ret = -ENOMEM;
+ goto out_free_mbox_log;
+ }
+
+ t4_write_reg(adap, SGE_STAT_CFG_A,
+ STATSOURCE_T5_V(7) | (is_t5(adap->params.chip) ?
+ STATMODE_V(0) :
+ T6_STATMODE_V(0)));
+ }
+
+ /* check for PCI Express bandwidth capabiltites */
+ pcie_print_link_status(pdev);
+
+ /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
+ pdev->needs_freset = 1;
+
+ return 0;
+
+out_free_mbox_log:
+ kfree(adap->mbox_log);
+ return ret;
+}
+
+void cxgb4_pci_chip_free(struct adapter *adap)
+{
+ if (!is_t4(adap->params.chip)) {
+ if (adap->bar2)
+ iounmap(adap->bar2);
+ }
+
+ kfree(adap->mbox_log);
+}
+
+void cxgb4_pci_setup_memwin(struct adapter *adap)
+{
+ u32 nic_win_base = t4_get_util_window(adap);
+
+ t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
+}
+
+void cxgb4_pci_setup_memwin_rdma(struct adapter *adap)
+{
+ unsigned int sz_kb;
+ u32 start;
+
+ if (!adap->vres.ocq.size)
+ return;
+
+ start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
+ start &= PCI_BASE_ADDRESS_MEM_MASK;
+ start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
+ sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> WINDOW_SHIFT_X;
+
+ /*
+ * Set up RDMA memory window for accessing adapter memory
+ * ranges. (Read back MA register to ensure that changes
+ * propagate before we attempt to use the new values.)
+ */
+ t4_write_reg(adap, t4_pcie_mem_access_base_win_reg(adap, MEMWIN_RDMA),
+ start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
+ t4_pcie_mem_access_offset_write(adap, adap->vres.ocq.start, MEMWIN_RDMA,
+ 0);
+}
+
+int cxgb4_pci_fw_init(struct adapter *adap, enum dev_state *state)
+{
+ int ret;
+
+ /* Contact FW, advertising Master capability */
+ ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, state);
+ if (ret < 0 && is_kdump_kernel())
+ ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MUST,
+ state);
+ if (ret < 0) {
+ dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
+ ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+bool cxgb4_pci_msix_enabled(struct adapter *adap)
+{
+ if (!pci_dev_msi_enabled(adap->pdev))
+ return false;
+
+ return adap->pdev->msix_enabled;
+}
+
+bool cxgb4_pci_msi_enabled(struct adapter *adap)
+{
+ if (!pci_dev_msi_enabled(adap->pdev))
+ return false;
+
+ return adap->pdev->msi_enabled;
+}
+
+#ifdef CONFIG_PCI_IOV
+static int cxgb4_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
+{
+ if (pci_is_bridge(pdev))
+ return -EOPNOTSUPP;
+
+ return cxgb4_iov_configure(pdev, num_vfs);
+}
+#endif
+
+static int cxgb4_pci_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct adapter *adap;
+ int ret;
+
+ if (pci_is_bridge(pdev))
+ return 0;
+
+ adap = devm_kzalloc(&pdev->dev, sizeof(struct adapter), GFP_KERNEL);
+ if (!adap)
+ return -ENOMEM;
+
+ pci_set_drvdata(pdev, adap);
+
+ adap->pdev = pdev;
+ adap->pdev_dev = &pdev->dev;
+
+ ret = cxgb4_adap_probe(adap);
+ if (ret < 0)
+ goto out_err;
+
+ return 0;
+
+out_err:
+ pci_set_drvdata(pdev, NULL);
+ return ret;
+}
+
+static void cxgb4_pci_remove_one(struct pci_dev *pdev)
+{
+ if (pci_is_bridge(pdev))
+ return;
+
+ cxgb4_adap_remove(pci_get_drvdata(pdev));
+ pci_set_drvdata(pdev, NULL);
+}
+
+static void cxgb4_pci_shutdown_one(struct pci_dev *pdev)
+{
+ if (pci_is_bridge(pdev))
+ return;
+
+ cxgb4_adap_shutdown(pci_get_drvdata(pdev));
+}
+
+#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
+static const struct pci_device_id cxgb4_pci_tbl[] = {
+#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
+#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
+
+#define CH_PCI_ID_TABLE_ENTRY(devid) \
+ { PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF }
+
+#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
+ { 0, } \
+}
+
+#include "t4_pci_id_tbl.h"
+
+static const struct pci_error_handlers cxgb4_pci_eeh = {
+ .error_detected = cxgb4_pci_eeh_err_detected,
+ .slot_reset = cxgb4_pci_eeh_slot_reset,
+ .resume = cxgb4_pci_eeh_resume,
+ .reset_prepare = cxgb4_pci_eeh_reset_prepare,
+ .reset_done = cxgb4_pci_eeh_reset_done,
+};
+
+static struct pci_driver cxgb4_pci_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = cxgb4_pci_tbl,
+ .probe = cxgb4_pci_init_one,
+ .remove = cxgb4_pci_remove_one,
+ .shutdown = cxgb4_pci_shutdown_one,
+#ifdef CONFIG_PCI_IOV
+ .sriov_configure = cxgb4_pci_sriov_configure,
+#endif
+ .err_handler = &cxgb4_pci_eeh,
+};
+
+int cxgb4_pci_driver_register(void)
+{
+ return pci_register_driver(&cxgb4_pci_driver);
+}
+
+void cxgb4_pci_driver_unregister(void)
+{
+ pci_unregister_driver(&cxgb4_pci_driver);
+}
+
+MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h
new file mode 100644
index 000000000000..78a814207f61
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ */
+
+#ifndef __CXGB4_PCI_H__
+#define __CXGB4_PCI_H__
+
+#define CXGB4_UNIFIED_PF 0x4
+
+int cxgb4_pci_resource_init(struct adapter *adap);
+void cxgb4_pci_resource_free(struct adapter *adap);
+int cxgb4_pci_chip_init(struct adapter *adap);
+void cxgb4_pci_chip_free(struct adapter *adap);
+void cxgb4_pci_setup_memwin(struct adapter *adap);
+void cxgb4_pci_setup_memwin_rdma(struct adapter *adap);
+int cxgb4_pci_fw_init(struct adapter *adap, enum dev_state *state);
+bool cxgb4_pci_msix_enabled(struct adapter *adap);
+bool cxgb4_pci_msi_enabled(struct adapter *adap);
+
+int cxgb4_pci_driver_register(void);
+void cxgb4_pci_driver_unregister(void);
+#endif /* __CXGB4_PCI_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 4fe6c10d50e0..492cd35ce9d2 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -496,8 +496,7 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
* mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
- t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
- val | QID_V(q->cntxt_id));
+ writel(val | QID_V(q->cntxt_id), adap->sge.tx_db_addr);
} else {
writel(val | QID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_KDOORBELL);
@@ -734,14 +733,14 @@ static inline int is_eth_imm(const struct sk_buff *skb, unsigned int chip_ver)
if (skb->encapsulation && skb_shinfo(skb)->gso_size &&
chip_ver > CHELSIO_T5) {
hdrlen = sizeof(struct cpl_tx_tnl_lso);
- hdrlen += sizeof(struct cpl_tx_pkt_core);
} else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
return 0;
} else {
hdrlen = skb_shinfo(skb)->gso_size ?
sizeof(struct cpl_tx_pkt_lso_core) : 0;
- hdrlen += sizeof(struct cpl_tx_pkt);
}
+
+ hdrlen += sizeof(struct cpl_tx_pkt);
if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen)
return hdrlen;
return 0;
@@ -984,6 +983,7 @@ void cxgb4_write_partial_sgl(const struct sk_buff *skb, struct sge_txq *q,
}
EXPORT_SYMBOL(cxgb4_write_partial_sgl);
+#if defined(ARCH_HAS_IOREMAP_WC)
/* This function copies 64 byte coalesced work request to
* memory mapped BAR2 space. For coalesced WR SGE fetches
* data from the FIFO instead of from Host.
@@ -999,6 +999,7 @@ static void cxgb_pio_copy(u64 __iomem *dst, u64 *src)
count--;
}
}
+#endif
/**
* cxgb4_ring_tx_db - check and potentially ring a Tx queue's doorbell
@@ -1010,11 +1011,6 @@ static void cxgb_pio_copy(u64 __iomem *dst, u64 *src)
*/
inline void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
{
- /* Make sure that all writes to the TX Descriptors are committed
- * before we tell the hardware about them.
- */
- wmb();
-
/* If we don't have access to the new User Doorbell (T5+), use the old
* doorbell mechanism; otherwise use the new BAR2 mechanism.
*/
@@ -1027,8 +1023,7 @@ inline void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
*/
spin_lock_irqsave(&q->db_lock, flags);
if (!q->db_disabled)
- t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
- QID_V(q->cntxt_id) | val);
+ writel(val | QID_V(q->cntxt_id), adap->sge.tx_db_addr);
else
q->db_pidx_inc += n;
q->db_pidx = q->pidx;
@@ -1044,6 +1039,15 @@ inline void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
*/
WARN_ON(val & DBPRIO_F);
+ /*
+ * Make sure that all writes to the TX Descriptors are committed
+ * before we tell the hardware about them.
+ */
+ wmb();
+
+#if !defined(ARCH_HAS_IOREMAP_WC)
+ writel(val | QID_V(q->bar2_qid), q->bar2_addr + SGE_UDB_KDOORBELL);
+#else
/* If we're only writing a single TX Descriptor and we can use
* Inferred QID registers, we can use the Write Combining
* Gather Buffer; otherwise we use the simple doorbell.
@@ -1072,6 +1076,7 @@ inline void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
* PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
* hardware DMA read the actual Work Request.
*/
+#endif
wmb();
}
}
@@ -1299,6 +1304,7 @@ enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb)
return tnl_type;
}
+EXPORT_SYMBOL(cxgb_encap_offload_supported);
static inline void t6_fill_tnl_lso(struct sk_buff *skb,
struct cpl_tx_tnl_lso *tnl_lso,
@@ -1510,6 +1516,7 @@ static netdev_tx_t cxgb4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
pi = netdev_priv(dev);
adap = pi->adapter;
ssi = skb_shinfo(skb);
+
#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE)
if (xfrm_offload(skb) && !ssi->gso_size)
return adap->uld[CXGB4_ULD_IPSEC].tx_handler(skb, dev);
@@ -3036,6 +3043,7 @@ static void service_ofldq(struct sge_uld_txq *q)
__skb_unlink(skb, &q->sendq);
if (is_ofld_imm(skb))
kfree_skb(skb);
+
}
if (likely(written))
cxgb4_ring_tx_db(q->adap, &q->q, written);
@@ -3662,17 +3670,17 @@ static int cxgb4_validate_lb_pkt(struct port_info *pi, const struct pkt_gl *si)
int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
const struct pkt_gl *si)
{
- bool csum_ok;
- struct sk_buff *skb;
- const struct cpl_rx_pkt *pkt;
struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
struct adapter *adapter = q->adap;
struct sge *s = &q->adap->sge;
int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
u16 err_vec, tnl_hdr_len = 0;
+ const struct cpl_rx_pkt *pkt;
+ struct sk_buff *skb;
struct port_info *pi;
int ret = 0;
+ bool csum_ok;
pi = netdev_priv(q->netdev);
/* If we're looking at TX Queue CIDX Update, handle that separately
@@ -4011,8 +4019,8 @@ static int napi_rx_handler(struct napi_struct *napi, int budget)
* doorbell mechanism; otherwise use the new BAR2 mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
- t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
- val | INGRESSQID_V((u32)q->cntxt_id));
+ writel(val | INGRESSQID_V((u32)q->cntxt_id),
+ q->adap->sge.rx_db_addr);
} else {
writel(val | INGRESSQID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_GTS);
@@ -4346,6 +4354,9 @@ static void __iomem *bar2_address(struct adapter *adapter,
u64 bar2_qoffset;
int ret;
+ if (!adapter->bar2)
+ return NULL;
+
ret = t4_bar2_sge_qregs(adapter, qid, qtype, 0,
&bar2_qoffset, pbar2_qid);
if (ret)
@@ -4409,17 +4420,19 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
* descriptor ring. The free list size needs to be a multiple
* of the Egress Queue Unit and at least 2 Egress Units larger
* than the SGE's Egress Congrestion Threshold
- * (fl_starve_thres - 1).
+ * (fl_starve_thres).
*/
- if (fl->size < s->fl_starve_thres - 1 + 2 * 8)
- fl->size = s->fl_starve_thres - 1 + 2 * 8;
+ if (fl->size < s->fl_starve_thres + 2 * 8)
+ fl->size = s->fl_starve_thres + 2 * 8;
fl->size = roundup(fl->size, 8);
fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
sizeof(struct rx_sw_desc), &fl->addr,
&fl->sdesc, s->stat_len,
dev_to_node(adap->pdev_dev));
- if (!fl->desc)
- goto fl_nomem;
+ if (!fl->desc) {
+ ret = -ENOMEM;
+ goto err;
+ }
flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
@@ -4532,8 +4545,6 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
return 0;
-fl_nomem:
- ret = -ENOMEM;
err:
if (iq->desc) {
dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len,
@@ -4644,18 +4655,12 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
FW_EQ_ETH_CMD_TIMERIX_V(txq->dbqtimerix));
ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
- if (ret) {
- kfree(txq->q.sdesc);
- txq->q.sdesc = NULL;
- dma_free_coherent(adap->pdev_dev,
- nentries * sizeof(struct tx_desc),
- txq->q.desc, txq->q.phys_addr);
- txq->q.desc = NULL;
- return ret;
- }
+ if (ret < 0)
+ goto out_free_txq;
txq->q.q_type = CXGB4_TXQ_ETH;
init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd)));
+
txq->txq = netdevq;
txq->tso = 0;
txq->uso = 0;
@@ -4663,8 +4668,15 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
txq->vlan_ins = 0;
txq->mapping_err = 0;
txq->dbqt = dbqt;
-
return 0;
+
+out_free_txq:
+ kfree(txq->q.sdesc);
+ txq->q.sdesc = NULL;
+ dma_free_coherent(adap->pdev_dev, nentries * sizeof(struct tx_desc),
+ txq->q.desc, txq->q.phys_addr);
+ txq->q.desc = NULL;
+ return ret;
}
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
@@ -4708,21 +4720,23 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
c.eqaddr = cpu_to_be64(txq->q.phys_addr);
ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
- if (ret) {
- dma_free_coherent(adap->pdev_dev,
- nentries * sizeof(struct tx_desc),
- txq->q.desc, txq->q.phys_addr);
- txq->q.desc = NULL;
- return ret;
- }
+ if (ret < 0)
+ goto out_free_ctrlq;
- txq->q.q_type = CXGB4_TXQ_CTRL;
init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid)));
+
+ txq->q.q_type = CXGB4_TXQ_CTRL;
txq->adap = adap;
skb_queue_head_init(&txq->sendq);
tasklet_setup(&txq->qresume_tsk, restart_ctrlq);
txq->full = 0;
return 0;
+
+out_free_ctrlq:
+ dma_free_coherent(adap->pdev_dev, nentries * sizeof(struct tx_desc),
+ txq->q.desc, txq->q.phys_addr);
+ txq->q.desc = NULL;
+ return ret;
}
int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 05/12] cxgb4: add T7 support to the main driver
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (3 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 04/12] cxgb4: move PCI device management into cxgb4_pci.c and rework driver helpers Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 06/12] cxgb4: update PTP register access for T7 Potnuri Bharat Teja
` (6 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Enable the T7 generation in the NIC driver proper, on top of the PCI
and helper rework done in the previous patch.
Firmware and configuration:
- Add FW7_FNAME/FW7_CFNAME, the T7 entry in fw_info_array[] and the
matching case in adap_init0_config().
- Bound the configuration file against the size reported by
t4_flash_location_size(FLASH_LOC_CFG) rather than the fixed
FLASH_CFG_MAX_SIZE, which no longer describes every generation.
- The high priority filter and PPOD EDRAM setup is enabled for
T6 and later rather than T6 only.
Reporting:
- link_report() learns 200G and 400G.
- t4_os_portmod_changed() learns the LR_SIMPLEX and DR module types.
Channel programming:
- Port related firmware commands and register accesses now use the
logical port number (pi->lport) rather than pi->tx_chan. These are
identical on T4/T5/T6; on T7 the TP channel for a port is supplied
by firmware via FW_PARAMS_PARAM_DEV_TPCHMAP and is read through
cxgb4_port_chan(), which the SGE queue allocation paths now use.
- t4_set_trace_rss_control() replaces the open coded, chip
conditional MPS trace RSS control register write.
UDP tunnels:
- VXLAN and GENEVE RX type registers moved on T7; select between the
legacy and T7 register offsets.
Multiple uP cores:
- t4_sge_alloc_eth_txq() and t4_sge_alloc_ctrl_txq() take a queue
index and program FW_EQ_{ETH,CTRL}_CMD_COREGROUP so that queues are
distributed across the available cores.
- setup_sge_queues() allocates num_up_cores control queues per port,
and cfg_queues()/enable_msix() size the offload queue sets and
vector requirements accordingly.
SGE:
- On T7 and later the firmware derives the congestion channel map
from the configured load balancer mode, so the driver passes the
channel vector directly instead of building the map itself.
- t4_sge_init() handles the T7 chip version.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 4 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 248 +++++++++---------
drivers/net/ethernet/chelsio/cxgb4/sge.c | 54 ++--
3 files changed, 167 insertions(+), 139 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 9cbf5bf5b555..f31959b9255f 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -1655,10 +1655,10 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
rspq_flush_handler_t flush_handler, int cong);
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
struct net_device *dev, struct netdev_queue *netdevq,
- unsigned int iqid, u8 dbqt);
+ unsigned int iqid, u8 dbqt, int index);
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
struct net_device *dev, unsigned int iqid,
- unsigned int cmplqid);
+ unsigned int cmplqid, int index);
int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
unsigned int cmplqid);
int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 05ee6c1f9923..be4c8cbbad95 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -92,7 +92,7 @@
char cxgb4_driver_name[] = KBUILD_MODNAME;
-#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
+#define DRV_DESC "Chelsio T4/T5/T6/T7 Network Driver"
#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
@@ -101,9 +101,11 @@ char cxgb4_driver_name[] = KBUILD_MODNAME;
#define FW4_FNAME "cxgb4/t4fw.bin"
#define FW5_FNAME "cxgb4/t5fw.bin"
#define FW6_FNAME "cxgb4/t6fw.bin"
+#define FW7_FNAME "cxgb4/t7fw.bin"
#define FW4_CFNAME "cxgb4/t4-config.txt"
#define FW5_CFNAME "cxgb4/t5-config.txt"
#define FW6_CFNAME "cxgb4/t6-config.txt"
+#define FW7_CFNAME "cxgb4/t7-config.txt"
#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
#define PHY_AQ1202_DEVICEID 0x4409
@@ -115,6 +117,7 @@ MODULE_LICENSE("Dual BSD/GPL");
MODULE_FIRMWARE(FW4_FNAME);
MODULE_FIRMWARE(FW5_FNAME);
MODULE_FIRMWARE(FW6_FNAME);
+MODULE_FIRMWARE(FW7_FNAME);
/*
* The driver uses the best interrupt scheme available on a platform in the
@@ -196,6 +199,12 @@ static void link_report(struct net_device *dev)
case 100000:
s = "100Gbps";
break;
+ case 200000:
+ s = "200Gbps";
+ break;
+ case 400000:
+ s = "400Gbps";
+ break;
default:
pr_info("%s: unsupported speed: %d\n",
dev->name, p->link_cfg.speed);
@@ -283,7 +292,8 @@ void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
void t4_os_portmod_changed(struct adapter *adap, int port_id)
{
static const char *mod_str[] = {
- NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
+ NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM",
+ "LR_SIMPLEX", "DR"
};
struct net_device *dev = adap->port[port_id];
@@ -529,8 +539,7 @@ static int link_start(struct net_device *dev)
ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
dev->dev_addr, true, &pi->smt_idx);
if (ret == 0)
- ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
- &pi->link_cfg);
+ ret = t4_link_l1cfg(pi->adapter, mb, pi->lport, &pi->link_cfg);
if (ret == 0) {
local_bh_disable();
ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
@@ -1074,7 +1083,7 @@ static int setup_sge_queues(struct adapter *adap)
struct sge_uld_rxq_info *rxq_info = NULL;
struct sge *s = &adap->sge;
unsigned int cmplqid = 0;
- int err, i, j, msix = 0;
+ int err, i, j, k, msix = 0;
if (is_uld(adap))
rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
@@ -1106,8 +1115,7 @@ static int setup_sge_queues(struct adapter *adap)
msix, &q->fl,
t4_ethrx_handler,
NULL,
- t4_get_tp_ch_map(adap,
- pi->tx_chan));
+ t4_get_tp_ch_map(adap, pi->lport));
if (err)
goto freeout;
q->rspq.idx = j;
@@ -1119,7 +1127,7 @@ static int setup_sge_queues(struct adapter *adap)
err = t4_sge_alloc_eth_txq(adap, t, dev,
netdev_get_tx_queue(dev, j),
q->rspq.cntxt_id,
- !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
+ !!(adap->flags & CXGB4_SGE_DBQ_TIMER), j);
if (err)
goto freeout;
}
@@ -1132,25 +1140,26 @@ static int setup_sge_queues(struct adapter *adap)
if (rxq_info)
cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
- err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
- s->fw_evtq.cntxt_id, cmplqid);
- if (err)
- goto freeout;
+ /* Allocate at least num_up_cores control queues per port */
+ j = i * adap->params.num_up_cores;
+ for (k = 0; k < adap->params.num_up_cores; k++, j++) {
+ err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[j], adap->port[i],
+ s->fw_evtq.cntxt_id, cmplqid, k);
+ if (err)
+ goto freeout;
+ }
}
if (!is_t4(adap->params.chip)) {
err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
netdev_get_tx_queue(adap->port[0], 0)
- , s->fw_evtq.cntxt_id, false);
+ , s->fw_evtq.cntxt_id, false, 0);
if (err)
goto freeout;
}
- t4_write_reg(adap, is_t4(adap->params.chip) ?
- MPS_TRC_RSS_CONTROL_A :
- MPS_T5_TRC_RSS_CONTROL_A,
- RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
- QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
+ t4_set_trace_rss_control(adap, netdev2pinfo(adap->port[0])->tx_chan,
+ s->ethrxq[0].rspq.abs_id);
return 0;
freeout:
dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
@@ -2282,70 +2291,16 @@ EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
{
- u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
- u32 edc0_end, edc1_end, mc0_end, mc1_end;
- u32 offset, memtype, memaddr;
- struct adapter *adap;
- u32 hma_size = 0;
+ struct adapter *adap = netdev2adap(dev);
+ u32 offset;
int ret;
- adap = netdev2adap(dev);
-
offset = ((stag >> 8) * 32) + adap->vres.stag.start;
-
- /* Figure out where the offset lands in the Memory Type/Address scheme.
- * This code assumes that the memory is laid out starting at offset 0
- * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
- * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
- * MC0, and some have both MC0 and MC1.
- */
- size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
- edc0_size = EDRAM0_SIZE_G(size) << 20;
- size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
- edc1_size = EDRAM1_SIZE_G(size) << 20;
- size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
- mc0_size = EXT_MEM0_SIZE_G(size) << 20;
-
- if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
- hma_size = EXT_MEM1_SIZE_G(size) << 20;
- }
- edc0_end = edc0_size;
- edc1_end = edc0_end + edc1_size;
- mc0_end = edc1_end + mc0_size;
-
- if (offset < edc0_end) {
- memtype = MEM_EDC0;
- memaddr = offset;
- } else if (offset < edc1_end) {
- memtype = MEM_EDC1;
- memaddr = offset - edc0_end;
- } else {
- if (hma_size && (offset < (edc1_end + hma_size))) {
- memtype = MEM_HMA;
- memaddr = offset - edc1_end;
- } else if (offset < mc0_end) {
- memtype = MEM_MC0;
- memaddr = offset - edc1_end;
- } else if (is_t5(adap->params.chip)) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
- mc1_size = EXT_MEM1_SIZE_G(size) << 20;
- mc1_end = mc0_end + mc1_size;
- if (offset < mc1_end) {
- memtype = MEM_MC1;
- memaddr = offset - mc0_end;
- } else {
- /* offset beyond the end of any memory */
- goto err;
- }
- } else {
- /* T4/T6 only has a single memory channel */
- goto err;
- }
- }
+ if (offset >= (adap->vres.stag.start + adap->vres.stag.size))
+ goto err;
spin_lock(&adap->win0_lock);
- ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
+ ret = t4_memory_rw(adap, MEMWIN_NIC, MEM_EDC0, offset, 32, tpte, T4_MEMORY_READ);
spin_unlock(&adap->win0_lock);
return ret;
@@ -3033,8 +2988,7 @@ static void cxgb_get_stats(struct net_device *dev,
spin_unlock(&adapter->stats_lock);
return;
}
- t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
- &p->stats_base);
+ t4_get_port_stats_offset(adapter, p->lport, &stats, &p->stats_base);
spin_unlock(&adapter->stats_lock);
ns->tx_bytes = stats.tx_octets;
@@ -3372,7 +3326,7 @@ static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
SCHED_CLASS_MODE_CLASS,
SCHED_CLASS_RATEUNIT_BITS,
SCHED_CLASS_RATEMODE_ABS,
- pi->tx_chan, class_id, 0,
+ pi->lport, class_id, 0,
max_tx_rate * 1000, 0, pktsize, 0);
if (ret) {
dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
@@ -3756,16 +3710,19 @@ static int cxgb_udp_tunnel_unset_port(struct net_device *netdev,
struct port_info *pi = netdev_priv(netdev);
struct adapter *adapter = pi->adapter;
u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
+ u32 chip_ver, reg;
int ret = 0, i;
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
+
switch (ti->type) {
case UDP_TUNNEL_TYPE_VXLAN:
adapter->vxlan_port = 0;
- t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
+ reg = chip_ver >= CHELSIO_T7 ? T7_MPS_RX_VXLAN_TYPE_A : MPS_RX_VXLAN_TYPE_A;
break;
case UDP_TUNNEL_TYPE_GENEVE:
adapter->geneve_port = 0;
- t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
+ reg = chip_ver >= CHELSIO_T7 ? T7_MPS_RX_GENEVE_TYPE_A : MPS_RX_GENEVE_TYPE_A;
break;
default:
return -EINVAL;
@@ -3778,17 +3735,16 @@ static int cxgb_udp_tunnel_unset_port(struct net_device *netdev,
return 0;
for_each_port(adapter, i) {
pi = adap2pinfo(adapter, i);
- ret = t4_free_raw_mac_filt(adapter, pi->viid,
- match_all_mac, match_all_mac,
- adapter->rawf_start + pi->port_id,
- 1, pi->port_id, false);
- if (ret < 0) {
- netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
- i);
- return ret;
- }
+ ret = t4_free_raw_mac_filt(adapter, pi->viid, match_all_mac, match_all_mac,
+ adapter->rawf_start + pi->port_id, 1, pi->port_id,
+ false);
+ if (ret < 0)
+ netdev_info(netdev,
+ "RAW MAC Filter free failed for port %d, UDP port %u, ret: %d\n",
+ i, be16_to_cpu(ti->port), ret);
}
+ t4_write_reg(adapter, reg, 0);
return 0;
}
@@ -3799,18 +3755,26 @@ static int cxgb_udp_tunnel_set_port(struct net_device *netdev,
struct port_info *pi = netdev_priv(netdev);
struct adapter *adapter = pi->adapter;
u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
+ u32 chip_ver, reg, val;
+ __be16 *port_save;
int i, ret;
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
+
switch (ti->type) {
case UDP_TUNNEL_TYPE_VXLAN:
adapter->vxlan_port = ti->port;
- t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
- VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
+ port_save = &adapter->vxlan_port;
+ reg = chip_ver >= CHELSIO_T7 ? T7_MPS_RX_VXLAN_TYPE_A :
+ MPS_RX_VXLAN_TYPE_A;
+ val = VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F;
break;
case UDP_TUNNEL_TYPE_GENEVE:
adapter->geneve_port = ti->port;
- t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
- GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
+ port_save = &adapter->geneve_port;
+ reg = chip_ver >= CHELSIO_T7 ?
+ T7_MPS_RX_GENEVE_TYPE_A : MPS_RX_GENEVE_TYPE_A;
+ val = GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F;
break;
default:
return -EINVAL;
@@ -3831,13 +3795,27 @@ static int cxgb_udp_tunnel_set_port(struct net_device *netdev,
adapter->rawf_start + pi->port_id,
1, pi->port_id, false);
if (ret < 0) {
- netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
- be16_to_cpu(ti->port));
- return ret;
+ netdev_info(netdev,
+ "RAW MAC Filter alloc failed for port %d, UDP port %u, ret: %d\n",
+ i, be16_to_cpu(ti->port), ret);
+ goto out_free;
}
}
+ *port_save = ti->port;
+ t4_write_reg(adapter, reg, val);
return 0;
+
+out_free:
+ while (i-- > 0) {
+ pi = adap2pinfo(adapter, i);
+ t4_free_raw_mac_filt(adapter, pi->viid, match_all_mac,
+ match_all_mac,
+ adapter->rawf_start + pi->port_id,
+ 1, pi->port_id, false);
+ }
+
+ return ret;
}
static const struct udp_tunnel_nic_info cxgb_udp_tunnels = {
@@ -4460,14 +4438,15 @@ static int adap_init0_phy(struct adapter *adap)
*/
static int adap_init0_config(struct adapter *adapter, int reset)
{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
char *fw_config_file, fw_config_file_path[256];
u32 finiver, finicsum, cfcsum, param, val;
struct fw_caps_config_cmd caps_cmd;
unsigned long mtype = 0, maddr = 0;
const struct firmware *cf;
char *config_name = NULL;
- int config_issued = 0;
- int ret;
+ int ret, config_issued = 0;
+ int devid = 0;
/*
* Reset device if necessary.
@@ -4484,7 +4463,8 @@ static int adap_init0_config(struct adapter *adapter, int reset)
* to be performed after any global adapter RESET above since some
* PHYs only have local RAM copies of the PHY firmware.
*/
- if (is_10gbt_device(adapter->pdev->device)) {
+ devid = adapter->pdev->device;
+ if (is_10gbt_device(devid)) {
ret = adap_init0_phy(adapter);
if (ret < 0)
goto bye;
@@ -4494,7 +4474,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
* then use that. Otherwise, use the configuration file stored
* in the adapter flash ...
*/
- switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
+ switch (chip_ver) {
case CHELSIO_T4:
fw_config_file = FW4_CFNAME;
break;
@@ -4504,9 +4484,12 @@ static int adap_init0_config(struct adapter *adapter, int reset)
case CHELSIO_T6:
fw_config_file = FW6_CFNAME;
break;
+ case CHELSIO_T7:
+ fw_config_file = FW7_CFNAME;
+ break;
default:
dev_err(adapter->pdev_dev, "Device %d is not supported\n",
- adapter->pdev->device);
+ devid);
ret = -EINVAL;
goto bye;
}
@@ -4523,9 +4506,10 @@ static int adap_init0_config(struct adapter *adapter, int reset)
"/lib/firmware/%s", fw_config_file);
config_name = fw_config_file_path;
- if (cf->size >= FLASH_CFG_MAX_SIZE)
+ ret = t4_flash_location_size(adapter, FLASH_LOC_CFG);
+ if (ret < 0 || cf->size >= ret) {
ret = -ENOMEM;
- else {
+ } else {
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
ret = t4_query_params(adapter, adapter->mbox,
@@ -4669,7 +4653,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
dev_err(adapter->pdev_dev,
"HMA configuration failed with error %d\n", ret);
- if (is_t6(adapter->params.chip)) {
+ if (chip_ver >= CHELSIO_T6) {
adap_config_hpfilter(adapter);
ret = setup_ppod_edram(adapter);
if (!ret)
@@ -4747,7 +4731,23 @@ static struct fw_info fw_info_array[] = {
.intfver_iscsi = FW_INTFVER(T6, ISCSI),
.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
.intfver_fcoe = FW_INTFVER(T6, FCOE),
- },
+ },
+ }, {
+ .chip = CHELSIO_T7,
+ .fs_name = FW7_CFNAME,
+ .fw_mod_name = FW7_FNAME,
+ .fw_hdr = {
+ .chip = FW_HDR_CHIP_T7,
+ .fw_ver = __cpu_to_be32(FW_VERSION(T7)),
+ .intfver_nic = FW_INTFVER(T7, NIC),
+ .intfver_vnic = FW_INTFVER(T7, VNIC),
+ .intfver_ofld = FW_INTFVER(T7, OFLD),
+ .intfver_ri = FW_INTFVER(T7, RI),
+ .intfver_iscsipdu = FW_INTFVER(T7, ISCSIPDU),
+ .intfver_iscsi = FW_INTFVER(T7, ISCSI),
+ .intfver_fcoepdu = FW_INTFVER(T7, FCOEPDU),
+ .intfver_fcoe = FW_INTFVER(T7, FCOE),
+ },
}
};
@@ -4768,12 +4768,11 @@ static struct fw_info *find_fw_info(int chip)
*/
static int adap_init0(struct adapter *adap, int vpd_skip)
{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
struct fw_caps_config_cmd caps_cmd;
- u32 params[7], val[7];
+ u32 port_vec, v, params[7], val[7];
enum dev_state state;
- u32 v, port_vec;
- int reset = 1;
- int ret;
+ int ret, reset = 1;
/* Grab Firmware Device Log parameters as early as possible so we have
* access to it for debugging, etc.
@@ -4803,20 +4802,20 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
if (ret)
state = DEV_STATE_UNINIT;
if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
- struct fw_info *fw_info;
- struct fw_hdr *card_fw;
const struct firmware *fw;
const u8 *fw_data = NULL;
unsigned int fw_size = 0;
+ struct fw_info *fw_info;
+ struct fw_hdr *card_fw;
/* This is the firmware whose headers the driver was compiled
* against
*/
- fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
+ fw_info = find_fw_info(chip_ver);
if (fw_info == NULL) {
dev_err(adap->pdev_dev,
"unable to get firmware info for chip %d.\n",
- CHELSIO_CHIP_VERSION(adap->params.chip));
+ chip_ver);
return -EINVAL;
}
@@ -5496,7 +5495,7 @@ pci_ers_result_t cxgb4_pci_eeh_slot_reset(struct pci_dev *pdev)
struct port_info *pi = adap2pinfo(adap, i);
u8 vivld = 0, vin = 0;
- ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
+ ret = t4_alloc_vi(adap, adap->mbox, pi->lport, adap->pf, 0, 1,
NULL, NULL, &vivld, &vin);
if (ret < 0)
return PCI_ERS_RESULT_DISCONNECT;
@@ -5756,6 +5755,16 @@ static int cfg_queues(struct adapter *adap)
s->ofldqsets = avail_uld_qsets;
}
+ /*
+ * 1. num_of_cores should not be less than one for tensilica
+ * 2. num of ofld queues per port should not be less than num cores
+ */
+
+ if (adap->params.tid_qid_sel_mask &&
+ s->ofldqsets <
+ adap->params.num_up_cores * adap->params.nports)
+ s->ofldqsets = adap->params.num_up_cores * adap->params.nports;
+
avail_qsets -= num_ulds * s->ofldqsets;
}
@@ -5899,7 +5908,7 @@ static int enable_msix(struct adapter *adap)
{
u32 eth_need, uld_need = 0, ethofld_need = 0, mirror_need = 0;
u32 ethqsets = 0, ofldqsets = 0, eoqsets = 0, mirrorqsets = 0;
- u8 num_uld = 0, nchan = adap->params.nports;
+ u8 nchan = adap->params.nports;
u32 i, want, need, num_vec;
struct sge *s = &adap->sge;
struct msix_entry *entries;
@@ -5917,9 +5926,8 @@ static int enable_msix(struct adapter *adap)
#endif
eth_need = need;
if (is_uld(adap)) {
- num_uld = adap->num_ofld_uld + adap->num_uld;
- want += num_uld * s->ofldqsets;
- uld_need = num_uld * nchan;
+ want += s->ofldqsets;
+ uld_need = adap->params.num_up_cores * nchan;
need += uld_need;
}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 492cd35ce9d2..83cb3f28ab81 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -1697,7 +1697,7 @@ static netdev_tx_t cxgb4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
#endif /* CONFIG_CHELSIO_T4_FCOE */
}
- ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) |
+ ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->lport) |
TXPKT_PF_V(adap->pf);
if (ptp_enabled)
ctrl0 |= TXPKT_TSTAMP_F;
@@ -2003,7 +2003,7 @@ static netdev_tx_t cxgb4_vf_eth_xmit(struct sk_buff *skb,
/* Fill in the TX Packet CPL message header. */
cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) |
- TXPKT_INTF_V(pi->port_id) |
+ TXPKT_INTF_V(pi->lport) |
TXPKT_PF_V(0));
cpl->pack = cpu_to_be16(0);
cpl->len = cpu_to_be16(skb->len);
@@ -4400,7 +4400,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
FW_IQ_CMD_IQANUD_V(UPDATEDELIVERY_INTERRUPT_X) |
FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx :
-intr_idx - 1));
- c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) |
+ c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(cxgb4_port_chan(dev)) |
FW_IQ_CMD_IQGTSMODE_F |
FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) |
FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4));
@@ -4527,13 +4527,21 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
if (cong == 0) {
val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X);
} else {
- val =
- CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X);
- for (i = 0; i < 4; i++) {
- if (cong & (1 << i))
- ch_map |= 1 << (i << cng_ch_bits_log);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ /*
+ * For T7+, firmware calculates the congestion channel
+ * map internally based on configured LB_MODE.
+ */
+ val = T7_DMAQ_CONM_CTXT_CH_VEC_V(cong);
+ } else {
+ val =
+ CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X);
+ for (i = 0; i < 4; i++) {
+ if (cong & (1 << i))
+ ch_map |= 1 << (i << cng_ch_bits_log);
+ }
+ val |= CONMCTXT_CNGCHMAP_V(ch_map);
}
- val |= CONMCTXT_CNGCHMAP_V(ch_map);
}
ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
¶m, &val);
@@ -4587,7 +4595,7 @@ static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
*/
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
struct net_device *dev, struct netdev_queue *netdevq,
- unsigned int iqid, u8 dbqt)
+ unsigned int iqid, u8 dbqt, int index)
{
unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
struct port_info *pi = netdev_priv(dev);
@@ -4595,6 +4603,9 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
struct fw_eq_eth_cmd c;
int ret, nentries;
+ if (adap->params.num_up_cores > 1)
+ txq->group_id = index % adap->params.num_up_cores;
+
/* Add status entries */
nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
@@ -4611,7 +4622,9 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
FW_EQ_ETH_CMD_PFN_V(adap->pf) |
FW_EQ_ETH_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F |
- FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c));
+ FW_EQ_ETH_CMD_EQSTART_F |
+ FW_EQ_ETH_CMD_COREGROUP_V(txq->group_id) |
+ (sizeof(c) / 16));
/* For TX Ethernet Queues using the SGE Doorbell Queue Timer
* mechanism, we use Ingress Queue messages for Hardware Consumer
@@ -4628,7 +4641,7 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V((chip_ver <= CHELSIO_T5) ?
HOSTFCMODE_INGRESS_QUEUE_X :
HOSTFCMODE_STATUS_PAGE_X) |
- FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) |
+ FW_EQ_ETH_CMD_PCIECHN_V(cxgb4_port_chan(dev)) |
FW_EQ_ETH_CMD_FETCHRO_F | FW_EQ_ETH_CMD_IQID_V(iqid));
/* Note that the CIDX Flush Threshold should match MAX_TX_RECLAIM. */
@@ -4681,13 +4694,17 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
struct net_device *dev, unsigned int iqid,
- unsigned int cmplqid)
+ unsigned int cmplqid, int index)
{
unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
- struct port_info *pi = netdev_priv(dev);
struct sge *s = &adap->sge;
struct fw_eq_ctrl_cmd c;
- int ret, nentries;
+ int ret, nentries, ngroups;
+
+ ngroups = (adap->params.tid_qid_sel_mask >>
+ adap->params.tid_qid_sel_shift) + 1;
+ if (adap->params.tid_qid_sel_mask)
+ txq->tid_qid_group_id = index % ngroups;
/* Add status entries */
nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
@@ -4703,12 +4720,14 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
FW_EQ_CTRL_CMD_PFN_V(adap->pf) |
FW_EQ_CTRL_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F |
- FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c));
+ FW_EQ_CTRL_CMD_EQSTART_F |
+ FW_EQ_CTRL_CMD_COREGROUP_V(txq->tid_qid_group_id) |
+ (sizeof(c) / 16));
c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid));
c.physeqid_pkd = htonl(0);
c.fetchszm_to_iqid =
htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
- FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) |
+ FW_EQ_CTRL_CMD_PCIECHN_V(cxgb4_port_chan(dev)) |
FW_EQ_CTRL_CMD_FETCHRO_F | FW_EQ_CTRL_CMD_IQID_V(iqid));
c.dcaen_to_eqsize =
htonl(FW_EQ_CTRL_CMD_FBMIN_V(chip_ver <= CHELSIO_T5
@@ -5196,6 +5215,7 @@ int t4_sge_init(struct adapter *adap)
egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
break;
case CHELSIO_T6:
+ case CHELSIO_T7:
egress_threshold = T6_EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
break;
default:
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 06/12] cxgb4: update PTP register access for T7
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (4 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 05/12] cxgb4: add T7 support to the main driver Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 07/12] cxgb4: extend ethtool support for T7 adapters Potnuri Bharat Teja
` (5 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
The MAC_PORT_TX_TS_VAL_LO/HI registers moved within the port register
block on T7, and the PTP clock sum is now read from the chip global
MAC_PTP_SUM_LO/HI instead of a per port register. Select the right
registers by chip version and read both values with t4_read_reg64().
PTP port accesses now use the logical port number (pi->lport).
On T7 a transmitted PTP event packet is looped back with equal source
and destination MAC addresses rather than an MPS timestamp header.
Detect that and hand the packet to the transmit timestamp path. The
loopback packet is not necessarily UDP, so the RXF_UDP_F test is
dropped and cxgb4_ptp_is_ptp_rx() parses the frame itself, handling
VLAN tagged and IEEE 802.3 encapsulated PTP. On transmit,
ptp_classify_raw() replaces the open coded IPv4/UDP test.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/cxgb4_ptp.c | 82 ++++++++++++++-----
drivers/net/ethernet/chelsio/cxgb4/sge.c | 13 ++-
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 1 +
3 files changed, 71 insertions(+), 25 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
index cbd06d9b95d4..fb0d4ae11196 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
@@ -57,14 +57,13 @@
*/
bool cxgb4_ptp_is_ptp_tx(struct sk_buff *skb)
{
- struct udphdr *uh;
-
- uh = udp_hdr(skb);
- return skb->len >= PTP_MIN_LENGTH &&
- skb->len <= PTP_IN_TRANSMIT_PACKET_MAXNUM &&
- likely(skb->protocol == htons(ETH_P_IP)) &&
- ip_hdr(skb)->protocol == IPPROTO_UDP &&
- uh->dest == htons(PTP_EVENT_PORT);
+ unsigned int ptp_class;
+
+ ptp_class = ptp_classify_raw(skb);
+ if (ptp_class == PTP_CLASS_NONE)
+ return false;
+
+ return true;
}
bool is_ptp_enabled(struct sk_buff *skb, struct net_device *dev)
@@ -83,11 +82,50 @@ bool is_ptp_enabled(struct sk_buff *skb, struct net_device *dev)
*/
bool cxgb4_ptp_is_ptp_rx(struct sk_buff *skb)
{
- struct udphdr *uh = (struct udphdr *)(skb->data + ETH_HLEN +
- IPV4_HLEN(skb->data));
+ int offset = ETH_HLEN;
+ struct ethhdr *eth;
+ __be16 proto;
+
+ if (skb->len < ETH_HLEN)
+ return false;
+
+ eth = (struct ethhdr *)skb->data;
+ proto = eth->h_proto;
+
+ if (proto == htons(ETH_P_8021Q)) {
+ struct vlan_hdr *vhdr;
+
+ if (skb->len < offset + VLAN_HLEN)
+ return false;
+
+ vhdr = (struct vlan_hdr *)(skb->data + offset);
+ proto = vhdr->h_vlan_encapsulated_proto;
+ offset += VLAN_HLEN;
+ }
+
+ if (proto == htons(ETH_P_1588))
+ return true;
+
+ if (proto == htons(ETH_P_IP)) {
+ struct iphdr *iph;
+ struct udphdr *uh;
+
+ if (skb->len < offset + sizeof(*iph))
+ return false;
+ iph = (struct iphdr *)(skb->data + offset);
+
+ if (iph->protocol != IPPROTO_UDP)
+ return false;
+ offset += (iph->ihl * 4);
+
+ if (skb->len < offset + sizeof(*uh))
+ return false;
+ uh = (struct udphdr *)(skb->data + offset);
+
+ return uh->dest == htons(PTP_EVENT_PORT);
+ }
- return uh->dest == htons(PTP_EVENT_PORT) &&
- uh->source == htons(PTP_EVENT_PORT);
+ return false;
}
/**
@@ -103,12 +141,11 @@ void cxgb4_ptp_read_hwstamp(struct adapter *adapter, struct port_info *pi)
skb_ts = skb_hwtstamps(adapter->ptp_tx_skb);
- tx_ts = t4_read_reg(adapter,
- T5_PORT_REG(pi->port_id, MAC_PORT_TX_TS_VAL_LO));
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T7)
+ tx_ts = t4_read_reg64(adapter, T7_PORT_REG(pi->lport, T7_MAC_PORT_TX_TS_VAL_LO));
+ else
+ tx_ts = t4_read_reg64(adapter, T5_PORT_REG(pi->lport, MAC_PORT_TX_TS_VAL_LO));
- tx_ts |= (u64)t4_read_reg(adapter,
- T5_PORT_REG(pi->port_id,
- MAC_PORT_TX_TS_VAL_HI)) << 32;
skb_ts->hwtstamp = ns_to_ktime(tx_ts);
skb_tstamp_tx(adapter->ptp_tx_skb, skb_ts);
dev_kfree_skb_any(adapter->ptp_tx_skb);
@@ -183,7 +220,7 @@ int cxgb4_ptp_redirect_rx_packet(struct adapter *adapter, struct port_info *pi)
c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
c.u.init.sc = FW_PTP_SC_RDRX_TYPE;
- c.u.init.txchan = pi->tx_chan;
+ c.u.init.txchan = pi->lport;
c.u.init.absid = cpu_to_be16(receive_q->rspq.abs_id);
err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
@@ -319,9 +356,10 @@ static int cxgb4_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
ptp_clock_info);
u64 ns;
- ns = t4_read_reg(adapter, T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
- ns |= (u64)t4_read_reg(adapter,
- T5_PORT_REG(0, MAC_PORT_PTP_SUM_HI_A)) << 32;
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T7)
+ ns = t4_read_reg64(adapter, MAC_PTP_SUM_LO_A);
+ else
+ ns = t4_read_reg64(adapter, T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
/* convert to timespec*/
*ts = ns_to_timespec64(ns);
@@ -432,7 +470,7 @@ void cxgb4_ptp_init(struct adapter *adapter)
spin_lock_init(&adapter->ptp_lock);
adapter->ptp_clock = ptp_clock_register(&adapter->ptp_clock_info,
- &adapter->pdev->dev);
+ adapter->pdev_dev);
if (IS_ERR_OR_NULL(adapter->ptp_clock)) {
adapter->ptp_clock = NULL;
dev_err(adapter->pdev_dev,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 83cb3f28ab81..cd151696b82c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -3483,7 +3483,8 @@ static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
enum {
RX_NON_PTP_PKT = 0,
RX_PTP_PKT_SUC = 1,
- RX_PTP_PKT_ERR = 2
+ RX_PTP_PKT_ERR = 2,
+ RX_PTP_PKT_T7 = 3
};
/**
@@ -3509,6 +3510,13 @@ static noinline int t4_systim_to_hwstamp(struct adapter *adapter,
data = skb->data + sizeof(*cpl);
skb_pull(skb, 2 * sizeof(u64) + sizeof(struct cpl_rx_mps_pkt));
+
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) == CHELSIO_T7) {
+ struct ethhdr *eth = (struct ethhdr *)skb->data;
+
+ if (ether_addr_equal(eth->h_source, eth->h_dest))
+ return RX_PTP_PKT_T7;
+ }
offset = ETH_HLEN + IPV4_HLEN(skb->data) + UDP_HLEN;
if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(short))
return RX_PTP_PKT_ERR;
@@ -3740,8 +3748,7 @@ int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
__skb_pull(skb, s->pktshift); /* remove ethernet header pad */
/* Handle the PTP Event Tx Loopback packet */
- if (unlikely(pi->ptp_enable && !ret &&
- (pkt->l2info & htonl(RXF_UDP_F)) &&
+ if (unlikely(pi->ptp_enable && (ret == RX_PTP_PKT_T7 || !ret) &&
cxgb4_ptp_is_ptp_rx(skb))) {
if (!t4_tx_hststamp(adapter, skb, q->netdev))
return 0;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 5ac262ec389f..e8bcce1993e1 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -4533,6 +4533,7 @@
#define MAC_PORT_EPIO_OP_A 0x8d0
#define MAC_PORT_CFG2_A 0x818
+#define MAC_PTP_SUM_LO_A 0x38108
#define MAC_PORT_PTP_SUM_LO_A 0x990
#define MAC_PORT_PTP_SUM_HI_A 0x994
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 07/12] cxgb4: extend ethtool support for T7 adapters
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (5 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 06/12] cxgb4: update PTP register access for T7 Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 08/12] cxgb4: Add T7 support to the filter infrastructure Potnuri Bharat Teja
` (4 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Update the ethtool implementation to support T7-specific port types,
link modes, and adapter capabilities.
Add support for new T7 port configurations including SFP56, QSFP56,
50G/100G/200G/400G backplane modes, and the associated ethtool link
mode mappings. Update port statistics handling and module type
reporting to account for the new hardware capabilities.
Extend RSS configuration support by implementing RSS hash key retrieval
and programming through ethtool. Also update module EEPROM handling for
new optical module types and CMIS-based devices.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../ethernet/chelsio/cxgb4/cxgb4_ethtool.c | 381 +++++++++++++-----
1 file changed, 278 insertions(+), 103 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
index 0092bc16f887..605c0783d3d5 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
@@ -14,6 +14,8 @@
#include "cxgb4_tc_flower.h"
#define EEPROM_MAGIC 0x38E2F10C
+#define RSS_HASH_KEY_SIZE 40
+#define CMIS_PAGE_SELECT_REG 127
static u32 get_msglevel(struct net_device *dev)
{
@@ -358,7 +360,7 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
int i;
u64 *p0;
- t4_get_port_stats_offset(adapter, pi->tx_chan,
+ t4_get_port_stats_offset(adapter, pi->lport,
(struct port_stats *)data,
&pi->stats_base);
@@ -440,10 +442,13 @@ static int from_fw_port_mod_type(enum fw_port_type port_type,
port_type == FW_PORT_TYPE_CR4_QSFP ||
port_type == FW_PORT_TYPE_CR_QSFP ||
port_type == FW_PORT_TYPE_CR2_QSFP ||
- port_type == FW_PORT_TYPE_SFP28) {
+ port_type == FW_PORT_TYPE_SFP28 ||
+ port_type == FW_PORT_TYPE_SFP56 ||
+ port_type == FW_PORT_TYPE_QSFP56) {
if (mod_type == FW_PORT_MOD_TYPE_LR ||
mod_type == FW_PORT_MOD_TYPE_SR ||
mod_type == FW_PORT_MOD_TYPE_ER ||
+ mod_type == FW_PORT_MOD_TYPE_DR ||
mod_type == FW_PORT_MOD_TYPE_LRM)
return PORT_FIBRE;
else if (mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
@@ -453,7 +458,11 @@ static int from_fw_port_mod_type(enum fw_port_type port_type,
return PORT_OTHER;
} else if (port_type == FW_PORT_TYPE_KR4_100G ||
port_type == FW_PORT_TYPE_KR_SFP28 ||
- port_type == FW_PORT_TYPE_KR_XLAUI) {
+ port_type == FW_PORT_TYPE_KR_XLAUI ||
+ port_type == FW_PORT_TYPE_KR_50G ||
+ port_type == FW_PORT_TYPE_KR2_100G ||
+ port_type == FW_PORT_TYPE_KR4_200G ||
+ port_type == FW_PORT_TYPE_KR8_400G) {
return PORT_NONE;
}
@@ -490,8 +499,100 @@ static unsigned int speed_to_fw_caps(int speed)
return 0;
}
+enum link_medium {
+ LINK_MEDIUM_NONE,
+ LINK_MEDIUM_TP, /* plain copper baseT */
+ LINK_MEDIUM_KR, /* electrical backplane */
+ LINK_MEDIUM_CR, /* copper direct-attach (TwinAx) */
+ LINK_MEDIUM_SR,
+ LINK_MEDIUM_LR, /* also covers ER FR */
+ LINK_MEDIUM_DR,
+ LINK_MEDIUM_LRM,
+};
+
+static bool fw_port_is_backplane(enum fw_port_type port_type)
+{
+ switch (port_type) {
+ case FW_PORT_TYPE_KX:
+ case FW_PORT_TYPE_KX4:
+ case FW_PORT_TYPE_BP_AP:
+ case FW_PORT_TYPE_BP4_AP:
+ case FW_PORT_TYPE_BP40_BA:
+ case FW_PORT_TYPE_KR:
+ case FW_PORT_TYPE_KR_50G:
+ case FW_PORT_TYPE_KR_SFP28:
+ case FW_PORT_TYPE_KR_XLAUI:
+ case FW_PORT_TYPE_KR2_100G:
+ case FW_PORT_TYPE_KR4_100G:
+ case FW_PORT_TYPE_KR4_200G:
+ case FW_PORT_TYPE_KR8_400G:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool fw_port_is_electrical_tp(enum fw_port_type port_type)
+{
+ switch (port_type) {
+ case FW_PORT_TYPE_BT_SGMII:
+ case FW_PORT_TYPE_BT_XFI:
+ case FW_PORT_TYPE_BT_XAUI:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool fw_port_is_fixed_baset(enum fw_port_type port_type)
+{
+ switch (port_type) {
+ case FW_PORT_TYPE_FIBER_XFI:
+ case FW_PORT_TYPE_FIBER_XAUI:
+ return true;
+ default:
+ return fw_port_is_electrical_tp(port_type);
+ }
+}
+
+static int fw_port_class_bit(enum fw_port_type port_type)
+{
+ if (fw_port_is_backplane(port_type))
+ return ETHTOOL_LINK_MODE_Backplane_BIT;
+ if (fw_port_is_electrical_tp(port_type))
+ return ETHTOOL_LINK_MODE_TP_BIT;
+ return ETHTOOL_LINK_MODE_FIBRE_BIT;
+}
+
+static enum link_medium fw_port_medium(enum fw_port_type port_type,
+ enum fw_port_module_type mod_type)
+{
+ if (fw_port_is_backplane(port_type))
+ return LINK_MEDIUM_KR;
+ if (fw_port_is_fixed_baset(port_type))
+ return LINK_MEDIUM_TP;
+
+ switch (mod_type) {
+ case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
+ case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
+ return LINK_MEDIUM_CR;
+ case FW_PORT_MOD_TYPE_SR:
+ return LINK_MEDIUM_SR;
+ case FW_PORT_MOD_TYPE_LR:
+ case FW_PORT_MOD_TYPE_ER:
+ return LINK_MEDIUM_LR;
+ case FW_PORT_MOD_TYPE_DR:
+ return LINK_MEDIUM_DR;
+ case FW_PORT_MOD_TYPE_LRM:
+ return LINK_MEDIUM_LRM;
+ default:
+ return LINK_MEDIUM_NONE; /* no module / unreadable */
+ }
+}
+
/**
* fw_caps_to_lmm - translate Firmware to ethtool Link Mode Mask
+ * @mod_type: Firmware Module Type
* @port_type: Firmware Port Type
* @fw_caps: Firmware Port Capabilities
* @link_mode_mask: ethtool Link Mode Mask
@@ -500,114 +601,93 @@ static unsigned int speed_to_fw_caps(int speed)
* Link Mode Mask.
*/
static void fw_caps_to_lmm(enum fw_port_type port_type,
+ enum fw_port_module_type mod_type,
fw_port_cap32_t fw_caps,
unsigned long *link_mode_mask)
{
- #define SET_LMM(__lmm_name) \
- do { \
- __set_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \
- link_mode_mask); \
- } while (0)
+ enum link_medium medium = fw_port_medium(port_type, mod_type);
#define FW_CAPS_TO_LMM(__fw_name, __lmm_name) \
do { \
if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
- SET_LMM(__lmm_name); \
+ __set_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \
+ link_mode_mask); \
} while (0)
- switch (port_type) {
- case FW_PORT_TYPE_BT_SGMII:
- case FW_PORT_TYPE_BT_XFI:
- case FW_PORT_TYPE_BT_XAUI:
- SET_LMM(TP);
- FW_CAPS_TO_LMM(SPEED_100M, 100baseT_Full);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
- break;
-
- case FW_PORT_TYPE_KX4:
- case FW_PORT_TYPE_KX:
- SET_LMM(Backplane);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
- break;
-
- case FW_PORT_TYPE_KR:
- SET_LMM(Backplane);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
- break;
-
- case FW_PORT_TYPE_BP_AP:
- SET_LMM(Backplane);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
- break;
+ if (medium != LINK_MEDIUM_NONE)
+ __set_bit(fw_port_class_bit(port_type), link_mode_mask);
- case FW_PORT_TYPE_BP4_AP:
- SET_LMM(Backplane);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
+ switch (medium) {
+ case LINK_MEDIUM_TP:
+ FW_CAPS_TO_LMM(SPEED_100M, 100baseT_Full);
+ FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
break;
- case FW_PORT_TYPE_FIBER_XFI:
- case FW_PORT_TYPE_FIBER_XAUI:
- case FW_PORT_TYPE_SFP:
- case FW_PORT_TYPE_QSFP_10G:
- case FW_PORT_TYPE_QSA:
- SET_LMM(FIBRE);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
+ case LINK_MEDIUM_KR:
+ FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
+ FW_CAPS_TO_LMM(SPEED_25G, 25000baseKR_Full);
+ FW_CAPS_TO_LMM(SPEED_40G, 40000baseKR4_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseKR_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseKR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseKR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseKR4_Full);
+ FW_CAPS_TO_LMM(SPEED_200G, 200000baseKR4_Full);
+ FW_CAPS_TO_LMM(SPEED_400G, 400000baseKR8_Full);
break;
- case FW_PORT_TYPE_BP40_BA:
- case FW_PORT_TYPE_QSFP:
- SET_LMM(FIBRE);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
- break;
-
- case FW_PORT_TYPE_CR_QSFP:
- case FW_PORT_TYPE_SFP28:
- SET_LMM(FIBRE);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
+ case LINK_MEDIUM_CR:
+ FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseCR_Full);
+ FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
+ FW_CAPS_TO_LMM(SPEED_40G, 40000baseCR4_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseCR_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseCR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR4_Full);
+ FW_CAPS_TO_LMM(SPEED_200G, 200000baseCR4_Full);
+ FW_CAPS_TO_LMM(SPEED_400G, 400000baseCR8_Full);
break;
- case FW_PORT_TYPE_KR_SFP28:
- SET_LMM(Backplane);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
- FW_CAPS_TO_LMM(SPEED_25G, 25000baseKR_Full);
+ case LINK_MEDIUM_SR:
+ FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseSR_Full);
+ FW_CAPS_TO_LMM(SPEED_25G, 25000baseSR_Full);
+ FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseSR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseSR4_Full);
+ FW_CAPS_TO_LMM(SPEED_200G, 200000baseSR4_Full);
+ FW_CAPS_TO_LMM(SPEED_400G, 400000baseSR8_Full);
break;
- case FW_PORT_TYPE_KR_XLAUI:
- SET_LMM(Backplane);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
- FW_CAPS_TO_LMM(SPEED_40G, 40000baseKR4_Full);
+ case LINK_MEDIUM_LR:
+ FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseLR_Full);
+ FW_CAPS_TO_LMM(SPEED_40G, 40000baseLR4_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseLR_ER_FR_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseLR2_ER2_FR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseLR4_ER4_Full);
+ FW_CAPS_TO_LMM(SPEED_200G, 200000baseLR4_ER4_FR4_Full);
+ FW_CAPS_TO_LMM(SPEED_400G, 400000baseLR8_ER8_FR8_Full);
break;
- case FW_PORT_TYPE_CR2_QSFP:
- SET_LMM(FIBRE);
- FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
+ case LINK_MEDIUM_DR:
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseDR2_Full);
+ FW_CAPS_TO_LMM(SPEED_200G, 200000baseDR4_Full);
+ FW_CAPS_TO_LMM(SPEED_400G, 400000baseDR8_Full);
break;
- case FW_PORT_TYPE_KR4_100G:
- case FW_PORT_TYPE_CR4_QSFP:
- SET_LMM(FIBRE);
- FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
- FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
- FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
- FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
- FW_CAPS_TO_LMM(SPEED_50G, 50000baseCR2_Full);
- FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR4_Full);
+ case LINK_MEDIUM_LRM:
+ FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
+ FW_CAPS_TO_LMM(SPEED_10G, 10000baseLRM_Full);
break;
+ case LINK_MEDIUM_NONE:
default:
break;
}
@@ -616,7 +696,7 @@ static void fw_caps_to_lmm(enum fw_port_type port_type,
FW_CAPS_TO_LMM(FEC_RS, FEC_RS);
FW_CAPS_TO_LMM(FEC_BASER_RS, FEC_BASER);
} else {
- SET_LMM(FEC_NONE);
+ __set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, link_mode_mask);
}
FW_CAPS_TO_LMM(ANEG, Autoneg);
@@ -624,7 +704,6 @@ static void fw_caps_to_lmm(enum fw_port_type port_type,
FW_CAPS_TO_LMM(802_3_ASM_DIR, Asym_Pause);
#undef FW_CAPS_TO_LMM
- #undef SET_LMM
}
/**
@@ -649,10 +728,46 @@ static unsigned int lmm_to_fw_caps(const unsigned long *link_mode_mask)
LMM_TO_FW_CAPS(100baseT_Full, SPEED_100M);
LMM_TO_FW_CAPS(1000baseT_Full, SPEED_1G);
LMM_TO_FW_CAPS(10000baseT_Full, SPEED_10G);
- LMM_TO_FW_CAPS(40000baseSR4_Full, SPEED_40G);
+ LMM_TO_FW_CAPS(10000baseKX4_Full, SPEED_10G);
+ LMM_TO_FW_CAPS(10000baseR_FEC, SPEED_10G);
+ LMM_TO_FW_CAPS(10000baseKR_Full, SPEED_10G);
+ LMM_TO_FW_CAPS(10000baseCR_Full, SPEED_10G);
+ LMM_TO_FW_CAPS(10000baseSR_Full, SPEED_10G);
+ LMM_TO_FW_CAPS(10000baseLR_Full, SPEED_10G);
+ LMM_TO_FW_CAPS(10000baseLRM_Full, SPEED_10G);
+ LMM_TO_FW_CAPS(25000baseKR_Full, SPEED_25G);
LMM_TO_FW_CAPS(25000baseCR_Full, SPEED_25G);
+ LMM_TO_FW_CAPS(25000baseSR_Full, SPEED_25G);
+ LMM_TO_FW_CAPS(40000baseKR4_Full, SPEED_40G);
+ LMM_TO_FW_CAPS(40000baseCR4_Full, SPEED_40G);
+ LMM_TO_FW_CAPS(40000baseSR4_Full, SPEED_40G);
+ LMM_TO_FW_CAPS(40000baseLR4_Full, SPEED_40G);
+ LMM_TO_FW_CAPS(50000baseKR_Full, SPEED_50G);
+ LMM_TO_FW_CAPS(50000baseKR2_Full, SPEED_50G);
+ LMM_TO_FW_CAPS(50000baseCR_Full, SPEED_50G);
LMM_TO_FW_CAPS(50000baseCR2_Full, SPEED_50G);
+ LMM_TO_FW_CAPS(50000baseSR_Full, SPEED_50G);
+ LMM_TO_FW_CAPS(50000baseSR2_Full, SPEED_50G);
+ LMM_TO_FW_CAPS(50000baseLR_ER_FR_Full, SPEED_50G);
+ LMM_TO_FW_CAPS(100000baseKR2_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(100000baseKR4_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(100000baseCR2_Full, SPEED_100G);
LMM_TO_FW_CAPS(100000baseCR4_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(100000baseSR2_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(100000baseSR4_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(100000baseLR2_ER2_FR2_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(100000baseLR4_ER4_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(100000baseDR2_Full, SPEED_100G);
+ LMM_TO_FW_CAPS(200000baseKR4_Full, SPEED_200G);
+ LMM_TO_FW_CAPS(200000baseCR4_Full, SPEED_200G);
+ LMM_TO_FW_CAPS(200000baseSR4_Full, SPEED_200G);
+ LMM_TO_FW_CAPS(200000baseLR4_ER4_FR4_Full, SPEED_200G);
+ LMM_TO_FW_CAPS(200000baseDR4_Full, SPEED_200G);
+ LMM_TO_FW_CAPS(400000baseKR8_Full, SPEED_400G);
+ LMM_TO_FW_CAPS(400000baseCR8_Full, SPEED_400G);
+ LMM_TO_FW_CAPS(400000baseSR8_Full, SPEED_400G);
+ LMM_TO_FW_CAPS(400000baseLR8_ER8_FR8_Full, SPEED_400G);
+ LMM_TO_FW_CAPS(400000baseDR8_Full, SPEED_400G);
#undef LMM_TO_FW_CAPS
@@ -688,14 +803,14 @@ static int get_link_ksettings(struct net_device *dev,
base->mdio_support = 0;
}
- fw_caps_to_lmm(pi->port_type, pi->link_cfg.pcaps,
+ fw_caps_to_lmm(pi->port_type, pi->mod_type, pi->link_cfg.pcaps,
link_ksettings->link_modes.supported);
- fw_caps_to_lmm(pi->port_type,
+ fw_caps_to_lmm(pi->port_type, pi->mod_type,
t4_link_acaps(pi->adapter,
pi->lport,
&pi->link_cfg),
link_ksettings->link_modes.advertising);
- fw_caps_to_lmm(pi->port_type, pi->link_cfg.lpacaps,
+ fw_caps_to_lmm(pi->port_type, pi->mod_type, pi->link_cfg.lpacaps,
link_ksettings->link_modes.lp_advertising);
base->speed = (netif_carrier_ok(dev)
@@ -800,7 +915,7 @@ static inline unsigned int eth_to_cc_fec(unsigned int eth_fec)
{
unsigned int cc_fec = 0;
- if (eth_fec & ETHTOOL_FEC_OFF)
+ if (eth_fec == ETHTOOL_FEC_OFF)
return cc_fec;
if (eth_fec & ETHTOOL_FEC_AUTO)
@@ -1576,6 +1691,11 @@ static int get_ts_info(struct net_device *dev, struct kernel_ethtool_ts_info *ts
return 0;
}
+static u32 get_rss_key_size(struct net_device *dev)
+{
+ return RSS_HASH_KEY_SIZE;
+}
+
static u32 get_rss_table_size(struct net_device *dev)
{
const struct port_info *pi = netdev_priv(dev);
@@ -1590,8 +1710,19 @@ static int get_rss_table(struct net_device *dev,
unsigned int n = pi->rss_size;
rxfh->hfunc = ETH_RSS_HASH_TOP;
+
+ if (rxfh->key) {
+ __be32 key[10];
+
+ t4_read_rss_key(pi->adapter, (u32 *)key, true);
+ /* RSS hash keys are read in order TP_RSS_SECRET_KEY9..0 */
+ for (int i = 0; i < 10; i++)
+ ((u32 *)rxfh->key)[i] = be32_to_cpu(key[9 - i]);
+ }
+
if (!rxfh->indir)
return 0;
+
while (n--)
rxfh->indir[n] = pi->rss[n];
return 0;
@@ -1607,10 +1738,19 @@ static int set_rss_table(struct net_device *dev,
/* We require at least one supported parameter to be changed and no
* change in any of the unsupported parameters
*/
- if (rxfh->key ||
- (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
- rxfh->hfunc != ETH_RSS_HASH_TOP))
+ if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
+ rxfh->hfunc != ETH_RSS_HASH_TOP)
return -EOPNOTSUPP;
+
+ if (rxfh->key) {
+ __be32 key[10];
+
+ /* RSS hash keys are written in order TP_RSS_SECRET_KEY9..0 */
+ for (int i = 0; i < 10; i++)
+ key[i] = cpu_to_be32(((u32 *)rxfh->key)[9 - i]);
+ t4_write_rss_key(pi->adapter, (u32 *)key, -1, true);
+ }
+
if (!rxfh->indir)
return 0;
@@ -2022,12 +2162,13 @@ static int cxgb4_get_module_info(struct net_device *dev,
case FW_PORT_TYPE_SFP:
case FW_PORT_TYPE_QSA:
case FW_PORT_TYPE_SFP28:
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ case FW_PORT_TYPE_SFP56:
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, SFF_8472_COMP_ADDR,
SFF_8472_COMP_LEN, &sff8472_comp);
if (ret)
return ret;
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, SFP_DIAG_TYPE_ADDR,
SFP_DIAG_TYPE_LEN, &sff_diag_type);
if (ret)
@@ -2046,11 +2187,12 @@ static int cxgb4_get_module_info(struct net_device *dev,
break;
case FW_PORT_TYPE_QSFP:
+ case FW_PORT_TYPE_QSFP56:
case FW_PORT_TYPE_QSFP_10G:
case FW_PORT_TYPE_CR_QSFP:
case FW_PORT_TYPE_CR2_QSFP:
case FW_PORT_TYPE_CR4_QSFP:
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, SFF_REV_ADDR,
SFF_REV_LEN, &sff_rev);
/* For QSFP type ports, revision value >= 3
@@ -2083,14 +2225,14 @@ static int cxgb4_get_module_eeprom(struct net_device *dev,
memset(data, 0, eprom->len);
if (offset + len <= I2C_PAGE_SIZE)
- return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ return t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, offset, len, data);
/* offset + len spans 0xa0 and 0xa1 pages */
if (offset <= I2C_PAGE_SIZE) {
/* read 0xa0 page */
len = I2C_PAGE_SIZE - offset;
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, offset, len, data);
if (ret)
return ret;
@@ -2101,10 +2243,41 @@ static int cxgb4_get_module_eeprom(struct net_device *dev,
len = eprom->len - len;
}
/* Read additional optical diagnostics from page 0xa2 if supported */
- return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan, I2C_DEV_ADDR_A2,
+ return t4_i2c_rd(adapter, adapter->mbox, pi->lport, I2C_DEV_ADDR_A2,
offset, len, &data[eprom->len - len]);
}
+static int
+cxgb4_get_module_eeprom_by_page(struct net_device *dev,
+ const struct ethtool_module_eeprom *page_data,
+ struct netlink_ext_ack *extack)
+{
+ struct port_info *pi = netdev_priv(dev);
+ struct adapter *adapter = pi->adapter;
+ int ret;
+
+ if (page_data->offset >= 128) {
+ u8 page = page_data->page;
+ /* Before reading EEPROM data first select the page in PageSelect register */
+ ret = t4_i2c_wr(adapter, adapter->mbox, pi->lport,
+ page_data->i2c_address << 1,
+ CMIS_PAGE_SELECT_REG, /* CMIS Page Select register */
+ 1, /* Page Select register length */
+ &page);
+ if (ret)
+ return ret;
+ }
+
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
+ page_data->i2c_address << 1, page_data->offset,
+ page_data->length, page_data->data);
+
+ if (ret)
+ return ret;
+
+ return page_data->length;
+}
+
static u32 cxgb4_get_priv_flags(struct net_device *netdev)
{
struct port_info *pi = netdev_priv(netdev);
@@ -2205,6 +2378,7 @@ static const struct ethtool_ops cxgb_ethtool_ops = {
.get_rxnfc = get_rxnfc,
.set_rxnfc = set_rxnfc,
.get_rx_ring_count = get_rx_ring_count,
+ .get_rxfh_key_size = get_rss_key_size,
.get_rxfh_indir_size = get_rss_table_size,
.get_rxfh = get_rss_table,
.set_rxfh = set_rss_table,
@@ -2217,6 +2391,7 @@ static const struct ethtool_ops cxgb_ethtool_ops = {
.get_dump_data = get_dump_data,
.get_module_info = cxgb4_get_module_info,
.get_module_eeprom = cxgb4_get_module_eeprom,
+ .get_module_eeprom_by_page = cxgb4_get_module_eeprom_by_page,
.get_priv_flags = cxgb4_get_priv_flags,
.set_priv_flags = cxgb4_set_priv_flags,
};
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 08/12] cxgb4: Add T7 support to the filter infrastructure.
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (6 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 07/12] cxgb4: extend ethtool support for T7 adapters Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 09/12] cxgb4: Add indirect register definitions for T7 Potnuri Bharat Teja
` (3 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
T7 introduces a number of changes in filter-related register fields,
firmware work request formats and CPL definitions. Update the filter
code to use the appropriate T7-specific encodings while preserving
existing behavior on earlier adapters.
The changes include:
- Use T7 reply channel and queue number encodings in filter-related
CPL requests.
- Add T7-specific filter capability validation using the new TP filter
field definitions.
- Enable validation and programming of the SYN-only filter field,
which is supported on T7.
- Adjust FW_FILTER_WR construction to match T7 semantics where the
RX channel is no longer programmed through the legacy field.
- Add support for T7 active-open filter requests using the T7 CPL
layout and T7 filter tuple encoding.
- Update filter resource handling to work correctly across T6 and T7
devices.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/cxgb4_filter.c | 214 ++++++++++++------
1 file changed, 141 insertions(+), 73 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
index 657d96b9e2f6..c9182c69cc7e 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
@@ -66,9 +66,14 @@ static int set_tcb_field(struct adapter *adap, struct filter_entry *f,
req = (struct cpl_set_tcb_field *)__skb_put_zero(skb, sizeof(*req));
INIT_TP_WR_CPL(req, CPL_SET_TCB_FIELD, ftid);
- req->reply_ctrl = htons(REPLY_CHAN_V(0) |
- QUEUENO_V(adap->sge.fw_evtq.abs_id) |
- NO_REPLY_V(no_reply));
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ req->reply_ctrl = htons(T7_REPLY_CHAN_V(0) |
+ T7_QUEUENO_V(adap->sge.fw_evtq.abs_id) |
+ NO_REPLY_V(no_reply));
+ else
+ req->reply_ctrl = htons(REPLY_CHAN_V(0) |
+ QUEUENO_V(adap->sge.fw_evtq.abs_id) |
+ NO_REPLY_V(no_reply));
req->word_cookie = htons(TCB_WORD_V(word) | TCB_COOKIE_V(ftid));
req->mask = cpu_to_be64(mask);
req->val = cpu_to_be64(val);
@@ -249,32 +254,53 @@ static int validate_filter(struct net_device *dev,
struct ch_filter_specification *fs)
{
struct adapter *adapter = netdev2adap(dev);
- u32 fconf, iconf;
+ u32 fconf, iconf, chip_ver;
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
/* Check for unconfigured fields being used. */
iconf = adapter->params.tp.ingress_config;
fconf = fs->hash ? adapter->params.tp.filter_mask :
adapter->params.tp.vlan_pri_map;
- if (unsupported(fconf, FCOE_F, fs->val.fcoe, fs->mask.fcoe) ||
- unsupported(fconf, PORT_F, fs->val.iport, fs->mask.iport) ||
- unsupported(fconf, TOS_F, fs->val.tos, fs->mask.tos) ||
- unsupported(fconf, ETHERTYPE_F, fs->val.ethtype,
- fs->mask.ethtype) ||
- unsupported(fconf, MACMATCH_F, fs->val.macidx, fs->mask.macidx) ||
- unsupported(fconf, MPSHITTYPE_F, fs->val.matchtype,
- fs->mask.matchtype) ||
- unsupported(fconf, FRAGMENTATION_F, fs->val.frag, fs->mask.frag) ||
- unsupported(fconf, PROTOCOL_F, fs->val.proto, fs->mask.proto) ||
- unsupported(fconf, VNIC_ID_F, fs->val.pfvf_vld,
- fs->mask.pfvf_vld) ||
- unsupported(fconf, VNIC_ID_F, fs->val.ovlan_vld,
- fs->mask.ovlan_vld) ||
- unsupported(fconf, VNIC_ID_F, fs->val.encap_vld,
- fs->mask.encap_vld) ||
- unsupported(fconf, VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld))
- return -EOPNOTSUPP;
-
+ if (chip_ver >= CHELSIO_T7) {
+ if (unsupported(fconf, T7_FCOE_F, fs->val.fcoe, fs->mask.fcoe) ||
+ unsupported(fconf, T7_PORT_F, fs->val.iport, fs->mask.iport) ||
+ unsupported(fconf, T7_TOS_F, fs->val.tos, fs->mask.tos) ||
+ unsupported(fconf, T7_ETHERTYPE_F, fs->val.ethtype,
+ fs->mask.ethtype) ||
+ unsupported(fconf, T7_MACMATCH_F, fs->val.macidx, fs->mask.macidx) ||
+ unsupported(fconf, T7_MPSHITTYPE_F, fs->val.matchtype,
+ fs->mask.matchtype) ||
+ unsupported(fconf, T7_FRAGMENTATION_F, fs->val.frag, fs->mask.frag) ||
+ unsupported(fconf, T7_PROTOCOL_F, fs->val.proto, fs->mask.proto) ||
+ unsupported(fconf, T7_VNIC_ID_F, fs->val.pfvf_vld,
+ fs->mask.pfvf_vld) ||
+ unsupported(fconf, T7_VNIC_ID_F, fs->val.ovlan_vld,
+ fs->mask.ovlan_vld) ||
+ unsupported(fconf, T7_VNIC_ID_F, fs->val.encap_vld,
+ fs->mask.encap_vld) ||
+ unsupported(fconf, T7_VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld))
+ return -EOPNOTSUPP;
+ } else {
+ if (unsupported(fconf, FCOE_F, fs->val.fcoe, fs->mask.fcoe) ||
+ unsupported(fconf, PORT_F, fs->val.iport, fs->mask.iport) ||
+ unsupported(fconf, TOS_F, fs->val.tos, fs->mask.tos) ||
+ unsupported(fconf, ETHERTYPE_F, fs->val.ethtype,
+ fs->mask.ethtype) ||
+ unsupported(fconf, MACMATCH_F, fs->val.macidx, fs->mask.macidx) ||
+ unsupported(fconf, MPSHITTYPE_F, fs->val.matchtype,
+ fs->mask.matchtype) ||
+ unsupported(fconf, FRAGMENTATION_F, fs->val.frag, fs->mask.frag) ||
+ unsupported(fconf, PROTOCOL_F, fs->val.proto, fs->mask.proto) ||
+ unsupported(fconf, VNIC_ID_F, fs->val.pfvf_vld,
+ fs->mask.pfvf_vld) ||
+ unsupported(fconf, VNIC_ID_F, fs->val.ovlan_vld,
+ fs->mask.ovlan_vld) ||
+ unsupported(fconf, VNIC_ID_F, fs->val.encap_vld,
+ fs->mask.encap_vld) ||
+ unsupported(fconf, VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld))
+ return -EOPNOTSUPP;
+ }
/* T4 inconveniently uses the same FT_VNIC_ID_W bits for both the Outer
* VLAN Tag and PF/VF/VFvld fields based on VNIC_F being set
* in TP_INGRESS_CONFIG. Hense the somewhat crazy checks
@@ -793,9 +819,12 @@ static int del_filter_wr(struct adapter *adapter, int fidx)
int set_filter_wr(struct adapter *adapter, int fidx)
{
struct fw_filter2_wr *fwr;
+ unsigned int chip_ver;
struct filter_entry *f;
struct sk_buff *skb;
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
+
if (fidx < adapter->tids.nhpftids)
f = &adapter->tids.hpftid_tab[fidx];
else
@@ -883,8 +912,10 @@ int set_filter_wr(struct adapter *adapter, int fidx)
if (f->fs.newsmac)
fwr->smac_sel = f->smt->idx;
fwr->rx_chan_rx_rpl_iq =
- htons(FW_FILTER_WR_RX_CHAN_V(0) |
- FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
+ htons(FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
+ if (chip_ver <= CHELSIO_T6)
+ fwr->rx_chan_rx_rpl_iq |=
+ htons(FW_FILTER_WR_RX_CHAN_V(cxgb4_port_e2cchan(f->dev)));
fwr->maci_to_matchtypem =
htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
@@ -993,7 +1024,9 @@ void clear_filter(struct adapter *adap, struct filter_entry *f)
t4_free_encap_mac_filt(adap, pi->viid,
f->fs.val.ovlan & 0x1ff, 0);
- if ((f->fs.hash || is_t6(adap->params.chip)) && f->fs.type)
+ if ((f->fs.hash ||
+ (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T6)) &&
+ f->fs.type)
cxgb4_clip_release(f->dev, (const u32 *)&f->fs.val.lip, 1);
/* The zeroing of the filter rule below clears the filter valid,
@@ -1296,20 +1329,16 @@ static void mk_act_open_req6(struct filter_entry *f, struct sk_buff *skb,
unsigned int qid_filterid, struct adapter *adap)
{
struct cpl_t6_act_open_req6 *t6req = NULL;
+ struct cpl_t7_act_open_req6 *t7req = NULL;
struct cpl_act_open_req6 *req = NULL;
+ u32 chip_ver;
+ __be32 opt2;
+ __be64 opt0;
- t6req = (struct cpl_t6_act_open_req6 *)__skb_put(skb, sizeof(*t6req));
- INIT_TP_WR(t6req, 0);
- req = (struct cpl_act_open_req6 *)t6req;
- OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6, qid_filterid));
- req->local_port = cpu_to_be16(f->fs.val.lport);
- req->peer_port = cpu_to_be16(f->fs.val.fport);
- req->local_ip_hi = *(__be64 *)(&f->fs.val.lip);
- req->local_ip_lo = *(((__be64 *)&f->fs.val.lip) + 1);
- req->peer_ip_hi = *(__be64 *)(&f->fs.val.fip);
- req->peer_ip_lo = *(((__be64 *)&f->fs.val.fip) + 1);
- req->opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
- f->fs.newvlan == VLAN_REWRITE) |
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
+ f->fs.newvlan == VLAN_REWRITE) |
DELACK_V(f->fs.hitcnts) |
L2T_IDX_V(f->l2t ? f->l2t->idx : 0) |
SMAC_SEL_V((cxgb4_port_viid(f->dev) &
@@ -1319,52 +1348,90 @@ static void mk_act_open_req6(struct filter_entry *f, struct sk_buff *skb,
ULP_MODE_V(f->fs.nat_mode ?
ULP_MODE_TCPDDP : ULP_MODE_NONE) |
TCAM_BYPASS_F | NON_OFFLOAD_F);
- t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs,
- f->dev)));
- t6req->opt2 = htonl(RSS_QUEUE_VALID_F |
- RSS_QUEUE_V(f->fs.iq) |
- TX_QUEUE_V(f->fs.nat_mode) |
- T5_OPT_2_VALID_F |
- RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
- PACE_V((f->fs.maskhash) |
+ opt2 = cpu_to_be32(RSS_QUEUE_VALID_F |
+ RSS_QUEUE_V(f->fs.iq) |
+ TX_QUEUE_V(f->fs.nat_mode) |
+ T5_OPT_2_VALID_F |
+ RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
+ PACE_V((f->fs.maskhash) |
((f->fs.dirsteerhash) << 1)));
+
+ if (chip_ver >= CHELSIO_T7) {
+ t7req = (struct cpl_t7_act_open_req6 *)__skb_put(skb, sizeof(*t7req));
+ INIT_TP_WR(t7req, 0);
+ req = (struct cpl_act_open_req6 *)t7req;
+ t7req->opt0 = opt0;
+ t7req->opt2 = opt2;
+ t7req->params = cpu_to_be64(T7_FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ } else {
+ t6req = (struct cpl_t6_act_open_req6 *)__skb_put(skb, sizeof(*t6req));
+ INIT_TP_WR(t6req, 0);
+ req = (struct cpl_act_open_req6 *)t6req;
+ t6req->opt0 = opt0;
+ t6req->opt2 = opt2;
+ t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ }
+
+ OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6, qid_filterid));
+ req->local_port = cpu_to_be16(f->fs.val.lport);
+ req->peer_port = cpu_to_be16(f->fs.val.fport);
+ req->local_ip_hi = *(__be64 *)(&f->fs.val.lip);
+ req->local_ip_lo = *(((__be64 *)&f->fs.val.lip) + 1);
+ req->peer_ip_hi = *(__be64 *)(&f->fs.val.fip);
+ req->peer_ip_lo = *(((__be64 *)&f->fs.val.fip) + 1);
}
static void mk_act_open_req(struct filter_entry *f, struct sk_buff *skb,
unsigned int qid_filterid, struct adapter *adap)
{
struct cpl_t6_act_open_req *t6req = NULL;
+ struct cpl_t7_act_open_req *t7req = NULL;
struct cpl_act_open_req *req = NULL;
+ u32 chip_ver;
+ __be32 opt2;
+ __be64 opt0;
+
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
+ f->fs.newvlan == VLAN_REWRITE) |
+ DELACK_V(f->fs.hitcnts) |
+ L2T_IDX_V(f->l2t ? f->l2t->idx : 0) |
+ SMAC_SEL_V((cxgb4_port_viid(f->dev) &
+ 0x7F) << 1) |
+ TX_CHAN_V(f->fs.eport) |
+ NO_CONG_V(f->fs.rpttid) |
+ ULP_MODE_V(f->fs.nat_mode ?
+ ULP_MODE_TCPDDP : ULP_MODE_NONE) |
+ TCAM_BYPASS_F | NON_OFFLOAD_F);
+ opt2 = cpu_to_be32(RSS_QUEUE_VALID_F |
+ RSS_QUEUE_V(f->fs.iq) |
+ TX_QUEUE_V(f->fs.nat_mode) |
+ T5_OPT_2_VALID_F |
+ RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
+ PACE_V((f->fs.maskhash) |
+ ((f->fs.dirsteerhash) << 1)));
+ if (chip_ver >= CHELSIO_T7) {
+ t7req = (struct cpl_t7_act_open_req *)__skb_put(skb, sizeof(*t7req));
+ INIT_TP_WR(t7req, 0);
+ req = (struct cpl_act_open_req *)t7req;
+ t7req->opt0 = opt0;
+ t7req->opt2 = opt2;
+ t7req->params = cpu_to_be64(T7_FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ } else {
+ t6req = (struct cpl_t6_act_open_req *)__skb_put(skb, sizeof(*t6req));
+ INIT_TP_WR(t6req, 0);
+ req = (struct cpl_act_open_req *)t6req;
+ t6req->opt0 = opt0;
+ t6req->opt2 = opt2;
+ t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ }
- t6req = (struct cpl_t6_act_open_req *)__skb_put(skb, sizeof(*t6req));
- INIT_TP_WR(t6req, 0);
- req = (struct cpl_act_open_req *)t6req;
OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ACT_OPEN_REQ, qid_filterid));
req->local_port = cpu_to_be16(f->fs.val.lport);
req->peer_port = cpu_to_be16(f->fs.val.fport);
memcpy(&req->local_ip, f->fs.val.lip, 4);
memcpy(&req->peer_ip, f->fs.val.fip, 4);
- req->opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
- f->fs.newvlan == VLAN_REWRITE) |
- DELACK_V(f->fs.hitcnts) |
- L2T_IDX_V(f->l2t ? f->l2t->idx : 0) |
- SMAC_SEL_V((cxgb4_port_viid(f->dev) &
- 0x7F) << 1) |
- TX_CHAN_V(f->fs.eport) |
- NO_CONG_V(f->fs.rpttid) |
- ULP_MODE_V(f->fs.nat_mode ?
- ULP_MODE_TCPDDP : ULP_MODE_NONE) |
- TCAM_BYPASS_F | NON_OFFLOAD_F);
-
- t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs,
- f->dev)));
- t6req->opt2 = htonl(RSS_QUEUE_VALID_F |
- RSS_QUEUE_V(f->fs.iq) |
- TX_QUEUE_V(f->fs.nat_mode) |
- T5_OPT_2_VALID_F |
- RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
- PACE_V((f->fs.maskhash) |
- ((f->fs.dirsteerhash) << 1)));
}
static int cxgb4_set_hash_filter(struct net_device *dev,
@@ -1663,7 +1730,7 @@ int __cxgb4_set_filter(struct net_device *dev, int ftid,
if (ret)
goto free_tid;
- if (is_t6(adapter->params.chip) && fs->type &&
+ if (chip_ver >= CHELSIO_T6 && fs->type &&
ipv6_addr_type((const struct in6_addr *)fs->val.lip) !=
IPV6_ADDR_ANY) {
ret = cxgb4_clip_get(dev, (const u32 *)&fs->val.lip, 1);
@@ -2140,12 +2207,13 @@ void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
void init_hash_filter(struct adapter *adap)
{
- u32 reg;
+ u32 reg, chip_ver;
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
/* On T6, verify the necessary register configs and warn the user in
* case of improper config
*/
- if (is_t6(adap->params.chip)) {
+ if (chip_ver >= CHELSIO_T6) {
if (is_offload(adap)) {
if (!(t4_read_reg(adap, TP_GLOBAL_CONFIG_A)
& ACTIVEFILTERCOUNTS_F)) {
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 09/12] cxgb4: Add indirect register definitions for T7
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (7 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 08/12] cxgb4: Add T7 support to the filter infrastructure Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 10/12] cxgb4: extend CUDBG support for T7 adapters Potnuri Bharat Teja
` (2 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Add indirect register definition headers used by the CUDBG
infrastructure.
Introduce cudbg_indir_reg.h and cudbg_indir_reg_t7.h containing the
indirect registers required for cudbg register collection.
These headers will be used by subsequent patch that add indirect
register handling support to cudbg.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../ethernet/chelsio/cxgb4/cudbg_indir_reg.h | 43 +
.../chelsio/cxgb4/cudbg_indir_reg_t7.h | 1113 +++++++++++++++++
2 files changed, 1156 insertions(+)
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
new file mode 100644
index 000000000000..a33e003c78d5
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ */
+
+#ifndef __CUDBG_INDIR_REG_H__
+#define __CUDBG_INDIR_REG_H__
+
+enum cudbg_indir_type {
+ CUDBG_INDIR_TYPE_CIM_CTL,
+ CUDBG_INDIR_TYPE_PM_RX_DBG_CTRL,
+ CUDBG_INDIR_TYPE_PM_TX_DBG_CTRL,
+ CUDBG_INDIR_TYPE_TP_MIB_INDEX,
+ CUDBG_INDIR_TYPE_TP_PIO_ADDR,
+ CUDBG_INDIR_TYPE_TP_TM_PIO_ADDR,
+ CUDBG_INDIR_TYPE_UP,
+ CUDBG_INDIR_TYPE_HMAT6_LOCAL_DEBUG_CFG,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_CFG,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_PERF_CFG,
+ CUDBG_INDIR_TYPE_MAX, /* New members need to be added at end */
+};
+
+struct cudbg_indir_reg {
+ u32 addr;
+};
+
+struct cudbg_indir_type_entry {
+ struct cudbg_indir_reg *reg_arr;
+ u32 nentries;
+};
+
+#include "cudbg_indir_reg_t7.h"
+
+static inline struct cudbg_indir_type_entry *
+cudbg_get_indir_reg_info(u32 chip_ver, enum cudbg_indir_type type)
+{
+ if (chip_ver >= CHELSIO_T7)
+ return &t7_indir_type_arr[type];
+
+ return NULL;
+}
+
+#endif /* __CUDBG_INDIR_REG_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
new file mode 100644
index 000000000000..a246009ffb8d
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
@@ -0,0 +1,1113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ */
+
+#ifndef __CUDBG_INDIR_REG_T7_H__
+#define __CUDBG_INDIR_REG_T7_H__
+
+static struct cudbg_indir_reg t7_cim_ctl[82] = {
+ { .addr = 0x2000 },
+ { .addr = 0x2040 },
+ { .addr = 0x2044 },
+ { .addr = 0x2050 },
+ { .addr = 0x2054 },
+ { .addr = 0x2060 },
+ { .addr = 0x2064 },
+ { .addr = 0x2068 },
+ { .addr = 0x206c },
+ { .addr = 0x2094 },
+ { .addr = 0x2098 },
+ { .addr = 0x209c },
+ { .addr = 0x20a0 },
+ { .addr = 0x20a4 },
+ { .addr = 0x20a8 },
+ { .addr = 0x20ac },
+ { .addr = 0x20b0 },
+ { .addr = 0x20b4 },
+ { .addr = 0x20b8 },
+ { .addr = 0x20bc },
+ { .addr = 0x20c0 },
+ { .addr = 0x20c4 },
+ { .addr = 0x20c8 },
+ { .addr = 0x20cc },
+ { .addr = 0x20d0 },
+ { .addr = 0x20e0 },
+ { .addr = 0x20e4 },
+ { .addr = 0x20e8 },
+ { .addr = 0x20ec },
+ { .addr = 0x20f0 },
+ { .addr = 0x20f4 },
+ { .addr = 0x20f8 },
+ { .addr = 0x20fc },
+ { .addr = 0x2500 },
+ { .addr = 0x2504 },
+ { .addr = 0x2508 },
+ { .addr = 0x250c },
+ { .addr = 0x2510 },
+ { .addr = 0x2514 },
+ { .addr = 0x2518 },
+ { .addr = 0x251c },
+ { .addr = 0x2520 },
+ { .addr = 0x2524 },
+ { .addr = 0x2528 },
+ { .addr = 0x252c },
+ { .addr = 0x2530 },
+ { .addr = 0x2534 },
+ { .addr = 0x2538 },
+ { .addr = 0x253c },
+ { .addr = 0x2540 },
+ { .addr = 0x2600 },
+ { .addr = 0x2604 },
+ { .addr = 0x2608 },
+ { .addr = 0x260c },
+ { .addr = 0x2610 },
+ { .addr = 0x2614 },
+ { .addr = 0x2618 },
+ { .addr = 0x261c },
+ { .addr = 0x2620 },
+ { .addr = 0x2624 },
+ { .addr = 0x2628 },
+ { .addr = 0x262c },
+ { .addr = 0x2630 },
+ { .addr = 0x2634 },
+ { .addr = 0x2638 },
+ { .addr = 0x263c },
+ { .addr = 0x2640 },
+ { .addr = 0x26fc },
+ { .addr = 0x2700 },
+ { .addr = 0x2704 },
+ { .addr = 0x2708 },
+ { .addr = 0x270c },
+ { .addr = 0x2710 },
+ { .addr = 0x2714 },
+ { .addr = 0x2718 },
+ { .addr = 0x271c },
+ { .addr = 0x2720 },
+ { .addr = 0x2724 },
+ { .addr = 0x2728 },
+ { .addr = 0x2780 },
+ { .addr = 0x2784 },
+ { .addr = 0x2788 },
+};
+
+static struct cudbg_indir_reg t7_hmat6_local_debug_cfg[32] = {
+ { .addr = 0xa000 },
+ { .addr = 0xa001 },
+ { .addr = 0xa002 },
+ { .addr = 0xa003 },
+ { .addr = 0xa004 },
+ { .addr = 0xa005 },
+ { .addr = 0xa006 },
+ { .addr = 0xa007 },
+ { .addr = 0xa008 },
+ { .addr = 0xa009 },
+ { .addr = 0xa00a },
+ { .addr = 0xa00b },
+ { .addr = 0xa00c },
+ { .addr = 0xa00d },
+ { .addr = 0xa00e },
+ { .addr = 0xa00f },
+ { .addr = 0xa010 },
+ { .addr = 0xa011 },
+ { .addr = 0xa012 },
+ { .addr = 0xa013 },
+ { .addr = 0xa014 },
+ { .addr = 0xa015 },
+ { .addr = 0xa016 },
+ { .addr = 0xa017 },
+ { .addr = 0xa018 },
+ { .addr = 0xa019 },
+ { .addr = 0xa01a },
+ { .addr = 0xa01b },
+ { .addr = 0xa01c },
+ { .addr = 0xa01d },
+ { .addr = 0xa01e },
+ { .addr = 0xa01f },
+};
+
+static struct cudbg_indir_reg t7_ma_local_debug_cfg[238] = {
+ { .addr = 0xa000 },
+ { .addr = 0xa001 },
+ { .addr = 0xa002 },
+ { .addr = 0xa003 },
+ { .addr = 0xa004 },
+ { .addr = 0xa005 },
+ { .addr = 0xa006 },
+ { .addr = 0xa007 },
+ { .addr = 0xa008 },
+ { .addr = 0xa009 },
+ { .addr = 0xa00a },
+ { .addr = 0xa00b },
+ { .addr = 0xa00c },
+ { .addr = 0xa00d },
+ { .addr = 0xa00e },
+ { .addr = 0xa00f },
+ { .addr = 0xa010 },
+ { .addr = 0xa011 },
+ { .addr = 0xa012 },
+ { .addr = 0xa013 },
+ { .addr = 0xa014 },
+ { .addr = 0xa015 },
+ { .addr = 0xa016 },
+ { .addr = 0xa400 },
+ { .addr = 0xa401 },
+ { .addr = 0xa402 },
+ { .addr = 0xa403 },
+ { .addr = 0xa404 },
+ { .addr = 0xa405 },
+ { .addr = 0xa406 },
+ { .addr = 0xa407 },
+ { .addr = 0xa408 },
+ { .addr = 0xa409 },
+ { .addr = 0xa40a },
+ { .addr = 0xa40b },
+ { .addr = 0xa40c },
+ { .addr = 0xa40d },
+ { .addr = 0xa40e },
+ { .addr = 0xa40f },
+ { .addr = 0xa410 },
+ { .addr = 0xa412 },
+ { .addr = 0xa413 },
+ { .addr = 0xa414 },
+ { .addr = 0xa415 },
+ { .addr = 0xa416 },
+ { .addr = 0xa417 },
+ { .addr = 0xa418 },
+ { .addr = 0xa419 },
+ { .addr = 0xa41a },
+ { .addr = 0xa41b },
+ { .addr = 0xa41c },
+ { .addr = 0xa41d },
+ { .addr = 0xa41e },
+ { .addr = 0xa800 },
+ { .addr = 0xa801 },
+ { .addr = 0xa802 },
+ { .addr = 0xa803 },
+ { .addr = 0xa804 },
+ { .addr = 0xa805 },
+ { .addr = 0xa806 },
+ { .addr = 0xa807 },
+ { .addr = 0xa808 },
+ { .addr = 0xa809 },
+ { .addr = 0xa80a },
+ { .addr = 0xa80b },
+ { .addr = 0xa80c },
+ { .addr = 0xa80d },
+ { .addr = 0xa80e },
+ { .addr = 0xa80f },
+ { .addr = 0xa810 },
+ { .addr = 0xa811 },
+ { .addr = 0xa812 },
+ { .addr = 0xa813 },
+ { .addr = 0xac00 },
+ { .addr = 0xac01 },
+ { .addr = 0xac02 },
+ { .addr = 0xac03 },
+ { .addr = 0xac04 },
+ { .addr = 0xac05 },
+ { .addr = 0xac06 },
+ { .addr = 0xac07 },
+ { .addr = 0xac08 },
+ { .addr = 0xac09 },
+ { .addr = 0xac0a },
+ { .addr = 0xac0b },
+ { .addr = 0xac0c },
+ { .addr = 0xac0d },
+ { .addr = 0xac0e },
+ { .addr = 0xac0f },
+ { .addr = 0xac10 },
+ { .addr = 0xac11 },
+ { .addr = 0xac12 },
+ { .addr = 0xac13 },
+ { .addr = 0xac14 },
+ { .addr = 0xac15 },
+ { .addr = 0xac16 },
+ { .addr = 0xac17 },
+ { .addr = 0xac18 },
+ { .addr = 0xac19 },
+ { .addr = 0xb000 },
+ { .addr = 0xb001 },
+ { .addr = 0xb002 },
+ { .addr = 0xb003 },
+ { .addr = 0xb004 },
+ { .addr = 0xb005 },
+ { .addr = 0xb006 },
+ { .addr = 0xb007 },
+ { .addr = 0xb008 },
+ { .addr = 0xb009 },
+ { .addr = 0xb00a },
+ { .addr = 0xb00b },
+ { .addr = 0xb00c },
+ { .addr = 0xb00d },
+ { .addr = 0xb00e },
+ { .addr = 0xb00f },
+ { .addr = 0xb010 },
+ { .addr = 0xb011 },
+ { .addr = 0xb012 },
+ { .addr = 0xb013 },
+ { .addr = 0xb014 },
+ { .addr = 0xb015 },
+ { .addr = 0xb016 },
+ { .addr = 0xb017 },
+ { .addr = 0xb018 },
+ { .addr = 0xb019 },
+ { .addr = 0xb400 },
+ { .addr = 0xb401 },
+ { .addr = 0xb402 },
+ { .addr = 0xb403 },
+ { .addr = 0xb404 },
+ { .addr = 0xb405 },
+ { .addr = 0xb406 },
+ { .addr = 0xb407 },
+ { .addr = 0xb408 },
+ { .addr = 0xb409 },
+ { .addr = 0xb40a },
+ { .addr = 0xb40b },
+ { .addr = 0xb40c },
+ { .addr = 0xb40d },
+ { .addr = 0xb40e },
+ { .addr = 0xb40f },
+ { .addr = 0xb410 },
+ { .addr = 0xb411 },
+ { .addr = 0xb412 },
+ { .addr = 0xb413 },
+ { .addr = 0xb414 },
+ { .addr = 0xb415 },
+ { .addr = 0xb416 },
+ { .addr = 0xb417 },
+ { .addr = 0xb418 },
+ { .addr = 0xb419 },
+ { .addr = 0xe400 },
+ { .addr = 0xe420 },
+ { .addr = 0xe440 },
+ { .addr = 0xe460 },
+ { .addr = 0xe480 },
+ { .addr = 0xe4a0 },
+ { .addr = 0xe4c0 },
+ { .addr = 0xe4e0 },
+ { .addr = 0xe500 },
+ { .addr = 0xe520 },
+ { .addr = 0xe540 },
+ { .addr = 0xe560 },
+ { .addr = 0xe580 },
+ { .addr = 0xe5a0 },
+ { .addr = 0xe5c0 },
+ { .addr = 0xe5e0 },
+ { .addr = 0xe600 },
+ { .addr = 0xe640 },
+ { .addr = 0xe660 },
+ { .addr = 0xe680 },
+ { .addr = 0xe6a0 },
+ { .addr = 0xe6c0 },
+ { .addr = 0xe6e0 },
+ { .addr = 0xe700 },
+ { .addr = 0xe720 },
+ { .addr = 0xe740 },
+ { .addr = 0xe760 },
+ { .addr = 0xe780 },
+ { .addr = 0xe7a0 },
+ { .addr = 0xe7c0 },
+ { .addr = 0xe800 },
+ { .addr = 0xe820 },
+ { .addr = 0xe840 },
+ { .addr = 0xe860 },
+ { .addr = 0xe880 },
+ { .addr = 0xe8a0 },
+ { .addr = 0xe8c0 },
+ { .addr = 0xe8e0 },
+ { .addr = 0xe900 },
+ { .addr = 0xe920 },
+ { .addr = 0xe940 },
+ { .addr = 0xe960 },
+ { .addr = 0xe980 },
+ { .addr = 0xe9a0 },
+ { .addr = 0xe9c0 },
+ { .addr = 0xe9e0 },
+ { .addr = 0xec00 },
+ { .addr = 0xec20 },
+ { .addr = 0xec40 },
+ { .addr = 0xec60 },
+ { .addr = 0xec80 },
+ { .addr = 0xeca0 },
+ { .addr = 0xecc0 },
+ { .addr = 0xece0 },
+ { .addr = 0xed00 },
+ { .addr = 0xed20 },
+ { .addr = 0xed40 },
+ { .addr = 0xed60 },
+ { .addr = 0xed80 },
+ { .addr = 0xeda0 },
+ { .addr = 0xedc0 },
+ { .addr = 0xede0 },
+ { .addr = 0xee00 },
+ { .addr = 0xee20 },
+ { .addr = 0xee40 },
+ { .addr = 0xee60 },
+ { .addr = 0xee80 },
+ { .addr = 0xeea0 },
+ { .addr = 0xeec0 },
+ { .addr = 0xeee0 },
+ { .addr = 0xef00 },
+ { .addr = 0xef20 },
+ { .addr = 0xf000 },
+ { .addr = 0xf020 },
+ { .addr = 0xf040 },
+ { .addr = 0xf100 },
+ { .addr = 0xf101 },
+ { .addr = 0xf102 },
+ { .addr = 0xf103 },
+ { .addr = 0xf104 },
+ { .addr = 0xf105 },
+ { .addr = 0xf106 },
+ { .addr = 0xf107 },
+ { .addr = 0xf108 },
+ { .addr = 0xf120 },
+ { .addr = 0xf140 },
+ { .addr = 0xf160 },
+};
+
+static struct cudbg_indir_reg t7_ma_local_debug_perf_cfg[4] = {
+ { .addr = 0xa000 },
+ { .addr = 0xa1e0 },
+ { .addr = 0xe000 },
+ { .addr = 0xe1e0 },
+};
+
+static struct cudbg_indir_reg t7_pm_rx_dbg_ctrl[57] = {
+ { .addr = 0x10013 },
+ { .addr = 0x10014 },
+ { .addr = 0x10015 },
+ { .addr = 0x10016 },
+ { .addr = 0x10019 },
+ { .addr = 0x1001a },
+ { .addr = 0x1001b },
+ { .addr = 0x1001c },
+ { .addr = 0x1001d },
+ { .addr = 0x10020 },
+ { .addr = 0x10021 },
+ { .addr = 0x10022 },
+ { .addr = 0x10023 },
+ { .addr = 0x10024 },
+ { .addr = 0x10025 },
+ { .addr = 0x10026 },
+ { .addr = 0x10027 },
+ { .addr = 0x10028 },
+ { .addr = 0x10029 },
+ { .addr = 0x1002a },
+ { .addr = 0x1002b },
+ { .addr = 0x1002c },
+ { .addr = 0x1002d },
+ { .addr = 0x1002e },
+ { .addr = 0x1002f },
+ { .addr = 0x10030 },
+ { .addr = 0x10031 },
+ { .addr = 0x10032 },
+ { .addr = 0x10033 },
+ { .addr = 0x10034 },
+ { .addr = 0x10035 },
+ { .addr = 0x10036 },
+ { .addr = 0x10037 },
+ { .addr = 0x10038 },
+ { .addr = 0x10039 },
+ { .addr = 0x1003a },
+ { .addr = 0x1003b },
+ { .addr = 0x1003c },
+ { .addr = 0x1003d },
+ { .addr = 0x1003e },
+ { .addr = 0x10049 },
+ { .addr = 0x10060 },
+ { .addr = 0x10061 },
+ { .addr = 0x10062 },
+ { .addr = 0x10063 },
+ { .addr = 0x10070 },
+ { .addr = 0x10071 },
+ { .addr = 0x10072 },
+ { .addr = 0x10073 },
+ { .addr = 0x10074 },
+ { .addr = 0x10075 },
+ { .addr = 0x10076 },
+ { .addr = 0x10077 },
+ { .addr = 0x10078 },
+ { .addr = 0x10080 },
+ { .addr = 0x10081 },
+ { .addr = 0x10082 },
+};
+
+static struct cudbg_indir_reg t7_pm_tx_dbg_ctrl[38] = {
+ { .addr = 0x10000 },
+ { .addr = 0x10001 },
+ { .addr = 0x10002 },
+ { .addr = 0x10003 },
+ { .addr = 0x10004 },
+ { .addr = 0x10005 },
+ { .addr = 0x10006 },
+ { .addr = 0x10007 },
+ { .addr = 0x10008 },
+ { .addr = 0x10009 },
+ { .addr = 0x1000a },
+ { .addr = 0x1000b },
+ { .addr = 0x1000c },
+ { .addr = 0x1000d },
+ { .addr = 0x1000e },
+ { .addr = 0x1000f },
+ { .addr = 0x10010 },
+ { .addr = 0x10011 },
+ { .addr = 0x10012 },
+ { .addr = 0x10013 },
+ { .addr = 0x10014 },
+ { .addr = 0x10015 },
+ { .addr = 0x10016 },
+ { .addr = 0x10017 },
+ { .addr = 0x10018 },
+ { .addr = 0x10019 },
+ { .addr = 0x1001a },
+ { .addr = 0x1001b },
+ { .addr = 0x1001c },
+ { .addr = 0x1001d },
+ { .addr = 0x1001e },
+ { .addr = 0x1001f },
+ { .addr = 0x10020 },
+ { .addr = 0x10021 },
+ { .addr = 0x10022 },
+ { .addr = 0x10023 },
+ { .addr = 0x10024 },
+ { .addr = 0x10025 },
+};
+
+static struct cudbg_indir_reg t7_tp_mib_index[130] = {
+ { .addr = 0x0 },
+ { .addr = 0x1 },
+ { .addr = 0x2 },
+ { .addr = 0x3 },
+ { .addr = 0x4 },
+ { .addr = 0x5 },
+ { .addr = 0x6 },
+ { .addr = 0x7 },
+ { .addr = 0x8 },
+ { .addr = 0x9 },
+ { .addr = 0xa },
+ { .addr = 0xb },
+ { .addr = 0xc },
+ { .addr = 0x10 },
+ { .addr = 0x11 },
+ { .addr = 0x12 },
+ { .addr = 0x13 },
+ { .addr = 0x14 },
+ { .addr = 0x15 },
+ { .addr = 0x18 },
+ { .addr = 0x19 },
+ { .addr = 0x1a },
+ { .addr = 0x1b },
+ { .addr = 0x1c },
+ { .addr = 0x1d },
+ { .addr = 0x1e },
+ { .addr = 0x1f },
+ { .addr = 0x20 },
+ { .addr = 0x21 },
+ { .addr = 0x22 },
+ { .addr = 0x23 },
+ { .addr = 0x24 },
+ { .addr = 0x25 },
+ { .addr = 0x26 },
+ { .addr = 0x27 },
+ { .addr = 0x28 },
+ { .addr = 0x29 },
+ { .addr = 0x2a },
+ { .addr = 0x2b },
+ { .addr = 0x2c },
+ { .addr = 0x30 },
+ { .addr = 0x31 },
+ { .addr = 0x32 },
+ { .addr = 0x33 },
+ { .addr = 0x34 },
+ { .addr = 0x35 },
+ { .addr = 0x36 },
+ { .addr = 0x37 },
+ { .addr = 0x38 },
+ { .addr = 0x39 },
+ { .addr = 0x3a },
+ { .addr = 0x3b },
+ { .addr = 0x3c },
+ { .addr = 0x3d },
+ { .addr = 0x3e },
+ { .addr = 0x3f },
+ { .addr = 0x40 },
+ { .addr = 0x41 },
+ { .addr = 0x42 },
+ { .addr = 0x43 },
+ { .addr = 0x44 },
+ { .addr = 0x45 },
+ { .addr = 0x46 },
+ { .addr = 0x47 },
+ { .addr = 0x48 },
+ { .addr = 0x49 },
+ { .addr = 0x4a },
+ { .addr = 0x4b },
+ { .addr = 0x4c },
+ { .addr = 0x4d },
+ { .addr = 0x4e },
+ { .addr = 0x4f },
+ { .addr = 0x50 },
+ { .addr = 0x51 },
+ { .addr = 0x52 },
+ { .addr = 0x53 },
+ { .addr = 0x54 },
+ { .addr = 0x55 },
+ { .addr = 0x56 },
+ { .addr = 0x57 },
+ { .addr = 0x58 },
+ { .addr = 0x59 },
+ { .addr = 0x5a },
+ { .addr = 0x5b },
+ { .addr = 0x5c },
+ { .addr = 0x5d },
+ { .addr = 0x5e },
+ { .addr = 0x5f },
+ { .addr = 0x60 },
+ { .addr = 0x61 },
+ { .addr = 0x62 },
+ { .addr = 0x63 },
+ { .addr = 0x64 },
+ { .addr = 0x65 },
+ { .addr = 0x68 },
+ { .addr = 0x69 },
+ { .addr = 0x6a },
+ { .addr = 0x6b },
+ { .addr = 0x6c },
+ { .addr = 0x6d },
+ { .addr = 0x6e },
+ { .addr = 0x6f },
+ { .addr = 0x70 },
+ { .addr = 0x71 },
+ { .addr = 0x72 },
+ { .addr = 0x73 },
+ { .addr = 0x80 },
+ { .addr = 0x81 },
+ { .addr = 0x82 },
+ { .addr = 0x83 },
+ { .addr = 0x84 },
+ { .addr = 0x85 },
+ { .addr = 0x86 },
+ { .addr = 0x87 },
+ { .addr = 0x88 },
+ { .addr = 0x89 },
+ { .addr = 0x8a },
+ { .addr = 0x8b },
+ { .addr = 0x90 },
+ { .addr = 0x91 },
+ { .addr = 0x92 },
+ { .addr = 0x93 },
+ { .addr = 0x94 },
+ { .addr = 0x95 },
+ { .addr = 0x96 },
+ { .addr = 0x97 },
+ { .addr = 0x98 },
+ { .addr = 0x99 },
+ { .addr = 0x9a },
+ { .addr = 0x9b },
+};
+
+static struct cudbg_indir_reg t7_tp_pio_addr[191] = {
+ { .addr = 0x1c },
+ { .addr = 0x1d },
+ { .addr = 0x1e },
+ { .addr = 0x1f },
+ { .addr = 0x20 },
+ { .addr = 0x21 },
+ { .addr = 0x22 },
+ { .addr = 0x23 },
+ { .addr = 0x24 },
+ { .addr = 0x25 },
+ { .addr = 0x26 },
+ { .addr = 0x27 },
+ { .addr = 0x28 },
+ { .addr = 0x29 },
+ { .addr = 0x2a },
+ { .addr = 0x2b },
+ { .addr = 0x2c },
+ { .addr = 0x2d },
+ { .addr = 0x2e },
+ { .addr = 0x2f },
+ { .addr = 0x30 },
+ { .addr = 0x31 },
+ { .addr = 0x32 },
+ { .addr = 0x33 },
+ { .addr = 0x34 },
+ { .addr = 0x35 },
+ { .addr = 0x36 },
+ { .addr = 0x37 },
+ { .addr = 0x38 },
+ { .addr = 0x39 },
+ { .addr = 0x3a },
+ { .addr = 0x3b },
+ { .addr = 0x40 },
+ { .addr = 0x41 },
+ { .addr = 0x42 },
+ { .addr = 0x43 },
+ { .addr = 0x44 },
+ { .addr = 0x45 },
+ { .addr = 0x46 },
+ { .addr = 0x47 },
+ { .addr = 0x48 },
+ { .addr = 0x49 },
+ { .addr = 0x50 },
+ { .addr = 0x51 },
+ { .addr = 0x52 },
+ { .addr = 0x53 },
+ { .addr = 0x54 },
+ { .addr = 0x55 },
+ { .addr = 0x56 },
+ { .addr = 0x57 },
+ { .addr = 0x58 },
+ { .addr = 0x59 },
+ { .addr = 0x60 },
+ { .addr = 0x61 },
+ { .addr = 0x62 },
+ { .addr = 0x63 },
+ { .addr = 0x64 },
+ { .addr = 0x65 },
+ { .addr = 0x66 },
+ { .addr = 0x67 },
+ { .addr = 0x68 },
+ { .addr = 0x69 },
+ { .addr = 0x6a },
+ { .addr = 0x6b },
+ { .addr = 0x6c },
+ { .addr = 0x6d },
+ { .addr = 0x6f },
+ { .addr = 0x70 },
+ { .addr = 0x71 },
+ { .addr = 0x72 },
+ { .addr = 0x73 },
+ { .addr = 0x74 },
+ { .addr = 0x75 },
+ { .addr = 0x80 },
+ { .addr = 0x81 },
+ { .addr = 0x82 },
+ { .addr = 0x83 },
+ { .addr = 0x84 },
+ { .addr = 0x85 },
+ { .addr = 0x86 },
+ { .addr = 0x87 },
+ { .addr = 0x88 },
+ { .addr = 0x89 },
+ { .addr = 0x8a },
+ { .addr = 0x8b },
+ { .addr = 0x8c },
+ { .addr = 0x8d },
+ { .addr = 0x8e },
+ { .addr = 0x8f },
+ { .addr = 0x90 },
+ { .addr = 0x91 },
+ { .addr = 0x92 },
+ { .addr = 0x93 },
+ { .addr = 0x94 },
+ { .addr = 0x95 },
+ { .addr = 0x96 },
+ { .addr = 0x97 },
+ { .addr = 0x98 },
+ { .addr = 0x99 },
+ { .addr = 0x130 },
+ { .addr = 0x131 },
+ { .addr = 0x132 },
+ { .addr = 0x133 },
+ { .addr = 0x134 },
+ { .addr = 0x135 },
+ { .addr = 0x136 },
+ { .addr = 0x137 },
+ { .addr = 0x138 },
+ { .addr = 0x139 },
+ { .addr = 0x13a },
+ { .addr = 0x13b },
+ { .addr = 0x13c },
+ { .addr = 0x13d },
+ { .addr = 0x13e },
+ { .addr = 0x13f },
+ { .addr = 0x140 },
+ { .addr = 0x141 },
+ { .addr = 0x145 },
+ { .addr = 0x146 },
+ { .addr = 0x147 },
+ { .addr = 0x148 },
+ { .addr = 0x149 },
+ { .addr = 0x14a },
+ { .addr = 0x14b },
+ { .addr = 0x14c },
+ { .addr = 0x14d },
+ { .addr = 0x14e },
+ { .addr = 0x14f },
+ { .addr = 0x150 },
+ { .addr = 0x151 },
+ { .addr = 0x152 },
+ { .addr = 0x153 },
+ { .addr = 0x154 },
+ { .addr = 0x155 },
+ { .addr = 0x156 },
+ { .addr = 0x157 },
+ { .addr = 0x158 },
+ { .addr = 0x159 },
+ { .addr = 0x15a },
+ { .addr = 0x15b },
+ { .addr = 0x160 },
+ { .addr = 0x161 },
+ { .addr = 0x162 },
+ { .addr = 0x164 },
+ { .addr = 0x165 },
+ { .addr = 0x166 },
+ { .addr = 0x168 },
+ { .addr = 0x169 },
+ { .addr = 0x230 },
+ { .addr = 0x231 },
+ { .addr = 0x232 },
+ { .addr = 0x233 },
+ { .addr = 0x234 },
+ { .addr = 0x235 },
+ { .addr = 0x236 },
+ { .addr = 0x237 },
+ { .addr = 0x238 },
+ { .addr = 0x239 },
+ { .addr = 0x23a },
+ { .addr = 0x23b },
+ { .addr = 0x23c },
+ { .addr = 0x23d },
+ { .addr = 0x23e },
+ { .addr = 0x23f },
+ { .addr = 0x240 },
+ { .addr = 0x241 },
+ { .addr = 0x242 },
+ { .addr = 0x243 },
+ { .addr = 0x244 },
+ { .addr = 0x245 },
+ { .addr = 0x246 },
+ { .addr = 0x247 },
+ { .addr = 0x248 },
+ { .addr = 0x24a },
+ { .addr = 0x24b },
+ { .addr = 0x24c },
+ { .addr = 0x24d },
+ { .addr = 0x24e },
+ { .addr = 0x24f },
+ { .addr = 0x250 },
+ { .addr = 0x251 },
+ { .addr = 0x252 },
+ { .addr = 0x253 },
+ { .addr = 0x254 },
+ { .addr = 0x255 },
+ { .addr = 0x256 },
+ { .addr = 0x257 },
+ { .addr = 0x258 },
+ { .addr = 0x259 },
+ { .addr = 0x260 },
+ { .addr = 0x8c0 },
+};
+
+static struct cudbg_indir_reg t7_tp_tm_pio_addr[14] = {
+ { .addr = 0x0 },
+ { .addr = 0x1 },
+ { .addr = 0x2 },
+ { .addr = 0x3 },
+ { .addr = 0x4 },
+ { .addr = 0x5 },
+ { .addr = 0x6 },
+ { .addr = 0x7 },
+ { .addr = 0x8 },
+ { .addr = 0x9 },
+ { .addr = 0xa },
+ { .addr = 0xb },
+ { .addr = 0xc },
+ { .addr = 0xd },
+};
+
+static struct cudbg_indir_reg t7_up[245] = {
+ { .addr = 0x0 },
+ { .addr = 0x4 },
+ { .addr = 0x8 },
+ { .addr = 0xc },
+ { .addr = 0x10 },
+ { .addr = 0x80 },
+ { .addr = 0x84 },
+ { .addr = 0x88 },
+ { .addr = 0x8c },
+ { .addr = 0x90 },
+ { .addr = 0xc0 },
+ { .addr = 0xc4 },
+ { .addr = 0xc8 },
+ { .addr = 0xcc },
+ { .addr = 0xd0 },
+ { .addr = 0xd4 },
+ { .addr = 0x100 },
+ { .addr = 0x104 },
+ { .addr = 0x108 },
+ { .addr = 0x10c },
+ { .addr = 0x110 },
+ { .addr = 0x114 },
+ { .addr = 0x118 },
+ { .addr = 0x11c },
+ { .addr = 0x120 },
+ { .addr = 0x130 },
+ { .addr = 0x140 },
+ { .addr = 0x144 },
+ { .addr = 0x14c },
+ { .addr = 0x200 },
+ { .addr = 0x204 },
+ { .addr = 0x208 },
+ { .addr = 0x20c },
+ { .addr = 0x210 },
+ { .addr = 0x214 },
+ { .addr = 0x218 },
+ { .addr = 0x21c },
+ { .addr = 0x220 },
+ { .addr = 0x224 },
+ { .addr = 0x228 },
+ { .addr = 0x22c },
+ { .addr = 0x230 },
+ { .addr = 0x234 },
+ { .addr = 0x238 },
+ { .addr = 0x23c },
+ { .addr = 0x240 },
+ { .addr = 0x244 },
+ { .addr = 0x250 },
+ { .addr = 0x254 },
+ { .addr = 0x260 },
+ { .addr = 0x264 },
+ { .addr = 0x270 },
+ { .addr = 0x274 },
+ { .addr = 0x400 },
+ { .addr = 0x404 },
+ { .addr = 0x408 },
+ { .addr = 0x40c },
+ { .addr = 0x410 },
+ { .addr = 0x414 },
+ { .addr = 0x418 },
+ { .addr = 0x41c },
+ { .addr = 0x420 },
+ { .addr = 0x424 },
+ { .addr = 0x428 },
+ { .addr = 0x42c },
+ { .addr = 0x430 },
+ { .addr = 0x434 },
+ { .addr = 0x438 },
+ { .addr = 0x43c },
+ { .addr = 0x440 },
+ { .addr = 0x444 },
+ { .addr = 0x448 },
+ { .addr = 0x44c },
+ { .addr = 0x450 },
+ { .addr = 0x454 },
+ { .addr = 0x458 },
+ { .addr = 0x45c },
+ { .addr = 0x460 },
+ { .addr = 0x464 },
+ { .addr = 0x468 },
+ { .addr = 0x46c },
+ { .addr = 0x470 },
+ { .addr = 0x474 },
+ { .addr = 0x478 },
+ { .addr = 0x47c },
+ { .addr = 0x480 },
+ { .addr = 0x484 },
+ { .addr = 0x488 },
+ { .addr = 0x48c },
+ { .addr = 0x490 },
+ { .addr = 0x494 },
+ { .addr = 0x498 },
+ { .addr = 0x49c },
+ { .addr = 0x4a0 },
+ { .addr = 0x4a4 },
+ { .addr = 0x4a8 },
+ { .addr = 0x4ac },
+ { .addr = 0x4b0 },
+ { .addr = 0x4b4 },
+ { .addr = 0x4b8 },
+ { .addr = 0x4bc },
+ { .addr = 0x4c0 },
+ { .addr = 0x4c4 },
+ { .addr = 0x4c8 },
+ { .addr = 0x4cc },
+ { .addr = 0x4d0 },
+ { .addr = 0x4d4 },
+ { .addr = 0x4d8 },
+ { .addr = 0x4dc },
+ { .addr = 0x4e0 },
+ { .addr = 0x4e4 },
+ { .addr = 0x4e8 },
+ { .addr = 0x4ec },
+ { .addr = 0x4f0 },
+ { .addr = 0x4f4 },
+ { .addr = 0x4f8 },
+ { .addr = 0x4fc },
+ { .addr = 0x500 },
+ { .addr = 0x504 },
+ { .addr = 0x510 },
+ { .addr = 0x514 },
+ { .addr = 0x520 },
+ { .addr = 0x524 },
+ { .addr = 0x530 },
+ { .addr = 0x534 },
+ { .addr = 0x540 },
+ { .addr = 0x544 },
+ { .addr = 0x550 },
+ { .addr = 0x554 },
+ { .addr = 0x560 },
+ { .addr = 0x564 },
+ { .addr = 0x570 },
+ { .addr = 0x574 },
+ { .addr = 0x580 },
+ { .addr = 0x584 },
+ { .addr = 0x590 },
+ { .addr = 0x594 },
+ { .addr = 0x5a0 },
+ { .addr = 0x5a4 },
+ { .addr = 0x5b0 },
+ { .addr = 0x5b4 },
+ { .addr = 0x5c0 },
+ { .addr = 0x5c4 },
+ { .addr = 0x5d0 },
+ { .addr = 0x5d4 },
+ { .addr = 0x5e0 },
+ { .addr = 0x5e4 },
+ { .addr = 0x5f0 },
+ { .addr = 0x5f4 },
+ { .addr = 0x600 },
+ { .addr = 0x604 },
+ { .addr = 0x608 },
+ { .addr = 0x60c },
+ { .addr = 0x610 },
+ { .addr = 0x614 },
+ { .addr = 0x618 },
+ { .addr = 0x61c },
+ { .addr = 0x620 },
+ { .addr = 0x624 },
+ { .addr = 0x628 },
+ { .addr = 0x62c },
+ { .addr = 0x630 },
+ { .addr = 0x634 },
+ { .addr = 0x638 },
+ { .addr = 0x63c },
+ { .addr = 0x640 },
+ { .addr = 0x644 },
+ { .addr = 0x648 },
+ { .addr = 0x64c },
+ { .addr = 0x650 },
+ { .addr = 0x654 },
+ { .addr = 0x658 },
+ { .addr = 0x65c },
+ { .addr = 0x660 },
+ { .addr = 0x664 },
+ { .addr = 0x668 },
+ { .addr = 0x66c },
+ { .addr = 0x670 },
+ { .addr = 0x674 },
+ { .addr = 0x678 },
+ { .addr = 0x67c },
+ { .addr = 0x680 },
+ { .addr = 0x684 },
+ { .addr = 0x688 },
+ { .addr = 0x68c },
+ { .addr = 0x690 },
+ { .addr = 0x694 },
+ { .addr = 0x698 },
+ { .addr = 0x69c },
+ { .addr = 0x6a0 },
+ { .addr = 0x6a4 },
+ { .addr = 0x6a8 },
+ { .addr = 0x6ac },
+ { .addr = 0x6b0 },
+ { .addr = 0x6b4 },
+ { .addr = 0x6b8 },
+ { .addr = 0x6bc },
+ { .addr = 0x6c0 },
+ { .addr = 0x6c4 },
+ { .addr = 0x6c8 },
+ { .addr = 0x6cc },
+ { .addr = 0x6d0 },
+ { .addr = 0x6d4 },
+ { .addr = 0x6d8 },
+ { .addr = 0x6dc },
+ { .addr = 0x6e0 },
+ { .addr = 0x6e4 },
+ { .addr = 0x6e8 },
+ { .addr = 0x6ec },
+ { .addr = 0x6f0 },
+ { .addr = 0x6f4 },
+ { .addr = 0x6f8 },
+ { .addr = 0x6fc },
+ { .addr = 0x700 },
+ { .addr = 0x704 },
+ { .addr = 0x710 },
+ { .addr = 0x714 },
+ { .addr = 0x720 },
+ { .addr = 0x724 },
+ { .addr = 0x730 },
+ { .addr = 0x734 },
+ { .addr = 0x740 },
+ { .addr = 0x744 },
+ { .addr = 0x750 },
+ { .addr = 0x754 },
+ { .addr = 0x760 },
+ { .addr = 0x764 },
+ { .addr = 0x770 },
+ { .addr = 0x774 },
+ { .addr = 0x780 },
+ { .addr = 0x784 },
+ { .addr = 0x790 },
+ { .addr = 0x794 },
+ { .addr = 0x7a0 },
+ { .addr = 0x7a4 },
+ { .addr = 0x7b0 },
+ { .addr = 0x7b4 },
+ { .addr = 0x7c0 },
+ { .addr = 0x7c4 },
+ { .addr = 0x7d0 },
+ { .addr = 0x7d4 },
+ { .addr = 0x7e0 },
+ { .addr = 0x7e4 },
+ { .addr = 0x7f0 },
+ { .addr = 0x7f4 },
+};
+
+static struct cudbg_indir_type_entry t7_indir_type_arr[CUDBG_INDIR_TYPE_MAX] = {
+ [CUDBG_INDIR_TYPE_CIM_CTL] = {
+ .reg_arr = t7_cim_ctl,
+ .nentries = ARRAY_SIZE(t7_cim_ctl),
+ },
+ [CUDBG_INDIR_TYPE_HMAT6_LOCAL_DEBUG_CFG] = {
+ .reg_arr = t7_hmat6_local_debug_cfg,
+ .nentries = ARRAY_SIZE(t7_hmat6_local_debug_cfg),
+ },
+ [CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_CFG] = {
+ .reg_arr = t7_ma_local_debug_cfg,
+ .nentries = ARRAY_SIZE(t7_ma_local_debug_cfg),
+ },
+ [CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_PERF_CFG] = {
+ .reg_arr = t7_ma_local_debug_perf_cfg,
+ .nentries = ARRAY_SIZE(t7_ma_local_debug_perf_cfg),
+ },
+ [CUDBG_INDIR_TYPE_PM_RX_DBG_CTRL] = {
+ .reg_arr = t7_pm_rx_dbg_ctrl,
+ .nentries = ARRAY_SIZE(t7_pm_rx_dbg_ctrl),
+ },
+ [CUDBG_INDIR_TYPE_PM_TX_DBG_CTRL] = {
+ .reg_arr = t7_pm_tx_dbg_ctrl,
+ .nentries = ARRAY_SIZE(t7_pm_tx_dbg_ctrl),
+ },
+ [CUDBG_INDIR_TYPE_TP_MIB_INDEX] = {
+ .reg_arr = t7_tp_mib_index,
+ .nentries = ARRAY_SIZE(t7_tp_mib_index),
+ },
+ [CUDBG_INDIR_TYPE_TP_PIO_ADDR] = {
+ .reg_arr = t7_tp_pio_addr,
+ .nentries = ARRAY_SIZE(t7_tp_pio_addr),
+ },
+ [CUDBG_INDIR_TYPE_TP_TM_PIO_ADDR] = {
+ .reg_arr = t7_tp_tm_pio_addr,
+ .nentries = ARRAY_SIZE(t7_tp_tm_pio_addr),
+ },
+ [CUDBG_INDIR_TYPE_UP] = {
+ .reg_arr = t7_up,
+ .nentries = ARRAY_SIZE(t7_up),
+ },
+};
+
+#endif /* __CUDBG_INDIR_REG_T7_H__ */
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 10/12] cxgb4: extend CUDBG support for T7 adapters
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (8 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 09/12] cxgb4: Add indirect register definitions for T7 Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 11/12] cxgb4: extend debugfs " Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 12/12] cxgb4: select ULD Tx and control queues by TID on T7 Potnuri Bharat Teja
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Update the CUDBG infrastructure to support T7-specific debug data
collection.
Add support for collecting CIM IBQ and OBQ debug entities from T7
adapters, including the additional queues introduced by T7 and support
for multicore.
Also add T7 indirect register collection support using the new indirect
register definitions, while preserving the existing register access
mechanism for T5/T6.
Debug tooling needs to read and write individual adapter registers and
to read SGE contexts and queue descriptors without collecting a full
cudbg dump. Add a private ioctl providing four commands
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/cudbg_entity.h | 114 +-
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h | 56 +-
.../net/ethernet/chelsio/cxgb4/cudbg_lib.c | 1085 ++++++++++++++---
.../net/ethernet/chelsio/cxgb4/cudbg_lib.h | 60 +-
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 -
.../net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c | 20 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 242 ++++
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 20 -
drivers/net/ethernet/chelsio/cxgb4/t4_hw.h | 1 +
9 files changed, 1399 insertions(+), 200 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
index d5218e74284c..8295b330a7b9 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
@@ -21,13 +21,58 @@ struct cudbg_mbox_log {
u32 lo[MBOX_LEN / 8];
};
-struct cudbg_cim_qcfg {
- u8 chip;
- u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
- u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
- u16 thres[CIM_NUM_IBQ];
- u32 obq_wr[2 * CIM_NUM_OBQ_T5];
- u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
+#define CUDBG_CIM_IBQ_REV 1
+
+struct cim_ibq_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 qid;
+ u8 coreid;
+ u32 data[]; /* Must be last */
+};
+
+#define CUDBG_CIM_OBQ_REV 1
+
+struct cim_obq_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 qid;
+ u8 coreid;
+ u32 data[]; /* Must be last */
+};
+
+#define CUDBG_CIM_QCFG_REV 1
+
+enum cudbg_entity_cim_qcfg_qtype {
+ CUDBG_ENTITY_CIM_QCFG_QTYPE_IBQ = 0,
+ CUDBG_ENTITY_CIM_QCFG_QTYPE_OBQ,
+};
+
+struct cim_qcfg_rev1_data {
+ u8 qtype;
+ u8 qid;
+ u16 base;
+ u16 size;
+ u16 thres;
+ u32 obq_wr[2];
+ u32 stat[4];
+};
+
+struct cim_qcfg_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 num_cim_ibq;
+ u8 num_cim_obq;
+ u8 coreid;
+ struct cim_qcfg_rev1_data data[]; /* Must be last */
+};
+
+#define CUDBG_CIM_LA_REV 1
+
+struct cim_la_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 coreid;
+ u8 ncol;
+ u16 nrow;
+ u32 config;
+ u32 data[]; /* Must be last */
};
struct cudbg_rss_vf_conf {
@@ -50,6 +95,25 @@ struct cudbg_hw_sched {
u32 map;
};
+#define CUDBG_TP_INDIR_REG_REV 1
+#define CUDBG_PM_INDIR_REG_REV 1
+#define CUDBG_MA_INDIR_REG_REV 1
+#define CUDBG_UP_CIM_INDIR_REG_REV 1
+#define CUDBG_HMA_INDIR_REG_REV 1
+
+struct cudbg_indir_reg_data {
+ u32 offset;
+ u32 data;
+};
+
+struct cudbg_indir_reg_entity {
+ struct cudbg_ver_hdr ver_hdr;
+ u32 indir_reg;
+ u32 indir_data;
+ u32 nentries;
+ struct cudbg_indir_reg_data data[];
+};
+
#define SGE_QBASE_DATA_REG_NUM 4
struct sge_qbase_reg_field {
@@ -91,8 +155,8 @@ static const char * const cudbg_region[] = {
"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
"RQUDP region:", "PBL region:", "TXPBL region:",
- "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
- "On-chip queues:"
+ "RRQ region:", "DBVFIFO region:", "ULPRX state:",
+ "ULPTX state:", "On-chip queues:"
};
/* Memory region info relative to current memory (i.e. wrt 0). */
@@ -187,20 +251,42 @@ struct cudbg_tid_info_region_rev1 {
struct cudbg_ver_hdr ver_hdr;
struct cudbg_tid_info_region tid;
u32 tid_start;
- u32 reserved[16];
+ u32 nhash;
+ u32 clip_base;
+ u32 nclip;
+ u32 route_base;
+ u32 nroute;
+ u32 reserved[11];
};
#define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
#define CUDBG_MAX_FL_QIDS 1024
-struct cudbg_ch_cntxt {
- u32 cntxt_type;
- u32 cntxt_id;
- u32 data[SGE_CTXT_SIZE / 4];
+#define CUDBG_SGE_CTXT_REV 1
+
+struct sge_ctxt_rev1_data {
+ u8 ctxt_type;
+ u8 size;
+ u32 ctxt_id;
+ u32 data[];
+};
+
+struct sge_ctxt_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u32 nentries;
+ u8 data[]; /* Must be last */
};
#define CUDBG_MAX_RPLC_SIZE 128
+struct cudbg_cntxt_field {
+ char *name;
+ u32 start_bit;
+ u32 end_bit;
+ u32 shift;
+ u32 islog2;
+};
+
struct cudbg_mps_tcam {
u64 mask;
u32 rplc[8];
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
index c84719e3ca08..85c4400bf419 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
@@ -17,6 +17,12 @@
#define CUDBG_MAJOR_VERSION 1
#define CUDBG_MINOR_VERSION 14
+#define CUDBG_MAX_PARAMS 16
+
+enum {
+ CUDBG_UP_COREID_PARAM = 13,
+};
+
enum cudbg_dbg_entity_type {
CUDBG_REG_DUMP = 1,
CUDBG_DEV_LOG = 2,
@@ -26,8 +32,8 @@ enum cudbg_dbg_entity_type {
CUDBG_CIM_IBQ_TP0 = 6,
CUDBG_CIM_IBQ_TP1 = 7,
CUDBG_CIM_IBQ_ULP = 8,
- CUDBG_CIM_IBQ_SGE0 = 9,
- CUDBG_CIM_IBQ_SGE1 = 10,
+ CUDBG_CIM_IBQ_SGE = 9,
+ CUDBG_CIM_IBQ_PCIE = 10,
CUDBG_CIM_IBQ_NCSI = 11,
CUDBG_CIM_OBQ_ULP0 = 12,
CUDBG_CIM_OBQ_ULP1 = 13,
@@ -71,11 +77,55 @@ enum cudbg_dbg_entity_type {
CUDBG_HMA = 68,
CUDBG_QDESC = 70,
CUDBG_FLASH = 71,
- CUDBG_MAX_ENTITY = 72,
+ CUDBG_CIM_IBQ_TP2 = 73,
+ CUDBG_CIM_IBQ_TP3 = 74,
+ CUDBG_CIM_IBQ_IPC1 = 75,
+ CUDBG_CIM_IBQ_IPC2 = 76,
+ CUDBG_CIM_IBQ_IPC3 = 77,
+ CUDBG_CIM_IBQ_IPC4 = 78,
+ CUDBG_CIM_IBQ_IPC5 = 79,
+ CUDBG_CIM_IBQ_IPC6 = 80,
+ CUDBG_CIM_IBQ_IPC7 = 81,
+ CUDBG_CIM_OBQ_IPC1 = 82,
+ CUDBG_CIM_OBQ_IPC2 = 83,
+ CUDBG_CIM_OBQ_IPC3 = 84,
+ CUDBG_CIM_OBQ_IPC4 = 85,
+ CUDBG_CIM_OBQ_IPC5 = 86,
+ CUDBG_CIM_OBQ_IPC6 = 87,
+ CUDBG_CIM_OBQ_IPC7 = 88,
+ CUDBG_MAX_ENTITY,
+};
+
+struct cudbg_param {
+ u16 param_type;
+ u16 reserved;
+ union {
+ struct {
+ u32 memtype; /* which memory (EDC0, EDC1, MC) */
+ u32 start; /* start of log in firmware memory */
+ u32 size; /* size of log */
+ } devlog_param;
+ struct {
+ struct mbox_cmd_log *log;
+ u16 mbox_cmds;
+ } mboxlog_param;
+ struct {
+ const char *caller_string;
+ u8 os_type;
+ } sw_state_param;
+ struct {
+ u32 itr;
+ } yield_param;
+ u64 time;
+ u8 tcb_bit_param;
+ void *adap;
+ u8 coreid;
+ } u;
};
struct cudbg_init {
struct adapter *adap; /* Pointer to adapter structure */
+ struct cudbg_param dbg_params[CUDBG_MAX_PARAMS];
void *outbuf; /* Output buffer */
u32 outbuf_size; /* Output buffer size */
u8 compress_type; /* Type of compression to use */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
index 4bae323351f7..554d52fceca8 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
@@ -15,6 +15,7 @@
#include "cudbg_lib.h"
#include "cudbg_zlib.h"
#include "cxgb4_tc_mqprio.h"
+#include "cudbg_indir_reg.h"
static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
@@ -193,12 +194,15 @@ u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
case CHELSIO_T6:
len = T5_REGMAP_SIZE;
break;
+ case CHELSIO_T7:
+ len = T7_REGMAP_SIZE;
+ break;
default:
break;
}
break;
case CUDBG_DEV_LOG:
- len = adap->params.devlogs.size;
+ len = adap->params.devlog[0].size;
break;
case CUDBG_CIM_LA:
if (is_t6(adap->params.chip)) {
@@ -214,39 +218,63 @@ u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
break;
case CUDBG_CIM_QCFG:
- len = sizeof(struct cudbg_cim_qcfg);
+ len = sizeof(struct cim_qcfg_rev1);
break;
case CUDBG_CIM_IBQ_TP0:
case CUDBG_CIM_IBQ_TP1:
case CUDBG_CIM_IBQ_ULP:
- case CUDBG_CIM_IBQ_SGE0:
- case CUDBG_CIM_IBQ_SGE1:
+ case CUDBG_CIM_IBQ_SGE:
+ case CUDBG_CIM_IBQ_PCIE:
case CUDBG_CIM_IBQ_NCSI:
len = CIM_IBQ_SIZE * 4 * sizeof(u32);
break;
+ case CUDBG_CIM_IBQ_TP2:
+ case CUDBG_CIM_IBQ_TP3:
+ case CUDBG_CIM_IBQ_IPC1:
+ case CUDBG_CIM_IBQ_IPC2:
+ case CUDBG_CIM_IBQ_IPC3:
+ case CUDBG_CIM_IBQ_IPC4:
+ case CUDBG_CIM_IBQ_IPC5:
+ case CUDBG_CIM_IBQ_IPC6:
+ case CUDBG_CIM_IBQ_IPC7:
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7)
+ break; /* len stays 0 */
+ len = CIM_IBQ_SIZE * 4 * sizeof(u32);
+ break;
case CUDBG_CIM_OBQ_ULP0:
- len = cudbg_cim_obq_size(adap, 0);
+ len = cudbg_cim_obq_size(adap, 0, 0);
break;
case CUDBG_CIM_OBQ_ULP1:
- len = cudbg_cim_obq_size(adap, 1);
+ len = cudbg_cim_obq_size(adap, 1, 0);
break;
case CUDBG_CIM_OBQ_ULP2:
- len = cudbg_cim_obq_size(adap, 2);
+ len = cudbg_cim_obq_size(adap, 2, 0);
break;
case CUDBG_CIM_OBQ_ULP3:
- len = cudbg_cim_obq_size(adap, 3);
+ len = cudbg_cim_obq_size(adap, 3, 0);
break;
case CUDBG_CIM_OBQ_SGE:
- len = cudbg_cim_obq_size(adap, 4);
+ len = cudbg_cim_obq_size(adap, 4, 0);
break;
case CUDBG_CIM_OBQ_NCSI:
- len = cudbg_cim_obq_size(adap, 5);
+ len = cudbg_cim_obq_size(adap, 5, 0);
break;
case CUDBG_CIM_OBQ_RXQ0:
- len = cudbg_cim_obq_size(adap, 6);
+ len = cudbg_cim_obq_size(adap, 6, 0);
break;
case CUDBG_CIM_OBQ_RXQ1:
- len = cudbg_cim_obq_size(adap, 7);
+ len = cudbg_cim_obq_size(adap, 7, 0);
+ break;
+ case CUDBG_CIM_OBQ_IPC1:
+ case CUDBG_CIM_OBQ_IPC2:
+ case CUDBG_CIM_OBQ_IPC3:
+ case CUDBG_CIM_OBQ_IPC4:
+ case CUDBG_CIM_OBQ_IPC5:
+ case CUDBG_CIM_OBQ_IPC6:
+ case CUDBG_CIM_OBQ_IPC7:
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T7)
+ break; /* len stays 0 */
+ len = 6 * CIM_OBQ_SIZE * 4 * sizeof(u32);
break;
case CUDBG_EDC0:
value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
@@ -350,7 +378,9 @@ u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
len = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
break;
case CUDBG_DUMP_CONTEXT:
- len = cudbg_dump_context_size(adap);
+ len = cudbg_dump_context_size(adap, (CHELSIO_CHIP_VERSION(adap->params.chip) >=
+ CHELSIO_T7) ? SGE_CTXT_SIZE_T7 :
+ SGE_CTXT_SIZE);
break;
case CUDBG_MPS_TCAM:
len = sizeof(struct cudbg_mps_tcam) *
@@ -537,10 +567,11 @@ static int cudbg_mem_desc_cmp(const void *a, const void *b)
int cudbg_fill_meminfo(struct adapter *padap,
struct cudbg_meminfo *meminfo_buff)
{
+ u32 lo, hi, used, alloc, chip_ver;
struct cudbg_mem_desc *md;
- u32 lo, hi, used, alloc;
int n, i;
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
memset(meminfo_buff->avail, 0,
ARRAY_SIZE(meminfo_buff->avail) *
sizeof(struct cudbg_mem_desc));
@@ -578,50 +609,66 @@ int cudbg_fill_meminfo(struct adapter *padap,
i++;
}
- if (is_t5(padap->params.chip)) {
+ if (chip_ver >= CHELSIO_T7) {
+ /* MC0:*/
if (lo & EXT_MEM0_ENABLE_F) {
hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
meminfo_buff->avail[i].base =
- cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
+ cudbg_mbytes_to_bytes(T7_EXT_MEM0_BASE_G(hi));
meminfo_buff->avail[i].limit =
meminfo_buff->avail[i].base +
- cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
+ cudbg_mbytes_to_bytes(T7_EXT_MEM0_SIZE_G(hi));
meminfo_buff->avail[i].idx = 3;
i++;
}
-
+ /* MC1:*/
if (lo & EXT_MEM1_ENABLE_F) {
hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
meminfo_buff->avail[i].base =
- cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
+ cudbg_mbytes_to_bytes(T7_EXT_MEM1_BASE_G(hi));
meminfo_buff->avail[i].limit =
meminfo_buff->avail[i].base +
- cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
+ cudbg_mbytes_to_bytes(T7_EXT_MEM1_SIZE_G(hi));
meminfo_buff->avail[i].idx = 4;
i++;
}
- } else {
- if (lo & EXT_MEM_ENABLE_F) {
- hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
+ /* HMA:*/
+ if (lo & HMA_MUX_F) {
+ hi = t4_read_reg(padap, MA_HOST_MEMORY_BAR_A);
meminfo_buff->avail[i].base =
- cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
+ cudbg_mbytes_to_bytes(HMATARGETBASE_G(hi));
meminfo_buff->avail[i].limit =
meminfo_buff->avail[i].base +
- cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
- meminfo_buff->avail[i].idx = 2;
+ cudbg_mbytes_to_bytes(T7_HMA_SIZE_G(hi));
+ meminfo_buff->avail[i].idx = 5;
i++;
}
- if (lo & HMA_MUX_F) {
- hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
+ } else {
+ /* MC0:*/
+ if (lo & EXT_MEM0_ENABLE_F) {
+ hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
meminfo_buff->avail[i].base =
- cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
+ cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
meminfo_buff->avail[i].limit =
meminfo_buff->avail[i].base +
- cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
- meminfo_buff->avail[i].idx = 5;
+ cudbg_mbytes_to_bytes(EXT_MEM0_SIZE_G(hi));
+ meminfo_buff->avail[i].idx = 2;
i++;
}
+ /* HMA: In t6 no mc1 so HMA shares mc1 address space */
+ if (chip_ver == CHELSIO_T6) {
+ if (lo & HMA_MUX_F) {
+ hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
+ meminfo_buff->avail[i].base =
+ cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
+ meminfo_buff->avail[i].limit =
+ meminfo_buff->avail[i].base +
+ cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
+ meminfo_buff->avail[i].idx = 5;
+ i++;
+ }
+ }
}
if (!i) /* no memory available */
@@ -820,10 +867,7 @@ int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
u32 buf_size = 0;
int rc = 0;
- if (is_t4(padap->params.chip))
- buf_size = T4_REGMAP_SIZE;
- else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
- buf_size = T5_REGMAP_SIZE;
+ buf_size = t4_get_regs_len(padap);
rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff);
if (rc)
@@ -839,15 +883,20 @@ int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
struct devlog_params *dparams;
+ u8 coreid = 0;
int rc = 0;
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
+ dparams = &padap->params.devlog[coreid];
rc = t4_init_devlog_params(padap);
if (rc < 0) {
cudbg_err->sys_err = rc;
return rc;
}
- dparams = &padap->params.devlogs;
rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
if (rc)
return rc;
@@ -875,39 +924,52 @@ int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
struct cudbg_error *cudbg_err)
{
struct adapter *padap = pdbg_init->adap;
+ struct cim_la_rev1 *cim_la_buff;
struct cudbg_buffer temp_buff = { 0 };
+ u8 ncol, coreid = 0;
int size, rc;
u32 cfg = 0;
+ u16 nrow;
- if (is_t6(padap->params.chip)) {
- size = padap->params.cim_la_size / 10 + 1;
- size *= 10 * sizeof(u32);
- } else {
- size = padap->params.cim_la_size / 8;
- size *= 8 * sizeof(u32);
- }
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6)
+ ncol = 10;
+ else
+ ncol = 8;
+
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
- size += sizeof(cfg);
+ nrow = padap->params.cim_la_size / ncol;
+ size = sizeof(*cim_la_buff) + padap->params.cim_la_size * sizeof(u32);
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
return rc;
- rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
+ cim_la_buff = (void *)temp_buff.data;
+ cim_la_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_la_buff->ver_hdr.revision = CUDBG_CIM_LA_REV;
+ cim_la_buff->ver_hdr.size = sizeof(*cim_la_buff) -
+ sizeof(struct cudbg_ver_hdr);
+
+ rc = t4_cim_read_core(padap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &cfg);
if (rc) {
cudbg_err->sys_err = rc;
cudbg_put_buff(pdbg_init, &temp_buff);
return rc;
}
- memcpy((char *)temp_buff.data, &cfg, sizeof(cfg));
- rc = t4_cim_read_la(padap,
- (u32 *)((char *)temp_buff.data + sizeof(cfg)),
- NULL);
+ rc = t4_cim_read_la_core(padap, coreid, cim_la_buff->data, NULL);
if (rc < 0) {
cudbg_err->sys_err = rc;
cudbg_put_buff(pdbg_init, &temp_buff);
return rc;
}
+
+ cim_la_buff->coreid = coreid;
+ cim_la_buff->config = cfg;
+ cim_la_buff->ncol = ncol;
+ cim_la_buff->nrow = nrow;
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
@@ -931,41 +993,160 @@ int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
+static void cudbg_cim_qcfg_copy(struct cim_qcfg_rev1_data *data, u8 num_cim_ibq,
+ u8 num_cim_obq, u16 *base, u16 *size,
+ u16 *thres, u32 *stat, u32 *obq_wr)
+{
+ u8 i = 0;
+
+ while (i < num_cim_ibq) {
+ data->qtype = CUDBG_ENTITY_CIM_QCFG_QTYPE_IBQ;
+ data->qid = i;
+ data->base = *base;
+ data->size = *size;
+ data->thres = *thres;
+ memcpy(data->stat, stat, sizeof(data->stat));
+
+ stat += ARRAY_SIZE(data->stat);
+ thres++;
+ size++;
+ base++;
+ data++;
+ i++;
+ }
+
+ while (i < num_cim_ibq + num_cim_obq) {
+ data->qtype = CUDBG_ENTITY_CIM_QCFG_QTYPE_OBQ;
+ data->qid = i - num_cim_ibq;
+ data->base = *base;
+ data->size = *size;
+ memcpy(data->stat, stat, sizeof(data->stat));
+ memcpy(data->obq_wr, obq_wr, sizeof(data->obq_wr));
+
+ obq_wr += ARRAY_SIZE(data->obq_wr);
+ stat += ARRAY_SIZE(data->stat);
+ size++;
+ base++;
+ data++;
+ i++;
+ }
+}
+
+static int cudbg_collect_cim_qcfg_t5(struct cudbg_init *pdbg_init,
+ struct cim_qcfg_rev1_data *data,
+ u8 num_cim_ibq, u8 num_cim_obq)
+{
+ u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
+ struct adapter *padap = pdbg_init->adap;
+ u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+ u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+ u32 obq_wr[2 * CIM_NUM_OBQ_T5];
+ u16 thres[CIM_NUM_IBQ];
+ int ret;
+
+ ret = t4_cim_read(padap, UP_IBQ_0_SHADOW_RDADDR_A,
+ 4 * (num_cim_ibq + num_cim_obq), stat);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_cim_read(padap, UP_OBQ_0_SHADOW_REALADDR_A, 2 * num_cim_obq,
+ obq_wr);
+ if (ret < 0)
+ return ret;
+
+ t4_read_cimq_cfg(padap, base, size, thres);
+
+ cudbg_cim_qcfg_copy(data, num_cim_ibq, num_cim_obq, base, size, thres,
+ stat, obq_wr);
+ return 0;
+}
+
+static int cudbg_collect_cim_qcfg_t7(struct cudbg_init *pdbg_init, u8 coreid,
+ struct cim_qcfg_rev1_data *data,
+ u8 num_cim_ibq, u8 num_cim_obq)
+{
+ u32 stat[4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7)];
+ u16 base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ u16 size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ struct adapter *padap = pdbg_init->adap;
+ u32 obq_wr[2 * CIM_NUM_OBQ_T7];
+ u16 thres[CIM_NUM_IBQ_T7];
+ u32 addr;
+ int ret;
+ u8 i;
+
+ ret = t4_cim_read_core(padap, 1, coreid, T7_UP_IBQ_0_SHADOW_RDADDR_A,
+ 4 * num_cim_ibq, stat);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_cim_read_core(padap, 1, coreid, T7_UP_OBQ_0_SHADOW_RDADDR_A,
+ 4 * num_cim_obq, &stat[4 * num_cim_ibq]);
+ if (ret < 0)
+ return ret;
+
+ addr = T7_UP_OBQ_0_SHADOW_REALADDR_A;
+ for (i = 0; i < num_cim_obq * 2; i++, addr += 8) {
+ ret = t4_cim_read_core(padap, 1, coreid, addr, 1, &obq_wr[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ t4_read_cimq_cfg_core(padap, coreid, base, size, thres);
+
+ cudbg_cim_qcfg_copy(data, num_cim_ibq, num_cim_obq, base, size, thres,
+ stat, obq_wr);
+ return 0;
+}
+
int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct cim_qcfg_rev1 *cim_qcfg_buff;
+ u8 num_cim_ibq, num_cim_obq, coreid = 0;
struct adapter *padap = pdbg_init->adap;
+ struct cim_qcfg_rev1_data *data;
struct cudbg_buffer temp_buff = { 0 };
- struct cudbg_cim_qcfg *cim_qcfg_data;
+ u32 size;
int rc;
- rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg),
- &temp_buff);
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
+ num_cim_ibq = t4_cim_num_ibq(padap);
+ num_cim_obq = t4_cim_num_obq(padap);
+ size = sizeof(*cim_qcfg_buff) +
+ ((num_cim_ibq + num_cim_obq) * sizeof(*data));
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
return rc;
- cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
- cim_qcfg_data->chip = padap->params.chip;
- rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
- ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
- if (rc) {
- cudbg_err->sys_err = rc;
- cudbg_put_buff(pdbg_init, &temp_buff);
- return rc;
- }
+ cim_qcfg_buff = (void *)((u8 *)temp_buff.data + temp_buff.offset);
+ cim_qcfg_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_qcfg_buff->ver_hdr.revision = CUDBG_CIM_QCFG_REV;
+ cim_qcfg_buff->ver_hdr.size = sizeof(*cim_qcfg_buff) -
+ sizeof(struct cudbg_ver_hdr);
+
+ cim_qcfg_buff->num_cim_ibq = num_cim_ibq;
+ cim_qcfg_buff->num_cim_obq = num_cim_obq;
+ cim_qcfg_buff->coreid = coreid;
+ data = cim_qcfg_buff->data;
- rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
- ARRAY_SIZE(cim_qcfg_data->obq_wr),
- cim_qcfg_data->obq_wr);
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ rc = cudbg_collect_cim_qcfg_t7(pdbg_init, coreid, data,
+ num_cim_ibq, num_cim_obq);
+ else
+ rc = cudbg_collect_cim_qcfg_t5(pdbg_init, data, num_cim_ibq,
+ num_cim_obq);
if (rc) {
cudbg_err->sys_err = rc;
cudbg_put_buff(pdbg_init, &temp_buff);
return rc;
}
- t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
- cim_qcfg_data->thres);
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
@@ -973,20 +1154,38 @@ static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err, int qid)
{
+ struct cim_ibq_rev1 *cim_ibq_buff;
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
int no_of_read_words, rc = 0;
+ u8 coreid = 0;
u32 qsize;
+ if (qid >= t4_cim_num_ibq(padap))
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
/* collect CIM IBQ */
qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
- rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(*cim_ibq_buff) + qsize,
+ &temp_buff);
if (rc)
return rc;
+ cim_ibq_buff = (void *)((u8 *)temp_buff.data + temp_buff.offset);
+ cim_ibq_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_ibq_buff->ver_hdr.revision = CUDBG_CIM_IBQ_REV;
+ cim_ibq_buff->ver_hdr.size = sizeof(*cim_ibq_buff) -
+ sizeof(struct cudbg_ver_hdr);
+ cim_ibq_buff->qid = qid;
+ cim_ibq_buff->coreid = coreid;
/* t4_read_cim_ibq will return no. of read words or error */
- no_of_read_words = t4_read_cim_ibq(padap, qid,
- (u32 *)temp_buff.data, qsize);
+ no_of_read_words = t4_read_cim_ibq_core(padap, coreid, qid,
+ cim_ibq_buff->data, qsize);
+
/* no_of_read_words is less than or equal to 0 means error */
if (no_of_read_words <= 0) {
if (!no_of_read_words)
@@ -1014,24 +1213,63 @@ int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1);
}
+int cudbg_collect_cim_ibq_tp2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T6)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
+}
+
+int cudbg_collect_cim_ibq_tp3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T6)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
+}
+
int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
}
-int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
- struct cudbg_buffer *dbg_buff,
- struct cudbg_error *cudbg_err)
+int cudbg_collect_cim_ibq_sge(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
}
-int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
+int cudbg_collect_cim_ibq_pcie(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 6);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
}
@@ -1039,17 +1277,83 @@ int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 7);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
}
-u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
+int cudbg_collect_cim_ibq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 9);
+}
+
+int cudbg_collect_cim_ibq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 10);
+}
+
+int cudbg_collect_cim_ibq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 11);
+}
+
+int cudbg_collect_cim_ibq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 12);
+}
+
+int cudbg_collect_cim_ibq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 13);
+}
+
+int cudbg_collect_cim_ibq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 14);
+}
+
+int cudbg_collect_cim_ibq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 15);
+}
+
+u32 cudbg_cim_obq_size(struct adapter *padap, int qid, u8 coreid)
+{
+ unsigned int v, m;
u32 value;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ v = T7_OBQSELECT_F | T7_QUENUMSELECT_V(qid) |
+ CORESELECT_V(coreid);
+ /* value is in 512-byte units */
+ m = 128;
+ } else {
+ v = OBQSELECT_F | QUENUMSELECT_V(qid);
+ /* value is in 256-byte units */
+ m = 64;
+ }
+
t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
QUENUMSELECT_V(qid));
value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A);
- value = CIMQSIZE_G(value) * 64; /* size in number of words */
+ value = CIMQSIZE_G(value) * m; /* size in number of words */
return value * sizeof(u32);
}
@@ -1057,20 +1361,38 @@ static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err, int qid)
{
+ struct cim_obq_rev1 *cim_obq_buff;
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
int no_of_read_words, rc = 0;
+ u8 coreid = 0;
u32 qsize;
+ if (qid >= t4_cim_num_obq(padap))
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
/* collect CIM OBQ */
- qsize = cudbg_cim_obq_size(padap, qid);
- rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
+ qsize = cudbg_cim_obq_size(padap, qid, coreid);
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(*cim_obq_buff) + qsize,
+ &temp_buff);
if (rc)
return rc;
+ cim_obq_buff = (void *)((u8 *)temp_buff.data + temp_buff.offset);
+ cim_obq_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_obq_buff->ver_hdr.revision = CUDBG_CIM_OBQ_REV;
+ cim_obq_buff->ver_hdr.size = sizeof(*cim_obq_buff) -
+ sizeof(struct cudbg_ver_hdr);
+ cim_obq_buff->qid = qid;
+ cim_obq_buff->coreid = coreid;
/* t4_read_cim_obq will return no. of read words or error */
- no_of_read_words = t4_read_cim_obq(padap, qid,
- (u32 *)temp_buff.data, qsize);
+ no_of_read_words = t4_read_cim_obq_core(padap, coreid, qid,
+ cim_obq_buff->data, qsize);
+
/* no_of_read_words is less than or equal to 0 means error */
if (no_of_read_words <= 0) {
if (!no_of_read_words)
@@ -1140,6 +1462,55 @@ int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
}
+int cudbg_collect_cim_obq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 9);
+}
+
+int cudbg_collect_cim_obq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 10);
+}
+
+int cudbg_collect_cim_obq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 11);
+}
+
+int cudbg_collect_cim_obq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 12);
+}
+
+int cudbg_collect_cim_obq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 13);
+}
+
+int cudbg_collect_cim_obq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 14);
+}
+
+int cudbg_collect_cim_obq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 15);
+}
+
static int cudbg_meminfo_get_mem_index(struct adapter *padap,
struct cudbg_meminfo *mem_info,
u8 mem_type, u8 *idx)
@@ -1286,9 +1657,9 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
{
u32 win_pf, memoffset, mem_aperture, mem_base;
struct adapter *adap = pdbg_init->adap;
- u32 pos, offset, resid;
+ u32 offset, resid;
+ u64 pos, *buf;
u32 *res_buf;
- u64 *buf;
int ret;
/* Argument sanity checks ...
@@ -1316,7 +1687,7 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
/* Set up initial PCI-E Memory Window to cover the start of our
* transfer.
*/
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
/* Transfer data from the adapter */
while (len > 0) {
@@ -1331,7 +1702,7 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
if (offset == mem_aperture) {
pos += mem_aperture;
offset = 0;
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
}
}
@@ -1349,7 +1720,7 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
if (offset == mem_aperture) {
pos += mem_aperture;
offset = 0;
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
}
}
@@ -1653,6 +2024,33 @@ int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
+static void *cudbg_collect_indir_reg_init(struct cudbg_indir_reg_entity *e,
+ u16 rev, u32 indir_reg,
+ u32 indir_data, u32 nentries)
+{
+ struct cudbg_ver_hdr *ver_hdr = &e->ver_hdr;
+
+ ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
+ ver_hdr->revision = rev;
+ ver_hdr->size = sizeof(*e) - sizeof(*ver_hdr);
+
+ e->indir_reg = indir_reg;
+ e->indir_data = indir_data;
+ e->nentries = nentries;
+ return e;
+}
+
+static void *cudbg_collect_indir_reg_init_next(struct cudbg_indir_reg_entity *e,
+ u16 rev, u32 indir_reg,
+ u32 indir_data, u32 nentries)
+{
+ struct cudbg_indir_reg_entity *n;
+
+ n = (void *)((u8 *)e + (sizeof(*e) + sizeof(e->data[0]) * e->nentries));
+ return cudbg_collect_indir_reg_init(n, rev, indir_reg, indir_data,
+ nentries);
+}
+
int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
@@ -1663,6 +2061,77 @@ int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
int i, rc, n = 0;
u32 size;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path - new indirect reg framework */
+ struct cudbg_indir_reg_entity *tp_tm_entity, *tp_pio_entity;
+ struct cudbg_indir_reg_entity *tp_mib_entity;
+ const struct cudbg_indir_type_entry *tp_tm_arr;
+ const struct cudbg_indir_type_entry *tp_pio_arr;
+ const struct cudbg_indir_type_entry *tp_mib_arr;
+ struct cudbg_indir_reg_data *reg_data;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ tp_tm_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_TP_TM_PIO_ADDR);
+ tp_pio_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_TP_PIO_ADDR);
+ tp_mib_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_TP_MIB_INDEX);
+
+ if (!tp_tm_arr || !tp_pio_arr || !tp_mib_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(*tp_tm_entity) + sizeof(*tp_pio_entity) +
+ sizeof(*tp_mib_entity) + sizeof(*reg_data) *
+ (tp_tm_arr->nentries + tp_pio_arr->nentries +
+ tp_mib_arr->nentries);
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ tp_tm_entity = cudbg_collect_indir_reg_init((void *)temp_buff.data,
+ CUDBG_TP_INDIR_REG_REV,
+ TP_TM_PIO_ADDR_A,
+ TP_TM_PIO_DATA_A,
+ tp_tm_arr->nentries);
+
+ tp_pio_entity = cudbg_collect_indir_reg_init_next(tp_tm_entity,
+ CUDBG_TP_INDIR_REG_REV,
+ TP_PIO_ADDR_A,
+ TP_PIO_DATA_A,
+ tp_pio_arr->nentries);
+
+ tp_mib_entity = cudbg_collect_indir_reg_init_next(tp_pio_entity,
+ CUDBG_TP_INDIR_REG_REV,
+ TP_MIB_INDEX_A,
+ TP_MIB_DATA_A,
+ tp_mib_arr->nentries);
+
+ reg_data = tp_tm_entity->data;
+ for (i = 0; i < tp_tm_entity->nentries; i++, reg_data++) {
+ reg_data->offset = tp_tm_arr->reg_arr[i].addr;
+ t4_tp_tm_pio_read(pdbg_init->adap, ®_data->data, 1,
+ reg_data->offset, true);
+ }
+
+ reg_data = tp_pio_entity->data;
+ for (i = 0; i < tp_pio_entity->nentries; i++, reg_data++) {
+ reg_data->offset = tp_pio_arr->reg_arr[i].addr;
+ t4_tp_pio_read(pdbg_init->adap, ®_data->data, 1,
+ reg_data->offset, true);
+ }
+
+ reg_data = tp_mib_entity->data;
+ for (i = 0; i < tp_mib_entity->nentries; i++, reg_data++) {
+ reg_data->offset = tp_mib_arr->reg_arr[i].addr;
+ t4_tp_mib_read(pdbg_init->adap, ®_data->data, 1,
+ reg_data->offset, true);
+ }
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T5/T6 path */
if (is_t5(padap->params.chip))
n = sizeof(t5_tp_pio_array) +
sizeof(t5_tp_tm_pio_array) +
@@ -2061,6 +2530,36 @@ int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
+static void cudbg_collect_indir_reg(struct adapter *padap,
+ struct cudbg_indir_reg_entity *e,
+ const struct cudbg_indir_type_entry *arr,
+ u16 rev, u32 indir_reg, u32 indir_data)
+{
+ struct cudbg_indir_reg_entity *entity;
+ struct cudbg_indir_reg_data *reg_data;
+ u32 i;
+
+ entity = cudbg_collect_indir_reg_init(e, rev, indir_reg, indir_data,
+ arr->nentries);
+ reg_data = entity->data;
+ for (i = 0; i < entity->nentries; i++, reg_data++) {
+ reg_data->offset = arr->reg_arr[i].addr;
+ t4_read_indirect(padap, entity->indir_reg, entity->indir_data,
+ ®_data->data, 1, reg_data->offset);
+ }
+}
+
+static void cudbg_collect_indir_reg_next(struct adapter *padap,
+ struct cudbg_indir_reg_entity *e,
+ const struct cudbg_indir_type_entry *arr,
+ u16 rev, u32 indir_reg, u32 indir_data)
+{
+ struct cudbg_indir_reg_entity *n;
+
+ n = (void *)((u8 *)e + (sizeof(*e) + sizeof(e->data[0]) * e->nentries));
+ cudbg_collect_indir_reg(padap, n, arr, rev, indir_reg, indir_data);
+}
+
int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
@@ -2071,6 +2570,46 @@ int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
int i, rc, n;
u32 size;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path - new indirect reg framework */
+ const struct cudbg_indir_type_entry *pm_rx_arr, *pm_tx_arr;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ pm_rx_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_PM_RX_DBG_CTRL);
+ pm_tx_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_PM_TX_DBG_CTRL);
+
+ if (!pm_rx_arr || !pm_tx_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) *
+ pm_rx_arr->nentries;
+ size += sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) *
+ pm_tx_arr->nentries;
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cudbg_collect_indir_reg(padap, (void *)temp_buff.data,
+ pm_rx_arr, CUDBG_PM_INDIR_REG_REV,
+ PM_RX_DBG_CTRL_A,
+ PM_RX_DBG_CTRL_A + 4);
+
+ cudbg_collect_indir_reg_next(padap, (void *)temp_buff.data,
+ pm_tx_arr, CUDBG_PM_INDIR_REG_REV,
+ PM_TX_DBG_CTRL_A,
+ PM_TX_DBG_CTRL_A + 4);
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T5/T6 path */
n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
size = sizeof(struct ireg_buf) * n * 2;
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
@@ -2153,16 +2692,18 @@ int cudbg_collect_tid(struct cudbg_init *pdbg_init,
FW_PARAMS_PARAM_Y_V(0) | \
FW_PARAMS_PARAM_Z_V(0))
- para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
- para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
- rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
- if (rc < 0) {
- cudbg_err->sys_err = rc;
- cudbg_put_buff(pdbg_init, &temp_buff);
- return rc;
+ if (padap->flags & CXGB4_FW_OK) {
+ para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
+ para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
+ rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
+ if (rc < 0) {
+ cudbg_err->sys_err = rc;
+ cudbg_put_buff(pdbg_init, &temp_buff);
+ return rc;
+ }
+ tid->uotid_base = val[0];
+ tid->nuotids = val[1] - val[0] + 1;
}
- tid->uotid_base = val[0];
- tid->nuotids = val[1] - val[0] + 1;
if (is_t5(padap->params.chip)) {
tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
@@ -2255,7 +2796,7 @@ static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)
return buf[index] & (1U << bit);
}
-static int cudbg_get_ctxt_region_info(struct adapter *padap,
+static int cudbg_get_ctxt_region_info(struct adapter *padap, u8 sge_ctxt_size,
struct cudbg_region_info *ctx_info,
u8 *mem_type)
{
@@ -2303,7 +2844,7 @@ static int cudbg_get_ctxt_region_info(struct adapter *padap,
/* Get number of data freelist queues */
flq = HDRSTARTFLQ_G(value);
ctx_info[CTXT_FLM].exist = true;
- ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE;
+ ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * sge_ctxt_size;
/* The number of CONM contexts are same as number of freelist
* queues.
@@ -2314,30 +2855,31 @@ static int cudbg_get_ctxt_region_info(struct adapter *padap,
return 0;
}
-int cudbg_dump_context_size(struct adapter *padap)
+static u32 cudbg_sge_ctxt_entry_size(u8 sge_ctxt_size)
{
- struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
- u8 mem_type[CTXT_INGRESS + 1] = { 0 };
- u32 i, size = 0;
- int rc;
+ return sizeof(struct sge_ctxt_rev1_data) + sge_ctxt_size;
+}
- /* Get max valid qid for each type of queue */
- rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
- if (rc)
- return rc;
+int cudbg_dump_context_size(struct adapter *padap, u8 sge_ctxt_size)
+{
+ struct cudbg_region_info region_info[CTXT_MAX] = { {0} };
+ u32 i, nr_entries = 0;
+ u32 entry_size;
- for (i = 0; i < CTXT_CNM; i++) {
+ for (i = 0; i < CTXT_MAX; i++) {
if (!region_info[i].exist) {
if (i == CTXT_EGRESS || i == CTXT_INGRESS)
- size += CUDBG_LOWMEM_MAX_CTXT_QIDS *
- SGE_CTXT_SIZE;
+ nr_entries += CUDBG_LOWMEM_MAX_CTXT_QIDS;
continue;
}
- size += (region_info[i].end - region_info[i].start + 1) /
- SGE_CTXT_SIZE;
+ nr_entries += (region_info[i].end -
+ region_info[i].start + 1) /
+ sge_ctxt_size;
}
- return size * sizeof(struct cudbg_ch_cntxt);
+
+ entry_size = cudbg_sge_ctxt_entry_size(sge_ctxt_size);
+ return nr_entries * entry_size;
}
static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
@@ -2359,32 +2901,48 @@ static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
}
-static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
- u8 ctxt_type,
- struct cudbg_ch_cntxt **out_buff)
+static u32 cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u8 sge_ctxt_size,
+ u32 max_qid, u8 ctxt_type,
+ struct sge_ctxt_rev1 *ctxt_buff,
+ struct sge_ctxt_rev1_data **out_buff)
{
- struct cudbg_ch_cntxt *buff = *out_buff;
+ struct sge_ctxt_rev1_data *buff;
+ u8 *out = (u8 *)*out_buff;
+ u32 j, total_size = 0;
+ u32 entry_size;
int rc;
- u32 j;
+
+ entry_size = cudbg_sge_ctxt_entry_size(sge_ctxt_size);
for (j = 0; j < max_qid; j++) {
+ buff = (struct sge_ctxt_rev1_data *)out;
+
cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data);
rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type);
if (!rc)
continue;
- buff->cntxt_type = ctxt_type;
- buff->cntxt_id = j;
- buff++;
+ buff->ctxt_type = ctxt_type;
+ buff->ctxt_id = j;
+ buff->size = sge_ctxt_size;
+ total_size += entry_size;
+ ctxt_buff->nentries++;
+ out += entry_size;
if (ctxt_type == CTXT_FLM) {
+ buff = (struct sge_ctxt_rev1_data *)out;
+
cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data);
- buff->cntxt_type = CTXT_CNM;
- buff->cntxt_id = j;
- buff++;
+ buff->ctxt_type = CTXT_CNM;
+ buff->ctxt_id = j;
+ buff->size = sge_ctxt_size;
+ total_size += entry_size;
+ ctxt_buff->nentries++;
+ out += entry_size;
}
}
- *out_buff = buff;
+ *out_buff = (struct sge_ctxt_rev1_data *)out;
+ return total_size;
}
int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
@@ -2393,27 +2951,39 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
{
struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
struct adapter *padap = pdbg_init->adap;
+ struct sge_ctxt_rev1 *ctxt_buff;
+ struct sge_ctxt_rev1_data *buff;
u32 j, size, max_ctx_size, max_ctx_qid;
u8 mem_type[CTXT_INGRESS + 1] = { 0 };
struct cudbg_buffer temp_buff = { 0 };
- struct cudbg_ch_cntxt *buff;
+ u8 i, k, sge_ctxt_size;
u8 *ctx_buf;
- u8 i, k;
int rc;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ sge_ctxt_size = SGE_CTXT_SIZE_T7;
+ else
+ sge_ctxt_size = SGE_CTXT_SIZE;
+
/* Get max valid qid for each type of queue */
- rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
+ rc = cudbg_get_ctxt_region_info(padap, sge_ctxt_size, region_info, mem_type);
if (rc)
return rc;
- rc = cudbg_dump_context_size(padap);
+ rc = cudbg_dump_context_size(padap, sge_ctxt_size);
if (rc <= 0)
return CUDBG_STATUS_ENTITY_NOT_FOUND;
size = rc;
- rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size + sizeof(*ctxt_buff), &temp_buff);
if (rc)
return rc;
+ ctxt_buff = (void *)temp_buff.data;
+ ctxt_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ ctxt_buff->ver_hdr.revision = CUDBG_SGE_CTXT_REV;
+ ctxt_buff->ver_hdr.size = sizeof(*ctxt_buff) -
+ sizeof(struct cudbg_ver_hdr);
+ ctxt_buff->nentries = 0;
/* Get buffer with enough space to read the biggest context
* region in memory.
@@ -2429,7 +2999,7 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
return -ENOMEM;
}
- buff = (struct cudbg_ch_cntxt *)temp_buff.data;
+ buff = (struct sge_ctxt_rev1_data *)ctxt_buff->data;
/* Collect EGRESS and INGRESS context data.
* In case of failures, fallback to collecting via FW or
@@ -2438,13 +3008,13 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
if (!region_info[i].exist) {
max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
- cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
- &buff);
+ cudbg_get_sge_ctxt_fw(pdbg_init, sge_ctxt_size, max_ctx_qid, i,
+ ctxt_buff, &buff);
continue;
}
max_ctx_size = region_info[i].end - region_info[i].start + 1;
- max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
+ max_ctx_qid = max_ctx_size / sge_ctxt_size;
/* If firmware is not attached/alive, use backdoor register
* access to collect dump.
@@ -2459,8 +3029,8 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
if (rc || !is_fw_attached(pdbg_init)) {
max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
- cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
- &buff);
+ cudbg_get_sge_ctxt_fw(pdbg_init, sge_ctxt_size, max_ctx_qid, i,
+ ctxt_buff, &buff);
continue;
}
@@ -2468,22 +3038,26 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
__be64 *dst_off;
u64 *src_off;
- src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE);
+ src_off = (u64 *)(ctx_buf + j * sge_ctxt_size);
dst_off = (__be64 *)buff->data;
/* The data is stored in 64-bit cpu order. Convert it
* to big endian before parsing.
*/
- for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
+ for (k = 0; k < sge_ctxt_size / sizeof(u64); k++)
dst_off[k] = cpu_to_be64(src_off[k]);
rc = cudbg_sge_ctxt_check_valid(buff->data, i);
if (!rc)
continue;
- buff->cntxt_type = i;
- buff->cntxt_id = j;
- buff++;
+ buff->ctxt_type = i;
+ buff->ctxt_id = j;
+ buff->size = sge_ctxt_size;
+ ctxt_buff->nentries++;
+ buff = (struct sge_ctxt_rev1_data *)
+ ((u8 *)buff +
+ cudbg_sge_ctxt_entry_size(sge_ctxt_size));
}
}
@@ -2492,11 +3066,11 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
/* Collect FREELIST and CONGESTION MANAGER contexts */
max_ctx_size = region_info[CTXT_FLM].end -
region_info[CTXT_FLM].start + 1;
- max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
+ max_ctx_qid = max_ctx_size / sge_ctxt_size;
/* Since FLM and CONM are 1-to-1 mapped, the below function
* will fetch both FLM and CONM contexts.
*/
- cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff);
+ cudbg_get_sge_ctxt_fw(pdbg_init, sge_ctxt_size, max_ctx_qid, CTXT_FLM, ctxt_buff, &buff);
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
@@ -2544,7 +3118,72 @@ static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
u32 ctl, data2;
int rc = 0;
- if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* CtlReqID - 1: use Host Driver Requester ID
+ * CtlCmdType - 0: Read, 1: Write
+ * CtlXYBitSel- 0: Y bit, 1: X bit
+ ####### for T6 ######
+ * CtlTcamSel - 26:25 Control bit. 0: TCAM0, 1: TCAM1.
+ * CtlTcamIndex - 24:17 Control bits. Index of TCAM location to be accessed.
+
+ ####### for T7B ######
+ * CtlTcamSel - 27:26 Control bit. 0: TCAM0, 1: TCAM1, 2: TCAM2.
+ * CtlTcamIndex - 25:17 Control bits. Index of TCAM location to be accessed.
+ */
+
+ /* Read tcamy */
+ ctl = (CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0));
+ if (idx < 512)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx) | T7_CTLTCAMSEL_V(0);
+ else if (idx < 1024)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 512) |
+ T7_CTLTCAMSEL_V(1);
+ else /* idx 1024 to 1535 */
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 1024) |
+ T7_CTLTCAMSEL_V(2);
+
+ t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamy = DMACH_G(val) << 32;
+ tcamy |= t4_read_reg(padap, MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ tcam->lookup_type = DATALKPTYPE_G(data2);
+
+ /* 0 - Outer header, 1 - Inner header
+ * [71:48] bit locations are overloaded for
+ * outer vs. inner lookup types.
+ */
+ if (tcam->lookup_type &&
+ tcam->lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI */
+ tcam->vniy =
+ (((data2 & DATAVIDH2_F) | (DATAVIDH1_G(data2)))
+ << 16) |
+ VIDL_G(val);
+ tcam->dip_hit = data2 & DATADIPHIT_F;
+ } else {
+ tcam->vlan_vld = data2 & DATAVIDH2_F;
+ tcam->ivlan = VIDL_G(val);
+ }
+
+ tcam->port_num = DATAPORTNUM_G(data2);
+
+ /* Read tcamx. Change the control param */
+ ctl |= CTLXYBITSEL_V(1);
+ t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamx = DMACH_G(val) << 32;
+ tcamx |= t4_read_reg(padap, MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ if (tcam->lookup_type &&
+ tcam->lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI mask */
+ tcam->vnix =
+ (((data2 & DATAVIDH2_F) | (DATAVIDH1_G(data2)))
+ << 16) |
+ VIDL_G(val);
+ }
+ } else if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
/* CtlReqID - 1: use Host Driver Requester ID
* CtlCmdType - 0: Read, 1: Write
* CtlTcamSel - 0: TCAM0, 1: TCAM1
@@ -2602,13 +3241,24 @@ static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
if (tcamx & tcamy)
return rc;
- tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
- tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
+ /* t7b changes MPS_T5_CLS_SRAM_H_A to indirect register */
+ if (is_t7(padap->params.chip)) {
+ u32 tmp_ctl = 0;
- if (is_t5(padap->params.chip))
- tcam->repli = (tcam->cls_lo & REPLICATE_F);
- else if (is_t6(padap->params.chip))
+ tmp_ctl |= SRAMWRN_V(0) |
+ SRAMINDEX_V(idx & SRAMINDEX_M);
+ t4_write_reg(padap, MPS_T5_CLS_SRAM_H_A, tmp_ctl);
+ tcam->cls_lo = t4_read_reg(padap, MPS_T5_CLS_SRAM_L_A);
+ tcam->cls_hi = t4_read_reg(padap, MPS_T5_CLS_SRAM_H_A);
+ } else {
+ tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
+ tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
+ }
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
+ else
+ tcam->repli = (tcam->cls_lo & REPLICATE_F);
if (tcam->repli) {
struct fw_ldst_cmd ldst_cmd;
@@ -2966,20 +3616,62 @@ int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
- struct ireg_buf *ma_indr;
- int i, rc, n;
- u32 size, j;
+ int i, j, rc, n;
+ u32 size;
if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
return CUDBG_STATUS_ENTITY_NOT_FOUND;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path - new indirect reg framework */
+ const struct cudbg_indir_type_entry *ma_arr, *ma_perf_arr;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ ma_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_CFG);
+ ma_perf_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_PERF_CFG);
+
+ if (!ma_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) * ma_arr->nentries;
+
+ if (ma_perf_arr)
+ size += sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) *
+ ma_perf_arr->nentries;
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cudbg_collect_indir_reg(padap, (void *)temp_buff.data,
+ ma_arr, CUDBG_MA_INDIR_REG_REV,
+ MA_LOCAL_DEBUG_CFG_A,
+ MA_LOCAL_DEBUG_CFG_A + 4);
+
+ if (ma_perf_arr)
+ cudbg_collect_indir_reg_next(padap, (void *)temp_buff.data, ma_perf_arr,
+ CUDBG_MA_INDIR_REG_REV,
+ MA_LOCAL_DEBUG_PERF_CFG_A,
+ MA_LOCAL_DEBUG_PERF_CFG_A + 4);
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T6 path */
n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
size = sizeof(struct ireg_buf) * n * 2;
+
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
return rc;
- ma_indr = (struct ireg_buf *)temp_buff.data;
+ struct ireg_buf *ma_indr = (struct ireg_buf *)temp_buff.data;
for (i = 0; i < n; i++) {
struct ireg_field *ma_fli = &ma_indr->tp_pio;
u32 *buff = ma_indr->outbuf;
@@ -3094,9 +3786,67 @@ int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
else if (is_t6(padap->params.chip))
n = sizeof(t6_up_cim_reg_array) /
((IREG_NUM_ELEM + 1) * sizeof(u32));
- else
+ else if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path - new indirect reg framework */
+ const struct cudbg_indir_type_entry *cim_arr, *up_arr;
+ struct cudbg_indir_reg_entity *cim_entity, *up_entity;
+ struct cudbg_indir_reg_data *reg_data;
+ u8 coreid = 0, groupid = 0;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ cim_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_CIM_CTL);
+ up_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_UP);
+
+ if (!cim_arr || !up_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
+ size = sizeof(*cim_entity) + sizeof(*up_entity) +
+ sizeof(*reg_data) * (cim_arr->nentries + up_arr->nentries);
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cim_entity = cudbg_collect_indir_reg_init((void *)temp_buff.data,
+ CUDBG_UP_CIM_INDIR_REG_REV,
+ CIM_HOST_ACC_CTRL_A,
+ CIM_HOST_ACC_DATA_A,
+ cim_arr->nentries);
+
+ up_entity = cudbg_collect_indir_reg_init_next(cim_entity,
+ CUDBG_UP_CIM_INDIR_REG_REV,
+ CIM_HOST_ACC_CTRL_A,
+ CIM_HOST_ACC_DATA_A,
+ up_arr->nentries);
+
+ reg_data = cim_entity->data;
+ for (i = 0; i < cim_entity->nentries; i++, reg_data++) {
+ reg_data->offset = cim_arr->reg_arr[i].addr;
+ t4_cim_read_core(padap, groupid, coreid,
+ reg_data->offset, 1, ®_data->data);
+ }
+
+ groupid = 1; /* T7 UP uses groupid 1 */
+
+ reg_data = up_entity->data;
+ for (i = 0; i < up_entity->nentries; i++, reg_data++) {
+ reg_data->offset = up_arr->reg_arr[i].addr;
+ t4_cim_read_core(padap, groupid, coreid,
+ reg_data->offset, 1, ®_data->data);
+ }
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ } else {
return CUDBG_STATUS_NOT_IMPLEMENTED;
+ }
+ /* T5/T6 path */
size = sizeof(struct ireg_buf) * n;
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
@@ -3275,20 +4025,47 @@ int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
- struct ireg_buf *hma_indr;
int i, rc, n;
u32 size;
if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
return CUDBG_STATUS_ENTITY_NOT_FOUND;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path - new indirect reg framework */
+ const struct cudbg_indir_type_entry *hma_arr;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ hma_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_HMAT6_LOCAL_DEBUG_CFG);
+ if (!hma_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) * hma_arr->nentries;
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cudbg_collect_indir_reg(padap, (void *)temp_buff.data,
+ hma_arr, CUDBG_HMA_INDIR_REG_REV,
+ HMA_LOCAL_DEBUG_CFG_A,
+ HMA_LOCAL_DEBUG_CFG_A + 4);
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T6 path */
n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
size = sizeof(struct ireg_buf) * n;
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
return rc;
- hma_indr = (struct ireg_buf *)temp_buff.data;
+ struct ireg_buf *hma_indr = (struct ireg_buf *)temp_buff.data;
for (i = 0; i < n; i++) {
struct ireg_field *hma_fli = &hma_indr->tp_pio;
u32 *buff = hma_indr->outbuf;
@@ -3581,7 +4358,7 @@ int cudbg_collect_flash(struct cudbg_init *pdbg_init,
u32 addr, i;
int rc;
- addr = FLASH_EXP_ROM_START;
+ addr = FLASH_LOC_EXP_ROM;
for (i = 0; i < count; i += SF_PAGE_SIZE) {
n = min_t(u32, count - i, SF_PAGE_SIZE);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
index d6d6cd298930..d92a445bf3b5 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
@@ -30,10 +30,10 @@ int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
-int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
- struct cudbg_buffer *dbg_buff,
- struct cudbg_error *cudbg_err);
-int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
+int cudbg_collect_cim_ibq_sge(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_pcie(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
@@ -165,13 +165,61 @@ int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,
int cudbg_collect_flash(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_tp2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_tp3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
u32 cudbg_get_entity_length(struct adapter *adap, u32 entity);
struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i);
void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
struct cudbg_entity_hdr *entity_hdr);
-u32 cudbg_cim_obq_size(struct adapter *padap, int qid);
-int cudbg_dump_context_size(struct adapter *padap);
+u32 cudbg_cim_obq_size(struct adapter *padap, int qid, u8 coreid);
+int cudbg_dump_context_size(struct adapter *padap, u8 sge_ctxt_size);
int cudbg_fill_meminfo(struct adapter *padap,
struct cudbg_meminfo *meminfo_buff);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index f31959b9255f..744d864d04b3 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -1857,7 +1857,6 @@ void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
u32 *mem_base, u32 *mem_aperture);
-void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
int dir);
#define T4_MEMORY_WRITE 0
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
index dd66b244466d..f2b98f1b4d61 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
@@ -27,8 +27,8 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
{ CUDBG_CIM_IBQ_TP0, cudbg_collect_cim_ibq_tp0 },
{ CUDBG_CIM_IBQ_TP1, cudbg_collect_cim_ibq_tp1 },
{ CUDBG_CIM_IBQ_ULP, cudbg_collect_cim_ibq_ulp },
- { CUDBG_CIM_IBQ_SGE0, cudbg_collect_cim_ibq_sge0 },
- { CUDBG_CIM_IBQ_SGE1, cudbg_collect_cim_ibq_sge1 },
+ { CUDBG_CIM_IBQ_SGE, cudbg_collect_cim_ibq_sge },
+ { CUDBG_CIM_IBQ_PCIE, cudbg_collect_cim_ibq_pcie },
{ CUDBG_CIM_IBQ_NCSI, cudbg_collect_cim_ibq_ncsi },
{ CUDBG_CIM_OBQ_ULP0, cudbg_collect_cim_obq_ulp0 },
{ CUDBG_CIM_OBQ_ULP1, cudbg_collect_cim_obq_ulp1 },
@@ -64,6 +64,22 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
{ CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect },
{ CUDBG_PBT_TABLE, cudbg_collect_pbt_tables },
{ CUDBG_HMA_INDIRECT, cudbg_collect_hma_indirect },
+ { CUDBG_CIM_IBQ_TP2, cudbg_collect_cim_ibq_tp2 },
+ { CUDBG_CIM_IBQ_TP3, cudbg_collect_cim_ibq_tp3 },
+ { CUDBG_CIM_IBQ_IPC1, cudbg_collect_cim_ibq_ipc1 },
+ { CUDBG_CIM_IBQ_IPC2, cudbg_collect_cim_ibq_ipc2 },
+ { CUDBG_CIM_IBQ_IPC3, cudbg_collect_cim_ibq_ipc3 },
+ { CUDBG_CIM_IBQ_IPC4, cudbg_collect_cim_ibq_ipc4 },
+ { CUDBG_CIM_IBQ_IPC5, cudbg_collect_cim_ibq_ipc5 },
+ { CUDBG_CIM_IBQ_IPC6, cudbg_collect_cim_ibq_ipc6 },
+ { CUDBG_CIM_IBQ_IPC7, cudbg_collect_cim_ibq_ipc7 },
+ { CUDBG_CIM_OBQ_IPC1, cudbg_collect_cim_obq_ipc1 },
+ { CUDBG_CIM_OBQ_IPC2, cudbg_collect_cim_obq_ipc2 },
+ { CUDBG_CIM_OBQ_IPC3, cudbg_collect_cim_obq_ipc3 },
+ { CUDBG_CIM_OBQ_IPC4, cudbg_collect_cim_obq_ipc4 },
+ { CUDBG_CIM_OBQ_IPC5, cudbg_collect_cim_obq_ipc5 },
+ { CUDBG_CIM_OBQ_IPC6, cudbg_collect_cim_obq_ipc6 },
+ { CUDBG_CIM_OBQ_IPC7, cudbg_collect_cim_obq_ipc7 },
};
static const struct cxgb4_collect_entity cxgb4_collect_flash_dump[] = {
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index be4c8cbbad95..a3b1f9db5cbe 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -3097,6 +3097,247 @@ static int cxgb_hwtstamp_set(struct net_device *dev,
return 0;
}
+enum {
+ CUDBG_SETREG = 1024,
+ CUDBG_GETREG = 1025,
+ CUDBG_GET_SGE_CTXT = 1059,
+ CUDBG_GET_SGE_DESC2 = 1060,
+};
+
+enum {
+ CUDBG_CNTXT_TYPE_EGRESS = 0,
+ CUDBG_CNTXT_TYPE_FL = 1,
+ CUDBG_CNTXT_TYPE_RSP = 2,
+ CUDBG_CNTXT_TYPE_CQ = 3,
+ CUDBG_CNTXT_TYPE_CONG = 4,
+};
+
+enum {
+ CUDBG_SGE_QTYPE_TX_ETH = 1,
+ CUDBG_SGE_QTYPE_TX_OFLD = 2,
+ CUDBG_SGE_QTYPE_TX_CTRL = 3,
+ CUDBG_SGE_QTYPE_FL = 4,
+ CUDBG_SGE_QTYPE_RSP = 5,
+ CUDBG_SGE_QTYPE_TX_CRYPTO = 6,
+};
+
+struct cudbg_reg {
+ u32 cmd;
+ u32 addr;
+ u32 val;
+};
+
+struct cudbg_mem_range {
+ u32 cmd;
+ u32 mem_id;
+ u32 addr;
+ u32 len;
+ u32 version;
+ u8 buf[];
+};
+
+static int cudbg_get_qdesc(struct adapter *adap, int qtype,
+ unsigned int qid, unsigned int idx,
+ unsigned char *data)
+{
+ struct sge *p = &adap->sge;
+ int i, len = sizeof(struct tx_desc);
+
+ if (qtype == CUDBG_SGE_QTYPE_TX_ETH) {
+ const struct sge_eth_txq *q = p->ethtxq;
+
+ for (i = 0; i < ARRAY_SIZE(p->ethtxq); i++, q++)
+ if (q->q.cntxt_id == qid && q->q.desc &&
+ idx < q->q.size) {
+ memcpy(data, &q->q.desc[idx], len);
+ return len;
+ }
+ }
+
+ if (qtype == CUDBG_SGE_QTYPE_TX_CTRL) {
+ const struct sge_ctrl_txq *q = p->ctrlq;
+
+ for (i = 0; i < ARRAY_SIZE(p->ctrlq); i++, q++)
+ if (q->q.cntxt_id == qid && q->q.desc &&
+ idx < q->q.size) {
+ memcpy(data, &q->q.desc[idx], len);
+ return len;
+ }
+ }
+
+ if (qtype == CUDBG_SGE_QTYPE_TX_OFLD ||
+ qtype == CUDBG_SGE_QTYPE_TX_CRYPTO) {
+ struct sge_uld_txq_info *utxq_info;
+ unsigned int uld_type;
+ int i;
+
+ uld_type = (qtype == CUDBG_SGE_QTYPE_TX_OFLD) ?
+ CXGB4_TX_OFLD : CXGB4_TX_CRYPTO;
+
+ utxq_info = adap->sge.uld_txq_info[uld_type];
+ if (!utxq_info)
+ return -EINVAL;
+
+ for (i = 0; i < utxq_info->ntxq; i++) {
+ const struct sge_uld_txq *q = &utxq_info->uldtxq[i];
+
+ if (q->q.cntxt_id == qid && q->q.desc &&
+ idx < q->q.size) {
+ memcpy(data, &q->q.desc[idx], len);
+ return len;
+ }
+ }
+ }
+
+ if (qtype == CUDBG_SGE_QTYPE_FL) {
+ const struct sge_fl *q = NULL;
+
+ if (qid >= p->egr_start &&
+ qid < p->egr_start + p->egr_sz)
+ q = p->egr_map[qid - p->egr_start];
+ if (q && idx < q->size) {
+ *(__be64 *)data = q->desc[idx];
+ return sizeof(u64);
+ }
+ }
+
+ if (qtype == CUDBG_SGE_QTYPE_RSP) {
+ const struct sge_rspq *q = NULL;
+
+ if (qid >= p->ingr_start &&
+ qid < p->ingr_start + p->ingr_sz)
+ q = p->ingr_map[qid - p->ingr_start];
+ if (q && idx < q->size) {
+ len = q->iqe_len;
+ idx *= len / sizeof(u64);
+ memcpy(data, &q->desc[idx], len);
+ return len;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int cxgb_extension_ioctl(struct net_device *dev,
+ void __user *useraddr)
+{
+ struct adapter *adap = netdev2adap(dev);
+ u32 cmd;
+ int ret = 0;
+
+ if (!ns_capable(dev_net(dev)->user_ns, CAP_NET_ADMIN))
+ return -EPERM;
+
+ if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
+ return -EFAULT;
+
+ switch (cmd) {
+ case CUDBG_GETREG: {
+ struct cudbg_reg edata;
+
+ if (copy_from_user(&edata, useraddr, sizeof(edata)))
+ return -EFAULT;
+ if ((edata.addr & 3) != 0 ||
+ edata.addr >= t4_get_regs_len(adap))
+ return -EINVAL;
+ edata.val = t4_read_reg(adap, edata.addr);
+ if (copy_to_user(useraddr, &edata, sizeof(edata)))
+ return -EFAULT;
+ break;
+ }
+ case CUDBG_SETREG: {
+ struct cudbg_reg edata;
+
+ if (copy_from_user(&edata, useraddr, sizeof(edata)))
+ return -EFAULT;
+ if ((edata.addr & 3) != 0 ||
+ edata.addr >= t4_get_regs_len(adap))
+ return -EINVAL;
+ t4_write_reg(adap, edata.addr, edata.val);
+ break;
+ }
+ case CUDBG_GET_SGE_CTXT: {
+ u32 buf[SGE_CTXT_SIZE_T7 / 4];
+ u8 size = SGE_CTXT_SIZE;
+ struct cudbg_mem_range t;
+ enum ctxt_type ctype;
+
+ if (copy_from_user(&t, useraddr, sizeof(t)))
+ return -EFAULT;
+ if (t.len < SGE_CTXT_SIZE || t.addr > CTXTQID_M)
+ return -EINVAL;
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ if (t.len < SGE_CTXT_SIZE_T7)
+ return -EINVAL;
+ size = SGE_CTXT_SIZE_T7;
+ }
+
+ switch (t.mem_id) {
+ case CUDBG_CNTXT_TYPE_EGRESS:
+ ctype = CTXT_EGRESS;
+ break;
+ case CUDBG_CNTXT_TYPE_FL:
+ ctype = CTXT_FLM;
+ break;
+ case CUDBG_CNTXT_TYPE_RSP:
+ case CUDBG_CNTXT_TYPE_CQ:
+ ctype = CTXT_INGRESS;
+ break;
+ case CUDBG_CNTXT_TYPE_CONG:
+ ctype = CTXT_CNM;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if ((adap->flags & CXGB4_FW_OK) && !adap->use_bd)
+ ret = t4_sge_ctxt_rd(adap, adap->mbox,
+ t.addr, ctype, buf);
+ else
+ ret = t4_sge_ctxt_rd_bd(adap, t.addr, ctype, buf);
+ if (ret)
+ return ret;
+
+ t.version = mk_adap_vers(adap);
+ if (copy_to_user(useraddr + sizeof(t), buf, size) ||
+ copy_to_user(useraddr, &t, sizeof(t)))
+ return -EFAULT;
+ break;
+ }
+ case CUDBG_GET_SGE_DESC2: {
+ unsigned char buf[128];
+ struct cudbg_mem_range edesc;
+
+ if (copy_from_user(&edesc, useraddr, sizeof(edesc)))
+ return -EFAULT;
+ /* upper 8 bits of mem_id = queue type, lower 24 = qid */
+ ret = cudbg_get_qdesc(adap,
+ edesc.mem_id >> 24,
+ edesc.mem_id & 0xffffff,
+ edesc.addr, buf);
+ if (ret < 0)
+ return ret;
+ if (edesc.len < ret)
+ return -EINVAL;
+ edesc.len = ret;
+ edesc.version = mk_adap_vers(adap);
+ if (copy_to_user(useraddr + sizeof(edesc), buf, edesc.len) ||
+ copy_to_user(useraddr, &edesc, sizeof(edesc)))
+ return -EFAULT;
+ break;
+ }
+ default:
+ return -EOPNOTSUPP;
+ }
+ return 0;
+}
+
+static int cxgb_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
+ void __user *data, int cmd)
+{
+ return cxgb_extension_ioctl(dev, data);
+}
+
static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
{
unsigned int mbox;
@@ -3866,6 +4107,7 @@ static const struct net_device_ops cxgb4_netdev_ops = {
.ndo_set_features = cxgb_set_features,
.ndo_validate_addr = eth_validate_addr,
.ndo_eth_ioctl = cxgb_ioctl,
+ .ndo_siocdevprivate = cxgb_siocdevprivate,
.ndo_change_mtu = cxgb_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = cxgb_netpoll,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index e2437aabc75c..a9cc401b2a1b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -580,26 +580,6 @@ int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
return 0;
}
-/**
- * t4_memory_update_win - Move memory window to specified address.
- * @adap: the adapter
- * @win: PCI-E Memory Window to use
- * @addr: location to move.
- *
- * Move memory window to specified address.
- */
-void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
-{
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
- addr);
- /* Read it back to ensure that changes propagate before we
- * attempt to use the new value.
- */
- t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
-}
-
/**
* t4_memory_rw_residual - Read/Write residual data.
* @adap: the adapter
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
index 13c56fedfc5c..6f45f68e4299 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
@@ -80,6 +80,7 @@ enum ctxt_type {
CTXT_INGRESS,
CTXT_FLM,
CTXT_CNM,
+ CTXT_MAX,
};
enum {
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 11/12] cxgb4: extend debugfs support for T7 adapters
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (9 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 10/12] cxgb4: extend CUDBG support for T7 adapters Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
2026-10-05 22:48 ` [PATCH net-next v3 12/12] cxgb4: select ULD Tx and control queues by TID on T7 Potnuri Bharat Teja
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Update the debugfs infrastructure to support T7-specific debug data and
multicore adapter architectures.
Add support for collecting and displaying debug information from
individual CIM cores, including CIM logic analyzer data, queue
configuration, and queue state information. Update debugfs handlers to
use the multicore-aware access mechanisms required by T7 devices.
Also extend debugfs support for T7-specific CIM IBQ and OBQ layouts,
per-core device logs, and related debug entities.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/clip_tbl.c | 10 +-
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 8 -
.../ethernet/chelsio/cxgb4/cxgb4_debugfs.c | 1029 ++++++++++++-----
.../ethernet/chelsio/cxgb4/cxgb4_debugfs.h | 17 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 2 +-
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 64 +-
6 files changed, 787 insertions(+), 343 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/clip_tbl.c b/drivers/net/ethernet/chelsio/cxgb4/clip_tbl.c
index 6954c15d2b82..7c13bc984883 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/clip_tbl.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/clip_tbl.c
@@ -17,6 +17,7 @@
#include <net/addrconf.h>
#include "cxgb4.h"
#include "clip_tbl.h"
+#include "cxgb4_debugfs.h"
static inline unsigned int ipv4_clip_hash(struct clip_tbl *c, const u32 *key)
{
@@ -249,12 +250,17 @@ EXPORT_SYMBOL(cxgb4_update_root_dev_clip);
int clip_tbl_show(struct seq_file *seq, void *v)
{
- struct adapter *adapter = seq->private;
- struct clip_tbl *ctbl = adapter->clipt;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adapter = d->adap;
+ struct clip_tbl *ctbl;
struct clip_entry *ce;
char ip[60];
int i;
+ ctbl = adapter->clipt;
+ if (!ctbl)
+ return 0;
+
read_lock_bh(&ctbl->lock);
seq_puts(seq, "IP Address Users\n");
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 744d864d04b3..8a483db4f72c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -455,7 +455,6 @@ struct adapter_params {
struct vpd_params vpd;
struct pf_resources pfres;
struct pci_params pci;
- struct devlog_params devlogs;
struct devlog_params devlog[MAX_UP_CORES];
enum pcie_memwin drv_memwin;
@@ -1957,12 +1956,8 @@ u8 t4_cim_num_ibq(struct adapter *adap);
u8 t4_cim_num_obq(struct adapter *adap);
void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
u16 *size, u16 *thres);
-int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
- size_t n);
int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
size_t n);
-int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
- size_t n);
int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
unsigned int addr, unsigned int n, unsigned int *valp);
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
@@ -1970,11 +1965,8 @@ int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
unsigned int addr, unsigned int n,
const unsigned int *valp);
-int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
- const unsigned int *valp);
int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
u32 *wrptr);
-int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
unsigned int *pif_req_wrptr,
unsigned int *pif_rsp_wrptr);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
index e0b4b04d4aac..226bd9cb5196 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
@@ -196,21 +196,22 @@ static int cim_la_show_pc_t6(struct seq_file *seq, void *v, int idx)
static int cim_la_open(struct inode *inode, struct file *file)
{
- int ret;
- unsigned int cfg;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ u8 coreid = d->coreid;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
+ unsigned int cfg;
+ int ret;
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &cfg);
if (ret)
return ret;
- if (is_t6(adap->params.chip)) {
- /* +1 to account for integer division of CIMLA_SIZE/10 */
- p = seq_open_tab(file, (adap->params.cim_la_size / 10) + 1,
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T6) {
+ p = seq_open_tab(file, adap->params.cim_la_size / 10,
10 * sizeof(u32), 1,
cfg & UPDBGLACAPTPCONLY_F ?
- cim_la_show_pc_t6 : cim_la_show_t6);
+ cim_la_show_pc_t6 : cim_la_show_t6);
} else {
p = seq_open_tab(file, adap->params.cim_la_size / 8,
8 * sizeof(u32), 1,
@@ -220,7 +221,7 @@ static int cim_la_open(struct inode *inode, struct file *file)
if (!p)
return -ENOMEM;
- ret = t4_cim_read_la(adap, (u32 *)p->data, NULL);
+ ret = t4_cim_read_la_core(adap, coreid, (u32 *)p->data, NULL);
if (ret)
seq_release_private(inode, file);
return ret;
@@ -256,8 +257,9 @@ static int cim_pif_la_show(struct seq_file *seq, void *v, int idx)
static int cim_pif_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
p = seq_open_tab(file, 2 * CIM_PIFLA_SIZE, 6 * sizeof(u32), 1,
cim_pif_la_show);
@@ -302,8 +304,9 @@ static int cim_ma_la_show(struct seq_file *seq, void *v, int idx)
static int cim_ma_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
p = seq_open_tab(file, 2 * CIM_MALA_SIZE, 5 * sizeof(u32), 1,
cim_ma_la_show);
@@ -323,8 +326,112 @@ static const struct file_operations cim_ma_la_fops = {
.release = seq_release_private
};
+static int cim_qcfg_show_t7(struct seq_file *seq, struct adapter *adap,
+ u8 coreid)
+{
+ static const char *const qname_t7[] = {
+ /* IBQ */
+ "TP0",
+ "TP1",
+ "TP2",
+ "TP3",
+ "ULP",
+ "SGE0",
+ "PCIE",
+ "NC-SI",
+ "RSVD",
+ "IPC1",
+ "IPC2",
+ "IPC3",
+ "IPC4",
+ "IPC5",
+ "IPC6",
+ "IPC7",
+ /* OBQ */
+ "ULP0",
+ "ULP1",
+ "ULP2",
+ "ULP3",
+ "SGE",
+ "NC-SI",
+ "SGE0-RX",
+ "RSVD",
+ "RSVD",
+ "IPC1",
+ "IPC2",
+ "IPC3",
+ "IPC4",
+ "IPC5",
+ "IPC6",
+ "IPC7",
+ };
+ u32 stat[(4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7))];
+ u16 base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ u16 size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ u32 obq_wr[2 * CIM_NUM_OBQ_T7];
+ u16 thres[CIM_NUM_IBQ_T7];
+ u32 *wr = obq_wr;
+ u32 *p = stat;
+ u32 addr;
+ int ret;
+ u8 i;
+
+ ret = t4_cim_read_core(adap, 1, coreid, T7_UP_IBQ_0_SHADOW_RDADDR_A,
+ 4 * CIM_NUM_IBQ_T7, stat);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_cim_read_core(adap, 1, coreid, T7_UP_OBQ_0_SHADOW_RDADDR_A,
+ 4 * CIM_NUM_OBQ_T7, &stat[4 * CIM_NUM_IBQ_T7]);
+ if (ret < 0)
+ return ret;
+
+ addr = T7_UP_OBQ_0_SHADOW_REALADDR_A;
+ for (i = 0; i < CIM_NUM_OBQ_T7 * 2; i++, addr += 8) {
+ ret = t4_cim_read_core(adap, 1, coreid, addr, 1, &obq_wr[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ t4_read_cimq_cfg_core(adap, coreid, base, size, thres);
+
+ seq_printf(seq,
+ " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n");
+
+ for (i = 0; i < CIM_NUM_IBQ_T7; i++, p += 4) {
+ if (!size[i])
+ continue;
+
+ seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n",
+ qname_t7[i], base[i], size[i], thres[i],
+ IBQRDADDR_G(p[0]) & 0xfff, IBQWRADDR_G(p[1]) & 0xfff,
+ QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
+ T7_QUEREMFLITS_G(p[2]) * 16);
+ }
+
+ for ( ; i < CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7; i++, p += 4, wr += 2) {
+ if (!size[i])
+ continue;
+
+ seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n",
+ qname_t7[i], base[i], size[i],
+ QUERDADDR_G(p[0]) & 0xfff, (wr[0] << 1),
+ QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
+ T7_QUEREMFLITS_G(p[2]) * 16);
+ }
+
+ return 0;
+}
+
static int cim_qcfg_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ u8 coreid = d->coreid;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return cim_qcfg_show_t7(seq, adap, coreid);
+
static const char * const qname[] = {
"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",
@@ -332,7 +439,6 @@ static int cim_qcfg_show(struct seq_file *seq, void *v)
};
int i;
- struct adapter *adap = seq->private;
u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))];
@@ -391,16 +497,19 @@ static int cimq_show(struct seq_file *seq, void *v, int idx)
static int cim_ibq_open(struct inode *inode, struct file *file)
{
- int ret;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int qid = d->data;
+ u8 coreid = d->coreid;
struct seq_tab *p;
- unsigned int qid = (uintptr_t)inode->i_private & 7;
- struct adapter *adap = inode->i_private - qid;
+ int ret;
p = seq_open_tab(file, CIM_IBQ_SIZE, 4 * sizeof(u32), 0, cimq_show);
if (!p)
return -ENOMEM;
- ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4);
+ ret = t4_read_cim_ibq_core(adap, coreid, qid, (u32 *)p->data,
+ CIM_IBQ_SIZE * 4);
if (ret < 0)
seq_release_private(inode, file);
else
@@ -418,16 +527,19 @@ static const struct file_operations cim_ibq_fops = {
static int cim_obq_open(struct inode *inode, struct file *file)
{
- int ret;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int qid = d->data;
+ u8 coreid = d->coreid;
struct seq_tab *p;
- unsigned int qid = (uintptr_t)inode->i_private & 7;
- struct adapter *adap = inode->i_private - qid;
+ int ret;
p = seq_open_tab(file, 6 * CIM_OBQ_SIZE, 4 * sizeof(u32), 0, cimq_show);
if (!p)
return -ENOMEM;
- ret = t4_read_cim_obq(adap, qid, (u32 *)p->data, 6 * CIM_OBQ_SIZE * 4);
+ ret = t4_read_cim_obq_core(adap, coreid, qid, (u32 *)p->data,
+ 6 * CIM_OBQ_SIZE * 4);
if (ret < 0) {
seq_release_private(inode, file);
} else {
@@ -638,8 +750,9 @@ static int tp_la_show3(struct seq_file *seq, void *v, int idx)
static int tp_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) {
case 2:
@@ -663,11 +776,14 @@ static int tp_la_open(struct inode *inode, struct file *file)
static ssize_t tp_la_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int err;
- char s[32];
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
unsigned long val;
- size_t size = min(sizeof(s) - 1, count);
- struct adapter *adap = file_inode(file)->i_private;
+ size_t size;
+ char s[32];
+ int err;
+
+ size = min(sizeof(s) - 1, count);
if (copy_from_user(s, buf, size))
return -EFAULT;
@@ -707,8 +823,9 @@ static int ulprx_la_show(struct seq_file *seq, void *v, int idx)
static int ulprx_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
p = seq_open_tab(file, ULPRX_LA_SIZE, 8 * sizeof(u32), 1,
ulprx_la_show);
@@ -748,10 +865,11 @@ static int pm_stats_show(struct seq_file *seq, void *v)
"Read:", "Write bypass:", "Write mem:", "Flush:"
};
- int i;
u32 tx_cnt[T6_PM_NSTATS], rx_cnt[T6_PM_NSTATS];
u64 tx_cyc[T6_PM_NSTATS], rx_cyc[T6_PM_NSTATS];
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ int i;
t4_pmtx_get_stats(adap, tx_cnt, tx_cyc);
t4_pmrx_get_stats(adap, rx_cnt, rx_cyc);
@@ -791,6 +909,61 @@ static int pm_stats_show(struct seq_file *seq, void *v)
seq_printf(seq, "Rx latency %10u %20llu\n",
rx_cnt[i], rx_cyc[i]);
}
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ u32 stats[T7_PM_RX_CACHE_NSTATS];
+
+ t4_pmrx_cache_get_stats(adap, stats);
+
+ i = 0;
+ seq_puts(seq, "\n\nPM RX Cache Stats\n");
+ seq_printf(seq, "%-40s %u\n", "ReqWrite", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "ReqReadInv", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "ReqReadNoInv", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Split Request",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Split (Read Invalidate)", stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Feedback Read Split (Read NoInvalidate)",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Hit", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Hit", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Feedback Read Hit",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Hit Full Avail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Hit Full UnAvail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Hit Partial Avail", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "FB Read Hit Full Avail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "FB Read Hit Full UnAvail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "FB Read Hit Partial Avail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Full Free",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Part-avail Mul-Regions", stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "FB Read Part-avail Mul-Regions", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Miss FL Used",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Miss LRU Used",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Write Miss LRU-Multiple Evict", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Hit Increasing Islands",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Island Read split", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Overflow Eviction",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Read Overflow Eviction",
+ stats[i++]);
+ }
return 0;
}
@@ -802,7 +975,8 @@ static int pm_stats_open(struct inode *inode, struct file *file)
static ssize_t pm_stats_clear(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- struct adapter *adap = file_inode(file)->i_private;
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0);
t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0);
@@ -820,8 +994,9 @@ static const struct file_operations pm_stats_debugfs_fops = {
static int tx_rate_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u64 nrate[NCHAN], orate[NCHAN];
- struct adapter *adap = seq->private;
t4_get_chan_txrate(adap, nrate, orate);
if (adap->params.arch.nchan == NCHAN) {
@@ -856,9 +1031,10 @@ static int cctrl_tbl_show(struct seq_file *seq, void *v)
"0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
"0.9375" };
- int i;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u16 (*incr)[NCCTRL_WIN];
- struct adapter *adap = seq->private;
+ int i;
incr = kmalloc_objs(*incr, NMTUS);
if (!incr)
@@ -902,13 +1078,16 @@ static char *unit_conv(char *buf, size_t len, unsigned int val,
static int clk_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ unsigned int cclk_ps, tre, dack_re, res;
+ struct adapter *adap = d->adap;
+ unsigned long long tp_tick_us;
char buf[32];
- struct adapter *adap = seq->private;
- unsigned int cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */
- u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
- unsigned int tre = TIMERRESOLUTION_G(res);
- unsigned int dack_re = DELAYEDACKRESOLUTION_G(res);
- unsigned long long tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */
+ cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */
+ res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
+ tre = TIMERRESOLUTION_G(res);
+ dack_re = DELAYEDACKRESOLUTION_G(res);
+ tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */
seq_printf(seq, "Core clock period: %s ns\n",
unit_conv(buf, sizeof(buf), cclk_ps, 1000));
@@ -1080,13 +1259,17 @@ static const struct seq_operations devlog_seq_ops = {
*/
static int devlog_open(struct inode *inode, struct file *file)
{
- struct adapter *adap = inode->i_private;
- struct devlog_params *dparams = &adap->params.devlogs;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ struct devlog_params *dparams;
struct devlog_info *dinfo;
+ u8 coreid = d->coreid;
unsigned int index;
u32 fseqno;
int ret;
+ dparams = &adap->params.devlog[coreid];
+
/* If we don't know where the log is we can't do anything.
*/
if (dparams->start == 0)
@@ -1153,11 +1336,13 @@ static const struct file_operations devlog_fops = {
*/
static int mboxlog_show(struct seq_file *seq, void *v)
{
- struct adapter *adapter = seq->private;
- struct mbox_cmd_log *log = adapter->mbox_log;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ struct mbox_cmd_log *log;
struct mbox_cmd *entry;
int entry_idx, i;
+ log = adap->mbox_log;
if (v == SEQ_START_TOKEN) {
seq_printf(seq,
"%10s %15s %5s %5s %s\n",
@@ -1191,10 +1376,11 @@ static int mboxlog_show(struct seq_file *seq, void *v)
static inline void *mboxlog_get_idx(struct seq_file *seq, loff_t pos)
{
- struct adapter *adapter = seq->private;
- struct mbox_cmd_log *log = adapter->mbox_log;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
- return ((pos <= log->size) ? (void *)(uintptr_t)(pos + 1) : NULL);
+ return ((pos <= adap->mbox_log->size) ?
+ (void *)(uintptr_t)(pos + 1) : NULL);
}
static void *mboxlog_start(struct seq_file *seq, loff_t *pos)
@@ -1241,14 +1427,16 @@ static const struct file_operations mboxlog_fops = {
static int mbox_show(struct seq_file *seq, void *v)
{
- static const char * const owner[] = { "none", "FW", "driver",
- "unknown", "<unread>" };
-
+ static const char * const owner[] = {
+ "none", "FW", "driver", "FW Deferred", "<unread>"
+ };
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ unsigned int mbox = d->data;
+ void __iomem *addr;
int i;
- unsigned int mbox = (uintptr_t)seq->private & 7;
- struct adapter *adap = seq->private - mbox;
- void __iomem *addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
+ addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
/* For T4 we don't have a shadow copy of the Mailbox Control register.
* And since reading that real register causes a side effect of
* granting ownership, we're best of simply not reading it at all.
@@ -1278,14 +1466,14 @@ static int mbox_open(struct inode *inode, struct file *file)
static ssize_t mbox_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int i;
- char c = '\n', s[256];
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int mbox = d->data;
unsigned long long data[8];
- const struct inode *ino;
- unsigned int mbox;
- struct adapter *adap;
+ char s[256], c = '\n';
void __iomem *addr;
void __iomem *ctrl;
+ int i;
if (count > sizeof(s) - 1 || !count)
return -EINVAL;
@@ -1298,9 +1486,6 @@ static ssize_t mbox_write(struct file *file, const char __user *buf,
&data[7], &c) < 8 || c != '\n')
return -EINVAL;
- ino = file_inode(file);
- mbox = (uintptr_t)ino->i_private & 7;
- adap = ino->i_private - mbox;
addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
ctrl = addr + MBOX_LEN;
@@ -1325,10 +1510,11 @@ static const struct file_operations mbox_debugfs_fops = {
static int mps_trc_show(struct seq_file *seq, void *v)
{
- int enabled, i;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ unsigned int trcidx = d->data;
struct trace_params tp;
- unsigned int trcidx = (uintptr_t)seq->private & 3;
- struct adapter *adap = seq->private - trcidx;
+ int enabled, i;
t4_get_trace_filter(adap, &tp, trcidx, &enabled);
if (!enabled) {
@@ -1411,18 +1597,13 @@ static unsigned int xdigit2int(unsigned char c)
static ssize_t mps_trc_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int i, enable, ret;
- u32 *data, *mask;
- struct trace_params tp;
- const struct inode *ino;
- unsigned int trcidx;
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int trcidx = d->data;
char *s, *p, *word, *end;
- struct adapter *adap;
- u32 j;
-
- ino = file_inode(file);
- trcidx = (uintptr_t)ino->i_private & 3;
- adap = ino->i_private - trcidx;
+ struct trace_params tp;
+ int i, enable, ret;
+ u32 *data, *mask, j;
/* Don't accept input more than 1K, can't be anything valid except lots
* of whitespace. Well, use less.
@@ -1619,9 +1800,10 @@ static const struct file_operations mps_trc_debugfs_fops = {
static ssize_t flash_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
- loff_t pos = *ppos;
+ struct t4_linux_debugfs_data *d = file->private_data;
loff_t avail = file_inode(file)->i_size;
- struct adapter *adap = file->private_data;
+ struct adapter *adap = d->adap;
+ loff_t pos = *ppos;
if (pos < 0)
return -EINVAL;
@@ -1671,8 +1853,11 @@ static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
static int mps_tcam_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
- unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ unsigned int chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
if (v == SEQ_START_TOKEN) {
if (chip_ver > CHELSIO_T5) {
seq_puts(seq, "Idx Ethernet address Mask "
@@ -1683,27 +1868,91 @@ static int mps_tcam_show(struct seq_file *seq, void *v)
" P0 P1 P2 P3 ML\n");
} else {
if (adap->params.arch.mps_rplc_size > 128)
- seq_puts(seq, "Idx Ethernet address Mask "
+ seq_puts(seq,
+ "Idx Ethernet address Mask "
"Vld Ports PF VF "
"Replication "
" P0 P1 P2 P3 ML\n");
else
- seq_puts(seq, "Idx Ethernet address Mask "
+ seq_puts(seq,
+ "Idx Ethernet address Mask "
"Vld Ports PF VF Replication"
" P0 P1 P2 P3 ML\n");
}
} else {
- u64 mask;
- u8 addr[ETH_ALEN];
+ u32 cls_lo, cls_hi, ctl, data2, vnix = 0, vniy = 0;
bool replicate, dip_hit = false, vlan_vld = false;
unsigned int idx = (uintptr_t)v - 2;
+ u8 lookup_type = 0, port_num = 0;
u64 tcamy, tcamx, val;
- u32 cls_lo, cls_hi, ctl, data2, vnix = 0, vniy = 0;
+ u8 addr[ETH_ALEN];
u32 rplc[8] = {0};
- u8 lookup_type = 0, port_num = 0;
u16 ivlan = 0;
+ u64 mask;
- if (chip_ver > CHELSIO_T5) {
+ if (chip_ver >= CHELSIO_T7) {
+ /* CtlReqID - 1: use Host Driver Requester ID
+ * CtlCmdType - 0: Read, 1: Write
+ * CtlXYBitSel- 0: Y bit, 1: X bit
+ ####### for T6 ######
+ * CtlTcamSel - 26:25 Control bit. 0: TCAM0, 1: TCAM1
+ * CtlTcamIndex - 24:17 Control bits. Index of TCAM location to be accessed
+ ####### for T7B ######
+ * CtlTcamSel - 27:26 Control bit. 0: TCAM0, 1: TCAM1, 2: TCAM2
+ * CtlTcamIndex - 25:17 Control bits. Index of TCAM location to be accessed
+ */
+
+ /* Read tcamy */
+ ctl = (CTLREQID_V(1) |
+ CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0));
+
+ if (idx < 512)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx) | T7_CTLTCAMSEL_V(0);
+ else if (idx < 1024)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 512) |
+ T7_CTLTCAMSEL_V(1);
+ else /* idx 1024 to 1535 */
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 1024) |
+ T7_CTLTCAMSEL_V(2);
+
+ t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamy = DMACH_G(val) << 32;
+ tcamy |= t4_read_reg(adap,
+ MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ lookup_type = DATALKPTYPE_G(data2);
+ /* 0 - Outer header, 1 - Inner header
+ * [71:48] bit locations are overloaded for
+ * outer vs. inner lookup types.
+ */
+ if (lookup_type && lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI */
+ vniy = (((data2 & DATAVIDH2_F) |
+ DATAVIDH1_G(data2)) << 16) |
+ VIDL_G(val);
+ dip_hit = data2 & DATADIPHIT_F;
+ } else {
+ vlan_vld = data2 & DATAVIDH2_F;
+ ivlan = VIDL_G(val);
+ }
+ port_num = DATAPORTNUM_G(data2);
+
+ /* Read tcamx. Change the control param */
+ vnix = 0;
+ ctl |= CTLXYBITSEL_V(1);
+ t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamx = DMACH_G(val) << 32;
+ tcamx |= t4_read_reg(adap, MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ if (lookup_type && lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI mask */
+ vnix = (((data2 & DATAVIDH2_F) |
+ DATAVIDH1_G(data2)) << 16) |
+ VIDL_G(val);
+ }
+ } else if (chip_ver > CHELSIO_T5) {
/* CtlCmdType - 0: Read, 1: Write
* CtlTcamSel - 0: TCAM0, 1: TCAM1
* CtlXYBitSel- 0: Y bit, 1: X bit
@@ -1755,8 +2004,19 @@ static int mps_tcam_show(struct seq_file *seq, void *v)
tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
}
- cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
- cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
+ /* t7b changes MPS_T5_CLS_SRAM_H_A to indirect register */
+ if (is_t7(adap->params.chip)) {
+ u32 tmp_ctl = 0;
+
+ tmp_ctl |= SRAMWRN_V(0) |
+ SRAMINDEX_V(idx & SRAMINDEX_M);
+ t4_write_reg(adap, MPS_T5_CLS_SRAM_H_A, tmp_ctl);
+ cls_lo = t4_read_reg(adap, MPS_T5_CLS_SRAM_L_A);
+ cls_hi = t4_read_reg(adap, MPS_T5_CLS_SRAM_H_A);
+ } else {
+ cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
+ cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
+ }
if (tcamx & tcamy) {
seq_printf(seq, "%3u -\n", idx);
@@ -1886,11 +2146,11 @@ out: return 0;
static inline void *mps_tcam_get_idx(struct seq_file *seq, loff_t pos)
{
- struct adapter *adap = seq->private;
- int max_mac_addr = is_t4(adap->params.chip) ?
- NUM_MPS_CLS_SRAM_L_INSTANCES :
- NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
- return ((pos <= max_mac_addr) ? (void *)(uintptr_t)(pos + 1) : NULL);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
+ return ((pos <= adap->params.arch.mps_tcam_size) ?
+ (void *)(uintptr_t)(pos + 1) : NULL);
}
static void *mps_tcam_start(struct seq_file *seq, loff_t *pos)
@@ -1939,7 +2199,8 @@ static const struct file_operations mps_tcam_debugfs_fops = {
*/
static int sensors_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u32 param[7], val[7];
int ret;
@@ -1988,9 +2249,10 @@ static int rss_show(struct seq_file *seq, void *v, int idx)
static int rss_open(struct inode *inode, struct file *file)
{
- struct adapter *adap = inode->i_private;
- int ret, nentries;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
+ int ret, nentries;
nentries = t4_chip_rss_size(adap);
p = seq_open_tab(file, nentries / 8, 8 * sizeof(u16), 0, rss_show);
@@ -2028,7 +2290,8 @@ static const char *yesno(int x)
static int rss_config_show(struct seq_file *seq, void *v)
{
- struct adapter *adapter = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
static const char * const keymode[] = {
"global",
"global and per-VF scramble",
@@ -2037,7 +2300,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
};
u32 rssconf;
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_A);
seq_printf(seq, "TP_RSS_CONFIG: %#x\n", rssconf);
seq_printf(seq, " Tnl4TupEnIpv6: %3s\n", yesno(rssconf &
TNL4TUPENIPV6_F));
@@ -2087,11 +2350,11 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_TNL_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_TNL_A);
seq_printf(seq, "TP_RSS_CONFIG_TNL: %#x\n", rssconf);
seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
seq_printf(seq, " MaskFilter: %3d\n", MASKFILTER_G(rssconf));
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) {
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
seq_printf(seq, " HashAll: %3s\n",
yesno(rssconf & HASHALL_F));
seq_printf(seq, " HashEth: %3s\n",
@@ -2101,7 +2364,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_OFD_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_OFD_A);
seq_printf(seq, "TP_RSS_CONFIG_OFD: %#x\n", rssconf);
seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
seq_printf(seq, " RRCplMapEn: %3s\n", yesno(rssconf &
@@ -2110,16 +2373,16 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_SYN_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_SYN_A);
seq_printf(seq, "TP_RSS_CONFIG_SYN: %#x\n", rssconf);
seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F));
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
seq_printf(seq, "TP_RSS_CONFIG_VRT: %#x\n", rssconf);
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) {
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
seq_printf(seq, " KeyWrAddrX: %3d\n",
KEYWRADDRX_G(rssconf));
seq_printf(seq, " KeyExtend: %3s\n",
@@ -2133,7 +2396,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
DISABLEVLAN_F));
seq_printf(seq, " EnUpSwt: %3s\n", yesno(rssconf & ENABLEUP0_F));
seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf));
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf));
else
seq_printf(seq, " VfWrAddr: %3d\n",
@@ -2145,7 +2408,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_CNG_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_CNG_A);
seq_printf(seq, "TP_RSS_CONFIG_CNG: %#x\n", rssconf);
seq_printf(seq, " ChnCount3: %3s\n", yesno(rssconf & CHNCOUNT3_F));
seq_printf(seq, " ChnCount2: %3s\n", yesno(rssconf & CHNCOUNT2_F));
@@ -2180,9 +2443,11 @@ DEFINE_SHOW_ATTRIBUTE(rss_config);
static int rss_key_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u32 key[10];
- t4_read_rss_key(seq->private, key, true);
+ t4_read_rss_key(adap, key, true);
seq_printf(seq, "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n",
key[9], key[8], key[7], key[6], key[5], key[4], key[3],
key[2], key[1], key[0]);
@@ -2197,10 +2462,11 @@ static int rss_key_open(struct inode *inode, struct file *file)
static ssize_t rss_key_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int i, j;
- u32 key[10];
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
char s[100], *p;
- struct adapter *adap = file_inode(file)->i_private;
+ u32 key[10];
+ int i, j;
if (count > sizeof(s) - 1)
return -EINVAL;
@@ -2285,10 +2551,11 @@ static int rss_pf_config_show(struct seq_file *seq, void *v, int idx)
static int rss_pf_config_open(struct inode *inode, struct file *file)
{
- struct adapter *adapter = inode->i_private;
- struct seq_tab *p;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
u32 rss_pf_map, rss_pf_mask;
struct rss_pf_conf *pfconf;
+ struct seq_tab *p;
int pf;
p = seq_open_tab(file, 8, sizeof(*pfconf), 1, rss_pf_config_show);
@@ -2296,12 +2563,12 @@ static int rss_pf_config_open(struct inode *inode, struct file *file)
return -ENOMEM;
pfconf = (struct rss_pf_conf *)p->data;
- rss_pf_map = t4_read_rss_pf_map(adapter, true);
- rss_pf_mask = t4_read_rss_pf_mask(adapter, true);
+ rss_pf_map = t4_read_rss_pf_map(adap, true);
+ rss_pf_mask = t4_read_rss_pf_mask(adap, true);
for (pf = 0; pf < 8; pf++) {
pfconf[pf].rss_pf_map = rss_pf_map;
pfconf[pf].rss_pf_mask = rss_pf_mask;
- t4_read_rss_pf_config(adapter, pf, &pfconf[pf].rss_pf_config,
+ t4_read_rss_pf_config(adap, pf, &pfconf[pf].rss_pf_config,
true);
}
return 0;
@@ -2353,18 +2620,20 @@ static int rss_vf_config_show(struct seq_file *seq, void *v, int idx)
static int rss_vf_config_open(struct inode *inode, struct file *file)
{
- struct adapter *adapter = inode->i_private;
- struct seq_tab *p;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct rss_vf_conf *vfconf;
- int vf, vfcount = adapter->params.arch.vfcount;
+ struct seq_tab *p;
+ int vf, vfcount;
+ vfcount = adap->params.arch.vfcount;
p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show);
if (!p)
return -ENOMEM;
vfconf = (struct rss_vf_conf *)p->data;
for (vf = 0; vf < vfcount; vf++) {
- t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl,
+ t4_read_rss_vf_config(adap, vf, &vfconf[vf].rss_vf_vfl,
&vfconf[vf].rss_vf_vfh, true);
}
return 0;
@@ -2384,7 +2653,8 @@ static const struct file_operations rss_vf_config_debugfs_fops = {
*/
static int dcb_info_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
if (v == SEQ_START_TOKEN) {
seq_puts(seq, "Data Center Bridging Information\n");
@@ -2405,7 +2675,6 @@ static int dcb_info_show(struct seq_file *seq, void *v)
if (dcb->msgs) {
int i;
-
seq_puts(seq, "\n Index\t\t\t :\t");
for (i = 0; i < 8; i++)
seq_printf(seq, " %3d", i);
@@ -2514,13 +2783,14 @@ static int dcb_info_show(struct seq_file *seq, void *v)
static inline void *dcb_info_get_idx(struct adapter *adap, loff_t pos)
{
return (pos <= adap->params.nports
- ? (void *)((uintptr_t)pos + 1)
- : NULL);
+ ? (void *)((uintptr_t)pos + 1)
+ : NULL);
}
static void *dcb_info_start(struct seq_file *seq, loff_t *pos)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
return (*pos
? dcb_info_get_idx(adap, *pos)
@@ -2533,7 +2803,8 @@ static void dcb_info_stop(struct seq_file *seq, void *v)
static void *dcb_info_next(struct seq_file *seq, void *v, loff_t *pos)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
(*pos)++;
return dcb_info_get_idx(adap, *pos);
@@ -2569,8 +2840,11 @@ static const struct file_operations dcb_info_debugfs_fops = {
static int resources_show(struct seq_file *seq, void *v)
{
- struct adapter *adapter = seq->private;
- struct pf_resources *pfres = &adapter->params.pfres;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ struct pf_resources *pfres;
+
+ pfres = &adap->params.pfres;
#define S(desc, fmt, var) \
seq_printf(seq, "%-60s " fmt "\n", \
@@ -2593,12 +2867,13 @@ static int resources_show(struct seq_file *seq, void *v)
}
DEFINE_SHOW_ATTRIBUTE(resources);
+#ifdef CONFIG_CHELSIO_T4_DCB
/**
* ethqset2pinfo - return port_info of an Ethernet Queue Set
* @adap: the adapter
* @qset: Ethernet Queue Set
*/
-static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
+static struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
{
int pidx;
@@ -2614,6 +2889,7 @@ static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
BUG();
return NULL;
}
+#endif /* CONFIG_CHELSIO_T4_DCB */
static int sge_qinfo_uld_txq_entries(const struct adapter *adap, int uld)
{
@@ -2656,7 +2932,10 @@ static int sge_qinfo_show(struct seq_file *seq, void *v)
const struct sge_uld_txq_info *utxq_info;
const struct sge_uld_rxq_info *urxq_info;
struct cxgb4_tc_port_mqprio *port_mqprio;
- struct adapter *adap = seq->private;
+
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
int i, j, n, r = (uintptr_t)v - 1;
struct sge *s = &adap->sge;
@@ -3101,7 +3380,6 @@ do { \
skip_uld:
if (r < ctrl_entries) {
const struct sge_ctrl_txq *tx = &s->ctrlq[r * 4];
-
n = min(4, adap->params.nports - 4 * r);
S("QType:", "Control");
@@ -3206,7 +3484,10 @@ static int sge_queue_entries(struct adapter *adap)
static void *sge_queue_start(struct seq_file *seq, loff_t *pos)
{
- int entries = sge_queue_entries(seq->private);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
+ int entries = sge_queue_entries(adap);
return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
}
@@ -3217,7 +3498,10 @@ static void sge_queue_stop(struct seq_file *seq, void *v)
static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos)
{
- int entries = sge_queue_entries(seq->private);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
+ int entries = sge_queue_entries(adap);
++*pos;
return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
@@ -3252,14 +3536,11 @@ static const struct file_operations sge_qinfo_debugfs_fops = {
int mem_open(struct inode *inode, struct file *file)
{
- unsigned int mem;
- struct adapter *adap;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
file->private_data = inode->i_private;
- mem = (uintptr_t)file->private_data & 0x7;
- adap = file->private_data - mem;
-
(void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH);
return 0;
@@ -3268,10 +3549,11 @@ int mem_open(struct inode *inode, struct file *file)
static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
- loff_t pos = *ppos;
+ struct t4_linux_debugfs_data *d = file->private_data;
loff_t avail = file_inode(file)->i_size;
- unsigned int mem = (uintptr_t)file->private_data & 0x7;
- struct adapter *adap = file->private_data - mem;
+ struct adapter *adap = d->adap;
+ unsigned int mem = d->data;
+ loff_t pos = *ppos;
__be32 *data;
int ret;
@@ -3311,18 +3593,19 @@ static const struct file_operations mem_debugfs_fops = {
static int tid_info_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
const struct tid_info *t;
- enum chip_type chip;
+ unsigned int chip_ver;
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
t = &adap->tids;
- chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+
if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) {
unsigned int sb;
seq_printf(seq, "Connections in use: %u\n",
atomic_read(&t->conns_in_use));
-
- if (chip <= CHELSIO_T5)
+ if (chip_ver <= CHELSIO_T5)
sb = t4_read_reg(adap, LE_DB_SERVER_INDEX_A) / 4;
else
sb = t4_read_reg(adap, LE_DB_SRVR_START_INDEX_A);
@@ -3363,12 +3646,11 @@ static int tid_info_show(struct seq_file *seq, void *v)
if (t->nstids)
seq_printf(seq, "STID range: %u..%u, in use-IPv4/IPv6: %u/%u\n",
(!t->stid_base &&
- (chip <= CHELSIO_T5)) ?
+ (chip_ver <= CHELSIO_T5)) ?
t->stid_base + 1 : t->stid_base,
t->stid_base + t->nstids - 1,
t->stids_in_use - t->v6_stids_in_use,
t->v6_stids_in_use);
-
if (t->natids)
seq_printf(seq, "ATID range: 0..%u, in use: %u\n",
t->natids - 1, t->atids_in_use);
@@ -3378,11 +3660,11 @@ static int tid_info_show(struct seq_file *seq, void *v)
seq_printf(seq, "SFTID range: %u..%u in use: %u\n",
t->sftid_base, t->sftid_base + t->nsftids - 2,
t->sftids_in_use);
- if (t->nhpftids)
+ if (t->nhpftids && chip_ver > CHELSIO_T5)
seq_printf(seq, "HPFTID range: %u..%u\n", t->hpftid_base,
t->hpftid_base + t->nhpftids - 1);
if (t->neotids)
- seq_printf(seq, "EOTID range: %u..%u, in use: %u\n",
+ seq_printf(seq, "UOTID range: %u..%u, in use: %u\n",
t->eotid_base, t->eotid_base + t->neotids - 1,
atomic_read(&t->eotids_in_use));
if (t->ntids)
@@ -3393,22 +3675,17 @@ static int tid_info_show(struct seq_file *seq, void *v)
}
DEFINE_SHOW_ATTRIBUTE(tid_info);
-static void add_debugfs_mem(struct adapter *adap, const char *name,
- unsigned int idx, unsigned int size_mb)
-{
- debugfs_create_file_size(name, 0400, adap->debugfs_root,
- (void *)adap + idx, &mem_debugfs_fops,
- size_mb << 20);
-}
-
static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf,
size_t count, loff_t *ppos)
{
- int len;
- const struct adapter *adap = filp->private_data;
+ struct t4_linux_debugfs_data *d = filp->private_data;
+ const struct adapter *adap = d->adap;
+ ssize_t size;
char *buf;
- ssize_t size = (adap->sge.egr_sz + 3) / 4 +
- adap->sge.egr_sz / 32 + 2; /* includes ,/\n/\0 */
+ int len;
+
+ size = (adap->sge.egr_sz + 3) / 4 + adap->sge.egr_sz / 32 +
+ 2; /* includes ,/\n/\0 */
buf = kzalloc(size, GFP_KERNEL);
if (!buf)
@@ -3425,9 +3702,10 @@ static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf,
static ssize_t blocked_fl_write(struct file *filp, const char __user *ubuf,
size_t count, loff_t *ppos)
{
- int err;
+ struct t4_linux_debugfs_data *d = filp->private_data;
+ struct adapter *adap = d->adap;
unsigned long *t;
- struct adapter *adap = filp->private_data;
+ int err;
t = bitmap_zalloc(adap->sge.egr_sz, GFP_KERNEL);
if (!t)
@@ -3453,20 +3731,21 @@ static const struct file_operations blocked_fl_fops = {
};
static void mem_region_show(struct seq_file *seq, const char *name,
- unsigned int from, unsigned int to)
+ u64 from, u64 to)
{
char buf[40];
string_get_size((u64)to - from + 1, 1, STRING_UNITS_2, buf,
sizeof(buf));
- seq_printf(seq, "%-15s %#x-%#x [%s]\n", name, from, to, buf);
+ seq_printf(seq, "%-20s %#llx-%#llx [%s]\n", name, from, to, buf);
}
static int meminfo_show(struct seq_file *seq, void *v)
{
static const char * const memory[] = { "EDC0:", "EDC1:", "MC:",
"MC0:", "MC1:", "HMA:"};
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct cudbg_meminfo meminfo;
int i, rc;
@@ -3527,11 +3806,12 @@ DEFINE_SHOW_ATTRIBUTE(meminfo);
static int chcr_stats_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
struct ch_ktls_port_stats_debug *ktls_port;
int i = 0;
#endif
- struct adapter *adap = seq->private;
+ struct adapter *adap = d->adap;
seq_puts(seq, "Chelsio Crypto Accelerator Stats \n");
seq_printf(seq, "Cipher Ops: %10u \n",
@@ -3615,7 +3895,8 @@ do { \
static void show_tcp_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_tcp_stats v4, v6;
spin_lock(&adap->stats_lock);
@@ -3634,7 +3915,8 @@ static void show_tcp_stats(struct seq_file *seq)
static void show_ddp_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_usm_stats stats;
spin_lock(&adap->stats_lock);
@@ -3648,8 +3930,9 @@ static void show_ddp_stats(struct seq_file *seq)
static void show_rdma_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
- struct tp_rdma_stats stats;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ struct tp_rdma_stats stats = {0};
spin_lock(&adap->stats_lock);
t4_tp_get_rdma_stats(adap, &stats, false);
@@ -3657,11 +3940,13 @@ static void show_rdma_stats(struct seq_file *seq)
PRINT_ADAP_STATS("rdma_no_rqe_mod_defer:", stats.rqe_dfr_mod);
PRINT_ADAP_STATS("rdma_no_rqe_pkt_defer:", stats.rqe_dfr_pkt);
+
}
static void show_tp_err_adapter_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_err_stats stats;
spin_lock(&adap->stats_lock);
@@ -3674,7 +3959,8 @@ static void show_tp_err_adapter_stats(struct seq_file *seq)
static void show_cpl_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_cpl_stats stats;
u8 i;
@@ -3688,7 +3974,8 @@ static void show_cpl_stats(struct seq_file *seq)
static void show_tp_err_channel_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_err_stats stats;
u8 i;
@@ -3708,7 +3995,8 @@ static void show_tp_err_channel_stats(struct seq_file *seq)
static void show_fcoe_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_fcoe_stats stats[NCHAN];
u8 i;
@@ -3728,7 +4016,8 @@ static void show_fcoe_stats(struct seq_file *seq)
static int tp_stats_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
seq_puts(seq, "\n--------Adapter Stats--------\n");
show_tcp_stats(seq);
@@ -3738,9 +4027,8 @@ static int tp_stats_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n-------- Channel Stats --------\n");
if (adap->params.arch.nchan == NCHAN)
- seq_printf(seq, "%-25s %-20s %-20s %-20s %-20s\n",
- " ", "channel 0", "channel 1",
- "channel 2", "channel 3");
+ seq_printf(seq, "%-25s %-20s %-20s %-20s %-20s\n", " ",
+ "channel 0", "channel 1", "channel 2", "channel 3");
else
seq_printf(seq, "%-25s %-20s %-20s\n",
" ", "channel 0", "channel 1");
@@ -3754,32 +4042,175 @@ DEFINE_SHOW_ATTRIBUTE(tp_stats);
/* Add an array of Debug FS files.
*/
-void add_debugfs_files(struct adapter *adap,
- struct t4_debugfs_entry *files,
- unsigned int nfiles)
+static void create_debugfs_file_entry(struct t4_linux_debugfs_entry *f,
+ const char *name,
+ const struct file_operations *ops,
+ umode_t mode, unsigned char data)
{
- int i;
+ f->name = name;
+ f->ops = ops;
+ f->mode = mode;
+ f->data = data;
+}
- /* debugfs support is best effort */
- for (i = 0; i < nfiles; i++)
- debugfs_create_file(files[i].name, files[i].mode,
- adap->debugfs_root,
- (void *)adap + files[i].data,
- files[i].ops);
+static void add_debugfs_file_size(struct adapter *adap, struct dentry *dentry,
+ struct t4_linux_debugfs_entry *f, u64 size)
+{
+ struct t4_linux_debugfs_data *data;
+
+ data = devm_kzalloc(adap->pdev_dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return;
+
+ data->adap = adap;
+ data->data = f->data;
+ data->coreid = 0;
+ debugfs_create_file_size(f->name, f->mode, dentry, data, f->ops, size);
+}
+
+static void add_debugfs_mem(struct adapter *adap, const char *name,
+ unsigned int i, unsigned int size_mb)
+{
+ struct t4_linux_debugfs_entry f;
+
+ create_debugfs_file_entry(&f, name, &mem_debugfs_fops, 0400, i);
+ add_debugfs_file_size(adap, adap->debugfs_root, &f, (u64)size_mb << 20);
}
-int t4_setup_debugfs(struct adapter *adap)
+void add_debugfs_files(struct adapter *adap, struct dentry *dentry,
+ unsigned char coreid, struct t4_linux_debugfs_entry *f,
+ unsigned int n)
{
+ struct t4_linux_debugfs_data *data;
int i;
- u32 size = 0;
- static struct t4_debugfs_entry t4_debugfs_files[] = {
+ for (i = 0; i < n; i++) {
+ data = devm_kzalloc(adap->pdev_dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ continue;
+
+ data->adap = adap;
+ data->data = f[i].data;
+ data->coreid = coreid;
+ debugfs_create_file(f[i].name, f[i].mode, dentry, data,
+ f[i].ops);
+ }
+}
+
+static void add_debugfs_files_multicore(struct adapter *adap)
+{
+ static struct t4_linux_debugfs_entry common_files[] = {
{ "cim_la", &cim_la_fops, 0400, 0 },
{ "cim_pif_la", &cim_pif_la_fops, 0400, 0 },
{ "cim_ma_la", &cim_ma_la_fops, 0400, 0 },
{ "cim_qcfg", &cim_qcfg_fops, 0400, 0 },
- { "clk", &clk_fops, 0400, 0 },
{ "devlog", &devlog_fops, 0400, 0 },
+ };
+ static struct t4_linux_debugfs_entry t4_files[] = {
+ { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
+ { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
+ { "ibq_ulp", &cim_ibq_fops, 0400, 2 },
+ { "ibq_sge", &cim_ibq_fops, 0400, 3 },
+ { "ibq_pcie", &cim_ibq_fops, 0400, 4 },
+ { "ibq_ncsi", &cim_ibq_fops, 0400, 5 },
+ { "obq_ulp0", &cim_obq_fops, 0400, 0 },
+ { "obq_ulp1", &cim_obq_fops, 0400, 1 },
+ { "obq_ulp2", &cim_obq_fops, 0400, 2 },
+ { "obq_ulp3", &cim_obq_fops, 0400, 3 },
+ { "obq_sge", &cim_obq_fops, 0400, 4 },
+ { "obq_ncsi", &cim_obq_fops, 0400, 5 },
+ };
+ static struct t4_linux_debugfs_entry t5_files[] = {
+ { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
+ { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
+ { "ibq_ulp", &cim_ibq_fops, 0400, 2 },
+ { "ibq_sge", &cim_ibq_fops, 0400, 3 },
+ { "ibq_pcie", &cim_ibq_fops, 0400, 4 },
+ { "ibq_ncsi", &cim_ibq_fops, 0400, 5 },
+ { "obq_ulp0", &cim_obq_fops, 0400, 0 },
+ { "obq_ulp1", &cim_obq_fops, 0400, 1 },
+ { "obq_ulp2", &cim_obq_fops, 0400, 2 },
+ { "obq_ulp3", &cim_obq_fops, 0400, 3 },
+ { "obq_sge", &cim_obq_fops, 0400, 4 },
+ { "obq_ncsi", &cim_obq_fops, 0400, 5 },
+ { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 },
+ { "obq_sge_rx_q1", &cim_obq_fops, 0400, 7 },
+ };
+ static struct t4_linux_debugfs_entry t7_files[] = {
+ { "ibq_pcie", &cim_ibq_fops, 0400, 6 },
+ { "ibq_ncsi", &cim_ibq_fops, 0400, 7 },
+ { "ibq_ipc2", &cim_ibq_fops, 0400, 10 },
+ { "ibq_ipc3", &cim_ibq_fops, 0400, 11 },
+ { "ibq_ipc4", &cim_ibq_fops, 0400, 12 },
+ { "ibq_ipc5", &cim_ibq_fops, 0400, 13 },
+ { "ibq_ipc6", &cim_ibq_fops, 0400, 14 },
+ { "ibq_ipc7", &cim_ibq_fops, 0400, 15 },
+ { "obq_ncsi", &cim_obq_fops, 0400, 5 },
+ { "obq_ipc2", &cim_obq_fops, 0400, 10 },
+ { "obq_ipc3", &cim_obq_fops, 0400, 11 },
+ { "obq_ipc4", &cim_obq_fops, 0400, 12 },
+ { "obq_ipc5", &cim_obq_fops, 0400, 13 },
+ { "obq_ipc6", &cim_obq_fops, 0400, 14 },
+ { "obq_ipc7", &cim_obq_fops, 0400, 15 },
+ };
+ static struct t4_linux_debugfs_entry t7_sec_files[] = {
+ { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
+ { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
+ { "ibq_tp2", &cim_ibq_fops, 0400, 2 },
+ { "ibq_tp3", &cim_ibq_fops, 0400, 3 },
+ { "ibq_ulp", &cim_ibq_fops, 0400, 4 },
+ { "ibq_sge", &cim_ibq_fops, 0400, 5 },
+ { "ibq_ipc1", &cim_ibq_fops, 0400, 9 },
+ { "obq_ulp0", &cim_obq_fops, 0400, 0 },
+ { "obq_ulp1", &cim_obq_fops, 0400, 1 },
+ { "obq_ulp2", &cim_obq_fops, 0400, 2 },
+ { "obq_ulp3", &cim_obq_fops, 0400, 3 },
+ { "obq_sge", &cim_obq_fops, 0400, 4 },
+ { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 },
+ { "obq_ipc1", &cim_obq_fops, 0400, 9 },
+ };
+ u32 chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ char name[8];
+ u8 i;
+
+ switch (chip) {
+ case CHELSIO_T4:
+ add_debugfs_files(adap, adap->debugfs_root, 0, common_files,
+ ARRAY_SIZE(common_files));
+ add_debugfs_files(adap, adap->debugfs_root, 0, t4_files,
+ ARRAY_SIZE(t4_files));
+ break;
+ case CHELSIO_T5:
+ case CHELSIO_T6:
+ add_debugfs_files(adap, adap->debugfs_root, 0, common_files,
+ ARRAY_SIZE(common_files));
+ add_debugfs_files(adap, adap->debugfs_root, 0, t5_files,
+ ARRAY_SIZE(t5_files));
+ break;
+ default:
+ for (i = 0; i < adap->params.num_up_cores; i++) {
+ snprintf(name, sizeof(name), "core_%u", i);
+ adap->debugfs_multicore[i] =
+ debugfs_create_dir(name, adap->debugfs_root);
+
+ if (i == 0) {
+ add_debugfs_files(adap, adap->debugfs_multicore[i], i,
+ t7_files, ARRAY_SIZE(t7_files));
+ }
+
+ add_debugfs_files(adap, adap->debugfs_multicore[i], i,
+ common_files, ARRAY_SIZE(common_files));
+ add_debugfs_files(adap, adap->debugfs_multicore[i], i,
+ t7_sec_files, ARRAY_SIZE(t7_sec_files));
+ }
+ break;
+ }
+}
+
+static int t4_setup_debugfs(struct adapter *adap)
+{
+ static struct t4_linux_debugfs_entry t4_debugfs_files[] = {
+ { "clk", &clk_fops, 0400, 0 },
{ "mboxlog", &mboxlog_fops, 0400, 0 },
{ "mbox0", &mbox_debugfs_fops, 0600, 0 },
{ "mbox1", &mbox_debugfs_fops, 0600, 1 },
@@ -3789,105 +4220,177 @@ int t4_setup_debugfs(struct adapter *adap)
{ "mbox5", &mbox_debugfs_fops, 0600, 5 },
{ "mbox6", &mbox_debugfs_fops, 0600, 6 },
{ "mbox7", &mbox_debugfs_fops, 0600, 7 },
- { "trace0", &mps_trc_debugfs_fops, 0600, 0 },
- { "trace1", &mps_trc_debugfs_fops, 0600, 1 },
- { "trace2", &mps_trc_debugfs_fops, 0600, 2 },
- { "trace3", &mps_trc_debugfs_fops, 0600, 3 },
- { "l2t", &t4_l2t_fops, 0400, 0},
{ "mps_tcam", &mps_tcam_debugfs_fops, 0400, 0 },
- { "rss", &rss_debugfs_fops, 0400, 0 },
- { "rss_config", &rss_config_fops, 0400, 0 },
- { "rss_key", &rss_key_debugfs_fops, 0400, 0 },
- { "rss_pf_config", &rss_pf_config_debugfs_fops, 0400, 0 },
- { "rss_vf_config", &rss_vf_config_debugfs_fops, 0400, 0 },
- { "resources", &resources_fops, 0400, 0 },
-#ifdef CONFIG_CHELSIO_T4_DCB
- { "dcb_info", &dcb_info_debugfs_fops, 0400, 0 },
-#endif
- { "sge_qinfo", &sge_qinfo_debugfs_fops, 0400, 0 },
- { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
- { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
- { "ibq_ulp", &cim_ibq_fops, 0400, 2 },
- { "ibq_sge0", &cim_ibq_fops, 0400, 3 },
- { "ibq_sge1", &cim_ibq_fops, 0400, 4 },
- { "ibq_ncsi", &cim_ibq_fops, 0400, 5 },
- { "obq_ulp0", &cim_obq_fops, 0400, 0 },
- { "obq_ulp1", &cim_obq_fops, 0400, 1 },
- { "obq_ulp2", &cim_obq_fops, 0400, 2 },
- { "obq_ulp3", &cim_obq_fops, 0400, 3 },
- { "obq_sge", &cim_obq_fops, 0400, 4 },
- { "obq_ncsi", &cim_obq_fops, 0400, 5 },
{ "tp_la", &tp_la_fops, 0400, 0 },
{ "ulprx_la", &ulprx_la_fops, 0400, 0 },
{ "sensors", &sensors_fops, 0400, 0 },
+ { "tp_stats", &tp_stats_fops, 0400, 0 },
{ "pm_stats", &pm_stats_debugfs_fops, 0400, 0 },
{ "tx_rate", &tx_rate_fops, 0400, 0 },
{ "cctrl", &cctrl_tbl_fops, 0400, 0 },
-#if IS_ENABLED(CONFIG_IPV6)
- { "clip_tbl", &clip_tbl_fops, 0400, 0 },
-#endif
- { "tids", &tid_info_fops, 0400, 0},
- { "blocked_fl", &blocked_fl_fops, 0600, 0 },
- { "meminfo", &meminfo_fops, 0400, 0 },
- { "crypto", &chcr_stats_fops, 0400, 0 },
- { "tp_stats", &tp_stats_fops, 0400, 0 },
- };
-
- /* Debug FS nodes common to all T5 and later adapters.
- */
- static struct t4_debugfs_entry t5_debugfs_files[] = {
- { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 },
- { "obq_sge_rx_q1", &cim_obq_fops, 0400, 7 },
+ { "rss", &rss_debugfs_fops, 0400, 0 },
+ { "rss_config", &rss_config_fops, 0400, 0 },
+ { "rss_key", &rss_key_debugfs_fops, 0400, 0 },
+ { "rss_pf_config", &rss_pf_config_debugfs_fops, 0400, 0 },
+ { "rss_vf_config", &rss_vf_config_debugfs_fops, 0400, 0 },
+ { "meminfo", &meminfo_fops, 0400, 0 }
};
+ u32 val, chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ struct t4_linux_debugfs_entry f;
+ int i;
- add_debugfs_files(adap,
- t4_debugfs_files,
+ add_debugfs_files(adap, adap->debugfs_root, 0, t4_debugfs_files,
ARRAY_SIZE(t4_debugfs_files));
- if (!is_t4(adap->params.chip))
- add_debugfs_files(adap,
- t5_debugfs_files,
- ARRAY_SIZE(t5_debugfs_files));
+
+ add_debugfs_files_multicore(adap);
i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
if (i & EDRAM0_ENABLE_F) {
- size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
- add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size));
+ val = t4_read_reg(adap, MA_EDRAM0_BAR_A);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ add_debugfs_mem(adap, "edc0", MEM_EDC0, T7_EDRAM0_SIZE_G(val));
+ else
+ add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(val));
}
+
if (i & EDRAM1_ENABLE_F) {
- size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
- add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));
+ val = t4_read_reg(adap, MA_EDRAM1_BAR_A);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ add_debugfs_mem(adap, "edc1", MEM_EDC1, T7_EDRAM1_SIZE_G(val));
+ else
+ add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(val));
}
- if (is_t5(adap->params.chip)) {
- if (i & EXT_MEM0_ENABLE_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
+
+ if (i & EXT_MEM_ENABLE_F) {
+ switch (chip) {
+ case CHELSIO_T4:
+ case CHELSIO_T5:
+ val = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
+ add_debugfs_mem(adap, "mc0", MEM_MC0,
+ EXT_MEM0_SIZE_G(val));
+ break;
+ case CHELSIO_T6:
+ val = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
+ add_debugfs_mem(adap, "mc", MEM_MC,
+ EXT_MEM_SIZE_G(val));
+ break;
+ default:
+ val = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
add_debugfs_mem(adap, "mc0", MEM_MC0,
- EXT_MEM0_SIZE_G(size));
+ T7_EXT_MEM0_SIZE_G(val));
+ break;
}
- if (i & EXT_MEM1_ENABLE_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+ }
+
+ if (i & EXT_MEM1_ENABLE_F) {
+ switch (chip) {
+ case CHELSIO_T4:
+ case CHELSIO_T5:
+ /* No mc1 when split mode enabled */
+ if (i & MC_SPLIT_F)
+ break;
+
+ val = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
add_debugfs_mem(adap, "mc1", MEM_MC1,
- EXT_MEM1_SIZE_G(size));
- }
- } else {
- if (i & EXT_MEM_ENABLE_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
- add_debugfs_mem(adap, "mc", MEM_MC,
- EXT_MEM_SIZE_G(size));
+ EXT_MEM1_SIZE_G(val));
+ break;
+ case CHELSIO_T6:
+ /* No support for mc1 */
+ break;
+ default:
+ /* No mc1 when split mode enabled */
+ if (i & MC_SPLIT_F)
+ break;
+
+ val = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+ add_debugfs_mem(adap, "mc1", MEM_MC1,
+ T7_EXT_MEM1_SIZE_G(val));
+ break;
}
+ }
- if (i & HMA_MUX_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+ if (i & HMA_MUX_F) {
+ switch (chip) {
+ case CHELSIO_T4:
+ case CHELSIO_T5:
+ /* No support for hma */
+ break;
+ case CHELSIO_T6:
+ val = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+ add_debugfs_mem(adap, "hma", MEM_HMA,
+ EXT_MEM_SIZE_G(val));
+ break;
+ default:
+ val = t4_read_reg(adap, MA_HOST_MEMORY_BAR_A);
add_debugfs_mem(adap, "hma", MEM_HMA,
- EXT_MEM1_SIZE_G(size));
+ T7_HMA_SIZE_G(val));
+ break;
}
}
- debugfs_create_file_size("flash", 0400, adap->debugfs_root, adap,
- &flash_debugfs_fops, adap->params.sf_size);
+ create_debugfs_file_entry(&f, "flash", &flash_debugfs_fops, 0400, 0);
+ add_debugfs_file_size(adap, adap->debugfs_root, &f,
+ adap->params.sf_size);
+
debugfs_create_bool("use_backdoor", 0600,
- adap->debugfs_root, &adap->use_bd);
+ adap->debugfs_root, &adap->use_bd);
debugfs_create_bool("trace_rss", 0600,
- adap->debugfs_root, &adap->trace_rss);
+ adap->debugfs_root, &adap->trace_rss);
+ return 0;
+}
+
+/*
+ * Add an array of Debug FS files.
+ */
+static void cxgb4_add_debugfs_files(struct adapter *adap,
+ struct t4_linux_debugfs_entry *files,
+ unsigned int nfiles)
+{
+ int i;
+
+ /* debugfs support is best effort */
+ for (i = 0; i < nfiles; i++)
+ add_debugfs_files(adap, adap->debugfs_root, 0, &files[i], 1);
+}
+
+int cxgb4_setup_debugfs(struct adapter *adap)
+{
+ static struct t4_linux_debugfs_entry cxgb4_debugfs_files[] = {
+ { "blocked_fl", &blocked_fl_fops, 0600 },
+#ifdef CONFIG_CHELSIO_T4_DCB
+ { "dcb_info", &dcb_info_debugfs_fops, 0400, 0 },
+ #endif /* CONFIG_CHELSIO_T4_DCB */
+ { "resources", &resources_fops, 0400, 0 },
+ { "sge_qinfo", &sge_qinfo_debugfs_fops, 0400, 0 },
+ { "clip_tbl", &clip_tbl_fops, 0400, 0 },
+ { "tids", &tid_info_fops, 0400, 0 },
+ { "trace0", &mps_trc_debugfs_fops, 0600, 0 },
+ { "trace1", &mps_trc_debugfs_fops, 0600, 1 },
+ { "trace2", &mps_trc_debugfs_fops, 0600, 2 },
+ { "trace3", &mps_trc_debugfs_fops, 0600, 3 },
+ { "l2t", &t4_l2t_fops, 0400, 0 },
+ { "crypto", &chcr_stats_fops, 0400, 0 },
+ };
+
+ static struct t4_linux_debugfs_entry cxgb4_t7_debugfs_files[] = {
+ { "trace4", &mps_trc_debugfs_fops, 0600, 4 },
+ { "trace5", &mps_trc_debugfs_fops, 0600, 5 },
+ { "trace6", &mps_trc_debugfs_fops, 0600, 6 },
+ { "trace7", &mps_trc_debugfs_fops, 0600, 7 },
+ };
+
+ if (IS_ERR_OR_NULL(adap->debugfs_root))
+ return -1;
+
+#ifdef CONFIG_DEBUG_FS
+ t4_setup_debugfs(adap);
+#endif
+
+ cxgb4_add_debugfs_files(adap, cxgb4_debugfs_files,
+ ARRAY_SIZE(cxgb4_debugfs_files));
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ cxgb4_add_debugfs_files(adap, cxgb4_t7_debugfs_files,
+ ARRAY_SIZE(cxgb4_t7_debugfs_files));
return 0;
}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
index 1471cf0deb58..77a0ed068baa 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
@@ -37,7 +37,13 @@
#include <linux/export.h>
-struct t4_debugfs_entry {
+struct t4_linux_debugfs_data {
+ struct adapter *adap;
+ unsigned int data;
+ unsigned char coreid;
+};
+
+struct t4_linux_debugfs_entry {
const char *name;
const struct file_operations *ops;
umode_t mode;
@@ -61,10 +67,9 @@ struct seq_tab *seq_open_tab(struct file *f, unsigned int rows,
unsigned int width, unsigned int have_header,
int (*show)(struct seq_file *seq, void *v, int i));
-int t4_setup_debugfs(struct adapter *adap);
-void add_debugfs_files(struct adapter *adap,
- struct t4_debugfs_entry *files,
- unsigned int nfiles);
+void add_debugfs_files(struct adapter *adap, struct dentry *dentry,
+ unsigned char coreid, struct t4_linux_debugfs_entry *f,
+ unsigned int n);
int mem_open(struct inode *inode, struct file *file);
-
+int cxgb4_setup_debugfs(struct adapter *adap);
#endif
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index a3b1f9db5cbe..563a0ee1ce2c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -7190,7 +7190,7 @@ int cxgb4_adap_probe(struct adapter *adapter)
const char *dir_name = pci_name(adapter->pdev);
adapter->debugfs_root = debugfs_create_dir(dir_name, cxgb4_debugfs_root);
- t4_setup_debugfs(adapter);
+ cxgb4_setup_debugfs(adapter);
}
if (is_uld(adapter))
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index a9cc401b2a1b..6b230e03b32c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -6521,7 +6521,7 @@ static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
ulprx_intr_info.details = ulprx_intr_details;
else if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T6)
- ulprx_intr_info.details = t6_ulprx_int_cause_details;
+ ulprx_intr_info.details = t6_ulprx_int_cause_details;
else
ulprx_intr_info.details = t7_ulprx_int_cause_details;
@@ -14246,22 +14246,6 @@ int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
return i;
}
-/*
- * t4_read_cim_ibq - read the contents of a CIM inbound queue
- * @adap: the adapter
- * @qid: the queue index
- * @data: where to store the queue contents
- * @n: capacity of @data in 32-bit words
- *
- * Reads the contents of the selected CIM queue starting at address 0 up
- * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
- * error and the number of 32-bit words actually read on success.
- */
-int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
-{
- return t4_read_cim_ibq_core(adap, 0, qid, data, n);
-}
-
static int t4_read_cim_obq_data_core(struct adapter *adap, u8 coreid, u32 addr,
u32 *data)
{
@@ -14321,22 +14305,6 @@ int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
return i;
}
-/*
- * t4_read_cim_obq - read the contents of a CIM outbound queue
- * @adap: the adapter
- * @qid: the queue index
- * @data: where to store the queue contents
- * @n: capacity of @data in 32-bit words
- *
- * Reads the contents of the selected CIM queue starting at address 0 up
- * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
- * error and the number of 32-bit words actually read on success.
- */
-int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
-{
- return t4_read_cim_obq_core(adap, 0, qid, data, n);
-}
-
/**
* t4_cim_read_core - read a block from CIM internal address space
* of a control register group on specific core.
@@ -14434,21 +14402,6 @@ int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
return ret;
}
-/**
- * t4_cim_write - write a block into CIM internal address space
- * @adap: the adapter
- * @addr: the start address within the CIM address space
- * @n: number of words to write
- * @valp: set of values to write
- *
- * Writes a block of 4-byte words into the CIM intenal address space.
- */
-int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
- const unsigned int *valp)
-{
- return t4_cim_write_core(adap, 0, 0, addr, n, valp);
-}
-
/**
* t4_cim_read_la_core - read CIM LA capture buffer on specific core
* @adap: the adapter
@@ -14531,21 +14484,6 @@ int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
return ret;
}
-/**
- * t4_cim_read_la - read CIM LA capture buffer
- * @adap: the adapter
- * @la_buf: where to store the LA data
- * @wrptr: the HW write pointer within the capture buffer
- *
- * Reads the contents of the CIM LA buffer with the most recent entry at
- * the end of the returned data and with the entry at @wrptr first.
- * We try to leave the LA in the running state we find it in.
- */
-int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
-{
- return t4_cim_read_la_core(adap, 0, la_buf, wrptr);
-}
-
/**
* t4_tp_read_la - read TP LA capture buffer
* @adap: the adapter
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH net-next v3 12/12] cxgb4: select ULD Tx and control queues by TID on T7
2026-10-05 22:48 [PATCH net-next v3 00/12] cxgb4: Add T7 adapter support Potnuri Bharat Teja
` (10 preceding siblings ...)
2026-10-05 22:48 ` [PATCH net-next v3 11/12] cxgb4: extend debugfs " Potnuri Bharat Teja
@ 2026-10-05 22:48 ` Potnuri Bharat Teja
11 siblings, 0 replies; 14+ messages in thread
From: Potnuri Bharat Teja @ 2026-10-05 22:48 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
On T7 adapters with more than one uP core, TIDs are distributed over
core groups and a work request carrying a TID must be sent on an egress
queue allocated in the core group owning that TID. Firmware reports the
TID bits selecting the group through the TID_QID_SEL_MASK device
parameter.
- Query TID_QID_SEL_MASK on T7 adapters with multiple cores and add
helpers returning the number of core groups and the group of a TID.
- Allocate the shared ULD offload Tx queues of each port round robin
over the core groups, passing the group to firmware in
FW_EQ_OFLD_CMD, with at least one queue per group and port.
- Add cxgb4_uld_tid_qid_sel_update() and
cxgb4_uld_tid_ctrlq_id_sel_update() for ULDs to move a connection's
Tx and control queue to the TID's core group once the TID is known.
Tx queues of a group are used round robin.
- Send CPL_TID_RELEASE on the control queue of the TID's group.
cxgb4_remove_tid() keeps taking a port, so ULDs that do not select
queues by TID release TIDs on the right queue as well.
- Control queues are now allocated num_up_cores per port. Route the
completions of all of them to the RDMA response queue, stopping at
the first failure, and pass num_up_cores to ULDs.
Without TID based queue selection, on T4 - T6 and single core T7, all
queues stay in group 0, the number of queues is unchanged and the
helpers leave queue indexes unchanged.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 28 +++-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 27 +++-
.../net/ethernet/chelsio/cxgb4/cxgb4_uld.c | 140 +++++++++++++++---
.../net/ethernet/chelsio/cxgb4/cxgb4_uld.h | 5 +
drivers/net/ethernet/chelsio/cxgb4/sge.c | 14 +-
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 5 +
6 files changed, 186 insertions(+), 33 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 8a483db4f72c..9eacf1638487 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -903,6 +903,7 @@ struct sge_uld_txq { /* state for an SGE offload Tx queue */
struct tasklet_struct qresume_tsk; /* restarts the queue */
bool service_ofldq_running; /* service_ofldq() is processing sendq */
u8 full; /* the Tx ring is full */
+ u8 tid_qid_group_id; /* uP core group of the queue */
unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
} ____cacheline_aligned_in_smp;
@@ -928,6 +929,7 @@ struct sge_uld_txq_info {
struct sge_uld_txq *uldtxq; /* Txq's for ULD */
atomic_t users; /* num users */
u16 ntxq; /* # of egress uld queues */
+ atomic_t *tid_qid_rr; /* per port, per core group round robin */
};
/* struct to maintain ULD list to reallocate ULD resources on hotplug */
@@ -1503,6 +1505,30 @@ struct filter_entry {
struct ch_filter_specification fs;
};
+static inline unsigned int cxgb4_tid_qid_ngroups(const struct adapter *adap)
+{
+ if (!adap->params.tid_qid_sel_mask)
+ return 1;
+ return (adap->params.tid_qid_sel_mask >>
+ adap->params.tid_qid_sel_shift) + 1;
+}
+
+static inline unsigned int cxgb4_tid_qid_group(const struct adapter *adap,
+ u32 tid)
+{
+ return (tid & adap->params.tid_qid_sel_mask) >>
+ adap->params.tid_qid_sel_shift;
+}
+
+static inline u16 cxgb4_tid_ctrlq_idx(const struct adapter *adap,
+ unsigned int port, u32 tid)
+{
+ if (port >= adap->params.nports)
+ port = 0;
+ return port * adap->params.num_up_cores +
+ cxgb4_tid_qid_group(adap, tid);
+}
+
static inline int is_offload(const struct adapter *adap)
{
return adap->params.offload;
@@ -1662,7 +1688,7 @@ int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
unsigned int cmplqid);
int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
struct net_device *dev, unsigned int iqid,
- unsigned int uld_type);
+ unsigned int uld_type, u8 group);
int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
struct net_device *dev, u32 iqid);
void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 563a0ee1ce2c..7a004b2de9c1 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -1749,13 +1749,15 @@ EXPORT_SYMBOL(cxgb4_free_stid);
/*
* Populate a TID_RELEASE WR. Caller must properly size the skb.
+ * @chan is the port whose control queues are used.
*/
-static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
- unsigned int tid)
+static void mk_tid_release(const struct adapter *adap, struct sk_buff *skb,
+ unsigned int chan, unsigned int tid)
{
struct cpl_tid_release *req;
- set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
+ set_wr_txq(skb, CPL_PRIORITY_SETUP,
+ cxgb4_tid_ctrlq_idx(adap, chan, tid));
req = __skb_put(skb, sizeof(*req));
INIT_TP_WR(req, tid);
OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
@@ -1806,7 +1808,7 @@ static void process_tid_release_list(struct work_struct *work)
GFP_KERNEL)))
schedule_timeout_uninterruptible(1);
- mk_tid_release(skb, chan, p - adap->tids.tid_tab);
+ mk_tid_release(adap, skb, chan, p - adap->tids.tid_tab);
t4_ofld_send(adap, skb);
spin_lock_bh(&adap->tid_release_lock);
}
@@ -1847,7 +1849,7 @@ void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
if (likely(skb)) {
- mk_tid_release(skb, chan, tid);
+ mk_tid_release(adap, skb, chan, tid);
t4_ofld_send(adap, skb);
} else
cxgb4_queue_tid_release(t, chan, tid);
@@ -5453,6 +5455,21 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
adap->vres.ddp.size = val[4] - val[3] + 1;
adap->params.ofldq_wr_cred = val[5];
+ /* On T7 with multiple uP cores, each TID is owned by one core
+ * group and TID bound work requests must be sent on an egress
+ * queue of that group.
+ */
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7 &&
+ adap->params.num_up_cores > 1) {
+ params[0] = FW_PARAM_DEV(TID_QID_SEL_MASK);
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
+ params, val);
+ if (!ret && val[0]) {
+ adap->params.tid_qid_sel_mask = val[0];
+ adap->params.tid_qid_sel_shift = ffs(val[0]) - 1;
+ }
+ }
+
if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
init_hash_filter(adap);
} else {
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c
index 23244cdfc1bc..2be70ccb6a96 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c
@@ -170,6 +170,28 @@ static int alloc_uld_rxqs(struct adapter *adap,
return err;
}
+/* Route the completions of all control queues of @port to @cmplqid.
+ * Control queues are allocated num_up_cores per port.
+ */
+static int uld_set_ctrlq_cmplqid(struct adapter *adap, int port, u32 cmplqid)
+{
+ struct sge *s = &adap->sge;
+ int k, idx, ret = 0;
+ u32 param;
+
+ for (k = 0; k < adap->params.num_up_cores; k++) {
+ idx = port * adap->params.num_up_cores + k;
+ param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
+ FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL) |
+ FW_PARAMS_PARAM_YZ_V(s->ctrlq[idx].q.cntxt_id));
+ ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
+ ¶m, &cmplqid);
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
static int
setup_sge_queues_uld(struct adapter *adap, unsigned int uld_type, bool lro)
{
@@ -182,18 +204,11 @@ setup_sge_queues_uld(struct adapter *adap, unsigned int uld_type, bool lro)
/* Tell uP to route control queue completions to rdma rspq */
if (adap->flags & CXGB4_FULL_INIT_DONE && uld_type == CXGB4_ULD_RDMA) {
- struct sge *s = &adap->sge;
- unsigned int cmplqid;
- u32 param, cmdop;
-
- cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
for_each_port(adap, i) {
- cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
- param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
- FW_PARAMS_PARAM_X_V(cmdop) |
- FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
- ret = t4_set_params(adap, adap->mbox, adap->pf,
- 0, 1, ¶m, &cmplqid);
+ ret = uld_set_ctrlq_cmplqid(adap, i,
+ rxq_info->uldrxq[i].rspq.cntxt_id);
+ if (ret)
+ break;
}
}
return ret;
@@ -214,18 +229,10 @@ static void free_sge_queues_uld(struct adapter *adap, unsigned int uld_type)
struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
if (adap->flags & CXGB4_FULL_INIT_DONE && uld_type == CXGB4_ULD_RDMA) {
- struct sge *s = &adap->sge;
- u32 param, cmdop, cmplqid = 0;
int i;
- cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
- for_each_port(adap, i) {
- param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
- FW_PARAMS_PARAM_X_V(cmdop) |
- FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
- t4_set_params(adap, adap->mbox, adap->pf,
- 0, 1, ¶m, &cmplqid);
- }
+ for_each_port(adap, i)
+ uld_set_ctrlq_cmplqid(adap, i, 0);
}
if (rxq_info->nciq)
@@ -428,10 +435,15 @@ alloc_sge_txq_uld(struct adapter *adap, struct sge_uld_txq_info *txq_info,
j = nq / adap->params.nports;
for (i = 0; i < nq; i++) {
struct sge_uld_txq *txq = &txq_info->uldtxq[i];
+ u8 group = 0;
+
+ /* Spread the queues of each port over all uP core groups */
+ if (uld_type == CXGB4_TX_OFLD)
+ group = (i % j) % cxgb4_tid_qid_ngroups(adap);
txq->q.size = 1024;
err = t4_sge_alloc_uld_txq(adap, txq, adap->port[i / j],
- s->fw_evtq.cntxt_id, uld_type);
+ s->fw_evtq.cntxt_id, uld_type, group);
if (err)
goto freeout;
}
@@ -451,6 +463,7 @@ release_sge_txq_uld(struct adapter *adap, unsigned int uld_type)
if (txq_info && atomic_dec_and_test(&txq_info->users)) {
free_sge_txq_uld(adap, txq_info);
+ kfree(txq_info->tid_qid_rr);
kfree(txq_info->uldtxq);
kfree(txq_info);
adap->sge.uld_txq_info[tx_uld_type] = NULL;
@@ -487,6 +500,9 @@ setup_sge_txq_uld(struct adapter *adap, unsigned int uld_type,
} else {
i = min_t(int, uld_info->ntxq, num_online_cpus());
txq_info->ntxq = roundup(i, adap->params.nports);
+ /* Each port needs at least one queue per uP core group */
+ i = cxgb4_tid_qid_ngroups(adap) * adap->params.nports;
+ txq_info->ntxq = max_t(int, txq_info->ntxq, i);
}
txq_info->uldtxq = kzalloc_objs(struct sge_uld_txq, txq_info->ntxq);
if (!txq_info->uldtxq) {
@@ -494,7 +510,18 @@ setup_sge_txq_uld(struct adapter *adap, unsigned int uld_type,
return -ENOMEM;
}
+ if (tx_uld_type == CXGB4_TX_OFLD && adap->params.tid_qid_sel_mask) {
+ i = cxgb4_tid_qid_ngroups(adap) * adap->params.nports;
+ txq_info->tid_qid_rr = kcalloc(i, sizeof(atomic_t), GFP_KERNEL);
+ if (!txq_info->tid_qid_rr) {
+ kfree(txq_info->uldtxq);
+ kfree(txq_info);
+ return -ENOMEM;
+ }
+ }
+
if (alloc_sge_txq_uld(adap, txq_info, tx_uld_type)) {
+ kfree(txq_info->tid_qid_rr);
kfree(txq_info->uldtxq);
kfree(txq_info);
return -ENOMEM;
@@ -601,6 +628,7 @@ static void uld_init(struct adapter *adap, struct cxgb4_lld_info *lld)
lld->mtus = adap->params.mtus;
lld->nchan = adap->params.nports;
lld->nports = adap->params.nports;
+ lld->num_up_cores = adap->params.num_up_cores;
lld->wr_cred = adap->params.ofldq_wr_cred;
lld->crypto = adap->params.crypto;
lld->iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
@@ -783,6 +811,74 @@ void cxgb4_uld_enable(struct adapter *adap)
mutex_unlock(&uld_mutex);
}
+/**
+ * cxgb4_uld_tid_ctrlq_id_sel_update - select the control queue for a TID
+ * @dev: net device of the adapter
+ * @tid: TID the work requests will carry
+ * @ctrlq_index: in: any control queue index of the port, normally the base
+ * index port * num_up_cores; out: the port's control queue in
+ * the uP core group owning @tid. Calling it again on the result
+ * is harmless.
+ *
+ * Work requests carrying a TID must be sent on a control queue of the
+ * core group owning the TID. Without TID based queue selection the index
+ * is left unchanged.
+ */
+void cxgb4_uld_tid_ctrlq_id_sel_update(struct net_device *dev, u32 tid,
+ u16 *ctrlq_index)
+{
+ struct adapter *adap = netdev2adap(dev);
+
+ if (!adap->params.tid_qid_sel_mask)
+ return;
+
+ *ctrlq_index = cxgb4_tid_ctrlq_idx(adap,
+ *ctrlq_index / adap->params.num_up_cores,
+ tid);
+}
+EXPORT_SYMBOL(cxgb4_uld_tid_ctrlq_id_sel_update);
+
+/**
+ * cxgb4_uld_tid_qid_sel_update - select the offload Tx queue for a TID
+ * @dev: net device of the adapter
+ * @uld: ULD type
+ * @tid: TID the work requests will carry
+ * @qid: in: an index into the ULD offload Tx queue array of the port;
+ * out: the index of a queue of the port in the uP core group owning
+ * @tid. This is an index into the uldtxq[] array, as used by
+ * cxgb4_ofld_send(), not a hardware queue context id.
+ *
+ * The queues of a port in the TID's core group are used round robin.
+ * Without TID based queue selection the index is left unchanged.
+ */
+void cxgb4_uld_tid_qid_sel_update(struct net_device *dev, enum cxgb4_uld uld,
+ u32 tid, u16 *qid)
+{
+ struct adapter *adap = netdev2adap(dev);
+ struct sge_uld_txq_info *txq_info;
+ unsigned int ngroups, per_port, port, group, n;
+
+ if (!adap->params.tid_qid_sel_mask)
+ return;
+
+ txq_info = adap->sge.uld_txq_info[TX_ULD(uld)];
+ if (!txq_info || !txq_info->tid_qid_rr)
+ return;
+
+ ngroups = cxgb4_tid_qid_ngroups(adap);
+ per_port = txq_info->ntxq / adap->params.nports;
+ port = *qid / per_port;
+ if (WARN_ON_ONCE(port >= adap->params.nports))
+ port = 0;
+ group = cxgb4_tid_qid_group(adap, tid);
+
+ /* Queue i of a port is in group i % ngroups, see alloc_sge_txq_uld() */
+ n = atomic_inc_return(&txq_info->tid_qid_rr[port * ngroups + group]);
+ n %= DIV_ROUND_UP(per_port - group, ngroups);
+ *qid = port * per_port + group + n * ngroups;
+}
+EXPORT_SYMBOL(cxgb4_uld_tid_qid_sel_update);
+
/* cxgb4_register_uld - register an upper-layer driver
* @type: the ULD type
* @p: the ULD methods
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
index d7713038386c..fd48886603d7 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
@@ -433,6 +433,7 @@ struct cxgb4_lld_info {
unsigned short nciq; /* # of concentrator IQ */
unsigned char nchan:4; /* # of channels */
unsigned char nports:4; /* # of ports */
+ u8 num_up_cores; /* # of control queues per port */
unsigned char wr_cred; /* WR 16-byte credits */
unsigned char adapter_type; /* type of adapter */
unsigned char fw_api_ver; /* FW API version */
@@ -500,6 +501,10 @@ struct cxgb4_uld_info {
void cxgb4_uld_enable(struct adapter *adap);
void cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
int cxgb4_unregister_uld(enum cxgb4_uld type);
+void cxgb4_uld_tid_ctrlq_id_sel_update(struct net_device *dev, u32 tid,
+ u16 *ctrlq_index);
+void cxgb4_uld_tid_qid_sel_update(struct net_device *dev, enum cxgb4_uld uld,
+ u32 tid, u16 *qid);
int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb);
int cxgb4_immdata_send(struct net_device *dev, unsigned int idx,
const void *src, unsigned int len);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index cd151696b82c..fa7e822b43f7 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -4778,7 +4778,8 @@ int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
}
static int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_txq *q,
- struct net_device *dev, u32 cmd, u32 iqid)
+ struct net_device *dev, u32 cmd, u32 iqid,
+ u8 group)
{
unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
struct port_info *pi = netdev_priv(dev);
@@ -4806,7 +4807,8 @@ static int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_txq *q,
FW_EQ_OFLD_CMD_PFN_V(adap->pf) |
FW_EQ_OFLD_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F |
- FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c));
+ FW_EQ_OFLD_CMD_EQSTART_F |
+ FW_EQ_OFLD_CMD_COREGROUP_V(group) | FW_LEN16(c));
c.fetchszm_to_iqid =
htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) |
@@ -4835,7 +4837,7 @@ static int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_txq *q,
int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
struct net_device *dev, unsigned int iqid,
- unsigned int uld_type)
+ unsigned int uld_type, u8 group)
{
u32 cmd = FW_EQ_OFLD_CMD;
int ret;
@@ -4843,7 +4845,7 @@ int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
if (unlikely(uld_type == CXGB4_TX_CRYPTO))
cmd = FW_EQ_CTRL_CMD;
- ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, cmd, iqid);
+ ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, cmd, iqid, group);
if (ret)
return ret;
@@ -4852,6 +4854,7 @@ int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
skb_queue_head_init(&txq->sendq);
tasklet_setup(&txq->qresume_tsk, restart_ofldq);
txq->full = 0;
+ txq->tid_qid_group_id = group;
txq->mapping_err = 0;
return 0;
}
@@ -4861,7 +4864,8 @@ int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
{
int ret;
- ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, FW_EQ_OFLD_CMD, iqid);
+ ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, FW_EQ_OFLD_CMD, iqid,
+ 0);
if (ret)
return ret;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index 7bd0c0d8a73c..778b2341e74a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -1346,6 +1346,7 @@ enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31,
+ FW_PARAMS_PARAM_DEV_TID_QID_SEL_MASK = 0x33,
};
/*
@@ -2139,6 +2140,10 @@ struct fw_eq_ofld_cmd {
#define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
#define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U)
+#define FW_EQ_OFLD_CMD_COREGROUP_S 16
+#define FW_EQ_OFLD_CMD_COREGROUP_M 0x3f
+#define FW_EQ_OFLD_CMD_COREGROUP_V(x) ((x) << FW_EQ_OFLD_CMD_COREGROUP_S)
+
#define FW_EQ_OFLD_CMD_EQSTOP_S 27
#define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
#define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U)
--
2.39.1
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