Re: [PATCH net-next v11 03/13] dt-bindings: dpll: add SiTime SiT95316 clock generator

[Ali Rouhi <arouhi@sitime.com>]

On Mon, 5 Oct 2026, netdev-bot+sashiko@kernel.org wrote:

Reply inline.

> [Severity: Low]
> This isn't a bug, but should the binding describe the chip's power
> supplies here? For example a core VDD supply and the per-bank VDDO
> output supplies.
>
> The schema ends with:
>
>     unevaluatedProperties: false
>
> With that, a board that adds a *-supply property to the dpll node fails
> dt_binding_check. A board that powers the part from switchable regulators
> then has no valid way to describe those rails.

Right, the schema described none and refused any.

v12 describes them by their pin names: vdd-supply for the PLL core
rail, vddin-supply for the input receivers and dividers, vdds-supply
for the GPIO rail the SiT95317 has, and one per output-driver pin --
vddo0 to vddo7 on the SiT95317, numbered as its datasheet numbers the
outputs, and vddo0_1, vddo2 to vddo9 and vddo10_11 on the SiT95316,
the two shared pins each powering the pair of outputs they are named
after. The variant conditional refuses the names the other part does
not have.

> The supply names were not checked against the SiTime datasheet. Any
> supply properties added should use the chip's actual VDD/VDDO pin
> names.

They are the pin names in the datasheets for both parts.

The driver does not enable them. The SiT95317 datasheet states that
there is no power supply sequencing requirement for VDD, VDDIN and
VDDO, so a board that powers the part permanently needs nothing from
the driver. The binding now gives a board with switchable rails a way
to describe them.