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From: Ali Rouhi <arouhi@sitime.com>
To: "netdev-bot+sashiko@kernel.org" <netdev-bot+sashiko@kernel.org>
Cc: Jiri Pirko <jiri@resnulli.us>,
	Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Ivan Vecera <ivecera@redhat.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Carolina Jubran <cjubran@nvidia.com>,
	Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next v11 04/13] dpll: add basic SiTime SiT9531x support
Date: Fri, 9 Oct 2026 18:23:25 +0000	[thread overview]
Message-ID: <20261009182323.76166-2-arouhi@sitime.com> (raw)
In-Reply-To: <179116259637.434549.13673583471206119318@kernel.org>

On Mon, 5 Oct 2026, netdev-bot+sashiko@kernel.org wrote:

Reply inline.

> [Severity: Medium]
> Does dropping the cache entry on error keep the cached page selector in
> sync with the chip? The comment above sit9531x_volatile_reg() says it
> does, but some paths seem to be missed.

The entry is dropped on every error path the driver controls:
sit9531x_read_u8(), sit9531x_write_u8() and sit9531x_update_pll_u8()
all call sit9531x_page_cache_drop() when regmap returns an error, and
sit9531x_resume() drops it before the first access after a sleep. That
covers the SMBus byte-data case: the failed selector write returns
through one of those three, and the next access re-selects the page.

> If the failed selector write happens inside a debugfs read, nothing
> drops the entry at all. Can the next sit9531x_write_u8() to page N then
> land on page P without any error?

It can, and that window stays. It is not a path the driver takes: the
regmap debugfs registers file is a developer interface that bypasses
every driver on every regmap.

> A later patch in the series drops the entry on resume. Nothing covers a
> reset the driver cannot see, though. After one, could writes meant for
> the PLL pages 0x0A-0x0D go to page 0 instead?

Yes, until the next access that fails or the next resume. Dropping the
entry at the top of each poll tick would bound that window to one poll
period at the cost of one selector write per tick. It is a reasonable
addition and is noted for a later revision rather than folded into this
one.

> Would it be simpler to make SIT9531X_PAGE_SEL volatile as well?

SIT9531X_PAGE_SEL is the one register sit9531x_volatile_reg() reports
as non-volatile, so it is the only cached register in the map. Marking
it volatile makes the _regmap_update_bits() in _regmap_select_page()
read the selector from the bus before every access rather than from the
cache, which adds a transfer to each access instead of removing one.
The driver's own paths are already covered, so that cost would buy only
the two windows above.

  reply	other threads:[~2026-10-09 18:23 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-30 23:37 [PATCH net-next v11 00/13] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 01/13] dt-bindings: dpll: allow hex unit addresses on output pins Ali Rouhi
2026-10-02  8:32   ` Krzysztof Kozlowski
2026-09-30 23:37 ` [PATCH net-next v11 02/13] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 03/13] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-10-05  1:09   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-10-06  3:22   ` Rob Herring (Arm)
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 04/13] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-10-05  1:09   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi [this message]
2026-09-30 23:37 ` [PATCH net-next v11 05/13] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
2026-10-05  1:09   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 06/13] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
2026-10-05  1:09   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 07/13] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-10-05  1:10   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 08/13] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-10-05  1:10   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 10/13] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-10-05  1:10   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 09/13] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
2026-10-05  1:10   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 11/13] dpll: sit9531x: add support to adjust output phase Ali Rouhi
2026-10-05  1:10   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 12/13] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
2026-10-05  1:10   ` netdev-bot+sashiko
2026-10-09 18:23     ` Ali Rouhi
2026-09-30 23:37 ` [PATCH net-next v11 13/13] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi
2026-10-05  1:10   ` netdev-bot+sashiko
2026-10-07  2:10 ` [PATCH net-next v11 00/13] dpll: add SiTime SiT9531x DPLL clock driver patchwork-bot+netdevbpf

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