From: Ali Rouhi <arouhi@sitime.com>
To: "robh@kernel.org" <robh@kernel.org>
Cc: Jiri Pirko <jiri@resnulli.us>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Ivan Vecera <ivecera@redhat.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Carolina Jubran <cjubran@nvidia.com>,
Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator
Date: Fri, 16 Oct 2026 00:55:06 +0000 [thread overview]
Message-ID: <20261016005505.10602-1-arouhi@sitime.com> (raw)
In-Reply-To: <20261015033143.GA485921-robh@kernel.org>
On Wed, 14 Oct 2026, Rob Herring wrote:
> > + supported-frequencies-hz = /bits/ 64 <10000000>;
>
> -hz is 32-bit.
Fixed in v14: the examples give the rates as 32-bit cells and the
driver reads the property with the u32 helpers. Every rate the part
accepts fits in 32 bits.
With the width right, the input pins' list also takes the maxItems: 1
that its single-entry description had promised, which the Sashiko
review asked for on the same patch. At 64 bits each rate decoded as
two cells and the constraint failed on the example itself.
Separate from this patch: microchip,zl30731.yaml writes the same
property /bits/ 64 in its examples and zl3073x reads it with
fwnode_property_read_u64_array(). dpll-pin.yaml gives the property no
type, so the -hz default applies there as well, and those examples
encode each rate as two cells.
pw-bot: cr
next prev parent reply other threads:[~2026-10-16 0:55 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 22:41 [PATCH net-next v13 00/12] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 01/12] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-10-15 3:31 ` Rob Herring
2026-10-16 0:55 ` Ali Rouhi [this message]
[not found] ` <sashiko-outbox-171992@kernel.org>
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 03/12] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 04/12] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
[not found] ` <sashiko-outbox-171991@kernel.org>
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 06/12] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 05/12] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
[not found] ` <sashiko-outbox-171990@kernel.org>
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 07/12] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 08/12] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
[not found] ` <sashiko-outbox-171996@kernel.org>
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 09/12] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 10/12] dpll: sit9531x: add support to adjust output phase Ali Rouhi
[not found] ` <sashiko-outbox-171998@kernel.org>
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 11/12] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 12/12] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi
[not found] ` <sashiko-outbox-172000@kernel.org>
2026-10-16 0:55 ` Ali Rouhi
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