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* [PATCH] mlxsw: pci: drain EQ tasklet during teardown
@ 2026-10-18  4:06 Jiale Yao
  2026-10-18  4:13 ` netdev-bot+sinfo
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Jiale Yao @ 2026-10-18  4:06 UTC (permalink / raw)
  To: Ido Schimmel, Petr Machata, Andrew Lunn, David S. Miller,
	Eric Dumazet, Jakub Kicinski, Paolo Abeni, Jiri Pirko, Elad Raz,
	Scott Feldman, netdev, linux-kernel
  Cc: Jiale Yao

The EQ interrupt handler only schedules a tasklet. free_irq() prevents
another interrupt handler from running, but it does not drain a tasklet
that was queued before the IRQ was released.

The pending tasklet can access the EQ DMA buffer and queue array after
mlxsw_pci_aqs_fini() releases them. Kill it after freeing the IRQ and
before tearing down the asynchronous queues.

Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation")
Signed-off-by: Jiale Yao <yaojiale02@163.com>
---
 drivers/net/ethernet/mellanox/mlxsw/pci.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
index bfe3268dfdc1..ba66142ae333 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
@@ -2085,8 +2085,11 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
 static void mlxsw_pci_fini(void *bus_priv)
 {
 	struct mlxsw_pci *mlxsw_pci = bus_priv;
+	struct mlxsw_pci_queue *q;
 
 	free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
+	q = mlxsw_pci_eq_get(mlxsw_pci);
+	tasklet_kill(&q->u.eq.tasklet);
 	mlxsw_pci_aqs_fini(mlxsw_pci);
 	mlxsw_pci_napi_devs_fini(mlxsw_pci);
 	mlxsw_pci_fw_area_fini(mlxsw_pci);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH] mlxsw: pci: drain EQ tasklet during teardown
  2026-10-18  4:06 [PATCH] mlxsw: pci: drain EQ tasklet during teardown Jiale Yao
@ 2026-10-18  4:13 ` netdev-bot+sinfo
  2026-10-18 15:32 ` Ido Schimmel
  2026-10-19  4:09 ` netdev-bot+sashiko
  2 siblings, 0 replies; 4+ messages in thread
From: netdev-bot+sinfo @ 2026-10-18  4:13 UTC (permalink / raw)
  To: Jiale Yao
  Cc: Ido Schimmel, Petr Machata, Andrew Lunn, David S. Miller,
	Eric Dumazet, Jakub Kicinski, Paolo Abeni, Jiri Pirko, Elad Raz,
	Scott Feldman, netdev, linux-kernel

Hi!

This is an automated message. This series looks like a fix, but its
commit messages seem to be missing some information:

 - How the issue was discovered, e.g. hit in production, hit during
   development, syzbot report, manual code inspection, LLM or static
   analysis tool scan.

 - Whether the issue was actually triggered, or is only theoretical
   (e.g. found by code inspection). If it was triggered please include
   the symptoms, like the stack trace or error messages.

 - What hardware the change was tested on. For driver fixes please
   mention the device (and if relevant firmware version) used for
   testing, or say that the change was not tested on real hardware.

Please do not repost the series just to address the above. Instead,
reply to this email with the missing information, so that reviewers
can take it into account. If the series needs another revision for
other reasons, please include the information in the commit messages
then.

The evaluation is done by an LLM so it may be wrong, if you think
that is the case please reply and explain.

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] mlxsw: pci: drain EQ tasklet during teardown
  2026-10-18  4:06 [PATCH] mlxsw: pci: drain EQ tasklet during teardown Jiale Yao
  2026-10-18  4:13 ` netdev-bot+sinfo
@ 2026-10-18 15:32 ` Ido Schimmel
  2026-10-19  4:09 ` netdev-bot+sashiko
  2 siblings, 0 replies; 4+ messages in thread
From: Ido Schimmel @ 2026-10-18 15:32 UTC (permalink / raw)
  To: Jiale Yao, petrm
  Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Jiri Pirko, Elad Raz, Scott Feldman, netdev,
	linux-kernel

On Sun, Oct 18, 2026 at 12:06:53PM +0800, Jiale Yao wrote:
> The EQ interrupt handler only schedules a tasklet. free_irq() prevents
> another interrupt handler from running, but it does not drain a tasklet
> that was queued before the IRQ was released.
> 
> The pending tasklet can access the EQ DMA buffer and queue array after
> mlxsw_pci_aqs_fini() releases them. Kill it after freeing the IRQ and
> before tearing down the asynchronous queues.
> 
> Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation")
> Signed-off-by: Jiale Yao <yaojiale02@163.com>
> ---
>  drivers/net/ethernet/mellanox/mlxsw/pci.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
> index bfe3268dfdc1..ba66142ae333 100644
> --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
> +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
> @@ -2085,8 +2085,11 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
>  static void mlxsw_pci_fini(void *bus_priv)
>  {
>  	struct mlxsw_pci *mlxsw_pci = bus_priv;
> +	struct mlxsw_pci_queue *q;
>  
>  	free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
> +	q = mlxsw_pci_eq_get(mlxsw_pci);
> +	tasklet_kill(&q->u.eq.tasklet);
>  	mlxsw_pci_aqs_fini(mlxsw_pci);
>  	mlxsw_pci_napi_devs_fini(mlxsw_pci);
>  	mlxsw_pci_fw_area_fini(mlxsw_pci);

Petr already looked into this [1]. Petr, please send your version when
net-next opens for 7.5.

[1] https://lore.kernel.org/netdev/875x2788ac.fsf@nvidia.com/

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] mlxsw: pci: drain EQ tasklet during teardown
  2026-10-18  4:06 [PATCH] mlxsw: pci: drain EQ tasklet during teardown Jiale Yao
  2026-10-18  4:13 ` netdev-bot+sinfo
  2026-10-18 15:32 ` Ido Schimmel
@ 2026-10-19  4:09 ` netdev-bot+sashiko
  2 siblings, 0 replies; 4+ messages in thread
From: netdev-bot+sashiko @ 2026-10-19  4:09 UTC (permalink / raw)
  To: yaojiale02
  Cc: idosch, petrm, andrew+netdev, davem, edumazet, kuba, pabeni, jiri,
	eladr, sfeldma, netdev, linux-kernel

Thank you for your contribution! Sashiko AI review found 1 potential
issue(s) to consider.

Critical: 0 · High: 1 (1) · Medium: 0 · Low: 0

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [High] The patch drains only the first stage of the deferred EQ chain
  (IRQ -> tasklet).

Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but the patch adds
  another unconditional EQ dereference to the path it affects.

--

mlxsw: pci: drain EQ tasklet during teardown

This patch adds a tasklet_kill() for the EQ tasklet in mlxsw_pci_fini(),
after free_irq() and before mlxsw_pci_aqs_fini(). The goal is to stop a
tasklet that was queued before the IRQ was released from touching the EQ
DMA buffer and queue array after they are freed.

> diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
> index bfe3268dfdc17..ba66142ae333c 100644
> --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
> +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
> @@ -2085,8 +2085,11 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
>  static void mlxsw_pci_fini(void *bus_priv)
>  {
>  	struct mlxsw_pci *mlxsw_pci = bus_priv;
> +	struct mlxsw_pci_queue *q;
>  
>  	free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
> +	q = mlxsw_pci_eq_get(mlxsw_pci);
> +	tasklet_kill(&q->u.eq.tasklet);

[Severity: High]
Does this fully close the teardown race the commit message describes?

tasklet_kill() waits for TASKLET_STATE_SCHED to clear. So a tasklet that
was pending when free_irq() ran will run to completion. At the end,
mlxsw_pci_eq_tasklet() schedules NAPI for each CQ that saw an event:

drivers/net/ethernet/mellanox/mlxsw/pci.c:mlxsw_pci_eq_tasklet() {
    ...
	cq_count = mlxsw_pci->num_cqs;
	for_each_set_bit(cqn, active_cqns, cq_count) {
		q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
		napi_schedule(&q->u.cq.napi);
	}
}

Nothing waits for those polls. The RX NAPI device is threaded, see
netif_threaded_enable(mlxsw_pci->napi_dev_rx) in
mlxsw_pci_napi_devs_init(). Its poll runs in a kthread and can run well
after tasklet_kill() returns.

mlxsw_pci_aqs_fini() frees the RDQ group first, then the SDQ group, and
the CQ group last:

	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);

The RDQ teardown frees memory in three places:

  - mlxsw_pci_rdq_fini() frees the RX pages
  - mlxsw_pci_queue_fini() frees elem_info and the DMA ring
  - mlxsw_pci_queue_group_fini() frees the queue structs

The only napi_disable() is in mlxsw_pci_cq_fini(), and that runs after
all of this.

A concurrent mlxsw_pci_napi_poll_cq_rx() can still be using the RDQ:

	struct mlxsw_pci_queue *rdq = q->u.cq.dq;
	...
		if (unlikely(dqn != rdq->num)) {
	...
		mlxsw_pci_cqe_rdq_handle(mlxsw_pci, napi, rdq,
					 wqe_counter, q->u.cq.v, cqe);
	...
	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, rdq);

The producer doorbell ring runs on every poll, even when there are no
CQEs. mlxsw_pci_napi_poll_cq_tx() uses sdq = q->u.cq.dq the same way.

Could this cause a use-after-free of the RDQ/SDQ structs, their elem_info
arrays and the RX pages?

Besides killing the tasklet, should the CQ NAPI instances be quiesced
(napi_disable() or napi_synchronize()) before the RDQ/SDQ groups are
freed?

[Severity: High]
This is a pre-existing issue, but this patch adds another unconditional
EQ dereference on a path that can run with no queues set up.

In mlxsw_pci_init(), the unsupported CQE version branch jumps to the
unwind path without setting err:

	} else {
		dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
		goto err_cqe_v_check;
	}

At that point err is still 0 from the earlier successful
mlxsw_core_resources_query(). The unwind runs mlxsw_pci_fw_area_fini()
and mlxsw_pci_free_irq_vectors(), then returns 0.

So __mlxsw_core_bus_device_register() treats bus init as successful. No
napi devs, async queues or IRQ were set up.

Suppose a later registration step fails, for example registering
resources or mlxsw_ports_init(). The unwind then calls the bus fini:

err_register_resources:
	mlxsw_bus->fini(bus_priv);

mlxsw_pci_fini() then calls free_irq() on an IRQ that was never
requested. With this patch, mlxsw_pci_eq_get() returns an address derived
from a NULL queues[].q array (or a stale freed one after a reload), and
tasklet_kill() dereferences it.

Before this patch, the same path already oopsed in
mlxsw_pci_napi_devs_fini()->free_netdev(NULL). mlxsw_pci_fw_area_fini()
also runs a second time, so the fw_area items get freed twice.

Should the CQE version check set err = -EINVAL before the goto? The
missing assignment seems to date back to commit 8404f6f2e8ed.

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261018040653.534066-1-yaojiale02%40163.com

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2026-10-19  4:09 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2026-10-18  4:06 [PATCH] mlxsw: pci: drain EQ tasklet during teardown Jiale Yao
2026-10-18  4:13 ` netdev-bot+sinfo
2026-10-18 15:32 ` Ido Schimmel
2026-10-19  4:09 ` netdev-bot+sashiko

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