From: Petr Oros <poros@redhat.com>
To: netdev@vger.kernel.org
Cc: Petr Oros <poros@redhat.com>, Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>,
Randy Dunlap <rdunlap@infradead.org>,
Jani Nikula <jani.nikula@intel.com>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Jiri Pirko <jiri@resnulli.us>, Ivan Vecera <ivecera@redhat.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: [PATCH net-next v2 09/14] dpll: dpllsim: Add support to set frequency on pins
Date: Thu, 5 Nov 2026 16:18:47 +0100 [thread overview]
Message-ID: <20261105151852.1844305-10-poros@redhat.com> (raw)
In-Reply-To: <20261105151852.1844305-1-poros@redhat.com>
Add support to set the frequency of input and output pins. The DPLL
core validates the requested value against the supported frequency
list the pin advertises, so the frequency_set callback only has to
store it. The same per type tables that validate the configured
frequency at live time serve as the supported list. The configfs
attribute is rejected with EBUSY while the device is live, so only the
netlink setter changes the frequency of a registered pin and the two
cannot race.
Signed-off-by: Petr Oros <poros@redhat.com>
---
drivers/dpll/dpllsim/dpll.c | 15 +++++++++++++++
drivers/dpll/dpllsim/dpllsim.h | 4 ++--
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/dpll/dpllsim/dpll.c b/drivers/dpll/dpllsim/dpll.c
index 8a302c2537c880..3caccd38a7e74a 100644
--- a/drivers/dpll/dpllsim/dpll.c
+++ b/drivers/dpll/dpllsim/dpll.c
@@ -79,6 +79,19 @@ static int dpllsim_pin_frequency_get(const struct dpll_pin *pin,
return 0;
}
+static int dpllsim_pin_frequency_set(const struct dpll_pin *pin,
+ void *pin_priv,
+ const struct dpll_device *dpll,
+ void *dpll_priv, u64 frequency,
+ struct netlink_ext_ack *extack)
+{
+ struct dpllsim_pin *sim_pin = pin_priv;
+
+ guard(mutex)(&sim_pin->dev->lock);
+ sim_pin->frequency = frequency;
+ return 0;
+}
+
static int dpllsim_pin_direction_get(const struct dpll_pin *pin,
void *pin_priv,
const struct dpll_device *dpll,
@@ -148,6 +161,7 @@ static int dpllsim_pin_prio_set(const struct dpll_pin *pin, void *pin_priv,
static const struct dpll_pin_ops dpllsim_input_pin_ops = {
.frequency_get = dpllsim_pin_frequency_get,
+ .frequency_set = dpllsim_pin_frequency_set,
.direction_get = dpllsim_pin_direction_get,
.state_on_dpll_get = dpllsim_pin_state_get,
.state_on_dpll_set = dpllsim_pin_state_set,
@@ -157,6 +171,7 @@ static const struct dpll_pin_ops dpllsim_input_pin_ops = {
static const struct dpll_pin_ops dpllsim_output_pin_ops = {
.frequency_get = dpllsim_pin_frequency_get,
+ .frequency_set = dpllsim_pin_frequency_set,
.direction_get = dpllsim_pin_direction_get,
.state_on_dpll_get = dpllsim_pin_state_get,
};
diff --git a/drivers/dpll/dpllsim/dpllsim.h b/drivers/dpll/dpllsim/dpllsim.h
index f9fced337dc881..f59447d26a8668 100644
--- a/drivers/dpll/dpllsim/dpllsim.h
+++ b/drivers/dpll/dpllsim/dpllsim.h
@@ -26,8 +26,8 @@ struct dpllsim_pin {
/*
* Configuration, set through configfs only until
- * dpllsim_dev_frozen(). The netlink prio setter changes prio at
- * runtime under dev->lock.
+ * dpllsim_dev_frozen(). The netlink setters change prio and
+ * frequency at runtime under dev->lock.
*/
enum dpll_pin_type type;
enum dpll_pin_direction direction;
--
2.56.0
next prev parent reply other threads:[~2026-11-05 15:19 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 15:18 [PATCH net-next v2 00/14] dpll: add a simulated DPLL device driver Petr Oros
2026-11-05 15:18 ` [PATCH net-next v2 01/14] dpll: dpllsim: Add " Petr Oros
2026-11-06 10:47 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 02/14] selftests: dpll: add test library and device lifecycle tests Petr Oros
2026-11-06 10:48 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 03/14] dpll: dpllsim: Add configurable pins Petr Oros
2026-11-06 10:48 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 04/14] selftests: dpll: add pin enumeration and property tests Petr Oros
2026-11-06 10:48 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 05/14] dpll: dpllsim: Add support to set input pin state Petr Oros
2026-11-06 10:41 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 06/14] selftests: dpll: add pin state tests Petr Oros
2026-11-06 10:49 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 07/14] dpll: dpllsim: Add support to get/set priority on input pins Petr Oros
2026-11-06 10:49 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 08/14] selftests: dpll: add pin priority test Petr Oros
2026-11-06 10:50 ` Ivan Vecera
2026-11-05 15:18 ` Petr Oros [this message]
2026-11-06 10:50 ` [PATCH net-next v2 09/14] dpll: dpllsim: Add support to set frequency on pins Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 10/14] selftests: dpll: add pin frequency test Petr Oros
2026-11-06 10:51 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 11/14] dpll: dpllsim: Add support to adjust phase Petr Oros
2026-11-06 10:51 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 12/14] selftests: dpll: add pin phase adjust test Petr Oros
2026-11-06 10:51 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 13/14] selftests: dpll: add concurrency stress tests Petr Oros
2026-11-06 10:52 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 14/14] selftests: dpll: add reference leak tests Petr Oros
2026-11-06 10:47 ` Ivan Vecera
2026-11-06 12:27 ` [PATCH net-next v2 00/14] dpll: add a simulated DPLL device driver Jiri Pirko
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