From: Petr Oros <poros@redhat.com>
To: netdev@vger.kernel.org
Cc: Petr Oros <poros@redhat.com>, Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>,
Randy Dunlap <rdunlap@infradead.org>,
Jani Nikula <jani.nikula@intel.com>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Jiri Pirko <jiri@resnulli.us>, Ivan Vecera <ivecera@redhat.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: [PATCH net-next v2 11/14] dpll: dpllsim: Add support to adjust phase
Date: Thu, 5 Nov 2026 16:18:49 +0100 [thread overview]
Message-ID: <20261105151852.1844305-12-poros@redhat.com> (raw)
In-Reply-To: <20261105151852.1844305-1-poros@redhat.com>
Add support to get and set the phase adjustment of input and output
pins. The pins advertise a granularity of 100 ps and a symmetric range
whose ends are the largest multiples of the granularity that fit a
32-bit signed value, so that the advertised ends themselves are
settable, the core validates the requested value against both and the
driver stores it. The adjustment is reset to zero every time the device
goes live, so that repeated deploy cycles start from a known state. It
becomes the baseline of the simulated phase offset measurements once
those exist.
Signed-off-by: Petr Oros <poros@redhat.com>
---
drivers/dpll/dpllsim/dpll.c | 40 ++++++++++++++++++++++++++++++++++
drivers/dpll/dpllsim/dpllsim.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/dpll/dpllsim/dpll.c b/drivers/dpll/dpllsim/dpll.c
index 3caccd38a7e74a..77e7ae994bf104 100644
--- a/drivers/dpll/dpllsim/dpll.c
+++ b/drivers/dpll/dpllsim/dpll.c
@@ -12,6 +12,11 @@
#include "dpllsim.h"
+#define DPLLSIM_PHASE_ADJUST_GRAN 100 /* ps */
+/* Largest multiple of the granularity, so the range ends are settable */
+#define DPLLSIM_PHASE_ADJUST_MAX \
+ (S32_MAX - S32_MAX % DPLLSIM_PHASE_ADJUST_GRAN)
+
static struct dpll_pin_frequency dpllsim_freq_1pps[] = {
DPLL_PIN_FREQUENCY_RANGE(1, 1),
};
@@ -159,6 +164,33 @@ static int dpllsim_pin_prio_set(const struct dpll_pin *pin, void *pin_priv,
return 0;
}
+static int dpllsim_pin_phase_adjust_get(const struct dpll_pin *pin,
+ void *pin_priv,
+ const struct dpll_device *dpll,
+ void *dpll_priv, s32 *phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ struct dpllsim_pin *sim_pin = pin_priv;
+
+ guard(mutex)(&sim_pin->dev->lock);
+ *phase_adjust = sim_pin->phase_adjust;
+ return 0;
+}
+
+static int dpllsim_pin_phase_adjust_set(const struct dpll_pin *pin,
+ void *pin_priv,
+ const struct dpll_device *dpll,
+ void *dpll_priv,
+ const s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ struct dpllsim_pin *sim_pin = pin_priv;
+
+ guard(mutex)(&sim_pin->dev->lock);
+ sim_pin->phase_adjust = phase_adjust;
+ return 0;
+}
+
static const struct dpll_pin_ops dpllsim_input_pin_ops = {
.frequency_get = dpllsim_pin_frequency_get,
.frequency_set = dpllsim_pin_frequency_set,
@@ -167,6 +199,8 @@ static const struct dpll_pin_ops dpllsim_input_pin_ops = {
.state_on_dpll_set = dpllsim_pin_state_set,
.prio_get = dpllsim_pin_prio_get,
.prio_set = dpllsim_pin_prio_set,
+ .phase_adjust_get = dpllsim_pin_phase_adjust_get,
+ .phase_adjust_set = dpllsim_pin_phase_adjust_set,
};
static const struct dpll_pin_ops dpllsim_output_pin_ops = {
@@ -174,6 +208,8 @@ static const struct dpll_pin_ops dpllsim_output_pin_ops = {
.frequency_set = dpllsim_pin_frequency_set,
.direction_get = dpllsim_pin_direction_get,
.state_on_dpll_get = dpllsim_pin_state_get,
+ .phase_adjust_get = dpllsim_pin_phase_adjust_get,
+ .phase_adjust_set = dpllsim_pin_phase_adjust_set,
};
static const struct dpll_pin_ops *
@@ -189,6 +225,9 @@ static void dpllsim_pin_props(struct dpllsim_pin *pin,
{
prop->type = pin->type;
prop->board_label = config_item_name(&pin->item);
+ prop->phase_range.min = -DPLLSIM_PHASE_ADJUST_MAX;
+ prop->phase_range.max = DPLLSIM_PHASE_ADJUST_MAX;
+ prop->phase_gran = DPLLSIM_PHASE_ADJUST_GRAN;
switch (pin->type) {
case DPLL_PIN_TYPE_GNSS:
@@ -250,6 +289,7 @@ static void dpllsim_pin_reset(struct dpllsim_pin *pin)
{
pin->ops = dpllsim_pin_select_ops(pin);
pin->state = DPLL_PIN_STATE_DISCONNECTED;
+ pin->phase_adjust = 0;
}
/* Build sim->pins in registration order, the order the pins were created */
diff --git a/drivers/dpll/dpllsim/dpllsim.h b/drivers/dpll/dpllsim/dpllsim.h
index f59447d26a8668..886ac27f5f92d6 100644
--- a/drivers/dpll/dpllsim/dpllsim.h
+++ b/drivers/dpll/dpllsim/dpllsim.h
@@ -43,6 +43,7 @@ struct dpllsim_pin {
/* Simulated state, guarded by dev->lock */
enum dpll_pin_state state;
+ s32 phase_adjust;
};
struct dpllsim_dev {
--
2.56.0
next prev parent reply other threads:[~2026-11-05 15:20 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 15:18 [PATCH net-next v2 00/14] dpll: add a simulated DPLL device driver Petr Oros
2026-11-05 15:18 ` [PATCH net-next v2 01/14] dpll: dpllsim: Add " Petr Oros
2026-11-06 10:47 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 02/14] selftests: dpll: add test library and device lifecycle tests Petr Oros
2026-11-06 10:48 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 03/14] dpll: dpllsim: Add configurable pins Petr Oros
2026-11-06 10:48 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 04/14] selftests: dpll: add pin enumeration and property tests Petr Oros
2026-11-06 10:48 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 05/14] dpll: dpllsim: Add support to set input pin state Petr Oros
2026-11-06 10:41 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 06/14] selftests: dpll: add pin state tests Petr Oros
2026-11-06 10:49 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 07/14] dpll: dpllsim: Add support to get/set priority on input pins Petr Oros
2026-11-06 10:49 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 08/14] selftests: dpll: add pin priority test Petr Oros
2026-11-06 10:50 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 09/14] dpll: dpllsim: Add support to set frequency on pins Petr Oros
2026-11-06 10:50 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 10/14] selftests: dpll: add pin frequency test Petr Oros
2026-11-06 10:51 ` Ivan Vecera
2026-11-05 15:18 ` Petr Oros [this message]
2026-11-06 10:51 ` [PATCH net-next v2 11/14] dpll: dpllsim: Add support to adjust phase Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 12/14] selftests: dpll: add pin phase adjust test Petr Oros
2026-11-06 10:51 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 13/14] selftests: dpll: add concurrency stress tests Petr Oros
2026-11-06 10:52 ` Ivan Vecera
2026-11-05 15:18 ` [PATCH net-next v2 14/14] selftests: dpll: add reference leak tests Petr Oros
2026-11-06 10:47 ` Ivan Vecera
2026-11-06 12:27 ` [PATCH net-next v2 00/14] dpll: add a simulated DPLL device driver Jiri Pirko
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