Re: BCM4908 Ethernet and 2.5G WAN: upstreaming plan and two questions

["Kordian Chmielewski (mlody1212)" <kudzo51@gmail.com>]

Three corrections to my mail above and my later correction.

The AX11000 has three BCM43684 radios, not two; I mixed it up with the
AX6000.

I should not have written that the SoC SerDes gives the BCM54991E a
50 MHz clock. I took the 50 MHz from a comment in Broadcom's SerDes
setup code, read it as the PHY's clock and did not test it. I have
tested it now: with the SerDes held in IDDQ, PWRDWN and RESETPLL, the
PHY answers MDIO right after its enable GPIO goes high, takes its
firmware over MDIO and starts its CPU, and a running PHY keeps its
link. So MDIO needs the enable GPIO, not the SerDes. The SerDes status
still showed PLL lock, so I can't say the PLL itself stopped.

And, unlike what I wrote in my earlier correction, the BCM54991E does
not set MDIO_READ_FAIL on good Clause 45 reads: with a counter on the
bit, 11640 reads, none with it set. My note was older than the fix that
made the PHY answer at all.

Kordian