From: Andrew Lunn <andrew@lunn.ch>
To: Coia Prant <coiaprant@gmail.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Romain Gantois <romain.gantois@bootlin.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Russell King <linux@armlinux.org.uk>,
Shawn Lin <shawn.lin@rock-chips.com>,
David Heidelberg <david@ixit.cz>,
netdev@vger.kernel.org, linux-rockchip@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v2 07/10] net: pcs: xpcs: add Rockchip RK3568 platform glue driver
Date: Sun, 2 Aug 2026 16:39:46 +0200 [thread overview]
Message-ID: <302c67b0-6729-4930-a409-a2408dde33fc@lunn.ch> (raw)
In-Reply-To: <CALj3r0i5yVcJY8V75y0Hm5xjtZSBpH0DXSAWKsAUqguChVcxYA@mail.gmail.com>
On Sun, Aug 02, 2026 at 11:20:27AM +0800, Coia Prant wrote:
> > On Sat, Aug 01, 2026 at 10:22:31PM +0800, Coia Prant wrote:
> > > The XPCS block contains four MII ports (0..3), each of which can be
> > > routed to GMAC0 or GMAC1 via the pcs-handle property in the MAC node.
> > > The hardware maps these ports to different MMDs:
> > > - port 0: MMD 7 (ROCKCHIP_MMD_MII)
> > > - port 1: MMD 2 (ROCKCHIP_MMD_MII1)
> > > - port 2: MMD 3 (ROCKCHIP_MMD_MII2)
> > > - port 3: MMD 4 (ROCKCHIP_MMD_MII3)
> >
> > Why is port 0 called ROCKCHIP_MMD_MII not ROCKCHIP_MMD_MII0 ?
>
> Hi Andrew,
>
> The naming follows the Rockchip TRM. The hardware documentation refers to
> the MMD for the first port as simply "MII" without a numeric suffix, while
> the other ports are named "MII1", "MII2", "MII3". I kept the naming
> consistent with the TRM to make it easier to cross-reference.
>
> As I understand it, this is probably because the MII controls not only
> Port 0, but
> also the entire PCS (these registers are read-only in Ports 1-3 and reflected
> back to the MII).
>
> If you prefer, I can rename it to ROCKCHIP_MMD_MII0 for consistency. Let me
> know and I'll update it in v3.
If the TRM gives it this name, then O.K. It just makes the code look
odd, unbalanced.
> > > +static int xpcs_rk_read_c22(struct mii_bus *bus, int addr, int reg)
> > > +{
> > > + struct dw_xpcs_rk *pxpcs = bus->priv;
> > > + int dev;
> > > +
> > > + if (!xpcs_rk_mdio_addr_validate(addr))
> > > + return -ENODEV;
> > > +
> > > + dev = xpcs_rk_mdio_read_remapping(addr, MDIO_MMD_VEND2, reg);
> >
> > Does this mean C22 registers are mapped into the first 32 of C45
> > MDIO_MMD_VEND2?
>
> Yes, exactly. The C22 register space (reg 0-31) is mapped into the first
> 32 registers of the VEND2 MMD (MMD 7). This is how the hardware is designed
> and matches the standard C22 to C45 address mapping.
Does the xpcs code actually perform any C22 access? A quick look
suggests it is C45 only. xpcs_read() calls mdiodev_c45_read(). If C22
is not needed, i would not provide these functions.
>
> >
> > > +static int xpcs_rk_read_c45(struct mii_bus *bus, int addr, int dev, int reg)
> > > +{
> > > + struct dw_xpcs_rk *pxpcs = bus->priv;
> > > +
> > > + if (!xpcs_rk_mdio_addr_validate(addr))
> > > + return -ENODEV;
> > > +
> > > + dev = xpcs_rk_mdio_read_remapping(addr, dev, reg);
> >
> > Should it be returning an error for dev == MDIO_MMD_VEND2? Or at least
> > if reg < 32?
>
> No, we cannot simply return an error here.
Thanks for the explanation.
Andrew
next prev parent reply other threads:[~2026-08-02 14:40 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 14:22 [PATCH v2 00/10] net-next: add basic support for RK3568 XPCS Coia Prant
2026-08-01 14:22 ` [PATCH v2 01/10] net: stmmac: move XPCS lifetime management to platform drivers Coia Prant
2026-08-01 14:22 ` [PATCH v2 02/10] dt-bindings: phy: rockchip: naneng-combphy: add rockchip,sgmii-mac-sel property Coia Prant
2026-08-01 14:22 ` [PATCH v2 03/10] phy: rockchip: naneng-combphy: add SGMII MAC selection for RK3568 Coia Prant
2026-08-01 20:58 ` Andrew Lunn
2026-08-02 2:51 ` Coia Prant
2026-08-01 14:22 ` [PATCH v2 04/10] dt-bindings: net: pcs: add rockchip,rk3568-xpcs binding Coia Prant
2026-08-01 14:22 ` [PATCH v2 05/10] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Coia Prant
2026-08-01 16:28 ` Heiko Stübner
2026-08-01 19:19 ` Coia Prant
2026-08-01 21:05 ` Andrew Lunn
2026-08-02 3:28 ` Coia Prant
2026-08-02 15:19 ` Andrew Lunn
2026-08-01 14:22 ` [PATCH v2 06/10] net: pcs: xpcs: add ANRESTART support for SGMII link recovery Coia Prant
2026-08-01 21:10 ` Andrew Lunn
2026-08-02 3:11 ` Coia Prant
2026-08-02 14:30 ` Andrew Lunn
2026-08-02 14:59 ` Maxime Chevallier
2026-08-01 14:22 ` [PATCH v2 07/10] net: pcs: xpcs: add Rockchip RK3568 platform glue driver Coia Prant
2026-08-02 1:29 ` Andrew Lunn
2026-08-02 3:20 ` Coia Prant
2026-08-02 14:39 ` Andrew Lunn [this message]
2026-08-01 14:22 ` [PATCH v2 08/10] net: stmmac: dwmac-rk: add SGMII support for RK3568 Coia Prant
2026-08-01 14:22 ` [PATCH v2 09/10] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port Coia Prant
2026-08-01 14:22 ` [PATCH v2 10/10] MAINTAINERS: add entry for Rockchip XPCS driver Coia Prant
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