Re: [PATCH v2 05/10] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes

[Andrew Lunn <andrew@lunn.ch>]

On Sun, Aug 02, 2026 at 11:28:12AM +0800, Coia Prant wrote:
> Hi Andrew,
> 
> Thanks for the detailed questions. I've looked into the clock tree
> more carefully.
> 
> > Do you have documentation for these Combo PHYs?
> 
> Yes, the information is available in the Rockchip RK3568 TRM
> (Technical Reference Manual).
> The relevant clock tree details are also mentioned in upstream
> discussions and patches.
> 
> > Can these clocks be enabled/disabled?
> 
> The 100 MHz input clock to the Combo PHY is a prerequisite for its operation.
> It is generated by the SoC's internal PPLL and fed to the PHY through
> a fixed divider.
> It is not a gate that can be individually enabled or disabled by
> software; it is part of the
> PHY's fundamental operating conditions.
> 
> > And how is the Combo PHY fed with a clock? Does it have an external oscillator/crystal?
> 
> The Combo PHY is fed by an internal 100 MHz clock derived from the PPLL.
> Specifically, the PPLL runs at 200 MHz, and this is divided by 2 to provide the
>  100 MHz clock input to the Combo PHY.
> So, it does not use an external oscillator or crystal for its main
> reference clock;
> it's generated internally by the SoC.
> 
> To summarize:
> - The 125 MHz clocks (xpcs_gmac0_clk / xpcs_gmac1_clk) are outputs
> from the Combo PHY.
> - The Combo PHY itself is clocked by an internal 100 MHz clock from the PPLL.
> - This is all internal to the SoC and does not involve a board-level oscillator.
> 
> I hope this clarifies the clock architecture.

So what is the purpose of the fixed-clock DT nodes?

If you want to describe the hardware, is the PPLL in DT? Should you
then add a fixed divider to give 100MHz? And then a fixed multiplier
to give 125MHz?

   Andrew