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From: Javen <javen_xu@realsil.com.cn>
To: "Maxime Chevallier" <maxime.chevallier@bootlin.com>,
	"andrew@lunn.ch" <andrew@lunn.ch>,
	"hkallweit1@gmail.com" <hkallweit1@gmail.com>,
	"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"edumazet@google.com" <edumazet@google.com>,
	"kuba@kernel.org" <kuba@kernel.org>,
	"pabeni@redhat.com" <pabeni@redhat.com>,
	顾晓军 <freddy_gu@realsil.com.cn>, "nb@tipi-net.de" <nb@tipi-net.de>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"daniel@makrotopia.org" <daniel@makrotopia.org>,
	"vladimir.oltean@nxp.com" <vladimir.oltean@nxp.com>
Subject: RE: [PATCH net-next v8 1/4] net: phy: c45: add genphy_c45_soft_reset()
Date: Fri, 3 Jul 2026 01:40:19 +0000	[thread overview]
Message-ID: <31db813874d04c49866c6353bbf0e0c7@realsil.com.cn> (raw)
In-Reply-To: <9f777a53-f38e-4730-b95f-25f53cdaafc7@bootlin.com>

>
>Hi Javen,
>
>On 7/2/26 05:20, javen wrote:
>> From: Javen Xu <javen_xu@realsil.com.cn>
>>
>> Add a generic Clause 45 software reset helper. The helper sets the
>> reset bit in the PMA/PMD control register and waits until the bit is
>> cleared by hardware.
>>
>> Reviewed-by: Nicolai Buchwitz <nb@tipi-net.de>
>> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
>> ---
>> Changes in v2:
>>  - no changes, new file
>>
>> Changes in v3:
>>  - re-order function according to the order in phy-c45.c
>>
>> Changes in v4:
>>  - no changes
>>
>> Changes in v5:
>>  - no changes
>>
>> Changes in v6:
>>  - increase timeout to 600ms
>>
>> Changes in v7:
>>  - no changes
>>
>> Changes in v8:
>>  - no changes
>> ---
>>  drivers/net/phy/phy-c45.c | 22 ++++++++++++++++++++++
>>  include/linux/phy.h       |  1 +
>>  2 files changed, 23 insertions(+)
>>
>> diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
>> index 126951741428..60d044156a83 100644
>> --- a/drivers/net/phy/phy-c45.c
>> +++ b/drivers/net/phy/phy-c45.c
>> @@ -384,6 +384,28 @@ int genphy_c45_check_and_restart_aneg(struct
>> phy_device *phydev, bool restart)  }
>> EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
>>
>> +/**
>> + * genphy_c45_soft_reset - software reset the PHY via Clause 45
>> +PMA/PMD control register
>> + * @phydev: target phy_device struct
>> + *
>> + * Return: 0 on success, negative errno on failure.
>> + */
>> +int genphy_c45_soft_reset(struct phy_device *phydev) {
>> +     int ret, val;
>> +
>> +     ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
>> +                            MDIO_CTRL1_RESET);
>> +     if (ret < 0)
>> +             return ret;
>> +
>> +     return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
>> +                                      MDIO_CTRL1, val,
>> +                                      !(val & MDIO_CTRL1_RESET),
>> +                                      5000, 600000, true); }
>> +EXPORT_SYMBOL_GPL(genphy_c45_soft_reset);
>
>Can you name it genphy_c45_pma_soft_reset() instead ? That's the common
>naming pattern for C45 generic helpers targetting the PMAPMD MMD.
>
>This will avoid some confusion as some in-tree drivers also configure the
>MDIO_CTRL1_RESET register, but from the PHYXS or PCS MMDs.
>

Sure. Thanks for review.

BRs,
Javen

>Thanks,
>
>Maxime
>
>>

  reply	other threads:[~2026-07-03  1:41 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-02  3:20 [PATCH net-next v8 0/4] Add support for RTL8261C_CG javen
2026-07-02  3:20 ` [PATCH net-next v8 1/4] net: phy: c45: add genphy_c45_soft_reset() javen
2026-07-02 12:12   ` Maxime Chevallier
2026-07-03  1:40     ` Javen [this message]
2026-07-02  3:20 ` [PATCH net-next v8 2/4] net: phy: c45: add setup and read master/slave helpers javen
2026-07-02  3:20 ` [PATCH net-next v8 3/4] net: phy: realtek: add support for RTL8261C_CG javen
2026-07-02 11:40   ` Nicolai Buchwitz
2026-07-02  3:20 ` [PATCH net-next v8 4/4] net: phy: realtek: load firmware " javen

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