Re: [PATCH net-next v8 1/4] net: phy: c45: add genphy_c45_soft_reset()

[Maxime Chevallier <maxime.chevallier@bootlin.com>]

Hi Javen,

On 7/2/26 05:20, javen wrote:
> From: Javen Xu <javen_xu@realsil.com.cn>
> 
> Add a generic Clause 45 software reset helper. The helper sets the reset
> bit in the PMA/PMD control register and waits until the bit is cleared by
> hardware.
> 
> Reviewed-by: Nicolai Buchwitz <nb@tipi-net.de>
> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
> ---
> Changes in v2:
>  - no changes, new file
> 
> Changes in v3:
>  - re-order function according to the order in phy-c45.c
> 
> Changes in v4:
>  - no changes
> 
> Changes in v5:
>  - no changes
> 
> Changes in v6:
>  - increase timeout to 600ms
> 
> Changes in v7:
>  - no changes
>  
> Changes in v8:
>  - no changes
> ---
>  drivers/net/phy/phy-c45.c | 22 ++++++++++++++++++++++
>  include/linux/phy.h       |  1 +
>  2 files changed, 23 insertions(+)
> 
> diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
> index 126951741428..60d044156a83 100644
> --- a/drivers/net/phy/phy-c45.c
> +++ b/drivers/net/phy/phy-c45.c
> @@ -384,6 +384,28 @@ int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
>  }
>  EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
>  
> +/**
> + * genphy_c45_soft_reset - software reset the PHY via Clause 45 PMA/PMD control register
> + * @phydev: target phy_device struct
> + *
> + * Return: 0 on success, negative errno on failure.
> + */
> +int genphy_c45_soft_reset(struct phy_device *phydev)
> +{
> +	int ret, val;
> +
> +	ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
> +			       MDIO_CTRL1_RESET);
> +	if (ret < 0)
> +		return ret;
> +
> +	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
> +					 MDIO_CTRL1, val,
> +					 !(val & MDIO_CTRL1_RESET),
> +					 5000, 600000, true);
> +}
> +EXPORT_SYMBOL_GPL(genphy_c45_soft_reset);

Can you name it genphy_c45_pma_soft_reset() instead ? That's the common
naming pattern for C45 generic helpers targetting the PMAPMD MMD.

This will avoid some confusion as some in-tree drivers also configure the
MDIO_CTRL1_RESET register, but from the PHYXS or PCS MMDs.

Thanks,

Maxime

>