From: Dan Williams <dan.j.williams@intel.com>
To: Alejandro Lucero Palau <alucerop@amd.com>,
Dan Williams <dan.j.williams@intel.com>,
<alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <martin.habets@xilinx.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
<dave.jiang@intel.com>
Subject: Re: [PATCH v8 01/27] cxl: add type2 device basic support
Date: Tue, 14 Jan 2025 15:48:16 -0800 [thread overview]
Message-ID: <6786f7bff1389_20f329429@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <58981468-ca67-0bb4-86b9-5cb2c3678737@amd.com>
Alejandro Lucero Palau wrote:
>
> On 1/7/25 23:42, Dan Williams wrote:
> > alejandro.lucero-palau@ wrote:
> >> From: Alejandro Lucero <alucerop@amd.com>
> >>
> >> Differentiate CXL memory expanders (type 3) from CXL device accelerators
> >> (type 2) with a new function for initializing cxl_dev_state.
> >>
> >> Create accessors to cxl_dev_state to be used by accel drivers.
> >>
> >> Based on previous work by Dan Williams [1]
> >>
> >> Link: [1] https://lore.kernel.org/linux-cxl/168592160379.1948938.12863272903570476312.stgit@dwillia2-xfh.jf.intel.com/
> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> >> Co-developed-by: Dan Williams <dan.j.williams@intel.com>
> >> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> >> Reviewed-by: Fan Ni <fan.ni@samsung.com>
> > This patch causes
> >> ---
> >> drivers/cxl/core/memdev.c | 51 +++++++++++++++++++++++++++++++++++++++
> >> drivers/cxl/core/pci.c | 1 +
> >> drivers/cxl/cxlpci.h | 16 ------------
> >> drivers/cxl/pci.c | 13 +++++++---
> >> include/cxl/cxl.h | 21 ++++++++++++++++
> >> include/cxl/pci.h | 23 ++++++++++++++++++
> >> 6 files changed, 105 insertions(+), 20 deletions(-)
> >> create mode 100644 include/cxl/cxl.h
> >> create mode 100644 include/cxl/pci.h
> >>
> >> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> >> index ae3dfcbe8938..99f533caae1e 100644
> >> --- a/drivers/cxl/core/memdev.c
> >> +++ b/drivers/cxl/core/memdev.c
> >> @@ -7,6 +7,7 @@
> >> #include <linux/slab.h>
> >> #include <linux/idr.h>
> >> #include <linux/pci.h>
> >> +#include <cxl/cxl.h>
> >> #include <cxlmem.h>
> >> #include "trace.h"
> >> #include "core.h"
> >> @@ -616,6 +617,25 @@ static void detach_memdev(struct work_struct *work)
> >>
> >> static struct lock_class_key cxl_memdev_key;
> >>
> >> +struct cxl_dev_state *cxl_accel_state_create(struct device *dev)
> > Lets just call this cxl_dev_state_create and have cxl_memdev_state use
> > it internally for the truly common init functionality.
> >
> > Move the cxlds->type setting to a passed in parameter as that appears to
> > be the only common init piece that needs to change to make this usable
> > by cxl_memdev_state_create().
> >
> > That would also fix the missing initialization of these values the
> > cxl_memdev_state_create() currently handles:
> >
> > mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
> > mds->ram_perf.qos_class = CXL_QOS_CLASS_INVALID;
> > mds->pmem_perf.qos_class = CXL_QOS_CLASS_INVALID;
> >
>
> Ok. It makes sense.
>
>
> >> +{
> >> + struct cxl_dev_state *cxlds;
> >> +
> >> + cxlds = kzalloc(sizeof(*cxlds), GFP_KERNEL);
> >> + if (!cxlds)
> >> + return ERR_PTR(-ENOMEM);
> >> +
> >> + cxlds->dev = dev;
> >> + cxlds->type = CXL_DEVTYPE_DEVMEM;
> >> +
> >> + cxlds->dpa_res = DEFINE_RES_MEM_NAMED(0, 0, "dpa");
> >> + cxlds->ram_res = DEFINE_RES_MEM_NAMED(0, 0, "ram");
> >> + cxlds->pmem_res = DEFINE_RES_MEM_NAMED(0, 0, "pmem");
> >> +
> >> + return cxlds;
> >> +}
> >> +EXPORT_SYMBOL_NS_GPL(cxl_accel_state_create, "CXL");
> > So, this is the only new function I would expect in this patch based on
> > the changelog...
> >
> >> +
> >> static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
> >> const struct file_operations *fops)
> >> {
> >> @@ -693,6 +713,37 @@ static int cxl_memdev_open(struct inode *inode, struct file *file)
> >> return 0;
> >> }
> >>
> >> +void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec)
> >> +{
> >> + cxlds->cxl_dvsec = dvsec;
> >> +}
> >> +EXPORT_SYMBOL_NS_GPL(cxl_set_dvsec, "CXL");
> >> +
> >> +void cxl_set_serial(struct cxl_dev_state *cxlds, u64 serial)
> >> +{
> >> + cxlds->serial = serial;
> >> +}
> >> +EXPORT_SYMBOL_NS_GPL(cxl_set_serial, "CXL");
> > What are these doing in this patch? Why are new exports needed for such
> > trivial functions? If they are common values to move to init time I would
> > just make them common argument to cxl_dev_state_create().
>
>
> I was told to merge those simple changes in this one instead of
> additional patches.
>
> And I have no problem dropping them and use extra args.
>
> I'll do so it v10.
>
>
> >> +
> >> +int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res,
> > Additionally, why does this take a 'struct resource' rather than a 'struct resource *'?
>
>
> The driver does not need the resource but for this initialization, so it
> is a locally allocated resource which will not exist later on.
>
> It is a small struct so I guess your concern is not with the stack,
> maybe about security. If it is due to some rule to avoid it which I'm
> not familiar with, it has gone undetected through a lot of eyes ...
It's not about security its about the semantic of how does an
accelerator initialize the DPA address space of a device, and can it do
it in a generic way that can be shared across acclerators,
pre-HDM-decoder expander devices, post HDM-decoder expanders, and
new-fangled DCD capable expanders.
> >> + enum cxl_resource type)
> >> +{
> >> + switch (type) {
> >> + case CXL_RES_DPA:
> >> + cxlds->dpa_res = res;
> >> + return 0;
> >> + case CXL_RES_RAM:
> >> + cxlds->ram_res = res;
> >> + return 0;
> >> + case CXL_RES_PMEM:
> >> + cxlds->pmem_res = res;
> >> + return 0;
> > This appears to misunderstand the relationship between these resources.
> > dpa_res is the overall device internal DPA address space resource tree.
> > ram_res and pmem_res are shortcuts to get to the volatile and pmem
> > partitions of the dpa space. I can imagine it would ever be desirable to
> > trust the caller to fully initialize all the values of the resource,
> > especially 'parent', 'sibling', and 'child' which should only be touched
> > under the resource lock in the common case.
>
>
> No, I'm aware of this, but also I think there is a need for setting them
> independently, and the reason behind this code.
>
> Maybe you have in mind some complex devices requiring another approach
> for this set up.
DPA space layout initialization is a common operation so I am looking
for a way for expanders and accelerators to stay unified on shared
library code for the similar semantics.
Let me see if I can draft something that also considers what the DCD
code is trying to do.
next prev parent reply other threads:[~2025-01-14 23:48 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-16 16:10 [PATCH v8 00/27] cxl: add type2 device basic support alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 01/27] " alejandro.lucero-palau
2024-12-24 16:35 ` Jonathan Cameron
2024-12-27 6:56 ` Alejandro Lucero Palau
2025-01-07 16:35 ` Alison Schofield
2025-01-07 23:42 ` Dan Williams
2025-01-08 1:33 ` Dan Williams
2025-01-08 14:32 ` Alejandro Lucero Palau
2025-01-14 14:35 ` Alejandro Lucero Palau
2025-01-14 16:40 ` Alejandro Lucero Palau
2025-01-14 22:52 ` Dan Williams
2025-01-15 16:01 ` Alejandro Lucero Palau
2025-01-16 6:16 ` Dan Williams
2025-01-16 10:02 ` Alejandro Lucero Palau
2025-02-05 20:05 ` Dan Williams
2025-02-06 17:37 ` Alejandro Lucero Palau
2025-02-07 1:57 ` Dan Williams
2025-01-24 13:38 ` Alejandro Lucero Palau
2025-01-08 14:11 ` Alejandro Lucero Palau
2025-01-14 23:48 ` Dan Williams [this message]
2024-12-16 16:10 ` [PATCH v8 02/27] sfc: add cxl support using new CXL API alejandro.lucero-palau
2024-12-24 17:04 ` Jonathan Cameron
2024-12-27 7:00 ` Alejandro Lucero Palau
2025-01-08 1:56 ` Dan Williams
2025-01-08 14:53 ` Alejandro Lucero Palau
2025-01-14 23:59 ` Dan Williams
2024-12-16 16:10 ` [PATCH v8 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2024-12-24 17:08 ` Jonathan Cameron
2024-12-27 7:07 ` Alejandro Lucero Palau
2025-01-02 12:49 ` Jonathan Cameron
2025-01-03 7:16 ` Alejandro Lucero Palau
2025-01-03 10:47 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 04/27] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2024-12-24 17:15 ` Jonathan Cameron
2024-12-27 7:47 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 05/27] cxl: move pci generic code alejandro.lucero-palau
2024-12-24 17:19 ` Jonathan Cameron
2024-12-27 7:53 ` Alejandro Lucero Palau
2025-01-08 5:19 ` Dan Williams
2025-01-08 14:39 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 06/27] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2024-12-24 17:22 ` Jonathan Cameron
2024-12-27 8:04 ` Alejandro Lucero Palau
2024-12-30 9:01 ` Alejandro Lucero Palau
2025-01-06 10:41 ` Dan Carpenter
2025-01-06 15:19 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 07/27] sfc: use cxl api for regs setup and checking alejandro.lucero-palau
2024-12-24 17:23 ` Jonathan Cameron
2024-12-27 8:05 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 08/27] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-12-24 17:25 ` Jonathan Cameron
2024-12-27 8:06 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 09/27] sfc: request cxl ram resource alejandro.lucero-palau
2024-12-24 17:27 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 10/27] resource: harden resource_contains alejandro.lucero-palau
2024-12-24 17:27 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 11/27] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-12-24 17:29 ` Jonathan Cameron
2024-12-27 8:08 ` Alejandro Lucero Palau
2025-01-02 12:45 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 12/27] sfc: set cxl media ready alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 13/27] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2024-12-24 17:32 ` Jonathan Cameron
2024-12-27 8:28 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 14/27] sfc: create type2 cxl memdev alejandro.lucero-palau
2024-12-24 17:33 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 15/27] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2024-12-24 17:42 ` Jonathan Cameron
2024-12-27 10:05 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 16/27] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2024-12-18 11:17 ` Edward Cree
2024-12-24 17:43 ` Jonathan Cameron
2024-12-25 20:21 ` kernel test robot
2024-12-16 16:10 ` [PATCH v8 17/27] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2024-12-24 17:53 ` Jonathan Cameron
2024-12-27 10:23 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 18/27] sfc: get endpoint decoder alejandro.lucero-palau
2024-12-17 10:42 ` Simon Horman
2024-12-18 8:22 ` Alejandro Lucero Palau
2025-01-07 11:34 ` Simon Horman
2024-12-16 16:10 ` [PATCH v8 19/27] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-12-24 17:54 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 20/27] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-12-24 17:56 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 21/27] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-12-24 17:56 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 22/27] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2024-12-24 18:01 ` Jonathan Cameron
2024-12-27 10:27 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 23/27] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2024-12-24 18:04 ` Jonathan Cameron
2024-12-27 8:46 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 24/27] sfc: create cxl region alejandro.lucero-palau
2024-12-24 18:05 ` Jonathan Cameron
2024-12-25 23:58 ` kernel test robot
2024-12-16 16:10 ` [PATCH v8 25/27] cxl: add function for obtaining region range alejandro.lucero-palau
2024-12-24 18:07 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 26/27] sfc: update MCDI protocol headers alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 27/27] sfc: support pio mapping based on cxl alejandro.lucero-palau
2024-12-17 10:47 ` Simon Horman
2024-12-18 8:32 ` Alejandro Lucero Palau
2024-12-30 12:16 ` Alejandro Lucero Palau
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