From: <dan.j.williams@intel.com>
To: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>,
Ben Cheatham <benjamin.cheatham@amd.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Alison Schofield <alison.schofield@intel.com>
Subject: Re: [PATCH v17 08/22] cxl: Prepare memdev creation for type2
Date: Fri, 25 Jul 2025 18:05:42 -0700 [thread overview]
Message-ID: <688429e658eba_134cc7100f9@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250624141355.269056-9-alejandro.lucero-palau@amd.com>
alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Current cxl core is relying on a CXL_DEVTYPE_CLASSMEM type device when
> creating a memdev leading to problems when obtaining cxl_memdev_state
> references from a CXL_DEVTYPE_DEVMEM type.
>
> Modify check for obtaining cxl_memdev_state adding CXL_DEVTYPE_DEVMEM
> support.
>
> Make devm_cxl_add_memdev accessible from a accel driver.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> ---
> drivers/cxl/core/memdev.c | 15 +++++++++++++--
> drivers/cxl/cxlmem.h | 2 --
> drivers/cxl/mem.c | 25 +++++++++++++++++++------
> include/cxl/cxl.h | 2 ++
> 4 files changed, 34 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index c73582d24dd7..f43d2aa2928e 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -7,6 +7,7 @@
> #include <linux/slab.h>
> #include <linux/idr.h>
> #include <linux/pci.h>
> +#include <cxl/cxl.h>
> #include <cxlmem.h>
> #include "trace.h"
> #include "core.h"
> @@ -562,9 +563,16 @@ static const struct device_type cxl_memdev_type = {
> .groups = cxl_memdev_attribute_groups,
> };
>
> +static const struct device_type cxl_accel_memdev_type = {
> + .name = "cxl_accel_memdev",
> + .release = cxl_memdev_release,
> + .devnode = cxl_memdev_devnode,
> +};
> +
> bool is_cxl_memdev(const struct device *dev)
> {
> - return dev->type == &cxl_memdev_type;
> + return (dev->type == &cxl_memdev_type ||
> + dev->type == &cxl_accel_memdev_type);
> }
> EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL");
>
> @@ -689,7 +697,10 @@ static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
> dev->parent = cxlds->dev;
> dev->bus = &cxl_bus_type;
> dev->devt = MKDEV(cxl_mem_major, cxlmd->id);
> - dev->type = &cxl_memdev_type;
> + if (cxlds->type == CXL_DEVTYPE_DEVMEM)
> + dev->type = &cxl_accel_memdev_type;
> + else
> + dev->type = &cxl_memdev_type;
> device_set_pm_not_required(dev);
> INIT_WORK(&cxlmd->detach_work, detach_memdev);
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 9cc4337cacfb..7be51f70902a 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -88,8 +88,6 @@ static inline bool is_cxl_endpoint(struct cxl_port *port)
> return is_cxl_memdev(port->uport_dev);
> }
>
> -struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
> - struct cxl_dev_state *cxlds);
> int devm_cxl_sanitize_setup_notifier(struct device *host,
> struct cxl_memdev *cxlmd);
> struct cxl_memdev_state;
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 9675243bd05b..7f39790d9d98 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -130,12 +130,18 @@ static int cxl_mem_probe(struct device *dev)
> dentry = cxl_debugfs_create_dir(dev_name(dev));
> debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
>
> - if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds))
> - debugfs_create_file("inject_poison", 0200, dentry, cxlmd,
> - &cxl_poison_inject_fops);
> - if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds))
> - debugfs_create_file("clear_poison", 0200, dentry, cxlmd,
> - &cxl_poison_clear_fops);
> + /*
> + * Avoid poison debugfs files for Type2 devices as they rely on
> + * cxl_memdev_state.
> + */
I know this already has my Reviewed-by, but this comment is going to
annoying long term. The CXL specification has already dropped "Type2" as
a name and Linux has already called this DEVMEM, and the comment belongs
on a helper.
Just call a new cxl_memdev_poison_enable() helper unconditionally, put
the mds NULL check inside of it and comment on that helper:
/* For CLASSMEM memory expanders enable poison injection */
cxl_memdev_poison_enable()
> + if (mds) {
> + if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds))
> + debugfs_create_file("inject_poison", 0200, dentry, cxlmd,
> + &cxl_poison_inject_fops);
> + if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds))
> + debugfs_create_file("clear_poison", 0200, dentry, cxlmd,
> + &cxl_poison_clear_fops);
> + }
>
> rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
> if (rc)
> @@ -219,6 +225,13 @@ static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n)
> struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
>
> + /*
> + * Avoid poison sysfs files for Type2 devices as they rely on
> + * cxl_memdev_state.
> + */
> + if (!mds)
> + return 0;
> +
> if (a == &dev_attr_trigger_poison_list.attr)
> if (!test_bit(CXL_POISON_ENABLED_LIST,
> mds->poison.enabled_cmds))
Same here, do not sprinle an "if (!mds)" check add a:
cxl_poison_attr_visible() helper and call it unconditionally in the "if
(a == &dev_attr_trigger_poison_list.attr)" case.
next prev parent reply other threads:[~2025-07-26 1:06 UTC|newest]
Thread overview: 115+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 14:13 [PATCH v17 00/22] Type2 device basic support alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-06-25 14:06 ` Jonathan Cameron
2025-06-30 14:38 ` Alejandro Lucero Palau
2025-07-25 21:46 ` dan.j.williams
2025-08-05 10:45 ` Alejandro Lucero Palau
2025-08-05 15:14 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 02/22] sfc: add cxl support alejandro.lucero-palau
2025-06-25 16:37 ` Jonathan Cameron
2025-06-30 14:52 ` Alejandro Lucero Palau
2025-06-30 14:55 ` Alejandro Lucero Palau
2025-06-30 16:07 ` Jonathan Cameron
2025-07-25 22:16 ` dan.j.williams
2025-08-06 8:37 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-07-25 22:41 ` dan.j.williams
2025-08-06 8:46 ` Alejandro Lucero Palau
2025-08-06 9:31 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 04/22] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-06-27 8:27 ` Jonathan Cameron
2025-07-25 22:55 ` dan.j.williams
2025-07-28 16:23 ` Dave Jiang
2025-08-06 9:43 ` Alejandro Lucero Palau
2025-08-06 9:41 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 05/22] sfc: setup cxl component regs and set media ready alejandro.lucero-palau
2025-06-27 8:39 ` Jonathan Cameron
2025-06-30 15:57 ` Alejandro Lucero Palau
2025-08-08 13:11 ` Alejandro Lucero Palau
2025-06-27 8:45 ` Jonathan Cameron
2025-08-08 13:14 ` Alejandro Lucero Palau
2025-07-25 23:04 ` dan.j.williams
2025-06-24 14:13 ` [PATCH v17 06/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-06-27 8:42 ` Jonathan Cameron
2025-06-27 16:43 ` Dave Jiang
2025-07-01 15:23 ` Alejandro Lucero Palau
2025-06-27 8:43 ` Jonathan Cameron
2025-07-01 15:25 ` Alejandro Lucero Palau
2025-07-26 0:54 ` dan.j.williams
2025-06-24 14:13 ` [PATCH v17 07/22] sfc: initialize dpa alejandro.lucero-palau
2025-07-26 0:55 ` dan.j.williams
2025-08-08 16:59 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 08/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-07-26 1:05 ` dan.j.williams [this message]
2025-08-08 17:01 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 09/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-06-27 8:51 ` Jonathan Cameron
2025-07-01 15:30 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 10/22] cx/memdev: Indicate probe deferral alejandro.lucero-palau
2025-06-27 8:59 ` Jonathan Cameron
2025-06-27 9:42 ` Jonathan Cameron
2025-07-01 15:30 ` Alejandro Lucero Palau
2025-06-27 18:17 ` Dave Jiang
2025-06-30 16:20 ` Jonathan Cameron
2025-07-01 16:07 ` Alejandro Lucero Palau
2025-07-01 16:25 ` Dave Jiang
2025-07-01 16:44 ` Jonathan Cameron
2025-07-01 16:02 ` Alejandro Lucero Palau
2025-07-28 17:45 ` dan.j.williams
2025-07-30 3:46 ` dan.j.williams
2025-08-09 11:24 ` Alejandro Lucero Palau
2025-07-16 22:52 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-06-27 22:42 ` Dave Jiang
2025-07-04 14:45 ` Alejandro Lucero Palau
2025-08-05 16:14 ` dan.j.williams
2025-08-11 12:04 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 12/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-06-27 9:10 ` Jonathan Cameron
2025-07-04 14:51 ` Alejandro Lucero Palau
2025-07-28 16:30 ` dan.j.williams
2025-08-11 14:24 ` Alejandro Lucero Palau
2025-09-02 7:11 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-06-27 9:06 ` Jonathan Cameron
2025-07-04 15:18 ` Alejandro Lucero Palau
2025-06-27 20:46 ` Dave Jiang
2025-07-04 15:21 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-06-27 9:11 ` Jonathan Cameron
2025-07-07 11:24 ` Alejandro Lucero Palau
2025-07-16 23:48 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-09-03 17:20 ` Davidlohr Bueso
2025-06-24 14:13 ` [PATCH v17 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-06-27 9:13 ` Jonathan Cameron
2025-06-27 23:05 ` Dave Jiang
2025-06-30 16:20 ` Jonathan Cameron
2025-06-30 16:34 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-06-27 9:32 ` Jonathan Cameron
2025-07-07 11:31 ` Alejandro Lucero Palau
2025-08-05 16:33 ` dan.j.williams
2025-08-11 14:45 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 19/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-06-27 9:33 ` Jonathan Cameron
2025-09-03 17:24 ` Davidlohr Bueso
2025-06-24 14:13 ` [PATCH v17 20/22] sfc: create cxl region alejandro.lucero-palau
2025-06-27 9:38 ` Jonathan Cameron
2025-07-07 11:37 ` Alejandro Lucero Palau
2025-07-28 16:20 ` dan.j.williams
2025-08-11 14:38 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-06-27 9:46 ` Jonathan Cameron
2025-07-07 12:06 ` Alejandro Lucero Palau
2025-08-27 17:26 ` ALOK TIWARI
2025-07-25 20:51 ` [PATCH v17 00/22] Type2 device basic support dan.j.williams
2025-07-25 21:11 ` dan.j.williams
2025-08-27 16:48 ` PJ Waskiewicz
2025-08-28 8:02 ` Alejandro Lucero Palau
2025-09-04 17:48 ` PJ Waskiewicz
2025-09-08 11:48 ` Alejandro Lucero Palau
2025-09-05 23:23 ` PJ Waskiewicz
2025-09-08 12:03 ` Alejandro Lucero Palau
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