From: <dan.j.williams@intel.com>
To: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v17 11/22] cxl: Define a driver interface for HPA free space enumeration
Date: Tue, 5 Aug 2025 09:14:56 -0700 [thread overview]
Message-ID: <68922e004131f_cff991001e@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250624141355.269056-12-alejandro.lucero-palau@amd.com>
alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> CXL region creation involves allocating capacity from device DPA
> (device-physical-address space) and assigning it to decode a given HPA
> (host-physical-address space). Before determining how much DPA to
> allocate the amount of available HPA must be determined. Also, not all
> HPA is created equal, some specifically targets RAM, some target PMEM,
> some is prepared for device-memory flows like HDM-D and HDM-DB, and some
> is host-only (HDM-H).
>
> In order to support Type2 CXL devices, wrap all of those concerns into
> an API that retrieves a root decoder (platform CXL window) that fits the
> specified constraints and the capacity available for a new region.
>
> Add a complementary function for releasing the reference to such root
> decoder.
>
> Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/region.c | 169 ++++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 3 +
> include/cxl/cxl.h | 11 +++
> 3 files changed, 183 insertions(+)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index c3f4dc244df7..03e058ab697e 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -695,6 +695,175 @@ static int free_hpa(struct cxl_region *cxlr)
> return 0;
> }
>
> +struct cxlrd_max_context {
> + struct device * const *host_bridges;
> + int interleave_ways;
> + unsigned long flags;
> + resource_size_t max_hpa;
> + struct cxl_root_decoder *cxlrd;
> +};
> +
> +static int find_max_hpa(struct device *dev, void *data)
> +{
> + struct cxlrd_max_context *ctx = data;
> + struct cxl_switch_decoder *cxlsd;
> + struct cxl_root_decoder *cxlrd;
> + struct resource *res, *prev;
> + struct cxl_decoder *cxld;
> + resource_size_t max;
> + int found = 0;
> +
> + if (!is_root_decoder(dev))
> + return 0;
> +
> + cxlrd = to_cxl_root_decoder(dev);
> + cxlsd = &cxlrd->cxlsd;
> + cxld = &cxlsd->cxld;
> +
> + /*
> + * Flags are single unsigned longs. As CXL_DECODER_F_MAX is less than
> + * 32 bits, the bitmap functions can be used.
> + */
Comments are supposed to explain the code, not repeat the code in
natural language.
> + if (!bitmap_subset(&ctx->flags, &cxld->flags, CXL_DECODER_F_MAX)) {
> + dev_dbg(dev, "flags not matching: %08lx vs %08lx\n",
> + cxld->flags, ctx->flags);
> + return 0;
> + }
How is this easier to read than:
if ((cxld->flags & ctx->flags) != ctx->flags)
return 0;
?
> +
> + for (int i = 0; i < ctx->interleave_ways; i++) {
> + for (int j = 0; j < ctx->interleave_ways; j++) {
> + if (ctx->host_bridges[i] == cxlsd->target[j]->dport_dev) {
> + found++;
> + break;
> + }
> + }
> + }
> +
> + if (found != ctx->interleave_ways) {
> + dev_dbg(dev,
> + "Not enough host bridges. Found %d for %d interleave ways requested\n",
> + found, ctx->interleave_ways);
> + return 0;
> + }
> +
> + /*
> + * Walk the root decoder resource range relying on cxl_region_rwsem to
> + * preclude sibling arrival/departure and find the largest free space
> + * gap.
> + */
> + lockdep_assert_held_read(&cxl_region_rwsem);
> + res = cxlrd->res->child;
> +
> + /* With no resource child the whole parent resource is available */
> + if (!res)
> + max = resource_size(cxlrd->res);
> + else
> + max = 0;
> +
> + for (prev = NULL; res; prev = res, res = res->sibling) {
> + struct resource *next = res->sibling;
> + resource_size_t free = 0;
> +
> + /*
> + * Sanity check for preventing arithmetic problems below as a
> + * resource with size 0 could imply using the end field below
> + * when set to unsigned zero - 1 or all f in hex.
> + */
> + if (prev && !resource_size(prev))
> + continue;
> +
> + if (!prev && res->start > cxlrd->res->start) {
> + free = res->start - cxlrd->res->start;
> + max = max(free, max);
> + }
> + if (prev && res->start > prev->end + 1) {
> + free = res->start - prev->end + 1;
> + max = max(free, max);
> + }
> + if (next && res->end + 1 < next->start) {
> + free = next->start - res->end + 1;
> + max = max(free, max);
> + }
> + if (!next && res->end + 1 < cxlrd->res->end + 1) {
> + free = cxlrd->res->end + 1 - res->end + 1;
> + max = max(free, max);
> + }
> + }
With the benefit of time to reflect, and looking at this again after all
this time it strikes me that it is simply duplicating
get_free_mem_region() and in a way that can still fail later.
Does it simplify the implementation if this just attempts to
allocate the capacity in each window that might support the mapping
constraints and then pass that allocation to the region construction
routine?
Otherwise, this completes a survey of the capacity that is not
guaranteed to be present when the region finally gets allocated.
next prev parent reply other threads:[~2025-08-05 16:15 UTC|newest]
Thread overview: 115+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 14:13 [PATCH v17 00/22] Type2 device basic support alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-06-25 14:06 ` Jonathan Cameron
2025-06-30 14:38 ` Alejandro Lucero Palau
2025-07-25 21:46 ` dan.j.williams
2025-08-05 10:45 ` Alejandro Lucero Palau
2025-08-05 15:14 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 02/22] sfc: add cxl support alejandro.lucero-palau
2025-06-25 16:37 ` Jonathan Cameron
2025-06-30 14:52 ` Alejandro Lucero Palau
2025-06-30 14:55 ` Alejandro Lucero Palau
2025-06-30 16:07 ` Jonathan Cameron
2025-07-25 22:16 ` dan.j.williams
2025-08-06 8:37 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-07-25 22:41 ` dan.j.williams
2025-08-06 8:46 ` Alejandro Lucero Palau
2025-08-06 9:31 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 04/22] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-06-27 8:27 ` Jonathan Cameron
2025-07-25 22:55 ` dan.j.williams
2025-07-28 16:23 ` Dave Jiang
2025-08-06 9:43 ` Alejandro Lucero Palau
2025-08-06 9:41 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 05/22] sfc: setup cxl component regs and set media ready alejandro.lucero-palau
2025-06-27 8:39 ` Jonathan Cameron
2025-06-30 15:57 ` Alejandro Lucero Palau
2025-08-08 13:11 ` Alejandro Lucero Palau
2025-06-27 8:45 ` Jonathan Cameron
2025-08-08 13:14 ` Alejandro Lucero Palau
2025-07-25 23:04 ` dan.j.williams
2025-06-24 14:13 ` [PATCH v17 06/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-06-27 8:42 ` Jonathan Cameron
2025-06-27 16:43 ` Dave Jiang
2025-07-01 15:23 ` Alejandro Lucero Palau
2025-06-27 8:43 ` Jonathan Cameron
2025-07-01 15:25 ` Alejandro Lucero Palau
2025-07-26 0:54 ` dan.j.williams
2025-06-24 14:13 ` [PATCH v17 07/22] sfc: initialize dpa alejandro.lucero-palau
2025-07-26 0:55 ` dan.j.williams
2025-08-08 16:59 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 08/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-07-26 1:05 ` dan.j.williams
2025-08-08 17:01 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 09/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-06-27 8:51 ` Jonathan Cameron
2025-07-01 15:30 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 10/22] cx/memdev: Indicate probe deferral alejandro.lucero-palau
2025-06-27 8:59 ` Jonathan Cameron
2025-06-27 9:42 ` Jonathan Cameron
2025-07-01 15:30 ` Alejandro Lucero Palau
2025-06-27 18:17 ` Dave Jiang
2025-06-30 16:20 ` Jonathan Cameron
2025-07-01 16:07 ` Alejandro Lucero Palau
2025-07-01 16:25 ` Dave Jiang
2025-07-01 16:44 ` Jonathan Cameron
2025-07-01 16:02 ` Alejandro Lucero Palau
2025-07-28 17:45 ` dan.j.williams
2025-07-30 3:46 ` dan.j.williams
2025-08-09 11:24 ` Alejandro Lucero Palau
2025-07-16 22:52 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-06-27 22:42 ` Dave Jiang
2025-07-04 14:45 ` Alejandro Lucero Palau
2025-08-05 16:14 ` dan.j.williams [this message]
2025-08-11 12:04 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 12/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-06-27 9:10 ` Jonathan Cameron
2025-07-04 14:51 ` Alejandro Lucero Palau
2025-07-28 16:30 ` dan.j.williams
2025-08-11 14:24 ` Alejandro Lucero Palau
2025-09-02 7:11 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-06-27 9:06 ` Jonathan Cameron
2025-07-04 15:18 ` Alejandro Lucero Palau
2025-06-27 20:46 ` Dave Jiang
2025-07-04 15:21 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-06-27 9:11 ` Jonathan Cameron
2025-07-07 11:24 ` Alejandro Lucero Palau
2025-07-16 23:48 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-09-03 17:20 ` Davidlohr Bueso
2025-06-24 14:13 ` [PATCH v17 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-06-27 9:13 ` Jonathan Cameron
2025-06-27 23:05 ` Dave Jiang
2025-06-30 16:20 ` Jonathan Cameron
2025-06-30 16:34 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-06-27 9:32 ` Jonathan Cameron
2025-07-07 11:31 ` Alejandro Lucero Palau
2025-08-05 16:33 ` dan.j.williams
2025-08-11 14:45 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 19/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-06-27 9:33 ` Jonathan Cameron
2025-09-03 17:24 ` Davidlohr Bueso
2025-06-24 14:13 ` [PATCH v17 20/22] sfc: create cxl region alejandro.lucero-palau
2025-06-27 9:38 ` Jonathan Cameron
2025-07-07 11:37 ` Alejandro Lucero Palau
2025-07-28 16:20 ` dan.j.williams
2025-08-11 14:38 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-06-27 9:46 ` Jonathan Cameron
2025-07-07 12:06 ` Alejandro Lucero Palau
2025-08-27 17:26 ` ALOK TIWARI
2025-07-25 20:51 ` [PATCH v17 00/22] Type2 device basic support dan.j.williams
2025-07-25 21:11 ` dan.j.williams
2025-08-27 16:48 ` PJ Waskiewicz
2025-08-28 8:02 ` Alejandro Lucero Palau
2025-09-04 17:48 ` PJ Waskiewicz
2025-09-08 11:48 ` Alejandro Lucero Palau
2025-09-05 23:23 ` PJ Waskiewicz
2025-09-08 12:03 ` Alejandro Lucero Palau
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