From: Jiri Pirko <jiri@resnulli.us>
To: "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"davem@davemloft.net" <davem@davemloft.net>,
"edumazet@google.com" <edumazet@google.com>,
"kuba@kernel.org" <kuba@kernel.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"donald.hunter@gmail.com" <donald.hunter@gmail.com>,
"vadim.fedorenko@linux.dev" <vadim.fedorenko@linux.dev>,
"saeedm@nvidia.com" <saeedm@nvidia.com>,
"leon@kernel.org" <leon@kernel.org>,
"tariqt@nvidia.com" <tariqt@nvidia.com>
Subject: Re: [PATCH net-next 1/2] dpll: add clock quality level attribute and op
Date: Wed, 9 Oct 2024 16:06:37 +0200 [thread overview]
Message-ID: <ZwaN7XZpS6tEnTdB@nanopsycho.orion> (raw)
In-Reply-To: <DM6PR11MB46571C9CAA9CBE56D6A5FCFD9B7F2@DM6PR11MB4657.namprd11.prod.outlook.com>
Wed, Oct 09, 2024 at 03:38:38PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Jiri Pirko <jiri@resnulli.us>
>>Sent: Wednesday, October 9, 2024 2:26 PM
>>
>>In order to allow driver expose quality level of the clock it is
>>running, introduce a new netlink attr with enum to carry it to the
>>userspace. Also, introduce an op the dpll netlink code calls into the
>>driver to obtain the value.
>>
>>Signed-off-by: Jiri Pirko <jiri@nvidia.com>
>>---
>> Documentation/netlink/specs/dpll.yaml | 28 +++++++++++++++++++++++++++
>> drivers/dpll/dpll_netlink.c | 22 +++++++++++++++++++++
>> include/linux/dpll.h | 4 ++++
>> include/uapi/linux/dpll.h | 21 ++++++++++++++++++++
>> 4 files changed, 75 insertions(+)
>>
>>diff --git a/Documentation/netlink/specs/dpll.yaml
>>b/Documentation/netlink/specs/dpll.yaml
>>index f2894ca35de8..77a8e9ddb254 100644
>>--- a/Documentation/netlink/specs/dpll.yaml
>>+++ b/Documentation/netlink/specs/dpll.yaml
>>@@ -85,6 +85,30 @@ definitions:
>> This may happen for example if dpll device was previously
>> locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
>> render-max: true
>>+ -
>>+ type: enum
>>+ name: clock-quality-level
>>+ doc: |
>>+ level of quality of a clock device.
>
>Hi Jiri,
>
>Thanks for your work on this!
>
>I do like the idea, but this part is a bit tricky.
>
>I assume it is all about clock/quality levels as mentioned in
>ITU-T spec "Table 11-7" of REC-G.8264?
For now, yes. That is the usecase I have currently. But, if anyone
will have a need to introduce any sort of different quality, I don't
see why not.
>
>Then what about table 11-8?
The names do not overlap. So if anyone need to add those, he is free to
do it.
>
>And in general about option 2(3?) networks?
>
>AFAIR there are 3 (I don't think 3rd is relevant? But still defined
>In REC-G.781, also REC-G.781 doesn't provide clock types at all,
>just Quality Levels).
>
>Assuming 2(3?) network options shall be available, either user can
>select the one which is shown, or driver just provides all (if can,
>one/none otherwise)?
>
>If we don't want to give the user control and just let the
>driver to either provide this or not, my suggestion would be to name
>the attribute appropriately: "clock-quality-level-o1" to make clear
>provided attribute belongs to option 1 network.
I was thinking about that but there are 2 groups of names in both
tables:
1) different quality levels and names. Then "o1/2" in the name is not
really needed, as the name itself is the differentiator.
2) same quality leves in both options. Those are:
PRTC
ePRTC
eEEC
ePRC
And for thesee, using "o1/2" prefix would lead to have 2 enum values
for exactly the same quality level.
But, talking about prefixes, perhaps I can put "ITU" as a prefix
to indicate this is ITU standartized clock quality leaving option
for some other clock quality namespace to appear?
[..]
next prev parent reply other threads:[~2024-10-09 14:06 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 12:25 [PATCH net-next 0/2] dpll: expose clock quality level Jiri Pirko
2024-10-09 12:25 ` [PATCH net-next 1/2] dpll: add clock quality level attribute and op Jiri Pirko
2024-10-09 13:33 ` Vadim Fedorenko
2024-10-09 13:39 ` Jiri Pirko
2024-10-09 13:38 ` Kubalewski, Arkadiusz
2024-10-09 14:06 ` Jiri Pirko [this message]
2024-10-10 9:53 ` Kubalewski, Arkadiusz
2024-10-10 11:36 ` Jiri Pirko
2024-10-10 13:48 ` Kubalewski, Arkadiusz
2024-10-10 14:36 ` Jiri Pirko
2024-10-10 16:02 ` Kubalewski, Arkadiusz
2024-10-11 6:45 ` Jiri Pirko
2024-10-11 14:25 ` Kubalewski, Arkadiusz
2024-10-11 15:57 ` Jiri Pirko
2024-10-11 19:50 ` Kubalewski, Arkadiusz
2024-10-09 12:25 ` [PATCH net-next 2/2] net/mlx5: DPLL, Add clock quality level op implementation Jiri Pirko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZwaN7XZpS6tEnTdB@nanopsycho.orion \
--to=jiri@resnulli.us \
--cc=arkadiusz.kubalewski@intel.com \
--cc=davem@davemloft.net \
--cc=donald.hunter@gmail.com \
--cc=edumazet@google.com \
--cc=kuba@kernel.org \
--cc=leon@kernel.org \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=saeedm@nvidia.com \
--cc=tariqt@nvidia.com \
--cc=vadim.fedorenko@linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox