* [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset
@ 2025-08-18 15:07 Prabhakar
2025-08-18 15:12 ` Andrew Lunn
2025-08-18 15:58 ` Wolfram Sang
0 siblings, 2 replies; 5+ messages in thread
From: Prabhakar @ 2025-08-18 15:07 UTC (permalink / raw)
To: Clément Léger, Andrew Lunn, Heiner Kallweit,
Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Florian Fainelli, Geert Uytterhoeven
Cc: linux-renesas-soc, netdev, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Prabhakar, stable
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
[0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
0x8, not 0x20 as previously defined.
[0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
Cc: stable@kernel.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/net/pcs/pcs-rzn1-miic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index d79bb9b06cd2..ce73d9474d5b 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -19,7 +19,7 @@
#define MIIC_PRCMD 0x0
#define MIIC_ESID_CODE 0x4
-#define MIIC_MODCTRL 0x20
+#define MIIC_MODCTRL 0x8
#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
#define MIIC_CONVCTRL(port) (0x100 + (port) * 4)
--
2.50.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset
2025-08-18 15:07 [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset Prabhakar
@ 2025-08-18 15:12 ` Andrew Lunn
2025-08-18 16:21 ` Lad, Prabhakar
2025-08-18 15:58 ` Wolfram Sang
1 sibling, 1 reply; 5+ messages in thread
From: Andrew Lunn @ 2025-08-18 15:12 UTC (permalink / raw)
To: Prabhakar
Cc: Clément Léger, Heiner Kallweit, Russell King,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Florian Fainelli, Geert Uytterhoeven, linux-renesas-soc, netdev,
linux-kernel, Biju Das, Fabrizio Castro, Prabhakar, stable
On Mon, Aug 18, 2025 at 04:07:57PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html
Please set the Subject: correctly.
> Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> 0x8, not 0x20 as previously defined.
What effect does this have? How would i notice it is broken?
Andrew
---
pw-bot: cr
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset
2025-08-18 15:07 [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset Prabhakar
2025-08-18 15:12 ` Andrew Lunn
@ 2025-08-18 15:58 ` Wolfram Sang
2025-08-18 16:23 ` Lad, Prabhakar
1 sibling, 1 reply; 5+ messages in thread
From: Wolfram Sang @ 2025-08-18 15:58 UTC (permalink / raw)
To: Prabhakar
Cc: Clément Léger, Andrew Lunn, Heiner Kallweit,
Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Florian Fainelli, Geert Uytterhoeven,
linux-renesas-soc, netdev, linux-kernel, Biju Das,
Fabrizio Castro, Prabhakar, stable
[-- Attachment #1: Type: text/plain, Size: 821 bytes --]
On Mon, Aug 18, 2025 at 04:07:57PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> 0x8, not 0x20 as previously defined.
>
> [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
>
> Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> Cc: stable@kernel.org
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
I can also test it on my N1D board next week.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset
2025-08-18 15:12 ` Andrew Lunn
@ 2025-08-18 16:21 ` Lad, Prabhakar
0 siblings, 0 replies; 5+ messages in thread
From: Lad, Prabhakar @ 2025-08-18 16:21 UTC (permalink / raw)
To: Andrew Lunn
Cc: Clément Léger, Heiner Kallweit, Russell King,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Florian Fainelli, Geert Uytterhoeven, linux-renesas-soc, netdev,
linux-kernel, Biju Das, Fabrizio Castro, Prabhakar, stable
Hi Andrew,
Thank you for the feedback.
On Mon, Aug 18, 2025 at 4:12 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Mon, Aug 18, 2025 at 04:07:57PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html
>
> Please set the Subject: correctly.
>
My bad, I'll take care of this in the next version.
> > Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> > According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> > [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> > 0x8, not 0x20 as previously defined.
>
> What effect does this have? How would i notice it is broken?
>
I will update the commit description.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset
2025-08-18 15:58 ` Wolfram Sang
@ 2025-08-18 16:23 ` Lad, Prabhakar
0 siblings, 0 replies; 5+ messages in thread
From: Lad, Prabhakar @ 2025-08-18 16:23 UTC (permalink / raw)
To: Wolfram Sang
Cc: Clément Léger, Andrew Lunn, Heiner Kallweit,
Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Florian Fainelli, Geert Uytterhoeven,
linux-renesas-soc, netdev, linux-kernel, Biju Das,
Fabrizio Castro, Prabhakar, stable
Hi Wolfram,
Thank for the review.
On Mon, Aug 18, 2025 at 4:58 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
> On Mon, Aug 18, 2025 at 04:07:57PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> > According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> > [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> > 0x8, not 0x20 as previously defined.
> >
> > [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
> >
> > Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> > Cc: stable@kernel.org
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> I can also test it on my N1D board next week.
>
Perfect, I dont have access to the RZ/N1 board but I'm working on
reusing the same driver for a new SoC which has the same register.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-08-18 16:24 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-18 15:07 [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset Prabhakar
2025-08-18 15:12 ` Andrew Lunn
2025-08-18 16:21 ` Lad, Prabhakar
2025-08-18 15:58 ` Wolfram Sang
2025-08-18 16:23 ` Lad, Prabhakar
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox