* [PATCH net-next] net: dsa: mv88e6xxx: SERDES support 2500BaseT via external PHY
@ 2019-02-08 21:25 Heiner Kallweit
2019-02-10 3:02 ` David Miller
0 siblings, 1 reply; 2+ messages in thread
From: Heiner Kallweit @ 2019-02-08 21:25 UTC (permalink / raw)
To: Andrew Lunn, Florian Fainelli, David Miller, Vivien Didelot
Cc: netdev@vger.kernel.org
From: Andrew Lunn <andrew@lunn.ch>
By using an external PHY, ports 9 and 10 can support 2500BaseT.
So set this link mode in the mask when validating.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 8dca2c949..739c0c168 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -647,8 +647,10 @@ static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
unsigned long *mask,
struct phylink_link_state *state)
{
- if (port >= 9)
+ if (port >= 9) {
phylink_set(mask, 2500baseX_Full);
+ phylink_set(mask, 2500baseT_Full);
+ }
/* No ethtool bits for 200Mbps */
phylink_set(mask, 1000baseT_Full);
--
2.20.1
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2019-02-08 21:25 [PATCH net-next] net: dsa: mv88e6xxx: SERDES support 2500BaseT via external PHY Heiner Kallweit
2019-02-10 3:02 ` David Miller
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