From: Frank Li <Frank.li@oss.nxp.com>
To: jan.petrous@oss.nxp.com
Cc: "Ciprian Marian Costea" <ciprianmarian.costea@oss.nxp.com>,
"NXP S32 Linux Team" <s32@nxp.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Ghennadi Procopciuc" <ghennadi.procopciuc@nxp.com>,
"Andrew Lunn" <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Bogdan Hamciuc" <bogdan.hamciuc@nxp.com>,
"Ionut Vicovan" <ionut.vicovan@nxp.com>,
"Andrew Lunn" <andrew@lunn.ch>,
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"Matthias Brugger" <mbrugger@suse.com>,
"Ghennadi Procopciuc" <ghennadi.procopciuc@oss.nxp.com>,
"Frank Li" <Frank.Li@nxp.com>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>,
"Richard Cochran" <richardcochran@gmail.com>,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, imx@lists.linux.dev,
linux-pci@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
"Vincent Guittot" <vincent.guittot@linaro.org>
Subject: Re: [PATCH RFC v3 03/12] dt-bindings: PCI: nxp,s32g-pcie: Fix SerDes PHY phandle in example
Date: Mon, 12 Oct 2026 13:43:05 -0500 [thread overview]
Message-ID: <as0qORxP0Roh9ktO@SMW015318> (raw)
In-Reply-To: <20260919-s32g_serdes-v3-3-9d68868c1e89@oss.nxp.com>
On Sat, Sep 19, 2026 at 08:54:31AM +0200, Jan Petrous via B4 Relay wrote:
> [You don't often get email from devnull+jan.petrous.oss.nxp.com@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> The example references the SerDes PHY as
>
> phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
>
> i.e. the SerDes node itself with three PHY cells. That does not match
> the SerDes binding: the per-lane child node is the generic PHY
> provider and carries '#phy-cells = <0>', while the SerDes node itself
> has no '#phy-cells' at all.
>
> Point the example at the PCIe lane child instead, which is also what
> the S32G3 board device trees use. The dt-bindings/phy/phy.h include is
> dropped along with the now-unused PHY_TYPE_PCIE constant.
>
> The schema itself is unchanged; 'phys: maxItems: 1' already describes
> the corrected form.
>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
> ---
> Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> index 66a050028278..29323e50bd8b 100644
> --- a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> @@ -82,7 +82,6 @@ unevaluatedProperties: false
> examples:
> - |
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> - #include <dt-bindings/phy/phy.h>
>
> bus {
> #address-cells = <2>;
> @@ -124,7 +123,7 @@ examples:
> ranges;
>
> device_type = "pci";
> - phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> + phys = <&serdes0_pcie0>;
I don't think it fix somethings. The "serdes0" just a label, point to
provider, which is not neccsary that "#phy-cells" is 0.
Examples just show need how many phys and don't care about phy provider's
arguments
Frank
> };
> };
> };
>
> --
> 2.55.0
>
>
>
next prev parent reply other threads:[~2026-10-12 18:43 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-19 6:54 [PATCH RFC v3 00/12] Add support for the NXP S32G SerDes subsystem Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 01/12] dt-bindings: phy: Add " Jan Petrous via B4 Relay
2026-10-12 18:57 ` Frank Li
2026-10-13 14:40 ` Jan Petrous
2026-09-19 6:54 ` [PATCH RFC v3 02/12] dt-bindings: net: nxp,s32-dwmac: Document pcs-handle Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 03/12] dt-bindings: PCI: nxp,s32g-pcie: Fix SerDes PHY phandle in example Jan Petrous via B4 Relay
2026-10-12 18:43 ` Frank Li [this message]
2026-10-13 14:37 ` Jan Petrous
2026-09-19 6:54 ` [PATCH RFC v3 04/12] net: pcs: add NXP SerDes XPCS shared core Jan Petrous via B4 Relay
2026-09-19 15:31 ` Maxime Chevallier
2026-09-19 16:31 ` Coia Prant
2026-10-11 6:01 ` Jan Petrous
2026-10-12 19:47 ` Coia Prant
2026-10-13 14:47 ` Jan Petrous
2026-09-20 18:39 ` Andrew Lunn
2026-10-11 6:03 ` Jan Petrous
2026-09-19 6:54 ` [PATCH RFC v3 05/12] net: pcs: Add NXP S32G XPCS driver Jan Petrous via B4 Relay
2026-09-20 17:07 ` Andrew Lunn
2026-10-11 5:56 ` Jan Petrous
2026-09-19 6:54 ` [PATCH RFC v3 06/12] phy: freescale: s32g: Add SerDes subsystem PHY Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 07/12] net: stmmac: dwmac-s32: Add SGMII support Jan Petrous via B4 Relay
2026-09-19 12:04 ` Maxime Chevallier
2026-10-11 5:53 ` Jan Petrous
2026-09-19 6:54 ` [PATCH RFC v3 08/12] MAINTAINERS: Add NXP S32G SerDes and SerDes xPCS core entries Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 09/12] arm64: dts: s32g: Add SCMI reset controller Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 10/12] arm64: dts: s32g: Add SerDes controller nodes Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 11/12] arm64: dts: s32g: Add PCIe " Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 12/12] arm64: dts: s32g: Add S32G3-RDB3 SerDes routing variants Jan Petrous via B4 Relay
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