Re: [PATCH RFC v3 04/12] net: pcs: add NXP SerDes XPCS shared core

[Jan Petrous <jan.petrous@oss.nxp.com>]

Hi Maxime, Coia

On Sat, Sep 19, 2026 at 05:31:42PM +0200, Maxime Chevallier wrote:
> Hi Jan,
> 
> On 9/19/26 08:54, Jan Petrous via B4 Relay wrote:
> > From: Clark Wang <xiaoning.wang@nxp.com>
> > 
> > The SerDes subsystems found on NXP S32G and i.MX SoCs integrate a
> > Synopsys DesignWare Ethernet XPCS and an Ethernet PHY (PMA) with an
> > identical register layout. Only the register transport differs: indirect
> > memory mapped access on S32G, Clause 45 MDIO on i.MX.
> > 
> > Add a transport agnostic phylink PCS core which operates on regmaps
> > provided by the platform glue. It implements the phylink PCS operations,
> > the Clause 37 SGMII / 2500BASE-X / USXGMII / 10GBASE-R configuration and
> > link state handling, soft reset and polling helpers, and the common
> > feature sets. The platform specific register sequences, compatibility
> > tables and quirks are supplied through a per revision descriptor by the
> > platform drivers selecting this core.
> > 
> > The register sequences and the feature lists are derived from the
> > Synopsys pcs-xpcs driver, so its copyright is retained. A separate driver
> > is needed because struct dw_xpcs is built around an mdio_device and owns
> > the transport, the reset and the identification of a standalone PCS,
> > while here the PMA can be shared with a PCIe controller, the bring-up is
> > sequenced across both XPCS instances by the SerDes PHY driver, and the
> > transport is not always MDIO.
> 
> Is there a way to avoid code duplication by wrapping the accesses into
> a mii_bus ?
> 
> This is what the Rockchip submission does : 
> 
> https://lore.kernel.org/r/20260919125119.2107089-8-coiaprant@gmail.com
> 

Yes. The S32G accessor is the same DW indirect scheme pcs-xpcs-plat
implements (page into the viewport at 0xff, then the low address byte
at a 4-byte stride), so there is no reason for S32G to carry its own
copy of the XPCS code. The next version drops the shared core, exposes
each XPCS instance as a mii_bus from the SerDes PHY driver and creates
the PCS with xpcs_create_pcs_mdiodev(), much like the RK3568 glue.
Details in my reply to Andrew.

The part that does not fit pcs-xpcs-plat as-is is ownership, not
access: the XPCS windows sit inside the SerDes subsystem register
space, and their bring-up is ordered against the PCIe lane and the
other XPCS instance, so the bus is registered by the SerDes PHY driver
rather than by a standalone snps,dw-xpcs device. The accessor itself
is a few lines; if Alex's pcs-xpcs-regmap is merged first I will use
it rather than open-code another bus.

On 9/20/26 00:31, Coia Prant wrote:
> A callback in dw_xpcs would let platform glues express those
> differences without copying the register sequences.

S32G needs the same kind of thing: skip the generic soft reset, and no
EEE registers. I will start with the existing PMA-ID mechanism, since
that is what TXGBE and FBNIC use today, and switch to a callback if one
is agreed in the Rockchip thread. I'll Cc you on those patches.

Thanks,
Jan