Re: [PATCH v1 11/11] drm/xe/ras: Add flag for Xe RAS

["Tauro, Riana" <riana.tauro@intel.com>]

On 4/18/2026 2:46 AM, Raag Jadav wrote:
> From: Riana Tauro <riana.tauro@intel.com>
>
> Add a flag for RAS. If enabled, XE driver registers with
> drm_ras and exposes supported counters.
>
> Currently this is enabled for PVC and CRI.

Can you please replace this with the latest
  patch in the next rev [PATCH v4 6/6] drm/xe/xe_ras: Control xe drm_ras 
registration with a flag - Riana Tauro 
<https://lore.kernel.org/intel-xe/20260429055147.1579576-14-riana.tauro@intel.com/> 


Thanks
Riana


<https://lore.kernel.org/intel-xe/20260429055147.1579576-14-riana.tauro@intel.com/> 

>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>   drivers/gpu/drm/xe/xe_hw_error.c     | 2 +-
>   drivers/gpu/drm/xe/xe_pci.c          | 3 +++
>   drivers/gpu/drm/xe/xe_pci_types.h    | 1 +
>   4 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 31df9debcbb0..7a8afd06e6b8 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -191,6 +191,8 @@ struct xe_device {
>   		u8 has_ctx_tlb_inval:1;
>   		/** @info.has_range_tlb_inval: Has range based TLB invalidations */
>   		u8 has_range_tlb_inval:1;
> +		/** @info.has_ras: Device supports RAS (Reliability, Availability, Serviceability) */
> +		u8 has_ras:1;
>   		/** @info.has_soc_remapper_sysctrl: Has SoC remapper system controller */
>   		u8 has_soc_remapper_sysctrl:1;
>   		/** @info.has_soc_remapper_telem: Has SoC remapper telemetry support */
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 2a31b430570e..3ab0fceb151f 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -520,7 +520,7 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
>   
>   static int hw_error_info_init(struct xe_device *xe)
>   {
> -	if (xe->info.platform != XE_PVC)
> +	if (!xe->info.has_ras)
>   		return 0;
>   
>   	return xe_drm_ras_init(xe);
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 278c2860a4f6..10ff207affa9 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -365,6 +365,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
>   	.vm_max_level = 4,
>   	.vram_flags = XE_VRAM_FLAGS_NEED64K,
>   	.has_mbx_power_limits = false,
> +	.has_ras = true,
>   };
>   
>   static const struct xe_device_desc mtl_desc = {
> @@ -472,6 +473,7 @@ static const struct xe_device_desc cri_desc = {
>   	.require_force_probe = true,
>   	.va_bits = 57,
>   	.vm_max_level = 4,
> +	.has_ras = true,
>   };
>   
>   static const struct xe_device_desc nvlp_desc = {
> @@ -761,6 +763,7 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
>   	xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
>   	xe->info.has_pxp = desc->has_pxp;
> +	xe->info.has_ras = desc->has_ras;
>   	xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl;
>   	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
>   	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 5b85e2c24b7b..70a9d4995cbd 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -54,6 +54,7 @@ struct xe_device_desc {
>   	u8 has_pre_prod_wa:1;
>   	u8 has_page_reclaim_hw_assist:1;
>   	u8 has_pxp:1;
> +	u8 has_ras:1;
>   	u8 has_soc_remapper_sysctrl:1;
>   	u8 has_soc_remapper_telem:1;
>   	u8 has_sriov:1;