* [PATCH] ctnetlink: fix typo in ctnl_exp_cb array
From: Harald Welte @ 2005-08-05 16:21 UTC (permalink / raw)
To: David Miller; +Cc: Linux Netdev List, Netfilter Development Mailinglist
[-- Attachment #1: Type: text/plain, Size: 1695 bytes --]
Hi Dave, please apply.
[NETFILTER] Fix typo in ctnl_exp_cb array (no bug, just memory waste)
This fixes the size of the ctnl_exp_cb array that is IPCTNL_MSG_EXP_MAX
instead of IPCTNL_MSG_MAX. Simple typo.
Signed-off-by: Pablo Neira Ayuso <pablo@eurodev.net>
Signed-off-by: Harald Welte <laforge@netfilter.org>
---
commit 76596b57e2fe552da8beef4a59d5b559dfc3d0e5
tree 84acf2c3953dd3b824cfdb0b501e1b778ac2de19
parent cc45a2a7c15b72bf38d611e469fa30d62ade8f1f
author Harald Welte <laforge@netfilter.org> Fr, 05 Aug 2005 14:23:56 +0200
committer Harald Welte <laforge@netfilter.org> Fr, 05 Aug 2005 14:23:56 +0200
net/ipv4/netfilter/ip_conntrack_netlink.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/net/ipv4/netfilter/ip_conntrack_netlink.c b/net/ipv4/netfilter/ip_conntrack_netlink.c
--- a/net/ipv4/netfilter/ip_conntrack_netlink.c
+++ b/net/ipv4/netfilter/ip_conntrack_netlink.c
@@ -1490,7 +1490,7 @@ static struct nfnl_callback ctnl_cb[IPCT
.cap_required = CAP_NET_ADMIN },
};
-static struct nfnl_callback ctnl_exp_cb[IPCTNL_MSG_MAX] = {
+static struct nfnl_callback ctnl_exp_cb[IPCTNL_MSG_EXP_MAX] = {
[IPCTNL_MSG_EXP_GET] = { .call = ctnetlink_get_expect,
.attr_count = CTA_EXPECT_MAX,
.cap_required = CAP_NET_ADMIN },
--
- Harald Welte <laforge@netfilter.org> http://netfilter.org/
============================================================================
"Fragmentation is like classful addressing -- an interesting early
architectural error that shows how much experimentation was going
on while IP was being designed." -- Paul Vixie
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^ permalink raw reply
* [patch 4/8] atheros driver - eeprom routines
From: Mateusz Berezecki @ 2005-08-05 14:23 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 47 bytes --]
resending patch 4/8 as it was reported missing
[-- Attachment #2: atheros5212-4.patch --]
[-- Type: text/plain, Size: 18628 bytes --]
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/eeprom.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/eeprom.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/eeprom.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/eeprom.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,501 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * the original assembly code has been created by Sam Leffler
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+//#include "atheros_devops.h"
+//#include "atheros_regops.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+
+/* XXX add calibration info */
+unsigned int get_cal(struct eeprom_info *e, unsigned int val)
+{
+ return 0;
+}
+
+
+/* should be called poll_read. waits some time for a specific value
+ * being read */
+unsigned int ath_timed_read(struct net_device *netdev,
+ unsigned int reg, unsigned int mask,
+ unsigned int val)
+{
+ unsigned int i, tmp;
+ for (i = 0; i < 1000; i++) {
+ tmp = ath_reg_read(netdev, reg) & mask;
+ if ((tmp & mask) == val)
+ return 1;
+ udelay(15);
+ }
+
+ printk(KERN_DEBUG"atheros: timed read failing: mask:%x val:%x\n",
+ mask, val);
+ return 0;
+}
+
+/* read from EEPROM */
+unsigned int eeprom_read(struct net_device *netdev,
+ unsigned int x, unsigned int *val)
+{
+
+ ath_reg_write(netdev, 0x6000, x);
+ ath_reg_write(netdev, 0x6008, 1);
+
+ if (!ath_timed_read(netdev, 0x600c, 3, 2))
+ return 0;
+
+ *val = ath_reg_read(netdev, 0x6004) & 0xffff;
+
+ return 1;
+}
+
+/* read antenna control stuff while initializing the chipset */
+void eeprom_read_ant_control(struct net_device *netdev, unsigned int reg, unsigned int idx)
+{
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+ struct eeprom_info *e = &pdata->eeinfo;
+ unsigned int val;
+
+ eeprom_read(netdev, reg++, &val);
+ e->switchval[idx] = (val >> 8) & 0x7f;
+ e->txrx[idx] = (val >> 2) & 0x3f;
+
+ e->antctrl[0][idx] = (val << 4) & 0x3f;
+ e->antctrl[0][idx] |= (val >> 12) & 0x0f;
+ e->antctrl[1][idx] = (val >> 6) & 0x3f;
+ e->antctrl[2][idx] = val & 0x3f;
+
+ eeprom_read(netdev, reg++, &val);
+ e->antctrl[3][idx] = (val >> 10) & 0x3f;
+ e->antctrl[4][idx] = (val >> 4) & 0x3f;
+ e->antctrl[5][idx] = (val << 2) & 0x3f;
+
+ eeprom_read(netdev, reg++, &val);
+ e->antctrl[5][idx] |= (val >> 14) & 3;
+ e->antctrl[6][idx] = (val >> 8) & 0x3f;
+ e->antctrl[7][idx] = (val >> 2) & 0x3f;
+ e->antctrl[8][idx] = (val << 4) & 0x3f;
+
+ eeprom_read(netdev, reg++, &val);
+ e->antctrl[8][idx] |= (val >> 12) & 0xf;
+ e->antctrl[9][idx] = (val >> 6) & 0x3f;
+ e->antctrl[10][idx] = val & 0x3f;
+
+
+}
+
+/* read wireless mode info from EEPROM
+ * XXX: this needs splitting to be more readable.
+ * though i have no idea how to do it yet
+ *
+ * this is UGLY UGLY UGLY
+ */
+void eeprom_read_mode(struct net_device *netdev, unsigned int reg, int k)
+{
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+ struct eeprom_info *e = &pdata->eeinfo;
+ unsigned int val;
+
+ eeprom_read_ant_control(netdev, reg, k);
+ reg += 4;
+
+ eeprom_read(netdev, reg++, &val);
+ e->adcsize[k] = (val >> 8) & 0xff;
+
+ switch (k) {
+ case 0:
+ e->g5_k4 = (val >> 5) & 7;
+ e->g5_v4 = (val >> 2) & 7;
+ e->g5_k3 = (val << 1) & 7;
+ break;
+
+ case 1:
+ e->g2_k1 = (val >> 4) & 7;
+ e->g2_v1 = val & 7;
+ break;
+
+ case 2:
+ e->g2_k2g = (val >> 4) & 7;
+ e->g2_v2g = val & 7;
+ break;
+ }
+
+ if (k == 0) {
+ eeprom_read(netdev, reg++, &val);
+ e->g5_k3 |= (val >> 15) & 1;
+ e->g5_v3 = (val >> 12) & 7;
+ e->g5_k2 = (val >> 9) & 7;
+ e->g5_v2 = (val >> 6) & 7;
+ e->g5_k1 = (val >> 3) & 7;
+ e->g5_v1 = val & 7;
+ }
+
+ eeprom_read(netdev, reg++, &val);
+ e->txendon[k] = (val >> 8) & 0xff;
+ e->thresh[k] = val & 0xff;
+
+ eeprom_read(netdev, reg++, &val);
+ e->txendoff[k] = (val >> 8) & 0xff;
+ e->txfrmctrl[k] = val & 0xff;
+
+ eeprom_read(netdev, reg++, &val);
+ e->pgasize[k] = (val >> 8) & 0xff;
+ e->noise_floor[k] = val & 0xff;
+
+ if (e->noise_floor[k] & 0x80) {
+ e->noise_floor[k] = 0 -
+ ((e->noise_floor[k] ^ 0xff) + 1);
+ }
+
+ eeprom_read(netdev, reg++, &val);
+ e->xlna_gain[k] = (val >> 5) & 0xff;
+ e->xgain[k] = (val >> 1) & 0x0f;
+ e->xpd[k] = val & 1;
+
+ if (e->version >= 0x4000) {
+ switch (k) {
+ case 0:
+ e->fixed5 = (val >> 13) & 1;
+ break;
+ case 2:
+ e->fixed2 = (val >> 13) & 1;
+ }
+ }
+
+ if (e->version >= 0x3003) {
+ eeprom_read(netdev, reg++, &val);
+ e->detbkoff[k] = (val >> 6) & 0x7f;
+
+ switch (k) {
+ case 0:
+ e->xr5_pwr_limit = val & 0x3f;
+ break;
+ case 1:
+ e->g2_k3[0] = val & 7;
+ e->g2_v3[0] = (val >> 3) & 7;
+ break;
+ case 2:
+ e->g2_k3[1] = val & 7;
+ e->g2_v3[1] = (val >> 3) & 7;
+ break;
+ }
+ }
+
+ if (e->version >= 0x3004) {
+ e->igain[k] = (val >> 13) & 7;
+ eeprom_read(netdev, reg++, &val);
+ e->igain[k] |= (val << 3) & 0x38;
+
+ switch (k) {
+ case 0:
+ if (e->version >= 0x4000) {
+ e->ical[0] =
+ (val >> 8) & 0x3f;
+ e->qcal[0] =
+ (val >> 3) & 0x1f;
+ }
+ break;
+ case 2:
+ e->pwr_diff = (val >> 3) & 0xff;
+ if (e->version >= 0x4006)
+ e->scale_14 =
+ (val >> 11) & 0x1f;
+ break;
+ }
+ } else {
+ e->igain[k] = 10;
+ e->pwr_diff = 10;
+ }
+
+ if (e->version >= 0x4000) {
+ switch (k) {
+ case 0:
+ if (e->version < 0x4001)
+ break;
+ eeprom_read(netdev,reg++, &val);
+ e->rxtx_epsilon[0] = val & 0x3f;
+ break;
+
+ case 1:
+ eeprom_read(netdev,reg++,&val);
+ e->cal11b[0] =
+ get_cal(e, val & 0xff);
+ e->cal11b[1] =
+ get_cal(e, (val >> 8) & 0xff);
+ eeprom_read(netdev,reg++,&val);
+ e->cal11b[2] =
+ get_cal(e, val & 0xff);
+
+ if (e->version < 0x4001)
+ break;
+
+ e->rxtx_epsilon[1] =
+ (val >> 8) & 0x3f;
+ break;
+
+ case 2:
+ eeprom_read(netdev,reg++,&val);
+ e->cal11g[0] =
+ get_cal(e, val & 0xff);
+ e->cal11g[1] =
+ get_cal(e,
+ (val >> 8) & 0xff);
+ eeprom_read(netdev,reg++,&val);
+ e->turbo2_pwr_limit =
+ val & 0x7f;
+ e->xr2_pwr_limit =
+ (val >> 7) & 0x3f;
+ eeprom_read(netdev,reg++,&val);
+ e->cal11g[2] =
+ get_cal(e, val & 0xff);
+
+ if (e->version >= 0x4001) {
+ e->rxtx_epsilon[2] =
+ (val >> 8)&0x3f;
+ }
+ eeprom_read(netdev,reg++,&val);
+ e->ical[1] = (val >> 8) & 0x3f;
+ e->qcal[1] = (val >> 3) & 0x1f;
+
+ if (e->version < 0x4002)
+ break;
+
+ eeprom_read(netdev,reg++,&val);
+ e->pwr_diff = val & 0xff;
+ break;
+ }
+ }
+}
+
+void eeprom_read_info3_3(struct net_device *netdev)
+{
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+ struct eeprom_info *e = &pdata->eeinfo;
+ unsigned int val, tmp, i;
+
+ eeprom_read(netdev, 0xc2, &val);
+ e->disabled_turbo5 = (val >> 15) & 1;
+ e->disabled_turbo2 = (val >> 3) & 1;
+ e->turbo2_pwr_limit = (val >> 4) & 0x7f;
+
+ e->rfkill = (val >> 14) & 1;
+ e->devtyp = (val >> 11) & 1;
+
+ e->mode_a = (val & 1);
+ e->mode_b = (val >> 1) & 1;
+ e->mode_g = (val >> 2) & 1;
+ printk(KERN_DEBUG"atheros: modes [A:%x B:%x G:%x]\n",
+ e->mode_a, e->mode_b, e->mode_g);
+
+ eeprom_read(netdev, 0xc3, &val);
+ e->antgain_limit[0] = (char) (val >> 8) & 0xff;
+ e->antgain_limit[1] = (char) (val >> 8);
+
+ if (e->version >= 0x4000) {
+ eeprom_read(netdev, 0xc4, &val);
+ e->mp = (val >> 14) & 3;
+ e->ear = (val & 0xfff);
+
+ eeprom_read(netdev, 0xc5, &val);
+ e->pwr_start = val & 0xfff;
+ e->clk_32khz = (val >> 14) & val;
+ }
+
+ eeprom_read_mode(netdev, 0xd4, 0);
+ eeprom_read_mode(netdev, 0xf2, 1);
+ eeprom_read_mode(netdev, 0x10d, 2);
+
+ if (e->version < 0x3003) {
+ eeprom_read(netdev, 0xec, &val);
+ e->g2_k3[0] = val & 7;
+ e->g2_v3[0] = (val >> 3) & 7;
+
+ eeprom_read(netdev, 0xed, &val);
+ e->g2_k3[1] = val & 7;
+ e->g2_v3[1] = (val >> 3) & 7;
+ }
+
+ e->cal.val3 = 4;
+ e->cal.val2 = 1;
+ e->cal.val1 = 1;
+ e->cal.sel = 0;
+
+ tmp = 0x128;
+ for(i = 0; i < e->count; i += 2) {
+ eeprom_read(netdev, tmp++, &val);
+ e->controls[i] = (val >> 8) & 0xff;
+ e->controls[i+1] = val & 0xff;
+ }
+
+ if (e->version <= 0x3002) {
+ e->noise_floor[0] = -54;
+ e->noise_floor[1] = -1;
+ e->noise_floor[2] = -1;
+
+ e->thresh[0] = 15;
+ e->thresh[1] = 28;
+ e->thresh[2] = 28;
+ }
+
+ return;
+}
+
+unsigned int eeprom_read_info(struct net_device *netdev)
+{
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+ struct eeprom_info *e = &pdata->eeinfo;
+
+ e->pwr_diff = 15;
+ e->scale_14 = 15;
+
+ printk(KERN_DEBUG"atheros: eeprom version %x\n",
+ e->version);
+ if (e->version >= 0x3003) {
+ printk(KERN_DEBUG"atheros: >= 3.3\n");
+ eeprom_read_info3_3(netdev);
+ return 1;
+ } else {
+ /* to be added yet XXX
+ eeprom_read_info3(netdev);
+ */
+ return 0;
+ }
+
+ return 1;
+}
+
+
+/* validates EEPROM checksum */
+unsigned int eeprom_chksum(struct net_device *netdev)
+{
+ unsigned int sum = 0, i, val;
+
+ for (i = 0; i < 832; i++) {
+ if (!eeprom_read(netdev, 0xc0 + i, &val))
+ return 0;
+ sum ^= val;
+ }
+
+ if (sum != 0xffff)
+ return 0;
+
+ return 1;
+}
+
+/* initialize EEPROM and prepare the chipset */
+unsigned int eeprom_init(struct net_device *netdev)
+{
+ unsigned int size;
+ unsigned int v;
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+
+ if (!eeprom_read(netdev, 0xc1, &v)) {
+ printk(KERN_ERR"atheros: eeprom version read failed!\n");
+ return 0;
+ }
+ pdata->eeinfo.version = v;
+
+ printk(KERN_DEBUG"atheros: eeprom_init eeprom version %x\n",
+ pdata->eeinfo.version);
+ if (pdata->eeinfo.version < 0x3002) {
+ printk(KERN_ERR"atheros: unsupported eeprom version\n");
+ return 0;
+ }
+
+ size = ath_reg_read(netdev, 0x4010);
+ size = (size & 0x18) >> 3;
+
+ if (size != 2) {
+ printk(KERN_ERR"atheros: invalid eeprom size!\n");
+ return 0;
+ }
+ if (eeprom_read(netdev, 0x3f, &v) == 0) {
+ printk(KERN_ERR"atheros: cant read eeprom 3f bit\n");
+ return 0;
+ }
+ pdata->eeinfo.rdonly = v;
+ printk(KERN_DEBUG"atheros: eeprom rdonly flag : %x\n", v);
+ if (!eeprom_chksum(netdev)) {
+ printk(KERN_ERR"atheros: bad eeprom checksum!\n");
+ return 0;
+ }
+
+
+ return 1;
+}
+
+/* read chipset capabilities */
+unsigned int eeprom_read_caps(struct net_device *netdev)
+{
+ if (!eeprom_read_info(netdev))
+ return 0;
+
+ /* TODO: read calibration info here */
+ return 1;
+}
+
+/* just as the name says. reads hardware MAC address directly from
+ * EEPROM */
+unsigned int eeprom_read_mac(struct net_device *netdev, unsigned char *mac)
+{
+ unsigned int total = 0, i, val;
+
+ if (mac == NULL)
+ return 0;
+
+ for (i = 0; i < 3; i++) {
+ if (!eeprom_read(netdev, 0x1f - i, &val))
+ return 0;
+ total += val;
+ mac[2*i] = val >> 8;
+ mac[2*i + 1] = val & 0xff;
+ }
+
+ if (total == 0 || total == 3*0xffff)
+ return 0;
+
+ return 1;
+}
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/eeprom.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/eeprom.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/eeprom.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/eeprom.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,209 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _EEPROM_H
+#define _EEPROM_H
+
+struct cal_info {
+ unsigned short sel;
+ unsigned short val1;
+ unsigned short val2;
+ unsigned short val3;
+};
+
+struct chan_data {
+ unsigned short chan_val;
+ unsigned short lower_limit;
+ unsigned short upper_limit;
+ unsigned short count;
+ unsigned short clk_values[11];
+ short pwr_values[11];
+};
+
+struct power_info {
+ unsigned short pwr1;
+ unsigned short pwr2;
+ unsigned short pwr3;
+ unsigned short pwr4;
+ unsigned short pwr5;
+};
+
+struct power_modes {
+ unsigned short num11a;
+ unsigned short num11b;
+ unsigned short num11g;
+
+ struct power_info pwr11a[8];
+ struct power_info pwr11b[2];
+ struct power_info pwr11g[3];
+};
+
+struct eestrct {
+ unsigned short val1;
+ unsigned short val2;
+ unsigned char flg;
+};
+
+struct chip_data {
+ unsigned short val1;
+ unsigned short val2;
+ unsigned short vals[4];
+ short vals2[4];
+};
+
+struct chip_chan_data {
+ unsigned short chanval;
+ short pwr_upper_limit;
+ struct chip_data cdata[4];
+};
+
+struct chip_chan_pwr_data {
+ unsigned short *pchans;
+ unsigned short chcount;
+ unsigned short val;
+ struct chip_chan_data *pchandata;
+};
+
+struct eeprom_info {
+ unsigned short version;
+ unsigned short rdonly;
+ unsigned short regdomain;
+ unsigned short devtyp;
+
+ unsigned short mode_a;
+ unsigned short mode_b;
+ unsigned short mode_g;
+
+ unsigned short turbo5_pwr_limit;
+ unsigned short turbo2_pwr_limit;
+
+ unsigned short ext5g;
+ unsigned short xr5_pwr_limit;
+ unsigned short xr2_pwr_limit;
+
+ unsigned short disabled_turbo5;
+ unsigned short disabled_turbo2;
+ unsigned short rfkill;
+
+ unsigned char antgain_limit[2];
+
+ unsigned char pwr_diff; /* cck ofdm delta */
+ unsigned short pwr_gain;
+
+ unsigned char clk_32khz;
+
+ unsigned short pwr_start;
+ unsigned short fixed5;
+ unsigned short fixed2;
+ unsigned short scale_14;
+ unsigned short mp;
+ unsigned short ear;
+
+
+ unsigned short switchval[3];
+ unsigned short txrx[3];
+ unsigned short txendon[3];
+ unsigned short thresh[3];
+ unsigned short txendoff[3];
+ unsigned short txfrmctrl[3];
+ char adcsize[3];
+ char pgasize[3];
+ unsigned short noise_floor[3];
+
+ unsigned short xlna_gain[3];
+ unsigned short xgain[3];
+ unsigned short xpd[3];
+ unsigned short antctrl[11][3];
+ unsigned short detbkoff[3];
+ unsigned short igain[3];
+ unsigned short rxtx_epsilon[3]; /* error margin */
+
+
+ unsigned short g5_k1;
+ unsigned short g5_v1;
+ unsigned short g5_k2;
+ unsigned short g5_v2;
+ unsigned short g5_k3;
+ unsigned short g5_v3;
+ unsigned short g5_k4;
+ unsigned short g5_v4;
+
+ unsigned short g2_k1;
+ unsigned short g2_v1;
+ unsigned short g2_k2g;
+ unsigned short g2_v2g;
+ unsigned short g2_k3[2];
+ unsigned short g2_v3[2];
+
+ unsigned short count;
+ unsigned short controls[32];
+
+ unsigned short ical[2];
+ unsigned short qcal[2];
+
+ unsigned short cal11g[3];
+ unsigned short cal11b[3];
+
+
+ struct cal_info cal;
+
+ unsigned short num_ch5;
+ unsigned short ch_11a[10];
+ struct chan_data chans_11a[10];
+
+ unsigned short num_ch2;
+ unsigned short ch_11g[3];
+ unsigned short ch_11b[3];
+ struct chan_data chans_11g[3];
+ struct chan_data chans_11b[3];
+
+ struct power_modes pmodes;
+
+ struct eestrct rsomething[128];
+ struct chip_chan_pwr_data pvals[3];
+};
+
+unsigned int ath_eeprom_read(struct net_device *,
+ unsigned int x, unsigned int *);
+
+unsigned int ath_timed_read(struct net_device *,
+ unsigned int, unsigned int, unsigned int);
+
+unsigned int eeprom_read(struct net_device *,
+ unsigned int, unsigned int *);
+
+unsigned int eeprom_init(struct net_device *);
+
+unsigned int eeprom_read_mac(struct net_device *, unsigned char *);
+
+unsigned int eeprom_read_caps(struct net_device *);
+
+
+#endif
+
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
_______________________________________________
Kernel-mentors mailing list
Kernel-mentors@selenic.com
http://selenic.com/mailman/listinfo/kernel-mentors
^ permalink raw reply
* Re: atheros driver - desc
From: Michael Renzmann @ 2005-08-05 10:14 UTC (permalink / raw)
To: Mateusz Berezecki; +Cc: kernel-mentors, netdev
In-Reply-To: <42F2D523.9020702@gmail.com>
Hi.
Mateusz Berezecki wrote:
> Im sending a series of 8 patches splitted and diffed as in
> SubmittingPatches documentation.
Patch 4/8 is missing here.
Bye, Mike
--
Use PGP/GPG!
My key: http://keys.indymedia.org/cgi-bin/lookup?op=get&search=62C29B94
Fingerprint: BC2E 79BF 0C8F 0282 864B 9CEC 8343 5169 62C2 9B94
^ permalink raw reply
* PHP netem
From: Amine ELKCHAOU @ 2005-08-05 10:03 UTC (permalink / raw)
To: netdev
Hello,
I heared about a user interface for the netem developped with PHP, and I'm
interested on it, but can't find it. If you have the link pionting on it it
would be great if you send me it.
Thanks.
----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.
^ permalink raw reply
* Re: [PATCH 0/6] nfnetlink / ctnetlink fixes + updates
From: David S. Miller @ 2005-08-05 9:13 UTC (permalink / raw)
To: laforge; +Cc: netdev, netfilter-devel
In-Reply-To: <20050802105427.GG4158@rama.de.gnumonks.org>
From: Harald Welte <laforge@netfilter.org>
Date: Tue, 2 Aug 2005 12:54:27 +0200
> I know you're travelling, but I already have this pile of patches/fixes
> for nfnetlink and ctnetlink. I'm sorry to keep patch-bombing you, but
> I think it's better we find those issues right now (before it is in mainline)
> rather than later, when it already is in the mainline tree.
>
> Please apply in sequential order (and also apply the nf_log patch you
> seem to have missed a short time ago).
Applied to net-2.6.14, thanks.
^ permalink raw reply
* Re: atheros driver (1/8)
From: Matt Mackall @ 2005-08-05 4:09 UTC (permalink / raw)
To: Mateusz Berezecki; +Cc: kernel-mentors, netdev
In-Reply-To: <42F2D58D.8040807@gmail.com>
Some initial comments:
- you should include a description of each patch in the message
- you should use more descriptive subjects, eg
[PATCH 1/8] atheros: Kconfig bits
--
Mathematics is the supreme nostalgia of our time.
^ permalink raw reply
* argh... ;/
From: Mateusz Berezecki @ 2005-08-05 3:04 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
I accidentaly posted the patches as MIME attachments... its 5:03 am here
already. Sorry guys.
I can resubmit if you want. I just dont want do that now and not trash
your mailboxes
Mateusz
^ permalink raw reply
* atheros driver (8/8)
From: Mateusz Berezecki @ 2005-08-05 3:01 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: atheros5212-8.patch --]
[-- Type: text/x-patch, Size: 29238 bytes --]
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/other.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/other.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/other.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/other.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,57 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+
+
+int ath_phy_disable(struct net_device *netdev)
+{
+ return ath_set_reset_register(netdev, AR5212_RC_BB);
+}
+
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/powermodes.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/powermodes.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/powermodes.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/powermodes.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,155 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+//#include "atheros_devops.h"
+//#include "atheros_regops.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+
+
+/* don return power mode from private device data.
+ * use hardware instead. thats better */
+POWER_MODE ath_get_power_mode(struct net_device *netdev)
+{
+ unsigned int mode = ath_reg_read(netdev, AR5212_SCR);
+ mode &= (AR5212_SCR_SLE >> 16);
+ return mode;
+}
+
+/* zZzZ... */
+void ath_pmode_fullsleep(struct net_device *netdev, int set)
+{
+ ath_reg_enable(netdev, AR5212_STA_ID1, AR5212_STA_ID1_PWR_SV);
+
+ if (set)
+ ath_reg_write(netdev, AR5212_SCR,
+ AR5212_SCR_SLE_SLP);
+ return;
+}
+
+/* oh, my god, its 6 am already... */
+unsigned int ath_pmode_awake(struct net_device *netdev, int set)
+{
+ int i;
+ unsigned int tmp;
+
+ if (set) {
+ ath_reg_write(netdev, 0x4004, 0);
+ udelay(10);
+
+ for (i = 10; i != 0; i--) {
+ tmp = ath_reg_read(netdev, 0x4010);
+ if ((tmp & 0x00010000) == 0)
+ break;
+ udelay(200);
+ ath_reg_write(netdev, 0x4004, 0);
+ }
+
+ if (i == 0) {
+ printk(KERN_DEBUG"atheros_pci: we are unlucky ;-(\n");
+ return 0;
+ }
+ }
+
+ ath_reg_disable(netdev, 0x8004, 0x00040000);
+ return 1;
+}
+
+/* i dont know how it differs from fullsleep but OpenBSD doesnt have it:D
+ *
+ * note: thats probably used in power saving situations... */
+void ath_pmode_netsleep(struct net_device *netdev,
+ int set, unsigned short sleepduration)
+{
+ ath_reg_enable(netdev, AR5212_STA_ID1,
+ AR5212_STA_ID1_PWR_SV);
+
+ if (set)
+ ath_reg_write(netdev, AR5212_SCR,
+ AR5212_SCR_SLE_ALLOW | sleepduration);
+ return;
+}
+
+
+/* set some power mode. nothing magical happens here */
+unsigned int ath_set_power_mode(struct net_device *netdev,
+ POWER_MODE mode, int set,
+ unsigned short sleep_duration)
+{
+ unsigned int ret = 0;
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+
+ switch (mode) {
+ case PMODE_FULL_SLEEP:
+ ret = 1;
+ ath_pmode_fullsleep(netdev, set);
+ break;
+
+ case PMODE_AWAKE:
+ ret = ath_pmode_awake(netdev, set);
+ break;
+
+ case PMODE_NETWORK_SLEEP:
+ ath_pmode_netsleep(netdev,
+ set, sleep_duration);
+ ret = 1;
+ break;
+
+ default:
+ return 0;
+ }
+
+ pdata->pmode = mode;
+ return ret;
+}
+
+void ath_update_txpow(struct net_device *netdev)
+{
+
+}
+
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/powermodes.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/powermodes.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/powermodes.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/powermodes.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,57 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#ifndef _POWERMODE_H
+#define _POWERMODE_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "regops.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+
+POWER_MODE ath_get_power_mode(struct net_device *);
+unsigned int ath_set_power_mode(struct net_device *,
+ POWER_MODE, int, unsigned short);
+
+#endif
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/regops.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/regops.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/regops.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/regops.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,83 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+
+
+/* write to hardware register. thats for little endian hosts
+ * right now. I/or someone else has to add support for big endians */
+void ath_reg_write(struct net_device *netdev,
+ unsigned int reg, unsigned int val)
+{
+ *((volatile unsigned int *)(netdev->mem_start + reg)) = val;
+ return;
+}
+
+/* reads from hw. same note as above */
+unsigned int ath_reg_read(struct net_device *netdev, unsigned int reg)
+{
+ return (*((volatile u_int32_t *)(netdev->mem_start + reg)));
+}
+
+/* just a wrapper. look above */
+void ath_reg_enable(struct net_device *netdev,
+ unsigned int reg, unsigned int flags)
+{
+ unsigned int tmp = ath_reg_read(netdev, reg);
+ ath_reg_write(netdev, reg, tmp | flags);
+}
+
+/* look above */
+void ath_reg_disable(struct net_device *netdev,
+ unsigned int reg, unsigned int flags)
+{
+ unsigned int val = ath_reg_read(netdev, reg);
+ val = val & ~flags;
+ ath_reg_write(netdev, reg, val);
+}
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/regops.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/regops.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/regops.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/regops.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,62 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+
+#ifndef _REGOPS_H
+#define _REGOPS_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+
+void ath_reg_write(struct net_device *, unsigned int, unsigned int);
+unsigned int ath_reg_read(struct net_device *, unsigned int);
+void ath_reg_enable(struct net_device *, unsigned int, unsigned int);
+void ath_reg_disable(struct net_device *,unsigned int, unsigned int);
+
+
+
+
+#endif
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/transmit_receive.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/transmit_receive.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/transmit_receive.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/transmit_receive.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,433 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+//#include "atheros_devops.h"
+//#include "atheros_regops.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+
+int ath_stopdmarecv(struct net_device *netdev)
+{
+ ath_reg_write(netdev, AR5212_CR, AR5212_CR_RXD);
+ if (ath_timed_read(netdev, AR5212_CR, AR5212_CR_RXE, 0) == 0) {
+ printk(KERN_DEBUG"atheros: failed to stop DMA engine.\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+void ath_stoppcurecv(struct net_device *netdev)
+{
+ ath_reg_enable(netdev, AR5212_DIAG_SW, AR5212_DIAG_SW_DIS_RX);
+}
+
+/* TODO: add routines for starting dma/pcu recv */
+
+
+int ath_startrecv(struct net_device *netdev)
+{
+ /* XXX TODO fix it asap ;-) that one comes directly
+ * from madwifi source */
+#if 0
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ struct ath_buf *bf;
+
+ if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) {
+ sc->sc_rxbufsize = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
+ } else {
+ sc->sc_rxbufsize = roundup(sizeof(struct ieee80211_frame) +
+ dev->mtu + IEEE80211_CRC_LEN +
+ (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN +
+ IEEE80211_WEP_CRCLEN), sc->sc_cachelsz);
+ }
+
+ p->rxlink = NULL;
+ STAILQ_FOREACH(bf, &p->rxbuf, bf_list) {
+ int error = ath_rxbuf_init(sc, bf);
+ if (error != 0) {
+ printk(KERN_DEBUG"atheros: startrecv failed\n");
+ return error;
+ }
+ }
+
+ bf = STAILQ_FIRST(&p->rxbuf);
+ ath_putrxbuf(netdev, bf->bf_daddr);
+ ath_rxena(ah); /* enable recv descriptors */
+ ath_mode_init(dev); /* set filters, etc. */
+ ath_startpcurecv(ah); /* re-enable PCU/DMA engine */
+#endif
+ return 0;
+}
+
+void ath_setrxfilter(struct net_device *netdev, unsigned int mask)
+{
+ unsigned int val;
+
+ ath_reg_write(netdev, AR5212_RX_FILTER, mask & 0xff);
+ val = 0;
+
+ if (mask & 0x200)
+ val |= 0x20;
+
+ if (mask & 0x100)
+ val |= 0x10;
+
+ ath_reg_write(netdev, AR5212_PHY_ERR_FIL, val);
+
+ if (val)
+ ath_reg_enable(netdev, AR5212_RXCFG, AR5212_RXCFG_ZLFDMA);
+ else
+ ath_reg_disable(netdev, AR5212_RXCFG, AR5212_RXCFG_ZLFDMA);
+
+}
+
+void ath_draintxq(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ int i;
+
+ /* XXX return value */
+ if (!p->invalid) {
+ /* don't touch the hardware if marked invalid */
+ /*
+ (void) ath_stoptxdma(netdev, p->bhalq);
+
+ for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+ if (ATH_TXQ_SETUP(sc, i))
+ ath_tx_stopdma(netdev, &p->txq[i]);
+ }
+ */
+ }
+ netdev->trans_start = jiffies;
+
+ netif_start_queue(netdev);
+ /* XXX
+ for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+ if (ATH_TXQ_SETUP(netdev, i))
+ ath_tx_draintxq(netdev, &p->txq[i]);
+ }
+ sc->sc_tx_timer = 0;
+ */
+}
+
+void ath_stoprecv(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ ath_stoppcurecv(netdev); /* disable PCU */
+ ath_setrxfilter(netdev, 0); /* clear recv filter */
+ ath_stopdmarecv(netdev); /* disable DMA engine */
+ udelay(3); /* 3ms is long enough for 1 frame */
+
+ p->rxlink = NULL;
+}
+
+
+unsigned int ath_setup_xtx_desc(struct net_device *netdev, struct ath_desc *desc,
+ unsigned int txrate1, unsigned int txtries1,
+ unsigned int txrate2, unsigned int txtries2,
+ unsigned int txrate3, unsigned int txtries3)
+{
+ if (txtries1 != 0) {
+ desc->u.tx.ctl2 |= (txtries1 << 20) & 0xf00000;
+ desc->u.tx.ctl3 |= (txrate1 << 5);
+ }
+ if (txtries2 != 0) {
+ desc->u.tx.ctl2 |= (txtries2 << 24) & 0xf000000;
+ desc->u.tx.ctl3 |= (txrate2 << 10);
+ }
+ if (txtries3 != 0) {
+ desc->u.tx.ctl2 |= (txtries3 << 28);
+ desc->u.tx.ctl3 |= (txrate3 << 15);
+ }
+
+ return 1;
+}
+
+unsigned int ath_set_tx_queue_params(struct net_device *netdev,
+ unsigned int q, struct tx_queue_info *txi)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ if (p->txq_info[q].tqi_type == 0)
+ return 0;
+
+ /* Q: why just do not memcopy it ? */
+ p->txq_info[q].tqi_ver = txi->tqi_ver;
+ p->txq_info[q].tqi_subtype = txi->tqi_subtype;
+ p->txq_info[q].tqi_qflags = txi->tqi_qflags;
+ p->txq_info[q].tqi_priority = txi->tqi_priority;
+ p->txq_info[q].tqi_aifs = txi->tqi_aifs;
+ p->txq_info[q].tqi_cwmin = txi->tqi_cwmin;
+ p->txq_info[q].tqi_cwmax = txi->tqi_cwmax;
+ p->txq_info[q].tqi_cbrPeriod = txi->tqi_cbrPeriod;
+ p->txq_info[q].tqi_cbrOverflowLimit = txi->tqi_cbrOverflowLimit;
+ p->txq_info[q].tqi_burstTime = txi->tqi_burstTime;
+ p->txq_info[q].tqi_readyTime = txi->tqi_readyTime;
+
+ switch (txi->tqi_subtype) {
+ case WME_AC_VI:
+ case WME_AC_VO:
+ case WME_UPSD:
+ if (p->txq_info[q].tqi_type == TX_QUEUE_DATA)
+ p->txq_info[q].tqi_flags = 1;
+ break;
+ default:
+ break;
+ }
+
+ return 1;
+}
+
+unsigned int ath_setup_tx_queue(struct net_device *netdev,
+ unsigned int type, struct tx_queue_info *txi)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ int q;
+
+ switch (type) {
+ case 2:
+ q = 9;
+ break;
+ default:
+ return 0;
+ }
+
+ memset(&p->tx_queues[q], 0, sizeof(struct tx_queue_info));
+ p->txq_info[q].tqi_type = type;
+
+ if (txi != NULL) {
+ ath_set_tx_queue_params(netdev, q, txi);
+ }
+
+ p->intr_mask |= 1 << q;
+ return q;
+}
+
+struct tx_queue *ath_txq_setup(struct net_device *netdev,
+ int qtype, int subtype)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ struct tx_queue_info qi;
+ int qnum;
+
+ memset(&qi, 0, sizeof(qi));
+ qi.tqi_subtype = subtype;
+ qi.tqi_aifs = 0xffffffff;
+ qi.tqi_cwmin = 0xffffffff;
+ qi.tqi_cwmax = 0xffffffff;
+ qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE;
+ qnum = ath_setup_tx_queue(netdev, qtype, &qi);
+ if (qnum == -1) {
+ return NULL;
+ }
+
+ if (p->tx_setup & (1 << qnum)) {
+ struct tx_queue *txq = &p->tx_queues[qnum];
+
+ txq->axq_qnum = qnum;
+ txq->axq_depth = 0;
+ txq->axq_intrcnt = 0;
+ txq->axq_link = NULL;
+ /* XXX
+ STAILQ_INIT(&txq->axq_q);
+ ATH_TXQ_LOCK_INIT(sc, txq);
+ */
+ p->tx_setup |= 1<<qnum;
+ }
+ return &p->tx_queues[qnum];
+}
+
+
+/*
+ * RECEIVE PART
+ */
+
+unsigned int ath_get_rx_desc(struct net_device *netdev,
+ unsigned int descriptor)
+{
+ return ath_reg_read(netdev, AR5212_RXDP);
+}
+
+void ath_set_rx_desc(struct net_device *netdev,
+ unsigned int descriptor)
+{
+ ath_reg_write(netdev, AR5212_RXDP, descriptor);
+ ath_reg_read(netdev, AR5212_RXDP);
+}
+
+void ath_enable_receive(struct net_device *netdev)
+{
+ ath_reg_write(netdev, AR5212_CR, AR5212_CR_RXE);
+}
+
+
+unsigned int ath_stop_dma_recv(struct net_device *netdev)
+{
+ ath_reg_write(netdev, AR5212_CR, AR5212_CR_RXD);
+ if (!ath_timed_read(netdev, AR5212_CR, AR5212_CR_RXE, 0)) {
+ printk(KERN_DEBUG"atheros: failed to stop DMA\n");
+ return 0;
+ }
+ return 1;
+}
+
+
+void ath_set_multicast_fltr(struct net_device *netdev,
+ unsigned int fil0, unsigned int fil1)
+{
+ ath_reg_write(netdev, AR5212_MCAST_FIL0, fil0);
+ ath_reg_write(netdev, AR5212_MCAST_FIL1, fil1);
+}
+
+unsigned int ath_set_multicast_filter_idx(struct net_device *netdev, unsigned int idx)
+{
+ unsigned int val;
+
+ if (idx >= 64)
+ return 0;
+
+ if (idx >= 32) {
+ val = ath_reg_read(netdev, AR5212_MCAST_FIL1);
+ ath_reg_write(netdev, AR5212_MCAST_FIL1, (val | (1<<(idx-32))));
+ } else {
+ val = ath_reg_read(netdev, AR5212_MCAST_FIL0);
+ ath_reg_write(netdev, AR5212_MCAST_FIL0, (val | (1<<idx)));
+ }
+ return 1;
+}
+
+unsigned int ath_clr_multicast_fltr_idx(struct net_device *netdev, unsigned int idx)
+{
+ unsigned int val;
+
+ if (idx >= 64)
+ return 0;
+
+ if (idx >= 32) {
+ val = ath_reg_read(netdev, AR5212_MCAST_FIL1);
+ ath_reg_write(netdev, AR5212_MCAST_FIL1, (val &~ (1<<(idx-32))));
+ } else {
+ val = ath_reg_read(netdev, AR5212_MCAST_FIL0);
+ ath_reg_write(netdev, AR5212_MCAST_FIL0, (val &~ (1<<idx)));
+ }
+ return 1;
+}
+
+unsigned int ath_get_rx_filter(struct net_device *netdev)
+{
+ unsigned int bits = ath_reg_read(netdev, AR5212_RX_FILTER);
+ unsigned int phy = ath_reg_read(netdev, AR5212_PHY_ERR_FIL);
+
+ if (phy & AR5212_PHY_ERR_FIL_RADAR)
+ bits |= RX_FILTER_PHYRADAR;
+ if (phy & (AR5212_PHY_ERR_FIL_OFDM|AR5212_PHY_ERR_FIL_CCK))
+ bits |= RX_FILTER_PHYERR;
+ return bits;
+}
+
+unsigned int ath_setup_rx_desc(struct net_device *netdev, struct ath_desc *ds,
+ unsigned int size, unsigned int flags)
+{
+ ds->ctl0 = 0;
+ ds->ctl1 = size & 0xfff;
+ if (ds->ctl1 != size) {
+ return 0;
+ }
+
+ if (flags & 0x20)
+ ds->ctl1 |= 0x2000;
+
+ ds->u.rx.status0 = ds->u.rx.status1 = 0;
+
+ return 1;
+}
+
+int ath_proc_rx_desc(struct net_device *netdev, struct ath_desc *ds,
+ unsigned int cx, struct ath_desc *nds)
+{
+ if ((ds->u.rx.status1 & 1) == 0)
+ return EINPROGRESS;
+
+ if ((nds->u.rx.status1 & 1) == 0 && ath_reg_read(netdev, AR5212_RXDP) == cx)
+ return EINPROGRESS;
+
+ ds->s.rxstat.rs_datalen = ds->u.rx.status0 & 0xfff;
+ ds->s.rxstat.rs_tstamp = (ds->u.rx.status1 & 0x7fff0000) >> 16;
+ ds->s.rxstat.rs_status = 0;
+
+ if ((ds->u.rx.status1 & 2) == 0) {
+ if (ds->u.rx.status1 & 4) /* CRC Error */
+ ds->s.rxstat.rs_status |= RXERR_CRC;
+ if (ds->u.rx.status1 & 8) /* crc decrypt error */
+ ds->s.rxstat.rs_status |= RXERR_DECRYPT;
+ if (ds->u.rx.status1 & 32) /* MIC error */
+ ds->s.rxstat.rs_status |= RXERR_MIC;
+ if (ds->u.rx.status1 & 16) { /* PHY error */
+ unsigned int phyerr;
+ //ds->s.rxstat.rs_status |= RXERR_PHY;
+ //phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
+ //ds->s.rxstat.rs_phyerr = phyerr;
+ }
+ }
+
+
+ ds->s.rxstat.rs_rssi = (ds->u.rx.status0 & 0x0ff00000) >> 20;
+ if (ds->u.rx.status1 & 0x100)
+ ds->s.rxstat.rs_keyix = (ds->u.rx.status1 & 0xfe00) >> 9;
+ else
+ ds->s.rxstat.rs_keyix = 0xff;
+
+
+ ds->s.rxstat.rs_rate = (ds->u.rx.status0 & 0xf8000) >> 15;
+ ds->s.rxstat.rs_antenna = (ds->u.rx.status0 & 0xf0000000) >> 28;
+ ds->s.rxstat.rs_more = (ds->u.rx.status0 & 0x1000) ? 1 : 0;
+
+ return 1;
+}
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/transmit_receive.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/transmit_receive.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/transmit_receive.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/transmit_receive.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,62 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+
+#ifndef _TRANSMIT_RECEIVE_H
+#define _TRANSMIT_RECEIVE_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+//#include "atheros_devops.h"
+//#include "atheros_regops.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+
+unsigned int ath_setup_xtx_desc(struct net_device *, struct ath_desc *,
+ unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int);
+
+
+#endif
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
_______________________________________________
Kernel-mentors mailing list
Kernel-mentors@selenic.com
http://selenic.com/mailman/listinfo/kernel-mentors
^ permalink raw reply
* atheros driver (7/8)
From: Mateusz Berezecki @ 2005-08-05 3:00 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: atheros5212-7.patch --]
[-- Type: text/x-patch, Size: 18742 bytes --]
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/keys.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/keys.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/keys.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/keys.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,268 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+//#include "atheros_devops.h"
+//#include "atheros_regops.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+
+
+unsigned int ath_keycache_valid(struct net_device *netdev,
+ unsigned short entry)
+{
+ struct atheros_priv *pdata;
+ unsigned int val;
+
+ pdata = ieee80211_priv(netdev);
+
+ if (entry > pdata->max_keycache)
+ return 0;
+
+ val = ath_reg_read(netdev, 0x8800 + entry * 32 + 28);
+
+ if (val & 0x8000)
+ return 1;
+
+ return 0;
+}
+
+unsigned int ath_reset_keycache(struct net_device *netdev,
+ unsigned short entry)
+{
+ struct atheros_priv *pdata;
+ unsigned int keytype;
+
+ pdata = ieee80211_priv(netdev);
+
+ if (entry > pdata->keycache_size)
+ return 0;
+
+ keytype = ath_reg_read(netdev, (entry * 32) + 0x8814);
+
+ ath_reg_write(netdev, (entry * 32) + 0x8800, 0);
+ ath_reg_write(netdev, (entry * 32) + 0x8804, 0);
+ ath_reg_write(netdev, (entry * 32) + 0x8808, 0);
+ ath_reg_write(netdev, (entry * 32) + 0x880c, 0);
+ ath_reg_write(netdev, (entry * 32) + 0x8810, 0);
+ ath_reg_write(netdev, (entry * 32) + 0x8814, 7);
+ ath_reg_write(netdev, (entry * 32) + 0x8818, 0);
+ ath_reg_write(netdev, (entry * 32) + 0x881c, 0);
+
+ if (keytype != 4)
+ return 1;
+
+ if (!pdata->ext_keycache)
+ return 1;
+
+ ath_reg_write(netdev, ((entry + 64) * 32) + 0x8800, 0);
+ ath_reg_write(netdev, ((entry + 64) * 32) + 0x8804, 0);
+ ath_reg_write(netdev, ((entry + 64) * 32) + 0x8808, 0);
+ ath_reg_write(netdev, ((entry + 64) * 32) + 0x880c, 0);
+
+ return 1;
+}
+
+unsigned int ath_set_keycache_entry_mac(struct net_device *netdev,
+ unsigned short entry, unsigned char *mac)
+{
+ struct atheros_priv *pdata;
+ unsigned int mac1, mac2;
+
+ pdata = ieee80211_priv(netdev);
+
+ if (entry > pdata->max_keycache)
+ return 0;
+
+ if (mac == NULL) {
+ mac1 = 0;
+ mac2 = 0;
+ } else {
+ mac1 = mac[5] << 8;
+ mac1 |= mac[4];
+
+ mac2 = mac[3] << 24;
+ mac2 |= mac[2] << 16;
+ mac2 |= mac[1] << 8;
+ mac2 |= mac[0];
+
+ mac2 = mac2 >> 1;
+ mac2 |= ((mac1 & 1)<< 31);
+
+ mac1 = mac1 >> 1;
+ }
+
+ ath_reg_write(netdev, (entry * 32) + 0x8800 + 24, mac2);
+ ath_reg_write(netdev, (entry * 32) + 0x8800 + 28, mac1 | 0x80);
+
+ return 1;
+}
+
+unsigned int ath_set_keycache_entry(struct net_device *netdev,
+ unsigned short entry, struct keyval *kv,
+ unsigned char *mac, int num)
+{
+ int flg = (num == 1) ? 0xffffffff : 0;
+ int cipher_opt;
+ int newentry;
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+ unsigned int part1, part2, part3, part4, part5;
+
+
+ flg &= 0xaaaaaaaa;
+
+ if (entry > pdata->max_keycache)
+ return 0;
+
+ switch (kv->kv_type) {
+ case CIPHER_AES_OCB:
+ cipher_opt = 5;
+ break;
+
+ case CIPHER_AES_CCM:
+ /* fixme TODO FIXME */
+ return 0;
+// break;
+
+ case CIPHER_TKIP:
+ cipher_opt = 4;
+
+ if ((entry + 0x40) > pdata->max_keycache)
+ return 0;
+
+ break;
+
+ case CIPHER_WEP:
+ if (kv->kv_len <= 4)
+ return 0;
+
+ cipher_opt = 0;
+
+ if (kv->kv_len <= 5)
+ break;
+
+ cipher_opt = (kv->kv_len == 14) ? 0 : 0xffffffff;
+ cipher_opt &= 0xfffffffe;
+ cipher_opt += 3;
+
+ break;
+
+ case CIPHER_CLR:
+ cipher_opt = 7;
+ break;
+
+ default:
+ return 0;
+ }
+
+ part1 = (kv->kv_val[0] | (kv->kv_val[1] << 8) |
+ (kv->kv_val[2] << 16) | (kv->kv_val[3] << 24)) ^ flg;
+
+
+ part2 = ((kv->kv_val[4] | (kv->kv_val[5] << 8)) ^ flg) & 0xffff;
+
+ part4 = ((kv->kv_val[6] | (kv->kv_val[7] << 8) |
+ (kv->kv_val[8] << 16) | (kv->kv_val[9] << 24)) ^ flg);
+
+ part3 = ((kv->kv_val[10] | (kv->kv_val[11] << 8)) ^ flg) & 0xffff;
+
+ part5 = (kv->kv_val[12] | (kv->kv_val[13] << 8) |
+ (kv->kv_val[14] << 16) | (kv->kv_val[15] << 24)) ^ flg;
+
+ if (kv->kv_len <= 13)
+ part5 &= 0xff;
+
+
+ /* if statement needs fixing */
+ if (cipher_opt == 4 && pdata->turbo != 0) {
+ newentry = (entry << 5);
+
+ ath_reg_write(netdev, 0x8800 + (entry << 5), ~part1);
+ ath_reg_write(netdev, 0x8804 + newentry, ~part2);
+ ath_reg_write(netdev, 0x8808 + newentry, part4);
+ ath_reg_write(netdev, 0x880c + newentry, part3);
+ ath_reg_write(netdev, 0x8810 + newentry, part5);
+ ath_reg_write(netdev, 0x8814 + newentry, 4);
+
+ ath_set_keycache_entry_mac(netdev, entry, mac);
+
+ ath_reg_write(netdev, 0x8800 + ((entry + 0x40) << 5),
+ (kv->kv_mic[0] | (kv->kv_mic[1] << 8) |
+ (kv->kv_mic[2] << 16) | (kv->kv_mic[3] << 24)));
+
+ ath_reg_write(netdev, 0x8804 + ((entry + 0x40) << 5), 0);
+
+ ath_reg_write(netdev, 0x8808 + ((entry + 0x40) << 5),
+ ( kv->kv_mic[4] | (kv->kv_mic[5] << 8) |
+ (kv->kv_mic[6] << 16) | (kv->kv_mic[7] << 24) ) );
+
+ ath_reg_write(netdev, 0x880c + ((entry + 0x40) << 5), 0);
+ ath_reg_write(netdev, 0x8810 + ((entry + 0x40) << 5), 0);
+ ath_reg_write(netdev, 0x8814 + ((entry + 0x40) << 5), 7);
+ ath_reg_write(netdev, 0x8818 + ((entry + 0x40) << 5), 0);
+ ath_reg_write(netdev, 0x881c + ((entry + 0x40) << 5), 0);
+
+ ath_reg_write(netdev, 0x8800 + newentry, part1);
+ ath_reg_write(netdev, 0x8800 + newentry, part2);
+
+ return 1;
+ } else {
+ ath_reg_write(netdev, 0x8800 + (entry << 5), part1);
+ ath_reg_write(netdev, 0x8804 + (entry << 5), part2);
+ ath_reg_write(netdev, 0x8808 + (entry << 5), part4);
+ ath_reg_write(netdev, 0x880c + (entry << 5), part3);
+ ath_reg_write(netdev, 0x8810 + (entry << 5), part5);
+ ath_reg_write(netdev, 0x8814 + (entry << 5), cipher_opt);
+
+ ath_set_keycache_entry_mac(netdev, entry, mac);
+ return 1;
+ }
+
+ return 0;
+}
+unsigned int ath_get_keycache_size(struct net_device *netdev)
+{
+ return 128;
+}
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/mode_tables.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/mode_tables.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/mode_tables.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/mode_tables.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,309 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * the original binary and source code created by
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "mode_tables.h"
+#include "chans.h"
+#include "atheros_defs.h"
+#include "atheros.h"
+#include "atheros_dev.h"
+
+
+/*
+ * ripping it out from madwifi is ... @#*$&@#&@%#$*$@# HARD!!!
+ */
+
+struct rate_table mode_a = {
+ .rate_count = 8,
+ .code_to_idx = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .info[0] = { /* 6 MB */
+ .valid = 1,
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 6000,
+ .rateCode = 11,
+ .shortPreamble = 0,
+ .dot11Rate = (12 | 0x80),
+ .controlRate = 0,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[1] = { /* 9 MB */
+ .valid = 1,
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 9000,
+ .rateCode = 15,
+ .shortPreamble = 0,
+ .dot11Rate = 18,
+ .controlRate = 0,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[2] = { /* 12 MB */
+ .valid = 1,
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 12000,
+ .rateCode = 10,
+ .shortPreamble = 0,
+ .dot11Rate = (0x80|24),
+ .controlRate = 2,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[3] = { /* 18 MB */
+ .valid = 1,
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 18000,
+ .rateCode = 14,
+ .shortPreamble = 0,
+ .dot11Rate = 36,
+ .controlRate = 2,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[4] = { /* 24 MB */
+ .valid = 1,
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 24000,
+ .rateCode = 9,
+ .shortPreamble = 0,
+ .dot11Rate = (0x80|48),
+ .controlRate = 4,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[5] = { /* 36 MB */
+ .valid = 1,
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 36000,
+ .rateCode = 13,
+ .shortPreamble = 0,
+ .dot11Rate = 72,
+ .controlRate = 4,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[6] = { /* 48 MB */
+ .valid = 1,
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 48000,
+ .rateCode = 8,
+ .shortPreamble = 0,
+ .dot11Rate = 96,
+ .controlRate = 4,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[7] = {
+ .valid = 1, /* 54 MB */
+ .phy = IEEE80211_OFDM_MODULATION,
+ .rateKbps = 54000,
+ .rateCode = 12,
+ .shortPreamble = 0,
+ .dot11Rate = 108,
+ .controlRate = 4,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+};
+
+struct rate_table mode_b = {
+ .rate_count = 4, /* +0 */
+ .code_to_idx = { /* +4 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .info[0] = { /* +32 */
+ .valid = 1, /* 0 - 1 */
+ .phy = 0, /* 1 - 2 */
+ .rateKbps = 1000, /* 2 - 4 */
+ .rateCode = 27, /* 4 - 5 */
+ .shortPreamble = 0, /* 5 - 6 */ /* 12 bytes */
+ .dot11Rate = 130, /* 6 - 7 */
+ .controlRate = 0, /* 7 - 8 */
+ .lpAckDuration = 0, /* 8 - 10 */
+ .spAckDuration = 0, /* 10 - 12 */
+ },
+ .info[1] = {
+ .valid = 1,
+ .phy = 0,
+ .rateKbps = 2000, /* 2 MBps */
+ .rateCode = 26,
+ .shortPreamble = 4,
+ .dot11Rate = 132,
+ .controlRate = 1,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[2] = {
+ .valid = 1,
+ .phy = 0,
+ .rateKbps = 5500, /* 5.5 MBps */
+ .rateCode = 25,
+ .shortPreamble = 4,
+ .dot11Rate = 139,
+ .controlRate = 1,
+ .lpAckDuration = 0,
+ .spAckDuration = 0,
+ },
+ .info[3] = {
+ .valid = 1,
+ .phy = 0,
+ .rateKbps = 11000, /* 11 MBps */
+ .rateCode = 24,
+ .shortPreamble = 4,
+ .dot11Rate = 150,
+ .controlRate = 1,
+ .lpAckDuration = 0,
+ .spAckDuration = 0
+ },
+};
+
+
+struct rate_table mode_g = {
+ .rate_count = 12,
+ .code_to_idx = { 0 },
+ .info[0] = { 1, IEEE80211_CCK_MODULATION, 1000, 0x1b, 0, 2, 0 },
+ .info[1] = { 1, IEEE80211_CCK_MODULATION, 2000, 0x1a, 4, 4, 1 },
+ .info[2] = { 1, IEEE80211_CCK_MODULATION, 5500, 0x19, 4, 11, 1 },
+ .info[3] = { 1, IEEE80211_CCK_MODULATION, 11000, 0x18, 4, 22, 1 },
+ .info[4] = { 0, IEEE80211_OFDM_MODULATION, 6000, 0x0b, 0, 12, 4 },
+ .info[5] = { 0, IEEE80211_OFDM_MODULATION, 9000, 0x0f, 0, 18, 4 },
+ .info[6] = { 1, IEEE80211_OFDM_MODULATION, 12000, 0x0a, 0, 24, 6 },
+ .info[7] = { 1, IEEE80211_OFDM_MODULATION, 18000, 0x0e, 0, 36, 6 },
+ .info[8] = { 1, IEEE80211_OFDM_MODULATION, 24000, 0x09, 0, 48, 8 },
+ .info[9] = { 1, IEEE80211_OFDM_MODULATION, 36000, 0x0d, 0, 72, 8 },
+ .info[10] = { 1, IEEE80211_OFDM_MODULATION, 48000, 0x08, 0, 96, 8 },
+ .info[11] = { 1, IEEE80211_OFDM_MODULATION, 54000, 0x0c, 0,108, 8 },
+};
+
+
+/* TODO: add Atheros eXtended Range rate table and also turbo g rates */
+
+
+struct rate_table *ath_get_rates(struct net_device *netdev, unsigned int mode)
+{
+ struct rate_table *rates = NULL;
+
+ switch (mode) {
+ case MODE_11A:
+ rates = &mode_a;
+ break;
+ case MODE_11B:
+ rates = &mode_b;
+ break;
+ case MODE_11G:
+ rates = &mode_g;
+
+ default:
+ printk(KERN_DEBUG"atheros: unsupported rate\n");
+ return NULL;
+ }
+
+ ath_setup_rates(netdev, rates);
+ return rates;
+}
+
+void ath_setup_rates(struct net_device *netdev,struct rate_table *r)
+{
+ int i;
+
+ if (r->code_to_idx[0] != 0)
+ return;
+
+ for (i = 0; i < 32; i++)
+ r->code_to_idx[i] = 0xff;
+
+ for (i = 0; i < r->rate_count; i++) {
+ unsigned char code = r->info[i].rateCode;
+ r->code_to_idx[code] = i;
+ r->code_to_idx[code | r->info[i].shortPreamble] = i;
+ }
+}
+
+int ath_rate_setup(struct net_device *netdev, unsigned int mode)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ struct rate_table *rt;
+ int i, maxrates;
+
+ switch (mode) {
+ case MODE_11A:
+ p->rates[mode] = ath_get_rates(netdev, MODE_11A);
+ break;
+ case MODE_11B:
+ printk(KERN_DEBUG"MODE 802.11B\n");
+ p->rates[mode] = ath_get_rates(netdev, MODE_11B);
+ break;
+
+ case MODE_11G:
+ p->rates[mode] = ath_get_rates(netdev, MODE_11G);
+ break;
+ /*
+ case IEEE80211_MODE_TURBO_A:
+ p->rates[mode] = ath_getratetable(netdev, HAL_MODE_TURBO);
+ break;
+ case IEEE80211_MODE_TURBO_G:
+ p->rates[mode] = ath_getratetable(netdev, HAL_MODE_108G);
+ break; */
+ default:
+ return 0;
+ }
+ rt = p->rates[mode];
+
+ if (rt == NULL)
+ return 0;
+
+ if (rt->rate_count > IEEE80211_RATE_MAXSIZE) {
+ maxrates = IEEE80211_RATE_MAXSIZE;
+ } else
+ maxrates = rt->rate_count;
+ /*
+ rs = &ic->ic_sup_rates[mode];
+ for (i = 0; i < maxrates; i++)
+ rs->rs_rates[i] = rt->info[i].dot11Rate;
+ rs->rs_nrates = maxrates;
+ */
+ return 1;
+}
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/mode_tables.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/mode_tables.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/mode_tables.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/mode_tables.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,60 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+
+#ifndef _MODE_TABLES_H
+#define _MODE_TABLES_H
+
+struct rate_info {
+ unsigned char valid;
+ unsigned char phy;
+ unsigned short rateKbps;
+ unsigned char rateCode;
+ unsigned char shortPreamble;
+ unsigned char dot11Rate;
+ unsigned char controlRate;
+ unsigned short lpAckDuration;
+ unsigned short spAckDuration;
+};
+
+struct rate_table {
+ int rate_count;
+ unsigned char code_to_idx[32]; /* back mapping */
+ struct rate_info info[32];
+};
+
+extern struct rate_table mode_a;
+extern struct rate_table mode_b;
+
+void ath_setup_rates(struct net_device *,struct rate_table *);
+struct rate_table *ath_get_rates(struct net_device *, unsigned int);
+int ath_rate_setup(struct net_device *, unsigned int);
+#endif
+
+
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
_______________________________________________
Kernel-mentors mailing list
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^ permalink raw reply
* atheros driver (6/8)
From: Mateusz Berezecki @ 2005-08-05 3:00 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: atheros5212-6.patch --]
[-- Type: text/x-patch, Size: 20981 bytes --]
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/ioctl.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/ioctl.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/ioctl.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/ioctl.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,590 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reverse engineered by Mateusz Berezecki
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/iw_handler.h>
+#include <linux/wireless.h>
+#include <net/ieee80211.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+#include "interrupts.h"
+#include "regops.h"
+#include "powermodes.h"
+#include "transmit_receive.h"
+#include "chans.h"
+
+
+/*
+ * These are just templates for future expansion. I would have done
+ * that already but unfortunately I have to get familiar with
+ * new ieee80211 API first... Help!!! ;-p
+ */
+
+int ath_ioctl_giwname(struct net_device *netdev, struct iw_request_info *info,
+ char *name, char *extra)
+{
+ struct ieee80211_device *dev = netdev_priv(netdev);
+
+ switch (dev->mode) {
+ case IEEE_A:
+ strncpy(name, "IEEE 802.11a", IFNAMSIZ);
+ break;
+ case IEEE_B:
+ strncpy(name, "IEEE 802.11b", IFNAMSIZ);
+ break;
+ case IEEE_G:
+ strncpy(name, "IEEE 802.11b", IFNAMSIZ);
+ break;
+ default:
+ strncpy(name, "IEEE 802.11", IFNAMSIZ);
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ath_ioctl_giwname);
+
+int ath_ioctl_siwencode(struct net_device *netdev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *extra)
+{
+ /* not yet supported */
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwencode);
+
+int ath_ioctl_giwencode(struct net_device *netdev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *extra)
+{
+ /* not yet supported */
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwencode);
+
+int ath_ioctl_siwrate(struct net_device *netdev,
+ struct iw_request_info *info,
+ struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwrate);
+
+int ath_ioctl_giwrate(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwrate);
+
+int ath_ioctl_siwsens(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwsens);
+
+int ath_ioctl_giwsens(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwsens);
+
+int ath_ioctl_siwrts(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwrts);
+
+int ath_ioctl_giwrts(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwrts);
+
+int ath_ioctl_siwfrag(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwfrag);
+
+int ath_ioctl_giwfrag(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwfrag);
+
+int ath_ioctl_siwap(struct net_device *netdev, struct iw_request_info *info, struct sockaddr *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwap);
+
+int ath_ioctl_giwap(struct net_device *netdev, struct iw_request_info *info, struct sockaddr *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwap);
+
+int ath_ioctl_siwnickn(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwnickn);
+
+int ath_ioctl_giwnickn(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwnickn);
+
+int ath_ioctl_siwfreq(struct net_device *netdev, struct iw_request_info *info, struct iw_freq *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwfreq);
+
+int ath_ioctl_giwfreq(struct net_device *netdev, struct iw_request_info *info, struct iw_freq *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwfreq);
+
+int ath_ioctl_siwessid(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ /* XXX: set essid. have to take a look at
+ * ieee80211_* files to take a look at
+ * how to use ieee80211_network structure */
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwessid);
+
+int ath_ioctl_giwessid(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ /* TODO: return current extended service set ID
+ * ref: take a look above if you are curious
+ * why it is not implemented yet */
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwessid);
+
+int ath_ioctl_giwrange(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwrange);
+
+int ath_ioctl_siwmode(struct net_device *netdev, struct iw_request_info *info, unsigned int *erq, char *extra)
+{
+
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwmode);
+
+int ath_ioctl_giwmode(struct net_device *netdev, struct iw_request_info *info, unsigned int *erq, char *extra)
+{
+
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwmode);
+
+int ath_ioctl_siwpower(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwpower);
+
+int ath_ioctl_giwpower(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwpower);
+
+int ath_ioctl_siwretry(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwretry);
+
+int ath_ioctl_giwretry(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwretry);
+
+int ath_ioctl_siwtxpow(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwtxpow);
+
+int ath_ioctl_giwtxpow(struct net_device *netdev, struct iw_request_info *info, struct iw_param *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwtxpow);
+
+int ath_ioctl_iwaplist(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_iwaplist);
+
+#ifdef SIOCGIWSCAN
+int ath_ioctl_siwscan(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_siwscan);
+
+int ath_ioctl_giwscan(struct net_device *netdev, struct iw_request_info *info, struct iw_point *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_giwscan);
+#endif
+
+int ath_ioctl_setparam(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_setparam);
+
+int ath_ioctl_getparam(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_getparam);
+
+int ath_ioctl_setkey(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_setkey);
+
+int ath_ioctl_delkey(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_delkey);
+
+int ath_ioctl_setmlme(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_setmlme);
+
+int ath_ioctl_setoptie(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_setoptie);
+
+int ath_ioctl_getoptie(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_getoptie);
+
+int ath_ioctl_addmac(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_addmac);
+
+int ath_ioctl_delmac(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_delmac);
+
+int ath_ioctl_chanlist(struct net_device *netdev, struct iw_request_info *info, void *erq, char *extra)
+{
+ return -1;
+}
+EXPORT_SYMBOL(ath_ioctl_chanlist);
+
+/* Structures to export the Wireless Handlers */
+const iw_handler ath_handlers[] = {
+ (iw_handler) NULL, /* SIOCSIWCOMMIT */
+ (iw_handler) ath_ioctl_giwname, /* SIOCGIWNAME */
+ (iw_handler) NULL, /* SIOCSIWNWID */
+ (iw_handler) NULL, /* SIOCGIWNWID */
+ (iw_handler) ath_ioctl_siwfreq, /* SIOCSIWFREQ */
+ (iw_handler) ath_ioctl_giwfreq, /* SIOCGIWFREQ */
+ (iw_handler) ath_ioctl_siwmode, /* SIOCSIWMODE */
+ (iw_handler) ath_ioctl_giwmode, /* SIOCGIWMODE */
+ (iw_handler) ath_ioctl_siwsens, /* SIOCSIWSENS */
+ (iw_handler) ath_ioctl_giwsens, /* SIOCGIWSENS */
+ (iw_handler) NULL /* not used */, /* SIOCSIWRANGE */
+ (iw_handler) ath_ioctl_giwrange, /* SIOCGIWRANGE */
+ (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */
+ (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */
+ (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */
+ (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */
+ (iw_handler) NULL, /* SIOCSIWSPY */
+ (iw_handler) NULL, /* SIOCGIWSPY */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ath_ioctl_siwap, /* SIOCSIWAP */
+ (iw_handler) ath_ioctl_giwap, /* SIOCGIWAP */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ath_ioctl_iwaplist, /* SIOCGIWAPLIST */
+#ifdef SIOCGIWSCAN
+ (iw_handler) ath_ioctl_siwscan, /* SIOCSIWSCAN */
+ (iw_handler) ath_ioctl_giwscan, /* SIOCGIWSCAN */
+#else
+ (iw_handler) NULL, /* SIOCSIWSCAN */
+ (iw_handler) NULL, /* SIOCGIWSCAN */
+#endif /* SIOCGIWSCAN */
+ (iw_handler) ath_ioctl_siwessid, /* SIOCSIWESSID */
+ (iw_handler) ath_ioctl_giwessid, /* SIOCGIWESSID */
+ (iw_handler) ath_ioctl_siwnickn, /* SIOCSIWNICKN */
+ (iw_handler) ath_ioctl_giwnickn, /* SIOCGIWNICKN */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ath_ioctl_siwrate, /* SIOCSIWRATE */
+ (iw_handler) ath_ioctl_giwrate, /* SIOCGIWRATE */
+ (iw_handler) ath_ioctl_siwrts, /* SIOCSIWRTS */
+ (iw_handler) ath_ioctl_giwrts, /* SIOCGIWRTS */
+ (iw_handler) ath_ioctl_siwfrag, /* SIOCSIWFRAG */
+ (iw_handler) ath_ioctl_giwfrag, /* SIOCGIWFRAG */
+ (iw_handler) ath_ioctl_siwtxpow, /* SIOCSIWTXPOW */
+ (iw_handler) ath_ioctl_giwtxpow, /* SIOCGIWTXPOW */
+ (iw_handler) ath_ioctl_siwretry, /* SIOCSIWRETRY */
+ (iw_handler) ath_ioctl_giwretry, /* SIOCGIWRETRY */
+ (iw_handler) ath_ioctl_siwencode, /* SIOCSIWENCODE */
+ (iw_handler) ath_ioctl_giwencode, /* SIOCGIWENCODE */
+ (iw_handler) ath_ioctl_siwpower, /* SIOCSIWPOWER */
+ (iw_handler) ath_ioctl_giwpower, /* SIOCGIWPOWER */
+};
+
+const iw_handler ath_priv_handlers[] = {
+ (iw_handler) ath_ioctl_setparam, /* SIOCWFIRSTPRIV+0 */
+ (iw_handler) ath_ioctl_getparam, /* SIOCWFIRSTPRIV+1 */
+ (iw_handler) ath_ioctl_setkey, /* SIOCWFIRSTPRIV+2 */
+ (iw_handler) NULL, /* SIOCWFIRSTPRIV+3 */
+ (iw_handler) ath_ioctl_delkey, /* SIOCWFIRSTPRIV+4 */
+ (iw_handler) NULL, /* SIOCWFIRSTPRIV+5 */
+ (iw_handler) ath_ioctl_setmlme, /* SIOCWFIRSTPRIV+6 */
+ (iw_handler) NULL, /* SIOCWFIRSTPRIV+7 */
+ (iw_handler) ath_ioctl_setoptie, /* SIOCWFIRSTPRIV+8 */
+ (iw_handler) ath_ioctl_getoptie, /* SIOCWFIRSTPRIV+9 */
+ (iw_handler) ath_ioctl_addmac, /* SIOCWFIRSTPRIV+10 */
+ (iw_handler) NULL, /* SIOCWFIRSTPRIV+11 */
+ (iw_handler) ath_ioctl_delmac, /* SIOCWFIRSTPRIV+12 */
+ (iw_handler) NULL, /* SIOCWFIRSTPRIV+13 */
+ (iw_handler) ath_ioctl_chanlist, /* SIOCWFIRSTPRIV+14 */
+};
+
+struct iw_handler_def ath_iw_handler_def = {
+#define N(a) (sizeof (a) / sizeof (a[0]))
+ .standard = (iw_handler *) ath_handlers,
+ .num_standard = N(ath_handlers),
+ .private = (iw_handler *) ath_priv_handlers,
+ .num_private = N(ath_priv_handlers),
+#undef N
+};
+
+#define IW_PRIV_TYPE_OPTIE IW_PRIV_TYPE_BYTE | IEEE80211_MAX_OPT_IE
+#define IW_PRIV_TYPE_KEY \
+ IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_key)
+#define IW_PRIV_TYPE_DELKEY \
+ IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_del_key)
+#define IW_PRIV_TYPE_MLME \
+ IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_mlme)
+#define IW_PRIV_TYPE_CHANLIST \
+ IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_chanlist)
+
+#ifdef NOT_YET
+const struct iw_priv_args ieee80211_priv_args[] = {
+ /* NB: setoptie & getoptie are !IW_PRIV_SIZE_FIXED */
+ { IEEE80211_IOCTL_SETOPTIE,
+ IW_PRIV_TYPE_OPTIE, 0, "setoptie" },
+ { IEEE80211_IOCTL_GETOPTIE,
+ 0, IW_PRIV_TYPE_OPTIE, "getoptie" },
+ { IEEE80211_IOCTL_SETKEY,
+ IW_PRIV_TYPE_KEY | IW_PRIV_SIZE_FIXED, 0, "setkey" },
+ { IEEE80211_IOCTL_DELKEY,
+ IW_PRIV_TYPE_DELKEY | IW_PRIV_SIZE_FIXED, 0, "delkey" },
+ { IEEE80211_IOCTL_SETMLME,
+ IW_PRIV_TYPE_MLME | IW_PRIV_SIZE_FIXED, 0, "setmlme" },
+ { IEEE80211_IOCTL_ADDMAC,
+ IW_PRIV_TYPE_ADDR | IW_PRIV_SIZE_FIXED | 1, 0,"addmac" },
+ { IEEE80211_IOCTL_DELMAC,
+ IW_PRIV_TYPE_ADDR | IW_PRIV_SIZE_FIXED | 1, 0,"delmac" },
+ { IEEE80211_IOCTL_CHANLIST,
+ IW_PRIV_TYPE_CHANLIST | IW_PRIV_SIZE_FIXED, 0,"chanlist" },
+#if WIRELESS_EXT >= 12
+ { IEEE80211_IOCTL_SETPARAM,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setparam" },
+ /*
+ * These depends on sub-ioctl support which added in version 12.
+ */
+ { IEEE80211_IOCTL_GETPARAM,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getparam" },
+
+ /* sub-ioctl handlers */
+ { IEEE80211_IOCTL_SETPARAM,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "" },
+ { IEEE80211_IOCTL_GETPARAM,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "" },
+
+ /* sub-ioctl definitions */
+ { IEEE80211_PARAM_TURBO,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "turbo" },
+ { IEEE80211_PARAM_TURBO,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_turbo" },
+ { IEEE80211_PARAM_MODE,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "mode" },
+ { IEEE80211_PARAM_MODE,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_mode" },
+ { IEEE80211_PARAM_AUTHMODE,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "authmode" },
+ { IEEE80211_PARAM_AUTHMODE,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_authmode" },
+ { IEEE80211_PARAM_PROTMODE,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "protmode" },
+ { IEEE80211_PARAM_PROTMODE,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_protmode" },
+ { IEEE80211_PARAM_MCASTCIPHER,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "mcastcipher" },
+ { IEEE80211_PARAM_MCASTCIPHER,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_mcastcipher" },
+ { IEEE80211_PARAM_MCASTKEYLEN,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "mcastkeylen" },
+ { IEEE80211_PARAM_MCASTKEYLEN,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_mcastkeylen" },
+ { IEEE80211_PARAM_UCASTCIPHERS,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "ucastciphers" },
+ { IEEE80211_PARAM_UCASTCIPHERS,
+ /*
+ * NB: can't use "get_ucastciphers" 'cuz iwpriv command names
+ * must be <IFNAMESIZ which is 16.
+ */
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_uciphers" },
+ { IEEE80211_PARAM_UCASTCIPHER,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "ucastcipher" },
+ { IEEE80211_PARAM_UCASTCIPHER,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_ucastcipher" },
+ { IEEE80211_PARAM_UCASTKEYLEN,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "ucastkeylen" },
+ { IEEE80211_PARAM_UCASTKEYLEN,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_ucastkeylen" },
+ { IEEE80211_PARAM_KEYMGTALGS,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "keymgtalgs" },
+ { IEEE80211_PARAM_KEYMGTALGS,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_keymgtalgs" },
+ { IEEE80211_PARAM_RSNCAPS,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "rsncaps" },
+ { IEEE80211_PARAM_RSNCAPS,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_rsncaps" },
+ { IEEE80211_PARAM_ROAMING,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "roaming" },
+ { IEEE80211_PARAM_ROAMING,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_roaming" },
+ { IEEE80211_PARAM_PRIVACY,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "privacy" },
+ { IEEE80211_PARAM_PRIVACY,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_privacy" },
+ { IEEE80211_PARAM_COUNTERMEASURES,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "countermeasures" },
+ { IEEE80211_PARAM_COUNTERMEASURES,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_countermeas" },
+ { IEEE80211_PARAM_DROPUNENCRYPTED,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "dropunencrypted" },
+ { IEEE80211_PARAM_DROPUNENCRYPTED,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_dropunencry" },
+ { IEEE80211_PARAM_WPA,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wpa" },
+ { IEEE80211_PARAM_WPA,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_wpa" },
+ { IEEE80211_PARAM_DRIVER_CAPS,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "driver_caps" },
+ { IEEE80211_PARAM_DRIVER_CAPS,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_driver_caps" },
+ { IEEE80211_PARAM_MACCMD,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "maccmd" },
+ { IEEE80211_PARAM_WME,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wme" },
+ { IEEE80211_PARAM_WME,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_wme" },
+ { IEEE80211_PARAM_HIDESSID,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "hide_ssid" },
+ { IEEE80211_PARAM_HIDESSID,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_hide_ssid" },
+ { IEEE80211_PARAM_APBRIDGE,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "ap_bridge" },
+ { IEEE80211_PARAM_APBRIDGE,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_ap_bridge" },
+ { IEEE80211_PARAM_INACT,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "inact" },
+ { IEEE80211_PARAM_INACT,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_inact" },
+ { IEEE80211_PARAM_INACT_AUTH,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "inact_auth" },
+ { IEEE80211_PARAM_INACT_AUTH,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_inact_auth" },
+ { IEEE80211_PARAM_INACT_INIT,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "inact_init" },
+ { IEEE80211_PARAM_INACT_INIT,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_inact_init" },
+ { IEEE80211_PARAM_IBSS,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "ibss" },
+ { IEEE80211_PARAM_IBSS,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_ibss" },
+ { IEEE80211_PARAM_PUREG,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "pureg" },
+ { IEEE80211_PARAM_PUREG,
+ 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "get_pureg" },
+ { IEEE80211_PARAM_RESET,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "reset" },
+#endif /* WIRELESS_EXT >= 12 */
+};
+
+unsigned int get_priv_size()
+{
+ return (sizeof(ieee80211_priv_args)/
+ sizeof(ieee80211_priv_args[0]));
+}
+
+#endif
+
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
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^ permalink raw reply
* atheros driver (5/8)
From: Mateusz Berezecki @ 2005-08-05 2:59 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: atheros5212-5.patch --]
[-- Type: text/x-patch, Size: 26852 bytes --]
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/init.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/init.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/init.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/init.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,788 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me are under copyright too... should they?:P
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+#include "interrupts.h"
+#include "regops.h"
+#include "powermodes.h"
+#include "transmit_receive.h"
+#include "chans.h"
+
+struct net_device *atheros_card = NULL;
+
+unsigned int ath_radio(struct net_device *netdev)
+{
+ unsigned int ret = 0,val = 0;
+ unsigned int i;
+
+ ath_reg_write(netdev, 0x9800 + (0x34 << 2), 0x1c16);
+
+ for (i = 0; i < 8; i++)
+ ath_reg_write(netdev, 0x9800 + (0x20 << 2), 0x10000);
+
+ val = ath_reg_read(netdev, 0x9800 + (256 << 2));
+ val = (val >> 24) & 0xff;
+ val = (val & 0xf0) >> 4;
+ val |= ((val & 0x0f) << 4);
+
+ for (i = 0; i < 8; i++) {
+ ret = (ret << 1) | (val & 1);
+ val = val >> 1;
+ }
+
+ return ret;
+}
+
+unsigned int ath_selftest(struct net_device *netdev)
+{
+ unsigned int i, j;
+ unsigned int regs[2] = { 0x8000, 0x9800 + (8 << 2) };
+ unsigned int vals[2];
+ unsigned int values[4] = {
+ 0x55555555, 0xaaaaaaaa,
+ 0x66666666, 0x99999999
+ };
+
+ for (i = 0; i < 2; i++) {
+ unsigned int addr = regs[i];
+ unsigned int wdata, rdata;
+
+ vals[i] = ath_reg_read(netdev, addr);
+
+ for (j = 0; j < 256; j++) {
+ wdata = (j << 16) | j;
+ ath_reg_write(netdev, addr, wdata);
+ rdata = ath_reg_read(netdev, addr);
+ if (wdata != rdata) {
+ printk(KERN_DEBUG"atheros:(%d) read %x exp. %x\n",
+ j, rdata, wdata);
+ return 0;
+ }
+ }
+
+ for (j = 0; j < 4; j++) {
+ unsigned int tmp;
+ ath_reg_write(netdev, regs[i], values[j]);
+ tmp = ath_reg_read(netdev, regs[i]);
+ if (values[j] != tmp) {
+ printk(KERN_DEBUG"atheros: 2nd loop\n");
+ return 0;
+ }
+ }
+ ath_reg_write(netdev, regs[i], vals[i]);
+ }
+ udelay(100);
+ return 1;
+}
+
+unsigned int ath_set_reset_register(struct net_device *netdev,
+ unsigned int rmask)
+{
+ unsigned int mask = rmask ? rmask : ~0;
+ unsigned int t;
+
+
+ ath_reg_read(netdev, 0x000c);
+ ath_reg_write(netdev, 0x4000, rmask);
+ udelay(15);
+
+ mask &= (0x0001 | 0x0002);
+ rmask &= (0x0001 | 0x0002);
+ t = ath_timed_read(netdev, 0x4000, mask, rmask);
+
+ if ((rmask & 1) == 0) {
+ ath_reg_write(netdev, 0x14, 0);
+ if (!ath_set_power_mode(netdev, 2, 1, 0))
+ return t;
+ ath_reg_read(netdev, 0xc0);
+ }
+ return t;
+}
+
+unsigned int ath_prep_reset(struct net_device *netdev)
+{
+ return 1;
+}
+
+unsigned int ath_chip_reset(struct net_device *netdev, void *unused)
+{
+
+ if (!ath_set_reset_register(netdev, 0x13)) {
+ printk(KERN_DEBUG"atheros: if 1 (warm reset)\n");
+ return 0;
+ }
+
+ if (!ath_set_power_mode(netdev, 2, 1, 0)) {
+ printk(KERN_DEBUG"atheros: if #2 (power mode)\n");
+ return 0;
+ }
+
+ if (!ath_set_reset_register(netdev, 0)) {
+ printk(KERN_DEBUG"atheros: if 3 (cold reset)\n");
+ return 0;
+ }
+
+ if (unused == NULL)
+ return 1;
+
+ return 0;
+}
+
+unsigned int ath_reset(struct net_device *netdev)
+{
+ return 0;
+}
+
+struct chip_gain_desc athgaindesc = {
+ .entrycnt = 9,
+ .defentry = 4,
+ .deltas[0] = { {4, 1, 1, 1, 0, 0, 0}, 6, "FG8" },
+ .deltas[1] = { {4, 0, 1, 1, 0, 0, 0}, 4, "FG7" },
+ .deltas[2] = { {3, 1, 1, 1, 0, 0, 0}, 3, "FG6" },
+ .deltas[3] = { {4, 0, 0, 1, 0, 0, 0}, 1, "FG5" },
+ .deltas[4] = { {4, 1, 1, 0, 0, 0, 0}, 0, "FG4" },
+ .deltas[5] = { {4, 0, 1, 0, 0, 0, 0}, -2, "FG3" },
+ .deltas[6] = { {3, 1, 1, 0, 0, 0, 0}, -3, "FG2" },
+ .deltas[7] = { {4, 0, 0, 0, 0, 0, 0}, -4, "FG1" },
+ .deltas[8] = { {2, 1, 1, 0, 0, 0, 0}, -6, "FG0" },
+};
+
+struct chip_gain_desc ath5112gaindesc = {
+ .entrycnt = 8,
+ .defentry = 1,
+ .deltas[0] = { {3, 0, 0, 0, 0, 0, 0}, 6, "FG7" },
+ .deltas[1] = { {2, 0, 0, 0, 0, 0, 0}, 0, "FG6" },
+ .deltas[2] = { {1, 0, 0, 0, 0, 0, 0}, -3, "FG5" },
+ .deltas[3] = { {0, 0, 0, 0, 0, 0, 0}, 0, "FG4" },
+ .deltas[4] = { {0, 1, 1, 0, 0, 0, 0}, -8, "FG3" },
+ .deltas[5] = { {0, 1, 1, 0, 1, 1, 0},-10, "FG2" },
+ .deltas[6] = { {0, 1, 0, 1, 1, 1, 0},-13, "FG1" },
+ .deltas[7] = { {0, 1, 0, 1, 1, 0, 1},-16, "FG0" },
+};
+
+void ath_init_gain(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ if ((p->rev_5ghz & 0xf0) >= (0x10|0x20)) {
+ p->gaindesc.number = ath5112gaindesc.defentry;
+ p->gaindesc.delta =
+ &ath5112gaindesc.deltas[ath5112gaindesc.defentry];
+ p->gaindesc.active = 1;
+ p->gaindesc.low = 20;
+ p->gaindesc.high = 85;
+ } else {
+ p->gaindesc.number = athgaindesc.defentry;
+ p->gaindesc.delta =
+ &athgaindesc.deltas[athgaindesc.defentry];
+ p->gaindesc.active = 1;
+ p->gaindesc.low = 20;
+ p->gaindesc.high = 35;
+ }
+}
+
+unsigned int ath_alloc_rf(struct net_device *netdev)
+{
+ /*
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ */
+ return 1;
+}
+
+unsigned short chans11b[] = {
+ 2412, 2447, 2484
+};
+
+unsigned short chans11g[] = {
+ 2312, 2412, 2484
+};
+
+int ath_dev_attach(unsigned short devid, struct net_device *netdev)
+{
+ unsigned int val;
+ struct atheros_priv *pdata;
+ unsigned int i;
+
+ pdata = ieee80211_priv(netdev);
+
+ pdata->tpc = 16;
+ pdata->atim_win = 0;
+ pdata->cts = 4;
+ pdata->divctrl = 0;
+ pdata->iqcal = 0;
+ pdata->scaletpfactor = 0;
+ pdata->aifs = 2;
+ pdata->enableqos = 0;
+ pdata->swretry = 0;
+ pdata->hwtxtrycount = 10;
+ pdata->txlimit = 10;
+ pdata->beacon_interval = 100;
+ pdata->pwroverride = 0;
+ pdata->enable32clk = 0;
+
+ printk(KERN_DEBUG"atheros: devid is %x\n", devid);
+
+ /* first, power on the device... */
+ if (!ath_set_power_mode(netdev, PMODE_AWAKE, 1, 0)) {
+ printk(KERN_DEBUG"atheros: failed to wake up the device\n");
+ return 0;
+ }
+
+ /* ...reset the radio chip afterwards */
+ if (!ath_chip_reset(netdev, NULL)) {
+ printk(KERN_DEBUG"atheros: failed to reset the chip\n");
+ return -1;
+ }
+
+ pdata->mac_version = (ath_reg_read(netdev, 0x4020) & 0xff) >> 4;
+ pdata->mac_revision = ath_reg_read(netdev, 0x4020) & 0x0f;
+
+ printk(KERN_DEBUG"atheros: mac version %d\n", pdata->mac_version);
+ printk(KERN_DEBUG"atheros: mac revision %d\n", pdata->mac_revision);
+
+ if (pdata->mac_version != 5 || pdata->mac_revision < 2) {
+ printk(KERN_ERR"atheros: chip not supported\n");
+ return 0;
+ }
+
+ pdata->phy_revision = ath_reg_read(netdev, 0x9818);
+
+ if (ath_selftest(netdev) == 0) {
+ printk(KERN_ERR"atheros: POST test failed!\n");
+ return 0;
+ }
+
+ ath_reg_write(netdev, 0x9800, 0x00000007);
+
+ pdata->rev_5ghz = ath_radio(netdev);
+
+ /* XXX TODO: add some checks here fo chipset versioning */
+
+ printk(KERN_DEBUG"atheros: 2ghz radio revision %x\n",
+ pdata->rev_5ghz);
+
+ if (!eeprom_init(netdev)) {
+ printk(KERN_DEBUG"atheros: eeprom init failed!\n");
+ return 0;
+ }
+
+ /* ustawic kanaly i inne takie gadzety */
+ pdata->eeinfo.num_ch5 = 10;
+ pdata->eeinfo.num_ch2 = 3;
+
+ for (i = 0; i < 10; i++)
+ pdata->eeinfo.chans_11a[i].count = 11;
+
+ for (i = 0; i < 3; i++) {
+ pdata->eeinfo.ch_11b[i] = chans11b[i];
+ pdata->eeinfo.ch_11g[i] = chans11g[i];
+ pdata->eeinfo.chans_11b[i].count = 3;
+ pdata->eeinfo.chans_11g[i].count = 3;
+ }
+
+
+ if (!eeprom_read_caps(netdev))
+ return 0;
+
+ if (pdata->eeinfo.mode_b && (pdata->rev_5ghz & 0xf0) == 0x10) {
+ unsigned int tmpval;
+ ath_reg_write(netdev, 0x9800, 0x00004007);
+ udelay(2000);
+ pdata->rev_2ghz = ath_radio(netdev);
+ ath_reg_write(netdev, 0x9800, 0x00000007);
+ udelay(2000);
+
+ tmpval = pdata->rev_2ghz & 0xf0;
+
+ if (tmpval != 0x20) {
+ return 0;
+ }
+ }
+
+ printk(KERN_DEBUG"atheros: 5GHz radio revision %x\n",pdata->rev_2ghz);
+ eeprom_read(netdev, 0xbf, &val);
+ printk(KERN_DEBUG"atheros: regulatory domain -> %x(%d)\n",val, val);
+
+ pdata->domain = val;
+
+ ath_init_gain(netdev);
+
+ if (!ath_alloc_rf(netdev)) {
+ return 0;
+ }
+
+ if (!eeprom_read_mac(netdev, pdata->mac)) {
+ printk(KERN_DEBUG"atheros: MAC reading failed\n");
+ }
+ printk(KERN_DEBUG"atheros: MAC is %x.%x.%x.%x.%x.%x\n",
+ pdata->mac[0],pdata->mac[1],pdata->mac[2],
+ pdata->mac[3],pdata->mac[4],pdata->mac[5]);
+
+ return 1;
+}
+
+int ath_attach(unsigned short devid, struct net_device *netdev)
+{
+ unsigned t, i;
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ if (!ath_dev_attach(devid, netdev))
+ return 0;
+
+
+ t = ath_setup_xtx_desc(netdev, NULL, 0, 0, 0, 0, 0, 0);
+ p->mretry = t;
+
+ if (ath_get_cap(netdev, CAP_PHYCOUNTERS, 0, NULL) == 0)
+ p->mib_enabled = 1;
+
+ p->keycache_size = ath_get_keycache_size(netdev);
+
+ printk(KERN_DEBUG"atheros: resetting key cache\n");
+ for (i = 0; i < p->keycache_size; i++) {
+ ath_reset_keycache(netdev, i);
+ }
+
+ for (i = 0; i < 4; i++) {
+ p->keymap[i/8] |= 1 << (i % 8);
+ /*
+ set_bit(p->keymap, i);
+ set_bit(p->keymap, i+32);
+ set_bit(p->keymap, i+64);
+ set_bit(p->keymap, i+32+64);
+ */
+ }
+
+ /* XXX this has to be finished yet. its quite complicated
+ * how it works, etc. */
+ if (!ath_get_channels(netdev, 0, -1, -1))
+ return 0;
+
+ /* XXX rate setup here */
+
+ ath_rate_setup(netdev, MODE_11A);
+ ath_rate_setup(netdev, MODE_11B);
+ ath_rate_setup(netdev, MODE_11G);
+
+
+ /* XXX allocate descriptors here */
+ /*
+ if (!ath_desc_alloc(netdev)) {
+ return 0;
+ }
+ */
+ p->beacon_q = ath_beacon_queue_setup(netdev);
+ if (p->beacon_q == (unsigned int) -1) {
+ printk(KERN_DEBUG"atheros: beacon queue setup failed\n");
+ return 0;
+ }
+
+ p->cabq = ath_txq_setup(netdev, TX_QUEUE_CAB, 0);
+ if (p->cabq == NULL) {
+ printk(KERN_DEBUG"atheros: unable to setup CAB xmit queue!\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+int ath_init(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ int opmode = 0, status = 0;
+
+ ath_stop_locked(netdev);
+
+ /* XXX use the proper mode first. Where to get it from?*g* */
+ /*
+ ath_reset(netdev, opmode, chan, 0, &status);
+ */
+ ath_update_txpow(netdev);
+
+ if (ath_startrecv(netdev) != 0) {
+ printk(KERN_DEBUG"atheros: cant init receieve\n");
+ return -1;
+ }
+
+ p->intr_mask = INT_RX | INT_TX | INT_RXEOL |
+ INT_RXORN | INT_FATAL | INT_GLOBAL;
+
+ ath_set_interruptmask(netdev, p->intr_mask);
+
+ netdev->flags |= IFF_RUNNING;
+
+ return 1;
+}
+
+int ath_stop(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ int error;
+
+ error = ath_stop_locked(netdev);
+
+ if (error == 0 && !p->invalid)
+ ath_set_power_mode(netdev, PMODE_FULL_SLEEP, 1, 0);
+
+ return error;
+}
+
+int ath_stop_locked(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ if (netdev->flags & IFF_RUNNING) {
+ netif_stop_queue(netdev);
+ netdev->flags &= ~IFF_RUNNING;
+
+ if (!p->invalid) {
+ /*
+ if (p->softled) {
+ del_timer(&p->ledtimer);
+ ath_gpioset(netdev, p->ledpin,
+ !p->ledon);
+ p->blinking = 0;
+ }
+ */
+ ath_set_interruptmask(netdev, 0);
+ }
+
+ ath_draintxq(netdev);
+
+ if (!p->invalid) {
+ ath_stoprecv(netdev);
+ ath_phy_disable(netdev);
+ } else
+ p->rxlink = NULL;
+#ifdef NOT_YET
+ ath_beacon_free(netdev);
+#endif
+ }
+
+ return 0;
+}
+
+void ath_mode_init(struct net_device *netdev)
+{
+}
+
+int ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ return -1;
+}
+
+struct net_device_stats *ath_getstats(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ /* same note as below applies here too */
+
+ return &p->devstats;
+}
+
+struct iw_statistics *ath_iw_getstats(struct net_device *netdev)
+{
+ /* returning stats from device.
+ * thats not so correct but will do for testing.
+ * in future versions use stats from associated
+ * node */
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ /* TODO: update stat counters here and return */
+
+ return &p->stats;
+}
+
+int ath_set_mac_address(struct net_device *netdev, void *addr)
+{
+ int error;
+ struct atheros_priv *p;
+ struct sockaddr *mac = addr;
+
+ p = ieee80211_priv(netdev);
+
+ if (netif_running(netdev)) {
+ printk(KERN_DEBUG"atheros: cannot set address; device running\n");
+ return -EBUSY;
+ }
+
+ memcpy(netdev->dev_addr, mac->sa_data, 6);
+ error = -ath_reset(netdev);
+
+ return error;
+}
+
+int ath_change_mtu(struct net_device *netdev, int mtu)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ int error;
+
+ if (!(ATH_MIN_MTU < mtu && mtu <= ATH_MAX_MTU))
+ return -EINVAL;
+
+ netdev->mtu = mtu;
+ tasklet_disable(&p->rxtq);
+ error = -ath_reset(netdev);
+ tasklet_enable(&p->rxtq);
+
+ return error;
+}
+
+void ath_netdev_init(struct net_device *netdev)
+{
+ unsigned int size;
+ struct net_device *ieee = netdev_priv(netdev);
+
+ printk(KERN_DEBUG"atheros pci: initializing netdevice\n");
+
+ netdev->open = ath_init;
+ netdev->stop = ath_stop;
+ //netdev->hard_start_xmit = ath_hardstart;
+// netdev->tx_timeout = ath_timeout;
+ netdev->watchdog_timeo = 5 * HZ;
+ netdev->set_multicast_list = ath_mode_init;
+ netdev->do_ioctl = ath_ioctl;
+ netdev->get_stats = ath_getstats;
+ netdev->set_mac_address = ath_set_mac_address;
+ netdev->change_mtu = ath_change_mtu;
+ netdev->tx_queue_len = ATHEROS_TXBUF-1;
+
+// ieee->hard_start_xmit = ath_hardstart;
+
+#ifdef CONFIG_NET_WIRELESS
+ netdev->get_wireless_stats = ath_iw_getstats;
+ netdev->wireless_handlers = &ath_iw_handler_def;
+
+#ifdef NOT_YET_BABE
+ /* just because it breaks stuff and its 2:13 am ;-P */
+ ath_iw_handler_def.private_args =
+ (struct iw_priv_args *) ieee80211_priv_args;
+
+ ath_iw_handler_def.num_private_args = get_priv_size();
+#endif
+#endif
+}
+
+int ath_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+ unsigned char cache_sz;
+ unsigned char timer;
+ unsigned int val;
+ struct net_device *netdev;
+ struct atheros_priv *priv;
+ unsigned long phy_mem, virt_mem;
+
+ if (pci_enable_device(dev))
+ return (-EIO);
+
+ /* atheros chipsets support 32bit addressing mode */
+ if (pci_set_dma_mask(dev, 0xffffffff)) {
+ printk(KERN_ERR"atheros pci: couldn't set 32-bit DMA mode\n");
+ goto disable;
+ }
+
+ pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cache_sz);
+
+ /* as madwifi source says rx buffer DMA will work if and only if
+ * we have some alignment set up */
+
+ if (cache_sz == 0) {
+ cache_sz = L1_CACHE_BYTES / sizeof(unsigned int);
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, cache_sz);
+ }
+
+ pci_read_config_byte(dev, PCI_LATENCY_TIMER, &timer);
+ if (timer == 0) {
+ /* XXX: Tune this ... */
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
+ }
+
+ pci_set_master(dev);
+ pci_read_config_dword(dev, 0x40, &val);
+ pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
+
+ /* grab first memory region address */
+ phy_mem = pci_resource_start(dev, 0);
+
+ if (request_mem_region(phy_mem, pci_resource_len(dev, 0),
+ "atheros") == NULL) {
+ printk(KERN_ERR"atheros pci: couldn't get PCI memory\n");
+ goto disable;
+ }
+
+ virt_mem = (unsigned long)ioremap(phy_mem,pci_resource_len(dev,0));
+ if (virt_mem == 0x00000000) {
+ printk(KERN_ERR"atheros pci: couldn't remap PCI memory\n");
+ goto release;
+ }
+ printk(KERN_DEBUG"atheros pci: Using IRQ : %d\n", dev->irq);
+ atheros_card = alloc_ieee80211(sizeof(struct atheros_priv));
+
+ ath_netdev_init(atheros_card);
+ atheros_card->irq = dev->irq;
+ atheros_card->mem_start = virt_mem;
+ atheros_card->mem_end = virt_mem + pci_resource_len(dev, 0);
+ printk(KERN_DEBUG"atheros pci: memory spans : %08lx-%08lx\n",
+ atheros_card->mem_start, atheros_card->mem_end);
+
+
+ priv = ieee80211_priv(atheros_card);
+ priv->busdev = dev;
+
+ priv->invalid = 1;
+
+
+ SET_MODULE_OWNER(atheros_card);
+ SET_NETDEV_DEV(atheros_card, &dev->dev);
+
+ printk(KERN_DEBUG"atheros pci: allocated atheros netdevice\n");
+
+ pci_set_drvdata(dev, atheros_card);
+
+ if (request_irq(atheros_card->irq,
+ ath_intr, SA_SHIRQ,
+ atheros_card->name,
+ atheros_card)) {
+ printk(KERN_ERR"atheros pci: IRQ request failed.\n");
+ goto netdev_free;
+ }
+
+ if (!ath_attach(id->device, atheros_card))
+ goto freeirq;
+
+
+ eeprom_read_mac(atheros_card, atheros_card->dev_addr);
+
+ if (register_netdev(atheros_card))
+ goto detach;
+
+ priv->invalid = 0;
+
+ return 0;
+
+detach:
+ ath_detach(atheros_card);
+freeirq:
+ free_irq(atheros_card->irq, dev);
+
+netdev_free:
+ free_ieee80211(atheros_card);
+ atheros_card = NULL;
+
+mem_unmap:
+ iounmap((void *)virt_mem);
+release:
+ release_mem_region(phy_mem, pci_resource_len(dev, 0));
+disable:
+ pci_disable_device(dev);
+ return -ENODEV;
+}
+
+int ath_detach(struct net_device *netdev)
+{
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+
+ printk(KERN_DEBUG"atheros pci: detaching\n");
+
+ ath_stop(netdev);
+ pdata->invalid = 1;
+
+ unregister_netdev(netdev);
+
+ printk(KERN_DEBUG"atheros pci: detached.\n");
+ return 0;
+}
+
+
+void ath_remove(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ ath_detach(dev);
+ if (dev->irq)
+ free_irq(dev->irq, dev);
+
+ iounmap((void *)dev->mem_start);
+ release_mem_region(pci_resource_start(pdev, 0),
+ pci_resource_len(pdev, 0));
+ pci_disable_device(pdev);
+ free_ieee80211(atheros_card);
+ atheros_card = NULL;
+}
+
+struct pci_device_id atheros_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_ATHEROS, ATHEROS_5212) },
+ { 0 }
+};
+MODULE_DEVICE_TABLE(pci, atheros_ids);
+
+static struct pci_driver atheros5212_id = {
+ .name = "Atheros5212",
+ .id_table = atheros_ids,
+ .probe = ath_probe,
+ .remove = ath_remove,
+ .resume = NULL,
+ .suspend = NULL,
+};
+
+static int __init atheros_init()
+{
+ if (pci_register_driver(&atheros5212_id) != 0)
+ return -1;
+ return 0;
+}
+
+static void __exit atheros_exit()
+{
+ pci_unregister_driver(&atheros5212_id);
+ return;
+}
+
+module_init(atheros_init);
+module_exit(atheros_exit);
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Mateusz Berezecki");
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/interrupts.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/interrupts.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/interrupts.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/interrupts.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,171 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+
+/* check if we got some interrupt pending signal from a device */
+int ath_int_pending(struct net_device *netdev)
+{
+ int val;
+
+ val = ath_reg_read(netdev, AR5212_INTPEND);
+
+ if (val == 1)
+ return 1;
+
+ return 0;
+}
+
+/* get type of pending interrupts from the device */
+int ath_get_pending_ints(struct net_device *netdev, int *imask)
+{
+ unsigned int val;
+
+ val = ath_reg_read(netdev, AR5212_RAC_PISR);
+ if (val == 0xffffffff) {
+ *imask = 0;
+ return 0;
+ }
+
+ *imask = val & INT_COMMON;
+
+ if (val & AR5212_PISR_HIUERR) { /* we got some fatal hw error */
+ *imask |= INT_FATAL;
+ return 0;
+ }
+
+ if (val & (AR5212_PISR_RXOK|AR5212_PISR_RXERR)) {
+ *imask |= INT_RX;
+ }
+
+ if (val & (AR5212_PISR_TXOK|AR5212_PISR_TXERR)) {
+ *imask |= INT_TX;
+ }
+
+ if (val & AR5212_PISR_RXORN) {
+ printk(KERN_DEBUG"atheros: receive overrun!\n");
+ *imask |= INT_FATAL;
+ }
+
+ return 1;
+}
+
+/* get current interrupt mask */
+unsigned int ath_get_interrupts(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ return p->intr_mask;
+}
+
+/* set new interrupt mask. this is a bit counter-intuitive.
+ * the masked interrupts will BE actually delivered. */
+unsigned int ath_set_interruptmask(struct net_device *netdev,
+ unsigned int mask)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ unsigned int tmp = p->intr_mask;
+ unsigned int val;
+
+ if (tmp & INT_GLOBAL) {
+ ath_reg_write(netdev, AR5212_IER, AR5212_IER_DISABLE);
+ ath_reg_read(netdev, AR5212_IER);
+ }
+
+ val = mask & INT_COMMON;
+ if (mask & INT_TX)
+ val |= AR5212_PIMR_TXOK |
+ AR5212_PIMR_TXERR |
+ AR5212_PIMR_TXDESC;
+
+ if (mask & INT_RX)
+ val |= AR5212_PIMR_RXOK |
+ AR5212_PIMR_RXERR |
+ AR5212_PIMR_RXDESC;
+
+ if (mask & INT_FATAL)
+ val |= AR5212_PISR_HIUERR;
+
+ ath_reg_write(netdev, AR5212_PIMR, val);
+ p->intr_mask = mask;
+
+ if (mask & INT_GLOBAL) {
+ ath_reg_write(netdev, AR5212_IER, AR5212_IER_ENABLE);
+ ath_reg_read(netdev, AR5212_IER);
+ }
+
+ return tmp;
+}
+
+
+/* just standard interrupt handling stuff goes here */
+irqreturn_t ath_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct net_device *netdev = (struct net_device *)dev_id;
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+ //INT status;
+
+ if (pdata->invalid)
+ return IRQ_NONE;
+
+// if (ath_intr_pending(netdev) == 0)
+// return IRQ_NONE;
+
+// if ((netdev->flags & (IFF_RUNNING | IFF_UP))
+// != (IFF_RUNNING | IFF_UP)) {
+// ath_get_pendingIntr(netdev, &status);
+// ath_set_intr(netdev, 0);
+// return IRQ_HANDLED;
+// }
+
+// /* add support for different hardware interrupts */
+// ath_get_pendingIntr(netdev, &status);
+//
+ return IRQ_NONE;
+}
+
+
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/interrupts.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/interrupts.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/interrupts.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/interrupts.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,50 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _H_INT
+#define _H_INT
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+extern irqreturn_t ath_intr(int, void *, struct pt_regs *);
+
+#endif
+
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
_______________________________________________
Kernel-mentors mailing list
Kernel-mentors@selenic.com
http://selenic.com/mailman/listinfo/kernel-mentors
^ permalink raw reply
* atheros driver (3/8)
From: Mateusz Berezecki @ 2005-08-05 2:58 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: atheros5212-3.patch --]
[-- Type: text/x-patch, Size: 22339 bytes --]
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/beacons.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/beacons.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/beacons.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/beacons.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,235 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+//#include "atheros_devops.h"
+//#include "atheros_regops.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+
+
+
+
+void ath_beacon_init(struct net_device *netdev, unsigned int nextbtt,
+ unsigned int intval)
+{
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+ struct ieee80211_device *dev = netdev_priv(netdev);
+ unsigned int val;
+
+ ath_reg_write(netdev, AR5212_TIMER0, nextbtt);
+
+ switch (dev->iw_mode) {
+ case IW_MODE_MONITOR:
+ case IW_MODE_INFRA:
+ ath_reg_write(netdev,
+ AR5212_TIMER1,
+ 0xffff);
+ ath_reg_write(netdev,
+ AR5212_TIMER2,
+ 0x7ffff);
+ break;
+
+ case IW_MODE_ADHOC:
+ ath_reg_write(netdev,
+ AR5212_TIMER1,
+ (nextbtt - 2) << 3);
+ ath_reg_write(netdev,
+ AR5212_TIMER2,
+ (nextbtt - 10) << 3);
+ break;
+
+ default:
+ break;
+ }
+
+ ath_reg_write(netdev, AR5212_TIMER3, nextbtt +
+ (pdata->atim_win ? pdata->atim_win : 1));
+
+ val = intval &
+ (AR5212_BEACON_PERIOD |
+ AR5212_BEACON_RESET_TSF |
+ AR5212_BEACON_ENABLE);
+
+ if (val & AR5212_BEACON_RESET_TSF)
+ ath_reg_write(netdev, AR5212_BEACON,
+ AR5212_BEACON_RESET_TSF);
+
+ ath_reg_write(netdev, AR5212_BEACON, val);
+}
+
+void ath_reset_station_btimers(struct net_device *netdev)
+{
+ int tmp;
+
+ ath_reg_write(netdev, AR5212_TIMER0, 0);
+ tmp = (ath_reg_read(netdev, AR5212_STA_ID1)
+ | AR5212_STA_ID1_PWR_SV) &
+ ~(AR5212_STA_ID1_DEFAULT_ANTENNA |
+ AR5212_STA_ID1_PCF);
+
+
+ ath_reg_write(netdev, AR5212_BEACON, 0xffff);
+ return;
+}
+
+void ath_set_station_btimers(struct net_device *netdev,
+ struct beacon_state *state, unsigned int tsf,
+ unsigned int dtcx, unsigned int cfpcx)
+{
+ unsigned int tmp, dtimp, nextt;
+ unsigned int bintval;
+
+ if (state->bs_cfpperiod) {
+ tmp = ath_reg_read(netdev, AR5212_STA_ID1);
+ tmp |= AR5212_STA_ID1_PCF;
+
+ ath_reg_write(netdev, AR5212_STA_ID1, tmp);
+
+ ath_reg_write(netdev, AR5212_CFP_PERIOD,
+ state->bs_cfpperiod *
+ state->bs_dtimperiod *
+ state->bs_intval);
+
+ ath_reg_write(netdev, AR5212_CFP_DUR,
+ state->bs_cfpmaxduration);
+
+ ath_reg_write(netdev, AR5212_TIMER2,
+ ((tsf +
+ ((cfpcx * state->bs_dtimperiod + dtcx) *
+ state->bs_intval))) << 3);
+ } else
+ ath_reg_disable(netdev,
+ AR5212_STA_ID1,
+ AR5212_STA_ID1_PCF);
+
+
+ bintval = state->bs_intval;
+
+ ath_reg_write(netdev, AR5212_TIMER0, state->bs_nexttbtt);
+
+ tmp = ath_reg_read(netdev, AR5212_BEACON) & 0xff800000;
+ tmp |= state->bs_intval & 0xffff;
+
+ if (state->bs_timoffset) {
+ tmp |= ((state->bs_timoffset + 4) << 16) & 0x7f0000;
+ } else {
+ tmp |= (4 << 16) & 0x7f0000;
+ }
+
+ ath_reg_write(netdev, AR5212_BEACON, tmp);
+
+
+ if (state->bs_bmissthreshold <= (0xff00 >> 8)) {
+ BUG();
+ return;
+ }
+
+ tmp = ath_reg_read(netdev, AR5212_RSSI_THR) & (~0xff00);
+ tmp |= (state->bs_bmissthreshold << 8) & 0xff00;
+ ath_reg_write(netdev, AR5212_RSSI_THR, tmp);
+
+
+ bintval = state->bs_intval;
+ if (bintval < state->bs_sleepduration)
+ bintval = state->bs_sleepduration;
+
+
+ dtimp = state->bs_dtimperiod;
+ if (state->bs_sleepduration > dtimp)
+ dtimp = state->bs_sleepduration;
+
+ if (bintval == dtimp)
+ nextt = state->bs_nextdtim;
+ else
+ nextt = state->bs_nexttbtt;
+
+ ath_reg_write(netdev, AR5212_SLEEP0,
+ ((state->bs_nextdtim - 3) & 0x7ffff) |
+ ((10 << 24) & 0xff000000) |
+ 0x00080000 | 0x00100000);
+
+ ath_reg_write(netdev, AR5212_SLEEP1,
+ ( ( (nextt - 3) << 3) & 0x7ffff) |
+ ((10 << 24) & 0xff000000));
+
+ ath_reg_write(netdev, AR5212_SLEEP2,
+ (bintval & 0x0000ffff) |
+ ((dtimp << 16) & 0xffff0000));
+}
+
+
+unsigned int ath_wait_for_beacon_done(struct net_device *netdev)
+{
+ unsigned int i;
+
+ for (i = 0; i < 1000; i++) {
+/* XXX remove this comment
+ * if ( !ath_num_tx_pending(netdev, 2) )
+ break;
+*/
+ udelay(10);
+ }
+
+ if (i < 1000)
+ return 1;
+
+ return 0;
+}
+
+
+unsigned int ath_beacon_queue_setup(struct net_device *netdev)
+{
+ struct tx_queue_info qi;
+ memset(&qi, 0, sizeof(qi));
+
+ qi.tqi_aifs = 0xffffffff;
+ qi.tqi_cwmin = 0xffffffff;
+ qi.tqi_cwmax = 0xffffffff;
+ qi.tqi_qflags = 0x00000002;
+
+ return ath_setup_tx_queue(netdev, 2, &qi);
+}
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/caps.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/caps.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/caps.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/caps.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,176 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+#include "interrupts.h"
+
+
+unsigned int ath_get_ext_cap(struct net_device *netdev, CAPABILITY_TYPE type,
+ unsigned int cap, unsigned int *result)
+{
+ switch (type) {
+ case CAP_REG_DMN:
+ *result = 0;
+ return 0;
+
+ case CAP_KEYCACHE_SIZE:
+ *result = 0x80; /* FIXME this is a default for testing
+ but we seriously need something better
+ than a hardcoded value. reversing
+ that part is quite hard though... :(
+ */
+ return 0;
+
+ case CAP_NUM_TXQUEUES:
+ return ENOTSUPP; /* FIXME */
+
+ case CAP_VEOL: /* FIXME */
+ return ENOTSUPP;
+
+ case CAP_COMPRESSION:
+ case CAP_BURST:
+ case CAP_FASTFRAME:
+ case CAP_DIAG:
+ case CAP_PSPOLL:
+ return ENOTSUPP; /* FIXME */
+
+ case CAP_TXPOW:
+ switch (cap) {
+ case 1:
+ /* FIXME */
+ break;
+
+ case 0:
+ return 0;
+
+ case 2:
+ break;
+
+ case 3:
+ break;
+
+ default:
+ return ENOTSUPP;
+ }
+
+ default:
+ return EINVAL;
+ }
+}
+
+
+unsigned int ath_get_cap(struct net_device *netdev, CAPABILITY_TYPE type,
+ unsigned int cap, unsigned int *result)
+{
+ struct atheros_priv *pdata = ieee80211_priv(netdev);
+
+ switch (type) {
+ case CAP_CIPHER:
+ switch (cap) {
+ case CIPHER_WEP:
+ case CIPHER_AES_OCB:
+ return 0; /* 5212 supports them */
+
+ case CIPHER_AES_CCM:
+ return ENOTSUPP;
+
+ case CIPHER_TKIP:
+ case CIPHER_CLR:
+ case CIPHER_MIC:
+ return 0;
+
+ default:
+ return ENOTSUPP;
+ }
+ break;
+
+ case CAP_TKIP_MIC: /* hardware TKIP MIC ? */
+ /* if blablabla fix IT */
+ return ENOTSUPP; /* not supported for now */
+
+ case CAP_TKIP_SPLIT: /* TKIP using split keys ? */
+ /* same as above. needs DOING :P */
+ return ENOTSUPP;
+
+ case CAP_PHYCOUNTERS:
+ if (pdata->disable_hw_counters == 0)
+ return 0;
+ return 1;
+
+ case CAP_DIVERSITY:
+ if (!cap)
+ return 0;
+
+ if (cap != 1)
+ return EINVAL;
+
+ if ( (ath_reg_read(netdev, 0xa208) & 0x20) == 0 )
+ return ENXIO;
+
+ return (ath_reg_read(netdev, 0xa208) & 0x20);
+
+ case CAP_TPC: /* tx power control (per-packet) */
+ if (!cap)
+ return 0;
+
+ if (cap != 1)
+ return 0;
+ /*
+ if (0x196c+hal == 0)
+ return 1
+ return 0;
+ */
+ return 0; /* just for now. it can break stuff but we don't care for a moment */
+
+ default:
+ return ath_get_ext_cap(netdev, type, cap, result);
+ }
+}
+
+
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/caps.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/caps.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/caps.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/caps.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,61 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _CAPS_H
+#define _CAPS_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+#include "interrupts.h"
+
+unsigned int ath_get_cap(struct net_device *, CAPABILITY_TYPE,
+ unsigned int, unsigned int *);
+
+
+
+#endif
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/chans.c netdev-atheros/drivers/net/wireless/atheros/atheros5212/chans.c
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/chans.c 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/chans.c 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,213 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+
+#include <net/ieee80211.h>
+
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+
+#include "atheros_id.h"
+#include "atheros_dev.h"
+#include "atheros_defs.h"
+#include "atheros_registers.h"
+#include "atheros.h"
+#include "eeprom.h"
+#include "interrupts.h"
+#include "chans.h"
+
+/* THIS IS A KILLER :/ */
+struct domain_table domains[] = {
+ {
+ .domain = WORLD0,
+ .ahmodes = ADHOC_MODE_11A_DSUPPORT,
+ .ahchans = NULL,
+ .chancnt = 10,
+
+ .chans[0] = {
+ .mode = MODE_11A,
+ .freq = { 5260, 5280, 5300, 5320, 5180, 5200, 5220, 5240, 0 },
+ },
+ .chans[1] = {
+ .mode = MODE_11A,
+ .freq = { 5170, 5190, 5210, 5230, 0 },
+ },
+ .chans[2] = {
+ .mode = MODE_11B,
+ .freq = { 2412, 2437, 2462, 2442, 2472, 0 },
+ },
+ .chans[3] = {
+ .mode = MODE_11A,
+ .freq = { 5745, 5765, 5785, 5805, 5825, 0 },
+ },
+ .chans[4] = {
+ .mode = MODE_TURBO,
+ .freq = { 5210, 5250, 5290, 0 },
+ },
+ .chans[5] = {
+ .mode = MODE_TURBO,
+ .freq = { 5760, 5800, 0 },
+ },
+ .chans[6] = {
+ .mode = MODE_11A,
+ .freq = { 5500, 5520, 5540, 5560, 5580, 5600, 5620, 5640, 5660,5680, 5700, 0},
+ },
+ .chans[7] = {
+ .mode = MODE_11B,
+ .freq = { 2417, 2422, 2427, 2432, 2447, 2452, 2457, 2467, 0 },
+ },
+ .chans[8] = {
+ .mode = MODE_11B,
+ .freq = { 2484, 0 },
+ },
+ .chans[9] = {
+ .mode = MODE_108G,
+ .freq = { 2437, 0 },
+ },
+ }
+};
+
+/* just for now, we support one domain. MY DOMAIN :-) */
+#define DOMAIN_TABLE_SIZE 1
+
+unsigned int getdmn(struct net_device *netdev,
+ unsigned int *result, unsigned int *ix)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ unsigned int d = p->domain;
+
+ if (d & 0x8000)
+ return 0;
+
+ printk(KERN_DEBUG"atheros: getdmn, SKU super domain\n");
+ d &= 0x0fff;
+ if (d != 0) {
+ unsigned int i;
+ for (i = 0; i < DOMAIN_TABLE_SIZE; i++) {
+ if (d == domains[i].domain) {
+ if (result != NULL)
+ *result = d;
+ if (ix != NULL)
+ *ix = i;
+ return 1;
+ }
+ }
+ }
+ return 0;
+}
+
+unsigned int ath_init_channels(struct net_device *netdev,
+ struct channel *ch, unsigned short max, unsigned int *nchans,
+ unsigned int country, unsigned short mode,
+ unsigned int outdoor, unsigned int extchan)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+
+ printk(KERN_DEBUG"atheros: calling getdmn with domain %x\n", country);
+ if (getdmn(netdev, NULL, NULL)) {
+ printk(KERN_DEBUG"atheros: SKU common mode enabled\n");
+ p->common = 1;
+ }
+
+ if (p->domain & 0x4000) {
+ printk(KERN_DEBUG"atheros: we got roaming to set up\n");
+ }
+
+ /* XXX */
+ return 1;
+}
+
+unsigned int ath_get_modes(struct net_device *netdev)
+{
+ struct atheros_priv *p = ieee80211_priv(netdev);
+ unsigned int mode = 0;
+
+ if (p->eeinfo.mode_a) {
+ mode |= MODE_11A;
+ /* XXX ignore turbo for a while */
+ }
+
+ if (p->eeinfo.mode_b)
+ mode |= MODE_11B;
+
+ if (p->eeinfo.mode_g) {
+ mode |= MODE_11G;
+ /* XXX ignore turbo for a while */
+ }
+
+ return mode;
+}
+
+unsigned int ath_getwirelessmodes(struct net_device *netdev,
+ unsigned int country)
+{
+ unsigned int mode;
+
+ mode = ath_get_modes(netdev); /* wtf nonsense ;-) */
+ return mode;
+}
+
+unsigned int ath_get_channels(struct net_device *netdev,
+ unsigned int country, unsigned int outdoor,
+ unsigned int xchanmode)
+{
+ struct channel *chans;
+ unsigned int nchan;
+ unsigned int ix, i;
+
+ chans = kmalloc(255 * sizeof(struct channel), GFP_KERNEL);
+
+ if (!chans) {
+ printk(KERN_ERR"atheros: no memory left!\n");
+ return 0;
+ }
+
+ if (!ath_init_channels(netdev, chans, 255, &nchan, 0,
+ 0xfff, outdoor, xchanmode)) {
+ printk(KERN_DEBUG"atheros: channel init failed\n");
+ kfree(chans);
+ return 0;
+ }
+
+ printk(KERN_DEBUG"atheros: nchan=%d\n", nchan);
+ for (i = 0; i < nchan; i++) {
+ }
+
+ //kfree(chans);
+ return 1;
+}
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/chans.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/chans.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/chans.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/chans.h 2005-08-05 03:48:36.000000000 +0200
@@ -0,0 +1,110 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+enum {
+ ADHOC_MODE_11A_DISABLED,
+ ADHOC_MODE_11A_ENABLED,
+ ADHOC_MODE_11B_ENABLED,
+ ADHOC_MODE_11A_DSUPPORT,
+};
+
+enum {
+ MODE_11A = 1,
+ MODE_11B = 2,
+ MODE_11G = 3,
+ MODE_TURBO = 4,
+ MODE_108G = 5,
+};
+
+enum {
+ NO_ENUMRD = 0x00,
+ CTRY_11B_ONLY = 0x03,
+ CTRY_ISRAEL = 0x07,
+ CTRY_ETSIC1 = 0x08,
+ CTRY_USA1 = 0x10,
+ CTRY_HONGKONG = 0x11,
+ CTRY_CANADA = 0x20,
+ CTRY_AUSTRALIA = 0x21,
+ CTRY_ETSIC2 = 0x22,
+ CTRY_FRANCE = 0x31,
+ CTRY_USA2 = 0x3A,
+ CTRY_WORLD1 = 0x37,
+ CTRY_FRANCE2 = 0x32,
+ CTRY_HUNGARY = 0x35,
+ CTRY_FRANCE3 = 0x36,
+ CTRY_WORLD2 = 0x30,
+ CTRY_ETSIC2 = 0x38,
+ CTRY_WORLD3 = 0x39,
+ CTRY_BULGARIA = 0x34,
+ CTRY_RESERVED = 0x33,
+ CTRY_JAPAN1 = 0x40,
+ CTRY_JAPAN2 = 0x41,
+ CTRY_SINGAPORE = 0x42,
+ CTRY_JAPAN3 = 0x43,
+ CTRY_RESERVED2 = 0x44,
+ CTRY_KOREA = 0x45,
+ CTRY_UNK1 = 0x46,
+ CTRY_UNK2 = 0x47,
+ CTRY_JAPAN4 = 0x48,
+ CTRY_KOREA2 = 0x49,
+ CTRY_JAPAN5 = 0x4A,
+ CTRY_JAPAN6 = 0x4B,
+ CTRY_LATIN = 0x52,
+ CTRY_UNK3 = 0x53,
+ CTRY_UNK4 = 0x54,
+ CTRY_UNK5 = 0x55,
+ CTRY_VENEZUELA = 0x56,
+ CTRY_CHILE = 0x58,
+ WORLD0 = 0x60,
+ WORLD1 = 0x61,
+ WORLD2 = 0x62,
+ WORLD3 = 0x63,
+ WORLD4 = 0x64,
+ WORLD5 = 0x65,
+ DEBUG_REG_DMN = 0x01ff,
+};
+
+
+struct domain_table {
+ unsigned int domain;
+ unsigned int ahmodes;
+ unsigned short *ahchans;
+
+ unsigned int chancnt;
+ struct {
+ unsigned short mode;
+ unsigned short freq[14];
+ } chans[10];
+};
+
+struct channel {
+ unsigned short flags;
+ unsigned short freq;
+};
+
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
_______________________________________________
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^ permalink raw reply
* atheros driver (2/8)
From: Mateusz Berezecki @ 2005-08-05 2:57 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: atheros5212-2.patch --]
[-- Type: text/x-patch, Size: 61341 bytes --]
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros.h 2005-08-05 03:48:35.000000000 +0200
@@ -0,0 +1,180 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _ATHEROS_H
+#define _ATHEROS_H
+
+#include "atheros_dev.h"
+
+typedef enum {
+ PMODE_UNDEFINED = 0,
+ PMODE_AUTO = 1,
+ PMODE_AWAKE = 2,
+ PMODE_FULL_SLEEP = 3,
+ PMODE_NETWORK_SLEEP = 4
+} POWER_MODE;
+
+#define IEEE80211_CHAN_2GHZ 0x0080 /* 2 GHz spectrum channel. */
+#define IEEE80211_CHAN_5GHZ 0x0100 /* 5 GHz spectrum channel */
+
+typedef enum {
+ CAP_REG_DMN = 0, /* current regulatory domain */
+ CAP_CIPHER = 1, /* hardware supports cipher */
+ CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
+ CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
+ CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
+ CAP_DIVERSITY = 5, /* hardware supports fast diversity */
+ CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
+ CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
+ CAP_VEOL = 9, /* hardware supports virtual EOL */
+ CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
+ CAP_DIAG = 11, /* hardware diagnostic support */
+ CAP_COMPRESSION = 12, /* hardware supports compression */
+ CAP_BURST = 13, /* hardware supports packet bursting */
+ CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
+ CAP_TXPOW = 15, /* global tx power limit */
+ CAP_TPC = 16 /* per-packet tx power control */
+} CAPABILITY_TYPE;
+
+typedef enum {
+ CIPHER_WEP = 0,
+ CIPHER_AES_OCB = 1,
+ CIPHER_AES_CCM = 2,
+ CIPHER_CKIP = 3,
+ CIPHER_TKIP = 4,
+ CIPHER_CLR = 5,
+ CIPHER_MIC = 127
+} CIPHER;
+
+typedef enum {
+ CHIP_5GHZ = IEEE80211_CHAN_5GHZ,
+ CHIP_2GHZ = IEEE80211_CHAN_2GHZ,
+} CHIP;
+
+enum version {
+ AR5210 = 0,
+ AR5211 = 1,
+ AR5212 = 2,
+};
+
+enum radio {
+ AR5110 = 0,
+ AR5111 = 1,
+ AR5112 = 2,
+};
+
+/* from madwifi source */
+enum opmode {
+ IEEE80211_M_STA = 1, /* infrastructure station */
+ IEEE80211_M_IBSS = 0, /* IBSS (adhoc) station */
+ IEEE80211_M_AHDEMO = 3, /* Old lucent compatible adhoc demo */
+ IEEE80211_M_HOSTAP = 6, /* Software Access Point */
+ IEEE80211_M_MONITOR = 8 /* Monitor mode */
+};
+
+typedef enum {
+ INT_RX = 0x00000001, /* Non-common mapping */
+ INT_RXDESC = 0x00000002,
+ INT_RXNOFRM = 0x00000008,
+ INT_RXEOL = 0x00000010,
+ INT_RXORN = 0x00000020,
+ INT_TX = 0x00000040, /* Non-common mapping */
+ INT_TXDESC = 0x00000080,
+ INT_TXURN = 0x00000800,
+ INT_MIB = 0x00001000,
+ INT_RXPHY = 0x00004000,
+ INT_RXKCM = 0x00008000,
+ INT_SWBA = 0x00010000,
+ INT_BMISS = 0x00040000,
+ INT_BNR = 0x00100000, /* Non-common mapping */
+ INT_GPIO = 0x01000000,
+ INT_FATAL = 0x40000000, /* Non-common mapping */
+ INT_GLOBAL = 0x80000000, /* Set/clear IER */
+
+ /* Interrupt bits that map directly to ISR/IMR bits */
+ INT_COMMON = INT_RXNOFRM
+ | INT_RXDESC
+ | INT_RXEOL
+ | INT_RXORN
+ | INT_TXURN
+ | INT_TXDESC
+ | INT_MIB
+ | INT_RXPHY
+ | INT_RXKCM
+ | INT_SWBA
+ | INT_BMISS
+ | INT_GPIO,
+
+ INT_NOCARD = 0xffffffff /* To signal the card was removed */
+} INT;
+
+
+
+/* declarations and prototypes */
+extern struct iw_handler_def ath_iw_handler_def;
+extern const struct iw_priv_args ieee80211_priv_args[];
+
+/* reg read and write */
+unsigned int ath_reg_read(struct net_device *, unsigned int);
+void ath_reg_write(struct net_device *, unsigned int, unsigned int);
+void ath_reg_disable(struct net_device *, unsigned int, unsigned int);
+void ath_reg_enable(struct net_device *, unsigned int, unsigned int);
+
+/* caps */
+unsigned int ath_get_cap(struct net_device *, CAPABILITY_TYPE,
+ unsigned int, unsigned int *);
+
+/* key */
+unsigned int ath_get_keycache_size(struct net_device *);
+unsigned int ath_reset_keycache(struct net_device *, unsigned short);
+
+/* chans */
+unsigned int ath_get_channels(struct net_device *,
+ unsigned int, unsigned int, unsigned int);
+
+/* beacons */
+unsigned int ath_beacon_queue_setup(struct net_device *);
+
+/* TX/RX */
+struct tx_queue *ath_txq_setup(struct net_device *, int, int);
+unsigned int ath_setup_tx_queue(struct net_device *, unsigned int,
+ struct tx_queue_info *);
+int ath_startrecv(struct net_device *);
+void ath_draintxq(struct net_device *);
+void ath_stoprecv(struct net_device *);
+
+
+/* init */
+int ath_stop_locked(struct net_device *);
+
+/* interrupts */
+unsigned int ath_set_interruptmask(struct net_device *, unsigned int);
+
+
+#endif
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_defs.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_defs.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_defs.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_defs.h 2005-08-05 03:48:35.000000000 +0200
@@ -0,0 +1,82 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#define ATHEROS_TXBUF 200
+
+#define TXQ_FLAG_TXOKINT_ENABLE 0x0001
+#define TXQ_FLAG_TXERRINT_ENABLE 0x0001
+#define TXQ_FLAG_TXDESCINT_ENABLE 0x0002
+#define TXQ_FLAG_TXEOLINT_ENABLE 0x0004
+#define TXQ_FLAG_TXURNINT_ENABLE 0x0008
+#define TXQ_FLAG_BACKOFF_DISABLE 0x0010
+#define TXQ_FLAG_COMPRESSION_ENABLE 0x0020
+#define TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040
+#define TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080
+
+#define TX_QUEUE_INACTIVE 0 /* queue is inactive/unused */
+#define TX_QUEUE_DATA 1 /* data xmit q's */
+#define TX_QUEUE_BEACON 2 /* beacon xmit q */
+#define TX_QUEUE_CAB 3 /* "crap after beacon" xmit q */
+#define TX_QUEUE_PSPOLL 4 /* power-save poll xmit q */
+
+#define WME_AC_BK 0 /* background access category */
+#define WME_AC_BE 1 /* best effort access category*/
+#define WME_AC_VI 2 /* video access category */
+#define WME_AC_VO 3 /* voice access category */
+#define WME_UPSD 4 /* uplink power save */
+
+
+#define IEEE80211_RATE_MAXSIZE 8
+
+
+#define RX_FILTER_PHYERR 0x100
+#define RX_FILTER_PHYRADAR 0x200
+
+#define RXERR_CRC 0x01 /* CRC error on frame */
+#define RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
+#define RXERR_FIFO 0x04 /* fifo overrun */
+#define RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
+#define RXERR_MIC 0x10 /* Michael MIC decrypt error */
+
+#define ATH_MIN_MTU 32
+#define ATH_MAX_MTU 2290
+
+
+#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0)
+#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+1)
+#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+2)
+#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+4)
+#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+6)
+#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+8)
+#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+9)
+#define IEEE80211_IOCTL_ADDMAC (SIOCIWFIRSTPRIV+10)
+#define IEEE80211_IOCTL_DELMAC (SIOCIWFIRSTPRIV+12)
+#define IEEE80211_IOCTL_CHANLIST (SIOCIWFIRSTPRIV+14)
+
+#define IEEE80211_MAX_OPT_IE 256
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_dev.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_dev.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_dev.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_dev.h 2005-08-05 03:48:35.000000000 +0200
@@ -0,0 +1,305 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _ATHEROS_DEV_H
+#define _ATHEROS_DEV_H
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <asm/semaphore.h>
+#include <linux/netdevice.h>
+
+#include "eeprom.h"
+#include "mode_tables.h"
+/*
+ * just a short memo:
+ *
+ * offsets inside binary hal
+ *
+ * 0x1b0 - current operating mode (STATION/IBSS/ADHOC etc.)
+ *
+ */
+
+
+struct mib_stats {
+ unsigned int ackrcv_bad;
+ unsigned int rts_bad;
+ unsigned int rts_good;
+ unsigned int fcs_bad;
+ unsigned int beacons;
+};
+
+struct beacon_state {
+ unsigned int bs_nexttbtt; /* next beacon in TU */
+ unsigned int bs_nextdtim; /* next DTIM in TU */
+ unsigned int bs_intval; /* beacon interval+flags */
+#define BEACON_PERIOD 0x0000ffff /* beacon interval period */
+#define BEACON_ENA 0x00800000 /* beacon xmit enable */
+#define BEACON_RESET_TSF 0x01000000 /* clear TSF */
+ unsigned int bs_dtimperiod;
+ unsigned short bs_cfpperiod; /* CFP period in TU */
+ unsigned short bs_cfpmaxduration; /* max CFP duration in TU */
+ unsigned int bs_cfpnext; /* next CFP in TU */
+ unsigned short bs_timoffset; /* byte offset to TIM bitmap */
+ unsigned short bs_bmissthreshold; /* beacon miss threshold */
+ unsigned int bs_sleepduration; /* max sleep duration */
+};
+
+struct gain_delta {
+ unsigned short values[7];
+ unsigned int gain;
+ char buf[16];
+};
+
+struct gain_desc {
+ unsigned int number;
+ unsigned int gain;
+ unsigned int t;
+ unsigned int low;
+ unsigned int high;
+ unsigned int correction;
+ unsigned int active;
+ struct gain_delta *delta;
+};
+
+struct chip_gain_desc {
+ unsigned int entrycnt;
+ unsigned int defentry;
+ struct gain_delta deltas[10];
+};
+
+struct keyval {
+ unsigned char kv_type; /* one of CIPHER */
+ unsigned char kv_pad;
+ unsigned short kv_len; /* length in bits */
+ unsigned char kv_val[16]; /* enough for 128-bit keys */
+ unsigned char kv_mic[8]; /* TKIP MIC key */
+};
+
+struct tx_queue_info {
+ unsigned int tqi_ver; /* hal TXQ version */
+ unsigned int tqi_type;
+ unsigned int tqi_subtype; /* subtype if applicable */
+ unsigned int tqi_qflags; /* flags (see above) */
+ unsigned int tqi_priority; /* (not used) */
+ unsigned int tqi_aifs; /* aifs */
+ unsigned int tqi_cwmin; /* cwMin */
+ unsigned int tqi_cwmax; /* cwMax */
+ unsigned short tqi_shretry; /* rts retry limit */
+ unsigned short tqi_lgretry; /* long retry limit (not used)*/
+ unsigned int tqi_cbrPeriod;
+ unsigned int tqi_cbrOverflowLimit;
+ unsigned int tqi_burstTime;
+ unsigned int tqi_readyTime;
+ unsigned int tqi_flags;
+};
+
+/*
+ * Data transmit queue state. One of these exists for each
+ * hardware transmit queue. Packets sent to us from above
+ * are assigned to queues based on their priority. Not all
+ * devices support a complete set of hardware transmit queues.
+ * For those devices the array sc_ac2q will map multiple
+ * priorities to fewer hardware queues (typically all to one
+ * hardware queue).
+ */
+struct tx_queue {
+ u_int axq_qnum; /* hardware q number */
+ u_int axq_depth; /* queue depth (stat only) */
+ u_int axq_intrcnt; /* interrupt count */
+ u_int32_t *axq_link; /* link ptr in last TX desc */
+ //STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
+ spinlock_t axq_lock; /* lock on q and link */
+ /*
+ * State for patching up CTS when bursting.
+ */
+ struct ath_buf *axq_linkbuf; /* va of last buffer */
+ struct ath_desc *axq_lastdsWithCTS;
+ /* first desc of last descriptor
+ * that contains CTS */
+ struct ath_desc *axq_gatingds; /* final desc of the gating desc
+ * that determines whether
+ * lastdsWithCTS has been DMA'ed
+ * or not */
+};
+
+
+struct atheros_priv {
+ struct tasklet_struct txtq;
+ struct tasklet_struct bmisstq;
+ struct tasklet_struct fataltq;
+ struct tasklet_struct rxtq;
+ struct tasklet_struct rxorntq;
+
+ void *busdev;
+ unsigned int pmode; /* current power mode */
+
+ unsigned char mac[6];
+ unsigned int chan;
+
+ unsigned int mac_version;
+ unsigned int mac_revision;
+ unsigned int phy_revision;
+ unsigned int rev_2ghz;
+ unsigned int rev_5ghz;
+
+ unsigned int version;
+ unsigned int radio;
+ unsigned int domain;
+ struct gain_desc gaindesc;
+
+ unsigned int atim_win; /* thats quite possible ;p */
+ unsigned int aifs;
+ unsigned int enableqos;
+
+ /* BEACON QUEUE */
+ unsigned int beacon_q; /*number of a beacon queue */
+
+ /* TX QUEUE SECTION */
+ spinlock_t tx_buflock;
+ int tx_timer;
+ unsigned int tx_setup;
+ unsigned int tx_intr_period;
+ struct tx_queue_info txq_info[16];
+ struct tx_queue tx_queues[16];
+
+ /* CAB QUEUE */
+ struct tx_queue_info *cabq;
+
+ /* rx/tx links */
+ unsigned int rxlink;
+
+ /* DEVICE STATISTICS */
+ struct iw_statistics stats;
+ struct net_device_stats devstats;
+
+ /* RATES */
+ struct rate_table *rates[8];
+ struct rate_table *currate;
+
+ unsigned int swretry;
+ unsigned int hwtxtrycount;
+ unsigned int txlimit;
+
+ unsigned int turbo; /* turbo mode supported ? */
+
+ unsigned int pwr_limit;
+ unsigned int pwroverride;
+
+ unsigned int slot_time;
+ unsigned int ack_timeout;
+ unsigned int cts_timeout;
+
+ unsigned int enable32clk;
+
+ unsigned int beacon_interval;
+
+ unsigned int mretry;
+ unsigned int disable_hw_counters;
+ unsigned int common;
+
+ unsigned char keymap[8];
+
+ unsigned char tpc;
+ unsigned char cts;
+ unsigned int divctrl;
+ unsigned int iqcal;
+ int scaletpfactor;
+ unsigned char bssid[6];
+
+ unsigned int max_queue;
+
+ unsigned int max_keycache;
+ unsigned int keycache_size;
+ unsigned int ext_keycache;
+
+ unsigned int intr_ready;
+ unsigned int invalid;
+ unsigned int intr_mask;
+
+ unsigned int mib_enabled;
+ struct mib_stats mib_stats;
+ struct eeprom_info eeinfo;
+};
+
+struct ath_rx_status {
+ unsigned short rs_datalen; /* rx frame length */
+ unsigned short rs_tstamp; /* h/w assigned timestamp */
+ unsigned char rs_status; /* rx status, 0 => recv ok */
+ unsigned char rs_phyerr; /* phy error code */
+ signed char rs_rssi; /* rx frame RSSI */
+ unsigned char rs_keyix; /* key cache index */
+ unsigned char rs_rate; /* h/w receive rate index */
+ unsigned char rs_antenna; /* antenna information */
+ unsigned char rs_more; /* more descriptors follow */
+};
+
+struct ath_tx_status {
+ unsigned short ts_seqnum; /* h/w assigned sequence number */
+ unsigned short ts_tstamp; /* h/w assigned timestamp */
+ unsigned char ts_status; /* frame status, 0 => xmit ok */
+ unsigned char ts_rate; /* h/w transmit rate index */
+//#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
+ signed char ts_rssi; /* tx ack RSSI */
+ unsigned char ts_shortretry; /* # short retries */
+ unsigned char ts_longretry; /* # long retries */
+ unsigned char ts_virtcol; /* virtual collision count */
+ unsigned char ts_antenna; /* antenna information */
+};
+
+struct ath_desc {
+ unsigned int link;
+ unsigned int data;
+ unsigned int ctl0;
+ unsigned int ctl1;
+
+ union {
+ struct {
+ unsigned int ctl2;
+ unsigned int ctl3;
+ unsigned int status0;
+ unsigned int status1;
+ } tx;
+ struct {
+ unsigned int status0;
+ unsigned int status1;
+ } rx;
+ } u;
+
+ union {
+ struct ath_tx_status txstat;
+ struct ath_rx_status rxstat;
+ } s;
+} __attribute__((__packed__));
+
+#include "mode_tables.h"
+
+#endif
+
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_id.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_id.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_id.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_id.h 2005-08-05 03:48:35.000000000 +0200
@@ -0,0 +1,59 @@
+/*
+ * All the work was created by reverse engineering and porting
+ * for interoperability. The creator is Mateusz Berezecki,
+ * unless explicitly marked ( some parts are derived
+ * from GPL'ed parts of madwifi project located at http://madwifi.sf.net)
+ *
+ * derived or copied parts of code licensed under
+ * dual GPL/BSD license
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * rest of the code has been reversed by me and is under copyright too
+ * Copyright (C) 2005 Mateusz Berezecki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+#define PCI_VENDOR_ID_ATHEROS 0x168c
+#define ATHEROS_5212 0x13
+
+
+#define MAX_GPIO 10
+
+/*
+ * Common silicon revision/version values
+ */
+#define SREV_REV_FPGA 1
+#define SREV_REV_PROTO 2
+#define SREV_REV_PROTOA 3
+#define SREV_REV_AR5210 4
+#define SREV_REV_AR5210M 5
+#define SREV_REV_AR5210M23 7
+#define SREV_REV_AR521023 8
+
+#define SREV_VER_AR5210 0
+#define SREV_VER_AR5311 1
+#define SREV_VER_AR5311A 2
+#define SREV_VER_AR5311B 3
+#define SREV_VER_AR5211 4
+#define SREV_VER_AR5212 5
+
+#define SREV_RAD_5111 0x10
+#define SREV_RAD_5111A 0x15
+#define SREV_RAD_2111 0x20
+#define SREV_RAD_5112 0x30
+#define SREV_RAD_5112A 0x35
+#define SREV_RAD_2112A 0x45
+
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_registers.h netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_registers.h
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/atheros_registers.h 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/atheros_registers.h 2005-08-05 03:48:35.000000000 +0200
@@ -0,0 +1,1341 @@
+/* this might be a problem, right ? :) */
+
+/* $OpenBSD: ar5212reg.h,v 1.1 2005/02/19 16:58:00 reyk Exp $ */
+
+/*
+ * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Known registers of the Atheros AR5001 Wireless LAN chipsets
+ * (AR5212/AR5311).
+ */
+
+#ifndef _AR5212_REG_H
+#define _AR5212_REG_H
+
+/*
+ * Command register
+ */
+#define AR5212_CR 0x0008
+#define AR5212_CR_RXE 0x00000004
+#define AR5212_CR_RXD 0x00000020
+#define AR5212_CR_SWI 0x00000040
+
+/*
+ * Receive queue descriptor pointer register
+ */
+#define AR5212_RXDP 0x000c
+
+/*
+ * Configuration and status register
+ */
+#define AR5212_CFG 0x0014
+#define AR5212_CFG_SWTD 0x00000001
+#define AR5212_CFG_SWTB 0x00000002
+#define AR5212_CFG_SWRD 0x00000004
+#define AR5212_CFG_SWRB 0x00000008
+#define AR5212_CFG_SWRG 0x00000010
+#define AR5212_CFG_ADHOC 0x00000020
+#define AR5212_CFG_PHY_OK 0x00000100
+#define AR5212_CFG_EEBS 0x00000200
+#define AR5212_CFG_CLKGD 0x00000400
+#define AR5212_CFG_PCI_THRES 0x00060000
+#define AR5212_CFG_PCI_THRES_S 17
+
+/*
+ * Interrupt enable register
+ */
+#define AR5212_IER 0x0024
+#define AR5212_IER_DISABLE 0x00000000
+#define AR5212_IER_ENABLE 0x00000001
+
+/*
+ * Transmit configuration register
+ */
+#define AR5212_TXCFG 0x0030
+#define AR5212_TXCFG_SDMAMR 0x00000007
+#define AR5212_TXCFG_B_MODE 0x00000008
+#define AR5212_TXCFG_TXFULL 0x000003f0
+#define AR5212_TXCFG_TXFULL_S 4
+#define AR5212_TXCFG_TXFULL_0B 0x00000000
+#define AR5212_TXCFG_TXFULL_64B 0x00000010
+#define AR5212_TXCFG_TXFULL_128B 0x00000020
+#define AR5212_TXCFG_TXFULL_192B 0x00000030
+#define AR5212_TXCFG_TXFULL_256B 0x00000040
+#define AR5212_TXCFG_TXCONT_ENABLE 0x00000080
+#define AR5212_TXCFG_JUMBO_TXE 0x00000400
+#define AR5212_TXCFG_RTSRND 0x00001000
+#define AR5212_TXCFG_FRMPAD_DIS 0x00002000
+#define AR5212_TXCFG_RDY_DIS 0x00004000
+
+/*
+ * Receive configuration register
+ */
+#define AR5212_RXCFG 0x0034
+#define AR5212_RXCFG_SDMAMW 0x00000007
+#define AR5311_RXCFG_DEFAULT_ANTENNA 0x00000008
+#define AR5212_RXCFG_ZLFDMA 0x00000010
+#define AR5212_RXCFG_JUMBO_RXE 0x00000020
+#define AR5212_RXCFG_JUMBO_WRAP 0x00000040
+
+/*
+ * MIB control register
+ */
+#define AR5212_MIBC 0x0040
+#define AR5212_MIBC_COW 0x00000001
+#define AR5212_MIBC_FMC 0x00000002
+#define AR5212_MIBC_CMC 0x00000004
+#define AR5212_MIBC_MCS 0x00000008
+
+/*
+ * Timeout prescale register
+ */
+#define AR5212_TOPS 0x0044
+#define AR5212_TOPS_M 0x0000ffff
+
+/*
+ * Receive timeout register (no frame received)
+ */
+#define AR5212_RXNOFRM 0x0048
+#define AR5212_RXNOFRM_M 0x000003ff
+
+/*
+ * Transmit timeout register (no frame sent)
+ */
+#define AR5212_TXNOFRM 0x004c
+#define AR5212_TXNOFRM_M 0x000003ff
+#define AR5212_TXNOFRM_QCU 0x000ffc00
+
+/*
+ * Receive frame gap timeout register
+ */
+#define AR5212_RPGTO 0x0050
+#define AR5212_RPGTO_M 0x000003ff
+
+/*
+ * Receive frame count limit register
+ */
+#define AR5212_RFCNT 0x0054
+#define AR5212_RFCNT_M 0x0000001f
+
+/*
+ * Misc settings register
+ */
+#define AR5212_MISC 0x0058
+#define AR5212_MISC_DMA_OBS_M 0x000001e0
+#define AR5212_MISC_DMA_OBS_S 5
+#define AR5212_MISC_MISC_OBS_M 0x00000e00
+#define AR5212_MISC_MISC_OBS_S 9
+#define AR5212_MISC_MAC_OBS_LSB_M 0x00007000
+#define AR5212_MISC_MAC_OBS_LSB_S 12
+#define AR5212_MISC_MAC_OBS_MSB_M 0x00038000
+#define AR5212_MISC_MAC_OBS_MSB_S 15
+
+/*
+ * Primary interrupt status register
+ */
+#define AR5212_PISR 0x0080
+#define AR5212_PISR_RXOK 0x00000001
+#define AR5212_PISR_RXDESC 0x00000002
+#define AR5212_PISR_RXERR 0x00000004
+#define AR5212_PISR_RXNOFRM 0x00000008
+#define AR5212_PISR_RXEOL 0x00000010
+#define AR5212_PISR_RXORN 0x00000020
+#define AR5212_PISR_TXOK 0x00000040
+#define AR5212_PISR_TXDESC 0x00000080
+#define AR5212_PISR_TXERR 0x00000100
+#define AR5212_PISR_TXNOFRM 0x00000200
+#define AR5212_PISR_TXEOL 0x00000400
+#define AR5212_PISR_TXURN 0x00000800
+#define AR5212_PISR_MIB 0x00001000
+#define AR5212_PISR_SWI 0x00002000
+#define AR5212_PISR_RXPHY 0x00004000
+#define AR5212_PISR_RXKCM 0x00008000
+#define AR5212_PISR_SWBA 0x00010000
+#define AR5212_PISR_BRSSI 0x00020000
+#define AR5212_PISR_BMISS 0x00040000
+#define AR5212_PISR_HIUERR 0x00080000
+#define AR5212_PISR_BNR 0x00100000
+#define AR5212_PISR_RXCHIRP 0x00200000
+#define AR5212_PISR_TIM 0x00800000
+#define AR5212_PISR_BCNMISC 0x00800000
+#define AR5212_PISR_GPIO 0x01000000
+#define AR5212_PISR_QCBRORN 0x02000000
+#define AR5212_PISR_QCBRURN 0x04000000
+#define AR5212_PISR_QTRIG 0x08000000
+
+/*
+ * Secondary interrupt status registers (0 - 4)
+ */
+#define AR5212_SISR0 0x0084
+#define AR5212_SISR0_QCU_TXOK 0x000003ff
+#define AR5212_SISR0_QCU_TXDESC 0x03ff0000
+
+#define AR5212_SISR1 0x0088
+#define AR5212_SISR1_QCU_TXERR 0x000003ff
+#define AR5212_SISR1_QCU_TXEOL 0x03ff0000
+
+#define AR5212_SISR2 0x008c
+#define AR5212_SISR2_QCU_TXURN 0x000003ff
+#define AR5212_SISR2_MCABT 0x00100000
+#define AR5212_SISR2_SSERR 0x00200000
+#define AR5212_SISR2_DPERR 0x00400000
+#define AR5212_SISR2_TIM 0x01000000
+#define AR5212_SISR2_CAB_END 0x02000000
+#define AR5212_SISR2_DTIM_SYNC 0x04000000
+#define AR5212_SISR2_BCN_TIMEOUT 0x08000000
+#define AR5212_SISR2_CAB_TIMEOUT 0x10000000
+#define AR5212_SISR2_DTIM 0x20000000
+
+#define AR5212_SISR3 0x0090
+#define AR5212_SISR3_QCBRORN 0x000003ff
+#define AR5212_SISR3_QCBRURN 0x03ff0000
+
+#define AR5212_SISR4 0x0094
+#define AR5212_SISR4_QTRIG 0x000003ff
+
+/*
+ * Shadow read-and-clear interrupt status registers
+ */
+#define AR5212_RAC_PISR 0x00c0
+#define AR5212_RAC_SISR0 0x00c4
+#define AR5212_RAC_SISR1 0x00c8
+#define AR5212_RAC_SISR2 0x00cc
+#define AR5212_RAC_SISR3 0c00d0
+#define AR5212_RAC_SISR4 0c00d4
+
+/*
+ * Primary interrupt mask register
+ */
+#define AR5212_PIMR 0x00a0
+#define AR5212_PIMR_RXOK 0x00000001
+#define AR5212_PIMR_RXDESC 0x00000002
+#define AR5212_PIMR_RXERR 0x00000004
+#define AR5212_PIMR_RXNOFRM 0x00000008
+#define AR5212_PIMR_RXEOL 0x00000010
+#define AR5212_PIMR_RXORN 0x00000020
+#define AR5212_PIMR_TXOK 0x00000040
+#define AR5212_PIMR_TXDESC 0x00000080
+#define AR5212_PIMR_TXERR 0x00000100
+#define AR5212_PIMR_TXNOFRM 0x00000200
+#define AR5212_PIMR_TXEOL 0x00000400
+#define AR5212_PIMR_TXURN 0x00000800
+#define AR5212_PIMR_MIB 0x00001000
+#define AR5212_PIMR_SWI 0x00002000
+#define AR5212_PIMR_RXPHY 0x00004000
+#define AR5212_PIMR_RXKCM 0x00008000
+#define AR5212_PIMR_SWBA 0x00010000
+#define AR5212_PIMR_BRSSI 0x00020000
+#define AR5212_PIMR_BMISS 0x00040000
+#define AR5212_PIMR_HIUERR 0x00080000
+#define AR5212_PIMR_BNR 0x00100000
+#define AR5212_PIMR_RXCHIRP 0x00200000
+#define AR5212_PIMR_TIM 0x00800000
+#define AR5212_PIMR_BCNMISC 0x00800000
+#define AR5212_PIMR_GPIO 0x01000000
+#define AR5212_PIMR_QCBRORN 0x02000000
+#define AR5212_PIMR_QCBRURN 0x04000000
+#define AR5212_PIMR_QTRIG 0x08000000
+
+/*
+ * Secondary interrupt mask registers (0 - 4)
+ */
+#define AR5212_SIMR0 0x00a4
+#define AR5212_SIMR0_QCU_TXOK 0x000003ff
+#define AR5212_SIMR0_QCU_TXOK_S 0
+#define AR5212_SIMR0_QCU_TXDESC 0x03ff0000
+#define AR5212_SIMR0_QCU_TXDESC_S 16
+
+#define AR5212_SIMR1 0x00a8
+#define AR5212_SIMR1_QCU_TXERR 0x000003ff
+#define AR5212_SIMR1_QCU_TXERR_S 0
+#define AR5212_SIMR1_QCU_TXEOL 0x03ff0000
+#define AR5212_SIMR1_QCU_TXEOL_S 16
+
+#define AR5212_SIMR2 0x00ac
+#define AR5212_SIMR2_QCU_TXURN 0x000003ff
+#define AR5212_SIMR2_QCU_TXURN_S 0
+#define AR5212_SIMR2_MCABT 0x00100000
+#define AR5212_SIMR2_SSERR 0x00200000
+#define AR5212_SIMR2_DPERR 0x00400000
+#define AR5212_SIMR2_TIM 0x01000000
+#define AR5212_SIMR2_CAB_END 0x02000000
+#define AR5212_SIMR2_DTIM_SYNC 0x04000000
+#define AR5212_SIMR2_BCN_TIMEOUT 0x08000000
+#define AR5212_SIMR2_CAB_TIMEOUT 0x10000000
+#define AR5212_SIMR2_DTIM 0x20000000
+
+#define AR5212_SIMR3 0x00b0
+#define AR5212_SIMR3_QCBRORN 0x000003ff
+#define AR5212_SIMR3_QCBRORN_S 0
+#define AR5212_SIMR3_QCBRURN 0x03ff0000
+#define AR5212_SIMR3_QCBRURN_S 16
+
+#define AR5212_SIMR4 0x00b4
+#define AR5212_SIMR4_QTRIG 0x000003ff
+#define AR5212_SIMR4_QTRIG_S 0
+
+/*
+ * Decompression mask registers
+ */
+#define AR5212_DCM_ADDR 0x0400
+#define AR5212_DCM_DATA 0x0404
+
+/*
+ * Decompression configuration registers
+ */
+#define AR5212_DCCFG 0x0420
+
+/*
+ * Compression configuration registers
+ */
+#define AR5212_CCFG 0x0600
+#define AR5212_CCFG_CUP 0x0604
+
+/*
+ * Compression performance counter registers
+ */
+#define AR5212_CPC0 0x0610
+#define AR5212_CPC1 0x0614
+#define AR5212_CPC2 0x0618
+#define AR5212_CPC3 0x061c
+#define AR5212_CPCORN 0x0620
+
+/*
+ * Queue control unit (QCU) registers (0 - 9)
+ */
+#define AR5212_QCU(_n, _a) (((_n) << 2) + _a)
+
+/*
+ * QCU Transmit descriptor pointer registers
+ */
+#define AR5212_QCU_TXDP(_n) AR5212_QCU(_n, 0x0800)
+
+/*
+ * QCU Transmit enable register
+ */
+#define AR5212_QCU_TXE 0x0840
+
+/*
+ * QCU Transmit disable register
+ */
+#define AR5212_QCU_TXD 0x0880
+
+/*
+ * QCU CBR configuration registers
+ */
+#define AR5212_QCU_CBRCFG(_n) AR5212_QCU(_n, 0x08c0)
+#define AR5212_QCU_CBRCFG_INTVAL 0x00ffffff
+#define AR5212_QCU_CBRCFG_INTVAL_S 0
+#define AR5212_QCU_CBRCFG_ORN_THRES 0xff000000
+#define AR5212_QCU_CBRCFG_ORN_THRES_S 24
+
+/*
+ * QCU Ready time configuration registers
+ */
+#define AR5212_QCU_RDYTIMECFG(_n) AR5212_QCU(_n, 0x0900)
+#define AR5212_QCU_RDYTIMECFG_INTVAL 0x00ffffff
+#define AR5212_QCU_RDYTIMECFG_INTVAL_S 0
+#define AR5212_QCU_RDYTIMECFG_DURATION 0x00ffffff
+#define AR5212_QCU_RDYTIMECFG_ENABLE 0x01000000
+
+/*
+ * QCU one shot arm set registers
+ */
+#define AR5212_QCU_ONESHOTARMS(_n) AR5212_QCU(_n, 0x0940)
+#define AR5212_QCU_ONESHOTARMS_M 0x0000ffff
+
+/*
+ * QCU one shot arm clear registers
+ */
+#define AR5212_QCU_ONESHOTARMC(_n) AR5212_QCU(_n, 0x0980)
+#define AR5212_QCU_ONESHOTARMC_M 0x0000ffff
+
+/*
+ * QCU misc registers
+ */
+#define AR5212_QCU_MISC(_n) AR5212_QCU(_n, 0x09c0)
+#define AR5212_QCU_MISC_FRSHED_M 0x0000000f
+#define AR5212_QCU_MISC_FRSHED_ASAP 0
+#define AR5212_QCU_MISC_FRSHED_CBR 1
+#define AR5212_QCU_MISC_FRSHED_DBA_GT 2
+#define AR5212_QCU_MISC_FRSHED_TIM_GT 3
+#define AR5212_QCU_MISC_FRSHED_BCN_SENT_GT 4
+#define AR5212_QCU_MISC_ONESHOT_ENABLE 0x00000010
+#define AR5212_QCU_MISC_CBREXP 0x00000020
+#define AR5212_QCU_MISC_CBREXP_BCN 0x00000040
+#define AR5212_QCU_MISC_BCN_ENABLE 0x00000080
+#define AR5212_QCU_MISC_CBR_THRES_ENABLE 0x00000100
+#define AR5212_QCU_MISC_TXE 0x00000200
+#define AR5212_QCU_MISC_CBR 0x00000400
+#define AR5212_QCU_MISC_DCU_EARLY 0x00000800
+
+/*
+ * QCU status registers
+ */
+#define AR5212_QCU_STS(_n) AR5212_QCU(_n, 0x0a00)
+#define AR5212_QCU_STS_FRMPENDCNT 0x00000003
+#define AR5212_QCU_STS_CBREXPCNT 0x0000ff00
+
+/*
+ * QCU ready time shutdown register
+ */
+#define AR5212_QCU_RDYTIMESHDN 0x0a40
+#define AR5212_QCU_RDYTIMESHDN_M 0x000003ff
+
+/*
+ * QCU compression buffer base registers
+ */
+#define AR5212_QCU_CBB_SELECT 0x0b00
+#define AR5212_QCU_CBB_ADDR 0x0b04
+
+/*
+ * QCU compression buffer configuration register
+ */
+#define AR5212_QCU_CBCFG 0x0b08
+
+/*
+ * DCF control unit (DCU) registers (0 - 9)
+ */
+#define AR5212_DCU(_n, _a) AR5212_QCU(_n, _a)
+
+/*
+ * DCU QCU mask registers
+ */
+#define AR5212_DCU_QCUMASK(_n) AR5212_DCU(_n, 0x1000)
+#define AR5212_DCU_QCUMASK_M 0x000003ff
+
+/*
+ * DCU local IFS settings register
+ */
+#define AR5212_DCU_LCL_IFS(_n) AR5212_DCU(_n, 0x1040)
+#define AR5212_DCU_LCL_IFS_CW_MIN 0x000003ff
+#define AR5212_DCU_LCL_IFS_CW_MIN_S 0
+#define AR5212_DCU_LCL_IFS_CW_MAX 0x000ffc00
+#define AR5212_DCU_LCL_IFS_CW_MAX_S 10
+#define AR5212_DCU_LCL_IFS_AIFS 0x0ff00000
+#define AR5212_DCU_LCL_IFS_AIFS_S 20
+
+/*
+ * DCU retry limit registers
+ */
+#define AR5212_DCU_RETRY_LMT(_n) AR5212_DCU(_n, 0x1080)
+#define AR5212_DCU_RETRY_LMT_SH_RETRY 0x0000000f
+#define AR5212_DCU_RETRY_LMT_SH_RETRY_S 0
+#define AR5212_DCU_RETRY_LMT_LG_RETRY 0x000000f0
+#define AR5212_DCU_RETRY_LMT_LG_RETRY_S 4
+#define AR5212_DCU_RETRY_LMT_SSH_RETRY 0x00003f00
+#define AR5212_DCU_RETRY_LMT_SSH_RETRY_S 8
+#define AR5212_DCU_RETRY_LMT_SLG_RETRY 0x000fc000
+#define AR5212_DCU_RETRY_LMT_SLG_RETRY_S 14
+
+/*
+ * DCU channel time registers
+ */
+#define AR5212_DCU_CHAN_TIME(_n) AR5212_DCU(_n, 0x10c0)
+#define AR5212_DCU_CHAN_TIME_DUR 0x000fffff
+#define AR5212_DCU_CHAN_TIME_DUR_S 0
+#define AR5212_DCU_CHAN_TIME_ENABLE 0x00100000
+
+/*
+ * DCU misc registers
+ */
+#define AR5212_DCU_MISC(_n) AR5212_DCU(_n, 0x1100)
+#define AR5212_DCU_MISC_BACKOFF 0x000007ff
+#define AR5212_DCU_MISC_BACKOFF_FRAG 0x00000200
+#define AR5212_DCU_MISC_HCFPOLL_ENABLE 0x00000800
+#define AR5212_DCU_MISC_BACKOFF_PERSIST 0x00001000
+#define AR5212_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000
+#define AR5212_DCU_MISC_VIRTCOL 0x0000c000
+#define AR5212_DCU_MISC_VIRTCOL_NORMAL 0
+#define AR5212_DCU_MISC_VIRTCOL_MODIFIED 1
+#define AR5212_DCU_MISC_VIRTCOL_IGNORE 2
+#define AR5212_DCU_MISC_BCN_ENABLE 0x00010000
+#define AR5212_DCU_MISC_ARBLOCK_CTL 0x00060000
+#define AR5212_DCU_MISC_ARBLOCK_CTL_S 17
+#define AR5212_DCU_MISC_ARBLOCK_CTL_NONE 0
+#define AR5212_DCU_MISC_ARBLOCK_CTL_INTFRM 1
+#define AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
+#define AR5212_DCU_MISC_ARBLOCK_IGNORE 0x00080000
+#define AR5212_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000
+#define AR5212_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000
+#define AR5212_DCU_MISC_VIRT_COLL_POLICY 0x00400000
+#define AR5212_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
+#define AR5212_DCU_MISC_SEQNUM_CTL 0x01000000
+
+/*
+ * DCU frame sequence number registers
+ */
+#define AR5212_DCU_SEQNUM(_n) AR5212_DCU(_n, 0x1140)
+#define AR5212_DCU_SEQNUM_M 0x00000fff
+/*
+ * DCU global IFS SIFS registers
+ */
+#define AR5212_DCU_GBL_IFS_SIFS 0x1030
+#define AR5212_DCU_GBL_IFS_SIFS_M 0x0000ffff
+
+/*
+ * DCU global IFS slot interval registers
+ */
+#define AR5212_DCU_GBL_IFS_SLOT 0x1070
+#define AR5212_DCU_GBL_IFS_SLOT_M 0x0000ffff
+
+/*
+ * DCU global IFS EIFS registers
+ */
+#define AR5212_DCU_GBL_IFS_EIFS 0x10b0
+#define AR5212_DCU_GBL_IFS_EIFS_M 0x0000ffff
+
+/*
+ * DCU global IFS misc registers
+ */
+#define AR5212_DCU_GBL_IFS_MISC 0x10f0
+#define AR5212_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
+#define AR5212_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008
+#define AR5212_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0
+#define AR5212_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
+#define AR5212_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
+
+/*
+ * DCU frame prefetch control register
+ */
+#define AR5212_DCU_FP 0x1230
+
+/*
+ * DCU transmit pause control/status register
+ */
+#define AR5212_DCU_TXP 0x1270
+#define AR5212_DCU_TXP_M 0x000003ff
+#define AR5212_DCU_TXP_STATUS 0x00010000
+
+/*
+ * DCU transmit filter register
+ */
+#define AR5212_DCU_TX_FILTER 0x1038
+
+/*
+ * DCU clear transmit filter register
+ */
+#define AR5212_DCU_TX_FILTER_CLR 0x143c
+
+/*
+ * DCU set transmit filter register
+ */
+#define AR5212_DCU_TX_FILTER_SET 0x147c
+
+/*
+ * DMA size definitions
+ */
+typedef enum {
+ AR5212_DMASIZE_4B = 0,
+ AR5212_DMASIZE_8B,
+ AR5212_DMASIZE_16B,
+ AR5212_DMASIZE_32B,
+ AR5212_DMASIZE_64B,
+ AR5212_DMASIZE_128B,
+ AR5212_DMASIZE_256B,
+ AR5212_DMASIZE_512B
+} ar5212_dmasize_t;
+
+/*
+ * Reset control register
+ */
+#define AR5212_RC 0x4000
+#define AR5212_RC_PCU 0x00000001
+#define AR5212_RC_BB 0x00000002
+#define AR5212_RC_PCI 0x00000010
+#define AR5212_RC_CHIP ( \
+ AR5212_RC_PCU | AR5212_RC_BB | AR5212_RC_PCI \
+)
+
+/*
+ * Sleep control register
+ */
+#define AR5212_SCR 0x4004
+#define AR5212_SCR_SLDUR 0x0000ffff
+#define AR5212_SCR_SLE 0x00030000
+#define AR5212_SCR_SLE_S 16
+#define AR5212_SCR_SLE_WAKE 0x00000000
+#define AR5212_SCR_SLE_SLP 0x00010000
+#define AR5212_SCR_SLE_ALLOW 0x00020000
+#define AR5212_SCR_SLE_UNITS 0x00000008
+
+/*
+ * Interrupt pending register
+ */
+#define AR5212_INTPEND 0x4008
+#define AR5212_INTPEND_M 0x00000001
+
+/*
+ * Sleep force register
+ */
+#define AR5212_SFR 0x400c
+#define AR5212_SFR_M 0x00000001
+
+/*
+ * PCI configuration register
+ */
+#define AR5212_PCICFG 0x4010
+#define AR5212_PCICFG_CLKRUNEN 0x00000004
+#define AR5212_PCICFG_EESIZE 0x00000018
+#define AR5212_PCICFG_EESIZE_S 3
+#define AR5212_PCICFG_EESIZE_4K 0
+#define AR5212_PCICFG_EESIZE_8K 1
+#define AR5212_PCICFG_EESIZE_16K 2
+#define AR5212_PCICFG_EESIZE_FAIL 3
+#define AR5212_PCICFG_LED 0x00000060
+#define AR5212_PCICFG_LED_NONE 0x00000000
+#define AR5212_PCICFG_LED_PEND 0x00000020
+#define AR5212_PCICFG_LED_ASSOC 0x00000040
+#define AR5212_PCICFG_BUS_SEL 0x00000380
+#define AR5212_PCICFG_CBEFIX_DIS 0x00000400
+#define AR5212_PCICFG_SL_INTEN 0x00000800
+#define AR5212_PCICFG_SL_INPEN 0x00002800
+#define AR5212_PCICFG_SPWR_DN 0x00010000
+#define AR5212_PCICFG_LEDMODE 0x000e0000
+#define AR5212_PCICFG_LEDMODE_PROP 0x00000000
+#define AR5212_PCICFG_LEDMODE_PROM 0x00020000
+#define AR5212_PCICFG_LEDMODE_PWR 0x00040000
+#define AR5212_PCICFG_LEDMODE_RAND 0x00060000
+#define AR5212_PCICFG_LEDBLINK 0x00700000
+#define AR5212_PCICFG_LEDBLINK_S 20
+#define AR5212_PCICFG_LEDSLOW 0x00800000
+
+/*
+ * "General Purpose Input/Output" (GPIO) control register
+ */
+#define AR5212_GPIOCR 0x4014
+#define AR5212_GPIOCR_INT_ENA 0x00008000
+#define AR5212_GPIOCR_INT_SELL 0x00000000
+#define AR5212_GPIOCR_INT_SELH 0x00010000
+#define AR5212_GPIOCR_NONE(n) (0 << ((n) * 2))
+#define AR5212_GPIOCR_OUT0(n) (1 << ((n) * 2))
+#define AR5212_GPIOCR_OUT1(n) (2 << ((n) * 2))
+#define AR5212_GPIOCR_ALL(n) (3 << ((n) * 2))
+#define AR5212_GPIOCR_INT_SEL(n) ((n) << 12)
+
+#define AR5212_NUM_GPIO 6
+
+/*
+ * "General Purpose Input/Output" (GPIO) data output register
+ */
+#define AR5212_GPIODO 0x4018
+
+/*
+ * "General Purpose Input/Output" (GPIO) data input register
+ */
+#define AR5212_GPIODI 0x401c
+#define AR5212_GPIODI_M 0x0000002f
+
+/*
+ * Silicon revision register
+ */
+#define AR5212_SREV 0x4020
+#define AR5212_SREV_M 0x000000ff
+#define AR5212_SREV_REVISION 0x0000000f
+#define AR5212_SREV_VERSION 0x000000f0
+
+/*
+ * EEPROM access registers
+ */
+#define AR5212_EEPROM_BASE 0x6000
+#define AR5212_EEPROM_DATA 0x6004
+#define AR5212_EEPROM_CMD 0x6008
+#define AR5212_EEPROM_CMD_READ 0x00000001
+#define AR5212_EEPROM_CMD_WRITE 0x00000002
+#define AR5212_EEPROM_CMD_RESET 0x00000004
+#define AR5212_EEPROM_STATUS 0x600c
+#define AR5212_EEPROM_STAT_RDERR 0x00000001
+#define AR5212_EEPROM_STAT_RDDONE 0x00000002
+#define AR5212_EEPROM_STAT_WRERR 0x00000004
+#define AR5212_EEPROM_STAT_WRDONE 0x00000008
+#define AR5212_EEPROM_CFG 0x6010
+
+/*
+ * PCU registers
+ */
+
+#define AR5212_PCU_MIN 0x8000
+#define AR5212_PCU_MAX 0x8fff
+
+/*
+ * First station id register (MAC address in lower 32 bits)
+ */
+#define AR5212_STA_ID0 0x8000
+
+/*
+ * Second station id register (MAC address in upper 16 bits)
+ */
+#define AR5212_STA_ID1 0x8004
+#define AR5212_STA_ID1_AP 0x00010000
+#define AR5212_STA_ID1_ADHOC 0x00020000
+#define AR5212_STA_ID1_PWR_SV 0x00040000
+#define AR5212_STA_ID1_NO_KEYSRCH 0x00080000
+#define AR5212_STA_ID1_PCF 0x00100000
+#define AR5212_STA_ID1_DEFAULT_ANTENNA 0x00200000
+#define AR5212_STA_ID1_DESC_ANTENNA 0x00400000
+#define AR5212_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000
+#define AR5212_STA_ID1_ACKCTS_6MB 0x01000000
+#define AR5212_STA_ID1_BASE_RATE_11B 0x02000000
+
+/*
+ * First BSSID register (MAC address, lower 32bits)
+ */
+#define AR5212_BSS_ID0 0x8008
+
+/*
+ * Second BSSID register (MAC address in upper 16 bits)
+ *
+ * AID: Association ID
+ */
+#define AR5212_BSS_ID1 0x800c
+#define AR5212_BSS_ID1_AID 0xffff0000
+#define AR5212_BSS_ID1_AID_S 16
+
+/*
+ * Backoff slot time register
+ */
+#define AR5212_SLOT_TIME 0x8010
+
+/*
+ * ACK/CTS timeout register
+ */
+#define AR5212_TIME_OUT 0x8014
+#define AR5212_TIME_OUT_ACK 0x00001fff
+#define AR5212_TIME_OUT_ACK_S 0
+#define AR5212_TIME_OUT_CTS 0x1fff0000
+#define AR5212_TIME_OUT_CTS_S 16
+
+/*
+ * RSSI threshold register
+ */
+#define AR5212_RSSI_THR 0x8018
+#define AR5212_RSSI_THR_M 0x000000ff
+#define AR5212_RSSI_THR_BMISS 0x0000ff00
+#define AR5212_RSSI_THR_BMISS_S 8
+
+/*
+ * Transmit latency register
+ */
+#define AR5212_USEC 0x801c
+#define AR5212_USEC_1 0x0000007f
+#define AR5212_USEC_1_S 0
+#define AR5212_USEC_32 0x00003f80
+#define AR5212_USEC_32_S 7
+#define AR5212_USEC_TX_LATENCY 0x007fc000
+#define AR5212_USEC_TX_LATENCY_S 14
+#define AR5212_USEC_RX_LATENCY 0x1f800000
+#define AR5212_USEC_RX_LATENCY_S 23
+#define AR5311_USEC_TX_LATENCY 0x000fc000
+#define AR5311_USEC_TX_LATENCY_S 14
+#define AR5311_USEC_RX_LATENCY 0x03f00000
+#define AR5311_USEC_RX_LATENCY_S 20
+
+/*
+ * PCU beacon control register
+ */
+#define AR5212_BEACON 0x8020
+#define AR5212_BEACON_PERIOD 0x0000ffff
+#define AR5212_BEACON_PERIOD_S 0
+#define AR5212_BEACON_TIM 0x007f0000
+#define AR5212_BEACON_TIM_S 16
+#define AR5212_BEACON_ENABLE 0x00800000
+#define AR5212_BEACON_RESET_TSF 0x01000000
+
+/*
+ * CFP period register
+ */
+#define AR5212_CFP_PERIOD 0x8024
+
+/*
+ * Next beacon time register
+ */
+#define AR5212_TIMER0 0x8028
+
+/*
+ * Next DMA beacon alert register
+ */
+#define AR5212_TIMER1 0x802c
+
+/*
+ * Next software beacon alert register
+ */
+#define AR5212_TIMER2 0x8030
+
+/*
+ * Next ATIM window time register
+ */
+#define AR5212_TIMER3 0x8034
+
+/*
+ * CFP duration register
+ */
+#define AR5212_CFP_DUR 0x8038
+
+/*
+ * Receive filter register
+ */
+#define AR5212_RX_FILTER 0x803c
+#define AR5212_RX_FILTER_UNICAST 0x00000001
+#define AR5212_RX_FILTER_MULTICAST 0x00000002
+#define AR5212_RX_FILTER_BROADCAST 0x00000004
+#define AR5212_RX_FILTER_CONTROL 0x00000008
+#define AR5212_RX_FILTER_BEACON 0x00000010
+#define AR5212_RX_FILTER_PROMISC 0x00000020
+#define AR5212_RX_FILTER_XR_POLL 0x00000040
+#define AR5212_RX_FILTER_PROBE_REQ 0x00000080
+
+/*
+ * Multicast filter register (lower 32 bits)
+ */
+#define AR5212_MCAST_FIL0 0x8040
+
+/*
+ * Multicast filter register (higher 16 bits)
+ */
+#define AR5212_MCAST_FIL1 0x8044
+
+/*
+ * PCU control register
+ */
+#define AR5212_DIAG_SW 0x8048
+#define AR5212_DIAG_SW_DIS_WEP_ACK 0x00000001
+#define AR5212_DIAG_SW_DIS_ACK 0x00000002
+#define AR5212_DIAG_SW_DIS_CTS 0x00000004
+#define AR5212_DIAG_SW_DIS_ENC 0x00000008
+#define AR5212_DIAG_SW_DIS_DEC 0x00000010
+#define AR5212_DIAG_SW_DIS_RX 0x00000020
+#define AR5212_DIAG_SW_LOOP_BACK 0x00000040
+#define AR5212_DIAG_SW_CORR_FCS 0x00000080
+#define AR5212_DIAG_SW_CHAN_INFO 0x00000100
+#define AR5212_DIAG_SW_EN_SCRAM_SEED 0x00000200
+#define AR5212_DIAG_SW_ECO_ENABLE 0x00000400
+#define AR5212_DIAG_SW_SCRAM_SEED_M 0x0001fc00
+#define AR5212_DIAG_SW_SCRAM_SEED_S 10
+#define AR5212_DIAG_SW_FRAME_NV0 0x00020000
+#define AR5212_DIAG_SW_OBSPT_M 0x000c0000
+#define AR5212_DIAG_SW_OBSPT_S 18
+
+/*
+ * TSF (clock) register (lower 32 bits)
+ */
+#define AR5212_TSF_L32 0x804c
+
+/*
+ * TSF (clock) register (higher 32 bits)
+ */
+#define AR5212_TSF_U32 0x8050
+
+/*
+ * ADDAC test register
+ */
+#define AR5212_ADDAC_TEST 0x8054
+
+/*
+ * Default antenna register
+ */
+#define AR5212_DEFAULT_ANTENNA 0x8058
+
+/*
+ * Last beacon timestamp register
+ */
+#define AR5212_LAST_TSTP 0x8080
+
+/*
+ * NAV register (current)
+ */
+#define AR5212_NAV 0x8084
+
+/*
+ * RTS success register
+ */
+#define AR5212_RTS_OK 0x8088
+
+/*
+ * RTS failure register
+ */
+#define AR5212_RTS_FAIL 0x808c
+
+/*
+ * ACK failure register
+ */
+#define AR5212_ACK_FAIL 0x8090
+
+/*
+ * FCS failure register
+ */
+#define AR5212_FCS_FAIL 0x8094
+
+/*
+ * Beacon count register
+ */
+#define AR5212_BEACON_CNT 0x8098
+
+/*
+ * XR (eXtended Range) mode register
+ */
+#define AR5212_XRMODE 0x80c0
+#define AR5212_XRMODE_POLL_TYPE_M 0x0000003f
+#define AR5212_XRMODE_POLL_TYPE_S 0
+#define AR5212_XRMODE_POLL_SUBTYPE_M 0x0000003c
+#define AR5212_XRMODE_POLL_SUBTYPE_S 2
+#define AR5212_XRMODE_POLL_WAIT_ALL 0x00000080
+#define AR5212_XRMODE_SIFS_DELAY 0x000fff00
+#define AR5212_XRMODE_FRAME_HOLD_M 0xfff00000
+#define AR5212_XRMODE_FRAME_HOLD_S 20
+
+/*
+ * XR delay register
+ */
+#define AR5212_XRDELAY 0x80c4
+#define AR5212_XRDELAY_SLOT_DELAY_M 0x0000ffff
+#define AR5212_XRDELAY_SLOT_DELAY_S 0
+#define AR5212_XRDELAY_CHIRP_DELAY_M 0xffff0000
+#define AR5212_XRDELAY_CHIRP_DELAY_S 16
+
+/*
+ * XR timeout register
+ */
+#define AR5212_XRTIMEOUT 0x80c8
+#define AR5212_XRTIMEOUT_CHIRP_M 0x0000ffff
+#define AR5212_XRTIMEOUT_CHIRP_S 0
+#define AR5212_XRTIMEOUT_POLL_M 0xffff0000
+#define AR5212_XRTIMEOUT_POLL_S 16
+
+/*
+ * XR chirp register
+ */
+#define AR5212_XRCHIRP 0x80cc
+#define AR5212_XRCHIRP_SEND 0x00000001
+#define AR5212_XRCHIRP_GAP 0xffff0000
+
+/*
+ * XR stomp register
+ */
+#define AR5212_XRSTOMP 0x80d0
+#define AR5212_XRSTOMP_TX 0x00000001
+#define AR5212_XRSTOMP_RX_ABORT 0x00000002
+#define AR5212_XRSTOMP_RSSI_THRES 0x0000ff00
+
+/*
+ * First enhanced sleep register
+ */
+#define AR5212_SLEEP0 0x80d4
+#define AR5212_SLEEP0_NEXT_DTIM_M 0x0007ffff
+#define AR5212_SLEEP0_NEXT_DTIM_S 0
+#define AR5212_SLEEP0_ASSUME_DTIM 0x00080000
+#define AR5212_SLEEP0_ENH_SLEEP_EN 0x00100000
+#define AR5212_SLEEP0_CAPTO_M 0xff000000
+#define AR5212_SLEEP0_CAPTO_S 24
+
+/*
+ * Second enhanced sleep register
+ */
+#define AR5212_SLEEP1 0x80d8
+#define AR5212_SLEEP1_NEXT_TIM_M 0x0007ffff
+#define AR5212_SLEEP1_NEXT_TIM_S 0
+#define AR5212_SLEEP1_BEACON_TO_M 0xff000000
+#define AR5212_SLEEP1_BEACON_TO_S 24
+
+/*
+ * Third enhanced sleep register
+ */
+#define AR5212_SLEEP2 0x80dc
+#define AR5212_SLEEP2_TIM_PER_M 0x0000ffff
+#define AR5212_SLEEP2_TIM_PER_S 0
+#define AR5212_SLEEP2_DTIM_PER_M 0xffff0000
+#define AR5212_SLEEP2_DTIM_PER_S 16
+
+/*
+ * BSSID mask registers
+ */
+#define AR5212_BSS_IDM0 0x80e0
+#define AR5212_BSS_IDM1 0x80e4
+
+/*
+ * TX power control (TPC) register
+ */
+#define AR5212_TXPC 0x80e8
+#define AR5212_TXPC_ACK_M 0x0000003f
+#define AR5212_TXPC_ACK_S 0
+#define AR5212_TXPC_CTS_M 0x00003f00
+#define AR5212_TXPC_CTS_S 8
+#define AR5212_TXPC_CHIRP_M 0x003f0000
+#define AR5212_TXPC_CHIRP_S 22
+
+/*
+ * Profile count registers
+ */
+#define AR5212_PROFCNT_TX 0x80ec
+#define AR5212_PROFCNT_RX 0x80f0
+#define AR5212_PROFCNT_RXCLR 0x80f4
+#define AR5212_PROFCNT_CYCLE 0x80f8
+
+/*
+ * TSF parameter register
+ */
+#define AR5212_TSF_PARM 0x8104
+#define AR5212_TSF_PARM_INC_M 0x000000ff
+#define AR5212_TSF_PARM_INC_S 0
+
+/*
+ * PHY error filter register
+ */
+#define AR5212_PHY_ERR_FIL 0x810c
+#define AR5212_PHY_ERR_FIL_RADAR 0x00000020
+#define AR5212_PHY_ERR_FIL_OFDM 0x00020000
+#define AR5212_PHY_ERR_FIL_CCK 0x02000000
+
+/*
+ * Rate duration register
+ */
+#define AR5212_RATE_DUR_0 0x8700
+#define AR5212_RATE_DUR(_n) (AR5212_RATE_DUR_0 + ((_n) << 2))
+
+/*
+ * Key table (WEP) register
+ */
+#define AR5212_KEYTABLE_0 0x8800
+#define AR5212_KEYTABLE(n) (AR5212_KEYTABLE_0 + ((n) * 32))
+#define AR5212_KEYTABLE_TYPE_40 0x00000000
+#define AR5212_KEYTABLE_TYPE_104 0x00000001
+#define AR5212_KEYTABLE_TYPE_128 0x00000003
+#define AR5212_KEYTABLE_TYPE_TKIP 0x00000004
+#define AR5212_KEYTABLE_TYPE_AES 0x00000005
+#define AR5212_KEYTABLE_TYPE_CCM 0x00000006
+#define AR5212_KEYTABLE_TYPE_NULL 0x00000007
+#define AR5212_KEYTABLE_ANTENNA 0x00000008
+#define AR5212_KEYTABLE_VALID 0x00008000
+
+#define AR5212_KEYTABLE_SIZE 64
+#define AR5212_KEYCACHE_SIZE 8
+
+/*
+ * PHY register
+ */
+#define AR5212_PHY(_n) (0x9800 + ((_n) << 2))
+#define AR5212_PHY_SHIFT_2GHZ 0x00004007
+#define AR5212_PHY_SHIFT_5GHZ 0x00000007
+
+/*
+ * PHY turbo mode register
+ */
+#define AR5212_PHY_TURBO 0x9804
+#define AR5212_PHY_TURBO_MODE 0x00000001
+#define AR5212_PHY_TURBO_SHORT 0x00000002
+
+/*
+ * PHY agility command register
+ */
+#define AR5212_PHY_AGC 0x9808
+#define AR5212_PHY_AGC_DISABLE 0x08000000
+
+/*
+ * PHY timing register
+ */
+#define AR5212_PHY_TIMING_3 0x9814
+#define AR5212_PHY_TIMING_3_DSC_MAN 0xfffe0000
+#define AR5212_PHY_TIMING_3_DSC_MAN_S 17
+#define AR5212_PHY_TIMING_3_DSC_EXP 0x0001e000
+#define AR5212_PHY_TIMING_3_DSC_EXP_S 13
+
+/*
+ * PHY chip revision register
+ */
+#define AR5212_PHY_CHIP_ID 0x9818
+
+/*
+ * PHY activation register
+ */
+#define AR5212_PHY_ACTIVE 0x981c
+#define AR5212_PHY_ENABLE 0x00000001
+#define AR5212_PHY_DISABLE 0x00000002
+
+/*
+ * PHY agility control register
+ */
+#define AR5212_PHY_AGCCTL 0x9860
+#define AR5212_PHY_AGCCTL_CAL 0x00000001
+#define AR5212_PHY_AGCCTL_NF 0x00000002
+
+/*
+ * PHY noise floor status register
+ */
+#define AR5212_PHY_NF 0x9864
+#define AR5212_PHY_NF_M 0x000001ff
+#define AR5212_PHY_NF_ACTIVE 0x00000100
+#define AR5212_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5212_PHY_NF_M)
+#define AR5212_PHY_NF_AVAL(_n) (-((_n) ^ AR5212_PHY_NF_M) + 1)
+#define AR5212_PHY_NF_SVAL(_n) (((_n) & AR5212_PHY_NF_M) | (1 << 9))
+
+/*
+ * PHY sleep registers
+ */
+#define AR5212_PHY_SCR 0x9870
+#define AR5212_PHY_SCR_32MHZ 0x0000001f
+#define AR5212_PHY_SLMT 0x9874
+#define AR5212_PHY_SLMT_32MHZ 0x0000007f
+#define AR5212_PHY_SCAL 0x9878
+#define AR5212_PHY_SCAL_32MHZ 0x0000000e
+
+/*
+ * PHY PLL control register
+ */
+#define AR5212_PHY_PLL 0x987c
+#define AR5212_PHY_PLL_40MHZ 0x000000aa
+#define AR5212_PHY_PLL_44MHZ 0x000000ab
+#define AR5212_PHY_PLL_AR5111 0x00000000
+#define AR5212_PHY_PLL_AR5112 0x00000040
+
+/*
+ * PHY receiver delay register
+ */
+#define AR5212_PHY_RX_DELAY 0x9914
+#define AR5212_PHY_RX_DELAY_M 0x00003fff
+
+/*
+ * PHY timing IQ control register
+ */
+#define AR5212_PHY_IQ 0x9920
+#define AR5212_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
+#define AR5212_PHY_IQ_CORR_Q_I_COFF 0x000007e0
+#define AR5212_PHY_IQ_CORR_Q_I_COFF_S 5
+#define AR5212_PHY_IQ_CORR_ENABLE 0x00000800
+#define AR5212_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
+#define AR5212_PHY_IQ_CAL_NUM_LOG_MAX_S 12
+#define AR5212_PHY_IQ_RUN 0x00010000
+
+/*
+ * PHY PAPD probe register
+ */
+#define AR5212_PHY_PAPD_PROBE 0x9930
+#define AR5212_PHY_PAPD_PROBE_TXPOWER 0x00007e00
+#define AR5212_PHY_PAPD_PROBE_TXPOWER_S 9
+#define AR5212_PHY_PAPD_PROBE_TX_NEXT 0x00008000
+#define AR5212_PHY_PAPD_PROBE_GAINF 0xfe000000
+#define AR5212_PHY_PAPD_PROBE_GAINF_S 25
+
+/*
+ * PHY TX power registers
+ */
+#define AR5212_PHY_TXPOWER_RATE1 0x9934
+#define AR5212_PHY_TXPOWER_RATE2 0x9938
+#define AR5212_PHY_TXPOWER_RATE_MAX 0x993c
+#define AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
+#define AR5212_PHY_TXPOWER_RATE3 0xa234
+#define AR5212_PHY_TXPOWER_RATE4 0xa238
+
+/*
+ * PHY frame control register
+ */
+#define AR5212_PHY_FC 0x9944
+#define AR5212_PHY_FC_TX_CLIP 0x00000038
+#define AR5212_PHY_FC_TX_CLIP_S 3
+
+/*
+ * PHY radar detection enable register
+ */
+#define AR5212_PHY_RADAR 0x9954
+#define AR5212_PHY_RADAR_DISABLE 0x00000000
+#define AR5212_PHY_RADAR_ENABLE 0x00000001
+
+/*
+ * PHY antenna switch table registers
+ */
+#define AR5212_PHY_ANT_SWITCH_TABLE_0 0x9960
+#define AR5212_PHY_ANT_SWITCH_TABLE_1 0x9964
+
+/*
+ * PHY clock sleep registers
+ */
+#define AR5212_PHY_SCLOCK 0x99f0
+#define AR5212_PHY_SCLOCK_32MHZ 0x0000000c
+#define AR5212_PHY_SDELAY 0x99f4
+#define AR5212_PHY_SDELAY_32MHZ 0x000000ff
+#define AR5212_PHY_SPENDING 0x99f8
+#define AR5212_PHY_SPENDING_AR5111 0x00000018
+#define AR5212_PHY_SPENDING_AR5112 0x00000014
+
+/*
+ * PHY timing IQ calibration result register
+ */
+#define AR5212_PHY_IQRES_CAL_PWR_I 0x9c10
+#define AR5212_PHY_IQRES_CAL_PWR_Q 0x9c14
+#define AR5212_PHY_IQRES_CAL_CORR 0x9c18
+
+/*
+ * PHY current RSSI register
+ */
+#define AR5212_PHY_CURRENT_RSSI 0x9c1c
+
+/*
+ * PHY PCDAC TX power register
+ */
+#define AR5212_PHY_PCDAC_TXPOWER(_n) (0xa180 + ((_n) << 2))
+
+/*
+ * PHY mode register
+ */
+#define AR5212_PHY_MODE 0x0a200
+#define AR5212_PHY_MODE_MOD 0x00000001
+#define AR5212_PHY_MODE_MOD_OFDM 0
+#define AR5212_PHY_MODE_MOD_CCK 1
+#define AR5212_PHY_MODE_FREQ 0x00000002
+#define AR5212_PHY_MODE_FREQ_5GHZ 0
+#define AR5212_PHY_MODE_FREQ_2GHZ 2
+#define AR5212_PHY_MODE_MOD_DYN 0x00000004
+#define AR5212_PHY_MODE_RAD 0x00000008
+#define AR5212_PHY_MODE_RAD_AR5111 0
+#define AR5212_PHY_MODE_RAD_AR5112 8
+#define AR5212_PHY_MODE_XR 0x00000010
+
+/*
+ * PHY 2GHz gain register
+ */
+#define AR5212_PHY_GAIN_2GHZ 0xa20c
+#define AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
+#define AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
+
+#endif
+
+/*
+ * Common ar5xxx EEPROM data registers
+ */
+
+#define EEPROM_MAGIC 0x003d
+#define EEPROM_MAGIC_VALUE 0x5aa5
+#define EEPROM_PROTECT 0x003f
+#define EEPROM_PROTECT_RD_0_31 0x0001
+#define EEPROM_PROTECT_WR_0_31 0x0002
+#define EEPROM_PROTECT_RD_32_63 0x0004
+#define EEPROM_PROTECT_WR_32_63 0x0008
+#define EEPROM_PROTECT_RD_64_127 0x0010
+#define EEPROM_PROTECT_WR_64_127 0x0020
+#define EEPROM_PROTECT_RD_128_191 0x0040
+#define EEPROM_PROTECT_WR_128_191 0x0080
+#define EEPROM_PROTECT_RD_192_207 0x0100
+#define EEPROM_PROTECT_WR_192_207 0x0200
+#define EEPROM_PROTECT_RD_208_223 0x0400
+#define EEPROM_PROTECT_WR_208_223 0x0800
+#define EEPROM_PROTECT_RD_224_239 0x1000
+#define EEPROM_PROTECT_WR_224_239 0x2000
+#define EEPROM_PROTECT_RD_240_255 0x4000
+#define EEPROM_PROTECT_WR_240_255 0x8000
+#define EEPROM_REG_DOMAIN 0x00bf
+#define EEPROM_INFO_BASE 0x00c0
+#define EEPROM_INFO_MAX \
+ (0x400 - EEPROM_INFO_BASE)
+#define EEPROM_INFO(_n) (EEPROM_INFO_BASE + (_n))
+
+#define EEPROM_VERSION EEPROM_INFO(1)
+#define EEPROM_VERSION_3_0 0x3000
+#define EEPROM_VERSION_3_1 0x3001
+#define EEPROM_VERSION_3_2 0x3002
+#define EEPROM_VERSION_3_3 0x3003
+#define EEPROM_VERSION_3_4 0x3004
+#define EEPROM_VERSION_4_0 0x4000
+#define EEPROM_VERSION_4_1 0x4001
+#define EEPROM_VERSION_4_2 0x4002
+#define EEPROM_VERSION_4_3 0x4003
+#define EEPROM_VERSION_4_6 0x4006
+#define EEPROM_VERSION_4_7 0x3007
+
+#define EEPROM_MODE_11A 0
+#define EEPROM_MODE_11B 1
+#define EEPROM_MODE_11G 2
+
+#define EEPROM_HDR EEPROM_INFO(2)
+#define EEPROM_HDR_11A(_v) (((_v) >> EEPROM_MODE_11A) & 0x1)
+#define EEPROM_HDR_11B(_v) (((_v) >> EEPROM_MODE_11B) & 0x1)
+#define EEPROM_HDR_11G(_v) (((_v) >> EEPROM_MODE_11G) & 0x1)
+#define EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1)
+#define EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f)
+#define EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
+#define EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1)
+#define EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1)
+
+#define EEPROM_RFKILL_GPIO_SEL 0x0000001c
+#define EEPROM_RFKILL_GPIO_SEL_S 2
+#define EEPROM_RFKILL_POLARITY 0x00000002
+#define EEPROM_RFKILL_POLARITY_S 1
+
+/* Newer EEPROMs are using a different offset */
+#define EEPROM_OFF(_v, _v3_0, _v3_3) \
+ (((_v) >= EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
+
+#define EEPROM_ANT_GAIN(_v) EEPROM_OFF(_v, 0x00c4, 0x00c3)
+#define EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
+#define EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
+
+#define EEPROM_MODES_11A(_v) EEPROM_OFF(_v, 0x00c5, 0x00d4)
+#define EEPROM_MODES_11B(_v) EEPROM_OFF(_v, 0x00d0, 0x00f2)
+#define EEPROM_MODES_11G(_v) EEPROM_OFF(_v, 0x00da, 0x010d)
+#define EEPROM_CTL(_v) EEPROM_OFF(_v, 0x00e4, 0x0128)
+
+/* Since 3.1 */
+#define EEPROM_OBDB0_2GHZ 0x00ec
+#define EEPROM_OBDB1_2GHZ 0x00ed
+
+/* Misc values available since EEPROM 4.0 */
+#define EEPROM_MISC0 0x00c4
+#define EEPROM_EARSTART(_v) ((_v) & 0xfff)
+#define EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
+#define EEPROM_MISC1 0x00c5
+#define EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
+#define EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
+
+/* Some EEPROM defines */
+#define EEPROM_EEP_SCALE 100
+#define EEPROM_EEP_DELTA 10
+#define EEPROM_MODES 3
+#define EEPROM_5GHZ_CHAN 10
+#define EEPROM_2GHZ_CHAN 3
+#define EEPROM_MAX_CHAN 10
+#define EEPROM_PCDAC 11
+#define EEPROM_TEST_FREQ 8
+#define EEPROM_EDGES 8
+#define EEPROM_INTERCEPTS 11
+#define EEPROM_FREQ_M(_v) EEPROM_OFF(_v, 0x7f, 0xff)
+#define EEPROM_PCDAC_M 0x3f
+#define EEPROM_PCDAC_START 1
+#define EEPROM_PCDAC_STOP 63
+#define EEPROM_PCDAC_STEP 1
+#define EEPROM_NON_EDGE_M 0x40
+#define EEPROM_CHANNEL_POWER 8
+#define EEPROM_OBDB 4
+#define EEPROM_OBDB_DIS 0xffff
+#define EEPROM_CHANNEL_DIS 0xff
+#define EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
+#define EEPROM_CTLS(_v) _EEPROM_OFF(_v, 16, 32)
+#define EEPROM_MAX_CTLS 32
+#define EEPROM_XPD_PER_CHANNEL 4
+#define EEPROM_XPD0_POINTS 4
+#define EEPROM_XPD3_POINTS 3
+#define EEPROM_INTERCEPT_10_2GHZ 35
+#define EEPROM_INTERCEPT_10_5GHZ 55
+#define EEPROM_POWER_M 0x3f
+#define EEPROM_POWER_MIN 0
+#define EEPROM_POWER_MAX 3150
+#define EEPROM_POWER_STEP 50
+#define EEPROM_POWER_TABLE_SIZE 64
+#define EEPROM_POWER_LOC_11B 4
+#define EEPROM_POWER_LOC_11G 6
+#define EEPROM_I_GAIN 10
+#define EEPROM_CCK_OFDM_DELTA 15
+#define EEPROM_IQ_CAL 2
+
+
+#define TXDESC_VEOL 0x20
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
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^ permalink raw reply
* atheros driver (1/8)
From: Mateusz Berezecki @ 2005-08-05 2:57 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: atheros5212-1.patch --]
[-- Type: text/x-patch, Size: 1885 bytes --]
--- netdev-2.6.git#ieee80211/drivers/net/wireless/Kconfig 2005-08-02 13:18:21.000000000 +0200
+++ netdev-atheros/drivers/net/wireless/Kconfig 2005-08-05 03:43:32.000000000 +0200
@@ -459,6 +459,14 @@ config PRISM54
say M here and read <file:Documentation/modules.txt>. The module
will be called prism54.ko.
+comment "Atheros combo cardbus cards support"
+config PCMCIA_ATHEROS_5212
+ tristate "Atheros 5212 (a/b/g) combo cards"
+ depends on NET_RADIO && EXPERIMENTAL && PCMCIA
+ ---help---
+ Experimental support for Atheros radio chips.
+
+
# yes, this works even when no drivers are selected
config NET_WIRELESS
bool
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/Makefile netdev-atheros/drivers/net/wireless/Makefile
--- netdev-2.6.git#ieee80211/drivers/net/wireless/Makefile 2005-08-02 13:18:22.000000000 +0200
+++ netdev-atheros/drivers/net/wireless/Makefile 2005-08-05 03:48:17.000000000 +0200
@@ -35,3 +35,5 @@ obj-$(CONFIG_PRISM54) += prism54/
# 16-bit wireless PCMCIA client drivers
obj-$(CONFIG_PCMCIA_RAYCS) += ray_cs.o
obj-$(CONFIG_PCMCIA_WL3501) += wl3501_cs.o
+
+obj-$(CONFIG_PCMCIA_ATHEROS_5212) += atheros/atheros5212/
diff -uprN -X 'netdev-2.6.git#ieee80211/Documentation/dontdiff' netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/Makefile netdev-atheros/drivers/net/wireless/atheros/atheros5212/Makefile
--- netdev-2.6.git#ieee80211/drivers/net/wireless/atheros/atheros5212/Makefile 1970-01-01 01:00:00.000000000 +0100
+++ netdev-atheros/drivers/net/wireless/atheros/atheros5212/Makefile 2005-08-05 03:51:53.000000000 +0200
@@ -0,0 +1,3 @@
+atheros5212-objs := init.o eeprom.o beacons.o powermodes.o keys.o mode_tables.o regops.o interrupts.o caps.o chans.o transmit_receive.o mode_tables.o other.o ioctl.o
+
+obj-$(CONFIG_PCMCIA_ATHEROS_5212) += atheros5212.o
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
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^ permalink raw reply
* atheros driver - desc
From: Mateusz Berezecki @ 2005-08-05 2:55 UTC (permalink / raw)
To: kernel-mentors; +Cc: netdev
Hi list members,
I just post the code for review for anyone interested.
I would be more than pleased to hear some feedback from you on the code.
Im sending a series of 8 patches splitted and diffed as in
SubmittingPatches documentation.
The driver is not yet fully working because I didn't finish kernel
integration yet. Almost all
driver I/O ops are reverse engineered independently of openbsd openhal
which is missing just too much.
Ok, enough talking. Most of the atheros 5212 hal is now open :)
sending patches...
Mateusz
^ permalink raw reply
* Re: latest netdev tree - (broadcom44 bug?) letting you know...
From: Jeff Garzik @ 2005-08-04 20:31 UTC (permalink / raw)
To: Mateusz Berezecki; +Cc: netdev
In-Reply-To: <42F22AD5.3020600@gmail.com>
Mateusz Berezecki wrote:
> Hi list readers
>
> I am using netdev treee (ieee80211 branch) fetched using git 2 days ago
> and what worries me is that
> my b44 card stopped working. I dont know if that's driver issue or
> something has changed inside the network subsystem.
> I am trying to track down the changes and hopefully will post the result.
Nothing in that tree has changed the b44 driver...
Jeff
^ permalink raw reply
* [PATCH ieee80211] ieee80211.h: minor changes to header
From: Michael Wu @ 2005-08-04 18:02 UTC (permalink / raw)
To: Jeff Garzik; +Cc: netdev
Hi,
This patch:
- fixes misc. whitespace/comments
- replaces u16 with __le16/__be16 where appropriate
Signed-off-by: Michael Wu <flamingice@sourmilk.net>
diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h
--- a/include/net/ieee80211.h
+++ b/include/net/ieee80211.h
@@ -47,22 +47,22 @@
#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
struct ieee80211_hdr {
- u16 frame_ctl;
- u16 duration_id;
+ __le16 frame_ctl;
+ __le16 duration_id;
u8 addr1[ETH_ALEN];
u8 addr2[ETH_ALEN];
u8 addr3[ETH_ALEN];
- u16 seq_ctl;
+ __le16 seq_ctl;
u8 addr4[ETH_ALEN];
} __attribute__ ((packed));
struct ieee80211_hdr_3addr {
- u16 frame_ctl;
- u16 duration_id;
+ __le16 frame_ctl;
+ __le16 duration_id;
u8 addr1[ETH_ALEN];
u8 addr2[ETH_ALEN];
u8 addr3[ETH_ALEN];
- u16 seq_ctl;
+ __le16 seq_ctl;
} __attribute__ ((packed));
enum eap_type {
@@ -88,10 +88,10 @@ static inline const char *eap_get_type(i
struct eapol {
u8 snap[6];
- u16 ethertype;
+ __be16 ethertype;
u8 version;
u8 type;
- u16 length;
+ __be16 length;
} __attribute__ ((packed));
#define IEEE80211_1ADDR_LEN 10
@@ -223,9 +223,9 @@ do { if (ieee80211_debug_level & (level)
#include <linux/if_arp.h> /* ARPHRD_ETHER */
#ifndef WIRELESS_SPY
-#define WIRELESS_SPY // enable iwspy support
+#define WIRELESS_SPY /* enable iwspy support */
#endif
-#include <net/iw_handler.h> // new driver API
+#include <net/iw_handler.h> /* new driver API */
#ifndef ETH_P_PAE
#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
@@ -520,9 +520,9 @@ struct ieee80211_info_element {
struct ieee80211_authentication {
struct ieee80211_hdr_3addr header;
- u16 algorithm;
- u16 transaction;
- u16 status;
+ __le16 algorithm;
+ __le16 transaction;
+ __le16 status;
struct ieee80211_info_element info_element;
} __attribute__ ((packed));
@@ -530,23 +530,23 @@ struct ieee80211_authentication {
struct ieee80211_probe_response {
struct ieee80211_hdr_3addr header;
u32 time_stamp[2];
- u16 beacon_interval;
- u16 capability;
+ __le16 beacon_interval;
+ __le16 capability;
struct ieee80211_info_element info_element;
} __attribute__ ((packed));
struct ieee80211_assoc_request_frame {
- u16 capability;
- u16 listen_interval;
+ __le16 capability;
+ __le16 listen_interval;
u8 current_ap[ETH_ALEN];
struct ieee80211_info_element info_element;
} __attribute__ ((packed));
struct ieee80211_assoc_response_frame {
struct ieee80211_hdr_3addr header;
- u16 capability;
- u16 status;
- u16 aid;
+ __le16 capability;
+ __le16 status;
+ __le16 aid;
struct ieee80211_info_element info_element; /* supported rates */
} __attribute__ ((packed));
@@ -561,7 +561,7 @@ struct ieee80211_txb {
};
-/* SWEEP TABLE ENTRIES NUMBER*/
+/* SWEEP TABLE ENTRIES NUMBER */
#define MAX_SWEEP_TAB_ENTRIES 42
#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7
/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs
@@ -791,8 +791,6 @@ extern struct net_device *alloc_ieee8021
extern int ieee80211_set_encryption(struct ieee80211_device *ieee);
/* ieee80211_tx.c */
-
-
extern int ieee80211_xmit(struct sk_buff *skb,
struct net_device *dev);
extern void ieee80211_txb_free(struct ieee80211_txb *);
@@ -805,7 +803,7 @@ extern void ieee80211_rx_mgt(struct ieee
struct ieee80211_hdr *header,
struct ieee80211_rx_stats *stats);
-/* iee80211_wx.c */
+/* ieee80211_wx.c */
extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee,
struct iw_request_info *info,
union iwreq_data *wrqu, char *key);
^ permalink raw reply
* latest netdev tree - (broadcom44 bug?) letting you know...
From: Mateusz Berezecki @ 2005-08-04 14:48 UTC (permalink / raw)
To: netdev
Hi list readers
I am using netdev treee (ieee80211 branch) fetched using git 2 days ago
and what worries me is that
my b44 card stopped working. I dont know if that's driver issue or
something has changed inside the network subsystem.
I am trying to track down the changes and hopefully will post the result.
regards
Mateusz
^ permalink raw reply
* Re: [PATCH 2.6.12.2] XFRM: BEET IPsec mode for Linux
From: Diego Beltrami @ 2005-08-04 14:38 UTC (permalink / raw)
To: Herbert Xu; +Cc: Miika Komu, netdev, infrahip, hipl-users, hipsec
In-Reply-To: <20050804131519.GB5831@gondor.apana.org.au>
> Well to me it's more of an issue of maintainability. BEET mode is
> more akin to transport/tunnel mode than AH/ESP/IPcomp. As such its
> implementation would be most at home where the existing encapsulation
> and decapsulation for transport/tunnel mode is done. That is, in
> xfrm[46]_input.c and xfrm[46]_output.c.
>
> For instance, the reason the current patch has to touch esp4.c at
> all is really because the patch to xfrm4_output.c isn't right.
> It should do what the comment says and set skb->h to the start
> of the payload, not the start of the ESP header. If it did that,
> then esp_output doesn't have to care about BEET at all.
This is totally true, and I agree with you but then this is somehow a
controversial thing with respect to the esp6_output. In fact the
esp6_output has the same purpose of esp_output, but it requires the
skb->h to be set at the beginning of ESP header.
>
> Also, the outer header generation should be done before
> x->type->output is called, not after. That way, the AH
> semantics falls out quite naturally.
BEET has been designed to be compatible with HIP. This means that the
ESP header should be computed with respect to the inner addresses.
In a very first implementation of BEET we were converting the inner
addresses to the outer addresses before x->type->output, but we couldn't
make interoperate BEET with HIP.
That's the reason why the outer header generation has been after
x->type->output.
This is one of the reasons why the AH, as Pekka Nikader said, is a bit
trickier with respect to ESP (the AH protocol protects the IP datagram
including immutable parts of the IP header like the IP addresses whereas
for ESP the IP header is not included in the calculation process).
--Diego
^ permalink raw reply
* Re: Fwd: opensource atheros driver almost done
From: Jirka Bohac @ 2005-08-04 12:09 UTC (permalink / raw)
To: Mateusz Berezecki; +Cc: netdev, jbenc
In-Reply-To: <aec8d6fc050802151125284155@mail.gmail.com>
Hi,
> I am developing that driver using ieee80211 branch of netdev
> kernel tree, and I am not so confident I do things right using
> new ieee80211 api. I would appreciate any suggestion and review
> of the source code.
please have a look at
http://forge.novell.com/modules/xfmod/cvs/cvsbrowse.php/ieee80211/patches-upstream/
These patches are likely to be merged by Jeff soon (apply using
quilt or use the order in the series file)
Also, you can have a look at
http://forge.novell.com/modules/xfmod/cvs/cvsbrowse.php/ieee80211/patches-netdev/
These patches break a lot of things, but can tell you more about
the ongoing development of the ieee80211 layer.
Regards,
--
Jirka Bohac <jbohac@suse.cz>
SUSE Labs, SUSE CR
^ permalink raw reply
* Re: [PATCH 2.6.12.2] XFRM: BEET IPsec mode for Linux
From: Herbert Xu @ 2005-08-03 23:40 UTC (permalink / raw)
To: Diego Beltrami; +Cc: netdev, infrahip, hipl-users, hipsec
In-Reply-To: <1122984099.1214.142.camel@odysse>
On Tue, Aug 02, 2005 at 03:01:39PM +0300, Diego Beltrami wrote:
>
> after sending the first version of BEET patch and having received a
> valuable feedback and after the discussion based upon the BEET design,
> we now send the new BEET patch which allows for BEET to work without the
> inter-family transform (i.e. inner address family different than outer
> address family).
Thanks for the new patch. Unfortunately it really looks quite similar
to the previous patch :)
> --- linux-2.6.12.2-orig/net/ipv4/esp4.c
> +++ linux-2.6.12.2/net/ipv4/esp4.c
I thought getting rid of the interfamily stuff would remove the
need to touch this file, no?
Thanks,
--
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [Hipsec] Re: [PATCH 2.6.12.2] XFRM: BEET IPsec mode for Linux
From: Miika Komu @ 2005-08-03 20:57 UTC (permalink / raw)
To: Diego Beltrami; +Cc: Herbert Xu, netdev, infrahip, hipl-users, hipsec
In-Reply-To: <1122984099.1214.142.camel@odysse>
On Tue, 2 Aug 2005, Diego Beltrami wrote:
Hi Herbert and others,
(sorry for the late comments - I am still on a holiday :)
> after sending the first version of BEET patch and having received a
> valuable feedback and after the discussion based upon the BEET design,
> we now send the new BEET patch which allows for BEET to work without the
> inter-family transform (i.e. inner address family different than outer
> address family).
> ...
>
> As it was originally designed the BEET patch at the moment works for
> only ESP protocol.
> As Pekka Nikader mentioned in one reply [1]: "[...] defining BEET mode
> for AH might be pretty tricky. [...] it probably would require some
> careful thinking to define the exact semantics, like what addresses
> (inner or outer) are covered by the AH integrity protection, what does
> the integrity protection really assert, etc. ".
>
> As previously written, the inter-family transform has been left out at
> the moment since the xfrm architecture doesn't support it. As a result,
> as soon as the xfrm architecture will be enhanced, the inter-family case
> will be properly included as, for example, it can be useful for
> supporting HIP over IPv4 network. But, as already mentioned, this would
> require more work in properly designing the xfrm architecture (thing
> which we consider necessary in order to make xfrm as generic as
> possible).
Based on the comments from Pekka Nikander, it seems like to me that
generalizing XFRM to support AH with different inner and outer families
may not very useful (a). On the other hand, the different inner and outer
families for BEET is *extremely* useful (b). Excluding this support from
BEET restricts the HIP implementations and applications quite radically.
My own thinking logic tells me the (a) + (b) equals to supporting
different inner and outer families in BEET in the way it is implemented
currently. Don't fix it if it ain't broken!)
We have tested that the BEET with different inner and outer addresses does
not break anything. Further, if you don't need it, you don't have to
compile it in :) Later, if AH seems really useful with different inner and
outer families, or a new XYZ header is introduced, we can refactor the
architecture for greater modularity. Even then, the XFRM/PFKEY APIs
should remain the same.
So, I'd vote for the original BEET patch, but of course it is up to you to
decide. The BEET support is the minimal support required from the kernel
in order for a usepace HIP implementation to work, and it would make both
HIP implementors and users life much more easier :) Additionally, we would
gain also more experience from using mixed inner and outer families within
the XFRM architecture.
--
Miika Komu miika@iki.fi http://www.iki.fi/miika/
^ permalink raw reply
* [PATCH 2.6.13-rc4 13/13] S2io: Errors found during review
From: raghavendra.koushik @ 2005-08-03 19:41 UTC (permalink / raw)
To: jgarzik, netdev
Cc: raghavendra.koushik, ravinandan.arakali, leonid.grossman,
rapuru.sriram
Hi,
This is a patch to incorporate comments from earlier 12 patches.
It also fixes a few issues we found during this time.
Following is a list of changes in this patch. Item 1 incorporates
earlier comments. Issues addressed in items 2 to 4 were discovered
recently.
1. wmb() call in s2io_xmit() replaced with mmiowb().
2. The dtx_control register was earlier programmed incorrectly
for Xframe II adapter.
3. As suggested by hardware team, after a reset, in case of
Xframe II adapter, we clear certain spurious errors by
clearing PCI-X ECC status register, "detected parity error"
bit in PCI_STATUS register and PCI_STATUS bit in txpic_int register.
4. On IBM PPC platforms, we found that in the Rx buffer replenish
function, two memory writes(one to the the descriptor length and
another to the ownership) were getting reordered. This was causing
the adapter to see the ownership transfered to it before the length
was updated.
One solution was to add a wmb() but since this would turnout expensive
on some platforms if called for every descriptor, we set the ownership
bit and other fields of '2' to 'N' Rx descriptors followed by a wmb()
and then set the ownership of first descriptor ('1').
Here the value 'N' is configurable by making it a module loadable
parameter (rxsync_frequency).
(NOTE: This parameter is a power of 2).
5. Bumped up the driver version no. to 2.0.2.1
Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com>
Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com>
---
diff -uprN vanilla_linux/drivers/net/s2io.c linux-2.6.13-rc4/drivers/net/s2io.c
--- vanilla_linux/drivers/net/s2io.c 2005-08-02 07:47:21.000000000 -0700
+++ linux-2.6.13-rc4/drivers/net/s2io.c 2005-08-02 08:47:16.000000000 -0700
@@ -67,7 +67,7 @@
/* S2io Driver name & version. */
static char s2io_driver_name[] = "Neterion";
-static char s2io_driver_version[] = "Version 2.0.2.0";
+static char s2io_driver_version[] = "Version 2.0.2.1";
static inline int RXD_IS_UP2DT(RxD_t *rxdp)
{
@@ -301,6 +301,8 @@ static unsigned int bimodal = 0;
#ifndef CONFIG_S2IO_NAPI
static unsigned int indicate_max_pkts;
#endif
+/* Frequency of Rx desc syncs expressed as power of 2 */
+static unsigned int rxsync_frequency = 3;
/*
* S2IO device table.
@@ -837,7 +839,7 @@ static int init_nic(struct s2io_nic *nic
*/
if (nic->device_type & XFRAME_II_DEVICE) {
while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
- SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
+ SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
&bar0->dtx_control, UF);
if (dtx_cnt & 0x1)
msleep(1); /* Necessary!! */
@@ -2083,6 +2085,7 @@ int fill_rx_buffers(struct s2io_nic *nic
#ifndef CONFIG_S2IO_NAPI
unsigned long flags;
#endif
+ RxD_t *first_rxdp = NULL;
mac_control = &nic->mac_control;
config = &nic->config;
@@ -2202,6 +2205,10 @@ int fill_rx_buffers(struct s2io_nic *nic
if (!skb) {
DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
+ if (first_rxdp) {
+ wmb();
+ first_rxdp->Control_1 |= RXD_OWN_XENA;
+ }
return -ENOMEM;
}
#ifndef CONFIG_2BUFF_MODE
@@ -2212,7 +2219,8 @@ int fill_rx_buffers(struct s2io_nic *nic
rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
rxdp->Host_Control = (unsigned long) (skb);
- rxdp->Control_1 |= RXD_OWN_XENA;
+ if (alloc_tab & ((1 << rxsync_frequency) - 1))
+ rxdp->Control_1 |= RXD_OWN_XENA;
off++;
off %= (MAX_RXDS_PER_BLOCK + 1);
mac_control->rings[ring_no].rx_curr_put_info.offset = off;
@@ -2239,17 +2247,34 @@ int fill_rx_buffers(struct s2io_nic *nic
rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */
rxdp->Host_Control = (u64) ((unsigned long) (skb));
- rxdp->Control_1 |= RXD_OWN_XENA;
+ if (alloc_tab & ((1 << rxsync_frequency) - 1))
+ rxdp->Control_1 |= RXD_OWN_XENA;
off++;
mac_control->rings[ring_no].rx_curr_put_info.offset = off;
#endif
rxdp->Control_2 |= SET_RXD_MARKER;
+ if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
+ if (first_rxdp) {
+ wmb();
+ first_rxdp->Control_1 |= RXD_OWN_XENA;
+ }
+ first_rxdp = rxdp;
+ }
atomic_inc(&nic->rx_bufs_left[ring_no]);
alloc_tab++;
}
end:
+ /* Transfer ownership of first descriptor to adapter just before
+ * exiting. Before that, use memory barrier so that ownership
+ * and other fields are seen by adapter correctly.
+ */
+ if (first_rxdp) {
+ wmb();
+ first_rxdp->Control_1 |= RXD_OWN_XENA;
+ }
+
return SUCCESS;
}
@@ -2783,16 +2808,16 @@ void s2io_reset(nic_t * sp)
s2io_set_swapper(sp);
/* Clear certain PCI/PCI-X fields after reset */
- pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
- pci_cmd &= 0x7FFF; /* Clear parity err detect bit */
- pci_write_config_word(sp->pdev, PCI_COMMAND, pci_cmd);
+ if (sp->device_type == XFRAME_II_DEVICE) {
+ /* Clear parity err detect bit */
+ pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
- val64 = readq(&bar0->txpic_int_reg);
- val64 &= ~BIT(62); /* Clearing PCI_STATUS error reflected here */
- writeq(val64, &bar0->txpic_int_reg);
+ /* Clearing PCIX Ecc status register */
+ pci_write_config_dword(sp->pdev, 0x68, 0x7C);
- /* Clearing PCIX Ecc status register */
- pci_write_config_dword(sp->pdev, 0x68, 0);
+ /* Clearing PCI_STATUS error reflected here */
+ writeq(BIT(62), &bar0->txpic_int_reg);
+ }
/* Reset device statistics maintained by OS */
memset(&sp->stats, 0, sizeof (struct net_device_stats));
@@ -3168,8 +3193,6 @@ int s2io_xmit(struct sk_buff *skb, struc
val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
writeq(val64, &tx_fifo->TxDL_Pointer);
- wmb();
-
val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
TX_FIFO_LAST_LIST);
@@ -3179,6 +3202,8 @@ int s2io_xmit(struct sk_buff *skb, struc
#endif
writeq(val64, &tx_fifo->List_Control);
+ mmiowb();
+
put_off++;
put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
@@ -5172,6 +5197,7 @@ module_param(bimodal, bool, 0);
#ifndef CONFIG_S2IO_NAPI
module_param(indicate_max_pkts, int, 0);
#endif
+module_param(rxsync_frequency, int, 0);
/**
* s2io_init_nic - Initialization of the adapter .
diff -uprN vanilla_linux/drivers/net/s2io.h linux-2.6.13-rc4/drivers/net/s2io.h
--- vanilla_linux/drivers/net/s2io.h 2005-08-02 07:47:21.000000000 -0700
+++ linux-2.6.13-rc4/drivers/net/s2io.h 2005-08-02 07:45:38.000000000 -0700
@@ -13,11 +13,6 @@
#ifndef _S2IO_H
#define _S2IO_H
-/* Enable 2 buffer mode by default for SGI system */
-#ifdef CONFIG_IA64_SGI_SN2
-#define CONFIG_2BUFF_MODE
-#endif
-
#define TBD 0
#define BIT(loc) (0x8000000000000000ULL >> (loc))
#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
^ permalink raw reply
* [PATCH 2.6.13-rc4 12/13] S2io: Miscellaneous fixes
From: raghavendra.koushik @ 2005-08-03 19:39 UTC (permalink / raw)
To: jgarzik, netdev
Cc: raghavendra.koushik, ravinandan.arakali, leonid.grossman,
rapuru.sriram
Hi,
The last patch in this series fixes the following issues found during
testing.
1. Ensure we don't pass zero sized buffers to the card(which can lockup)
2. Restore the PCI-X parameters(in case of Xframe I adapter) after a reset.
3. Make sure total size of all FIFOs does not exceed 8192.
Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com>
Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com>
---
diff -uprN vanilla_linux/drivers/net/s2io.c linux-2.6.13-rc4/drivers/net/s2io.c
--- vanilla_linux/drivers/net/s2io.c 2005-08-02 07:05:12.000000000 -0700
+++ linux-2.6.13-rc4/drivers/net/s2io.c 2005-08-02 07:05:24.000000000 -0700
@@ -365,10 +365,9 @@ static int init_shared_mem(struct s2io_n
size += config->tx_cfg[i].fifo_len;
}
if (size > MAX_AVAILABLE_TXDS) {
- DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ",
- dev->name);
- DBG_PRINT(ERR_DBG, "exceeds the maximum value ");
- DBG_PRINT(ERR_DBG, "that can be used\n");
+ DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
+ __FUNCTION__);
+ DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
return FAILURE;
}
@@ -611,8 +610,9 @@ static void free_shared_mem(struct s2io_
lst_per_page);
for (j = 0; j < page_num; j++) {
int mem_blks = (j * lst_per_page);
- if (!mac_control->fifos[i].list_info[mem_blks].
- list_virt_addr)
+ if ((!mac_control->fifos[i].list_info) ||
+ (!mac_control->fifos[i].list_info[mem_blks].
+ list_virt_addr))
break;
pci_free_consistent(nic->pdev, PAGE_SIZE,
mac_control->fifos[i].
@@ -2594,6 +2594,8 @@ static void tx_intr_handler(fifo_info_t
for (j = 0; j < frg_cnt; j++, txdlp++) {
skb_frag_t *frag =
&skb_shinfo(skb)->frags[j];
+ if (!txdlp->Buffer_Pointer)
+ break;
pci_unmap_page(nic->pdev,
(dma_addr_t)
txdlp->
@@ -2744,6 +2746,10 @@ void s2io_reset(nic_t * sp)
u64 val64;
u16 subid, pci_cmd;
+ /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
+ if (sp->device_type == XFRAME_I_DEVICE)
+ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
+
val64 = SW_RESET_ALL;
writeq(val64, &bar0->sw_reset);
@@ -2762,8 +2768,10 @@ void s2io_reset(nic_t * sp)
msleep(250);
if (!(sp->device_type & XFRAME_II_DEVICE)) {
- /* Restore the PCI state saved during initializarion. */
+ /* Restore the PCI state saved during initializarion. */
pci_restore_state(sp->pdev);
+ pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ pci_cmd);
} else {
pci_set_master(sp->pdev);
}
@@ -2974,7 +2982,7 @@ int s2io_open(struct net_device *dev)
* Nic is initialized
*/
netif_carrier_off(dev);
- sp->last_link_state = LINK_DOWN;
+ sp->last_link_state = 0;
/* Initialize H/W and enable interrupts */
if (s2io_card_up(sp)) {
@@ -3102,6 +3110,15 @@ int s2io_xmit(struct sk_buff *skb, struc
spin_unlock_irqrestore(&sp->tx_lock, flags);
return 0;
}
+
+ /* A buffer with no data will be dropped */
+ if (!skb->len) {
+ DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
+ dev_kfree_skb(skb);
+ spin_unlock_irqrestore(&sp->tx_lock, flags);
+ return 0;
+ }
+
#ifdef NETIF_F_TSO
mss = skb_shinfo(skb)->tso_size;
if (mss) {
@@ -3136,6 +3153,9 @@ int s2io_xmit(struct sk_buff *skb, struc
/* For fragmented SKB. */
for (i = 0; i < frg_cnt; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+ /* A '0' length fragment will be ignored */
+ if (!frag->size)
+ continue;
txdp++;
txdp->Buffer_Pointer = (u64) pci_map_page
(sp->pdev, frag->page, frag->page_offset,
@@ -5257,7 +5277,8 @@ s2io_init_nic(struct pci_dev *pdev, cons
config = &sp->config;
/* Tx side parameters. */
- tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
+ if (tx_fifo_len[0] == 0)
+ tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
config->tx_fifo_num = tx_fifo_num;
for (i = 0; i < MAX_TX_FIFOS; i++) {
config->tx_cfg[i].fifo_len = tx_fifo_len[i];
@@ -5280,7 +5301,8 @@ s2io_init_nic(struct pci_dev *pdev, cons
config->max_txds = MAX_SKB_FRAGS;
/* Rx side parameters. */
- rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
+ if (rx_ring_sz[0] == 0)
+ rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
config->rx_ring_num = rx_ring_num;
for (i = 0; i < MAX_RX_RINGS; i++) {
config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
@@ -5310,7 +5332,7 @@ s2io_init_nic(struct pci_dev *pdev, cons
/* initialize the shared memory used by the NIC and the host */
if (init_shared_mem(sp)) {
DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
- dev->name);
+ __FUNCTION__);
ret = -ENOMEM;
goto mem_alloc_failed;
}
@@ -5488,7 +5510,7 @@ s2io_init_nic(struct pci_dev *pdev, cons
sp->def_mac_addr[0].mac_addr[3],
sp->def_mac_addr[0].mac_addr[4],
sp->def_mac_addr[0].mac_addr[5]);
- int mode = s2io_print_pci_mode(sp);
+ mode = s2io_print_pci_mode(sp);
if (mode < 0) {
DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
ret = -EBADSLT;
^ permalink raw reply
* [PATCH 2.6.13-rc4 11/13] S2io: New link handling scheme for Xframe II
From: raghavendra.koushik @ 2005-08-03 19:38 UTC (permalink / raw)
To: jgarzik, netdev
Cc: raghavendra.koushik, ravinandan.arakali, leonid.grossman,
rapuru.sriram
Hi,
The below patch implements a new "Link state change handling"
scheme supported by the Xframe II adapter. It also bumps up the
driver version to 2.0.2.0.
Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com>
Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com>
---
diff -uprN vanilla_linux/drivers/net/s2io-regs.h linux-2.6.13-rc4/drivers/net/s2io-regs.h
--- vanilla_linux/drivers/net/s2io-regs.h 2005-08-02 06:59:35.000000000 -0700
+++ linux-2.6.13-rc4/drivers/net/s2io-regs.h 2005-08-02 06:59:45.000000000 -0700
@@ -167,7 +167,11 @@ typedef struct _XENA_dev_config {
u8 unused4[0x08];
u64 gpio_int_reg;
+#define GPIO_INT_REG_LINK_DOWN BIT(1)
+#define GPIO_INT_REG_LINK_UP BIT(2)
u64 gpio_int_mask;
+#define GPIO_INT_MASK_LINK_DOWN BIT(1)
+#define GPIO_INT_MASK_LINK_UP BIT(2)
u64 gpio_alarms;
u8 unused5[0x38];
@@ -279,8 +283,10 @@ typedef struct _XENA_dev_config {
u64 gpio_control;
#define GPIO_CTRL_GPIO_0 BIT(8)
+ u64 misc_control;
+#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
- u8 unused7_1[0x240 - 0x200];
+ u8 unused7_1[0x240 - 0x208];
u64 wreq_split_mask;
#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
diff -uprN vanilla_linux/drivers/net/s2io.c linux-2.6.13-rc4/drivers/net/s2io.c
--- vanilla_linux/drivers/net/s2io.c 2005-08-02 06:59:35.000000000 -0700
+++ linux-2.6.13-rc4/drivers/net/s2io.c 2005-08-02 06:59:45.000000000 -0700
@@ -67,7 +67,7 @@
/* S2io Driver name & version. */
static char s2io_driver_name[] = "Neterion";
-static char s2io_driver_version[] = "Version 1.7.7";
+static char s2io_driver_version[] = "Version 2.0.2.0";
static inline int RXD_IS_UP2DT(RxD_t *rxdp)
{
@@ -1456,8 +1456,28 @@ static int init_nic(struct s2io_nic *nic
writeq(val64, &bar0->wreq_split_mask);
}
+ /* Setting Link stability period to 64 ms */
+ if (nic->device_type == XFRAME_II_DEVICE) {
+ val64 = MISC_LINK_STABILITY_PRD(3);
+ writeq(val64, &bar0->misc_control);
+ }
+
return SUCCESS;
}
+#define LINK_UP_DOWN_INTERRUPT 1
+#define MAC_RMAC_ERR_TIMER 2
+
+#if defined(CONFIG_MSI_MODE) || defined(CONFIG_MSIX_MODE)
+#define s2io_link_fault_indication(x) MAC_RMAC_ERR_TIMER
+#else
+int s2io_link_fault_indication(nic_t *nic)
+{
+ if (nic->device_type == XFRAME_II_DEVICE)
+ return LINK_UP_DOWN_INTERRUPT;
+ else
+ return MAC_RMAC_ERR_TIMER;
+}
+#endif
/**
* en_dis_able_nic_intrs - Enable or Disable the interrupts
@@ -1485,11 +1505,22 @@ static void en_dis_able_nic_intrs(struct
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
/*
- * Disabled all PCIX, Flash, MDIO, IIC and GPIO
+ * If Hercules adapter enable GPIO otherwise
+ * disabled all PCIX, Flash, MDIO, IIC and GPIO
* interrupts for now.
* TODO
*/
- writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
+ if (s2io_link_fault_indication(nic) ==
+ LINK_UP_DOWN_INTERRUPT ) {
+ temp64 = readq(&bar0->pic_int_mask);
+ temp64 &= ~((u64) PIC_INT_GPIO);
+ writeq(temp64, &bar0->pic_int_mask);
+ temp64 = readq(&bar0->gpio_int_mask);
+ temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
+ writeq(temp64, &bar0->gpio_int_mask);
+ } else {
+ writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
+ }
/*
* No MSI Support is available presently, so TTI and
* RTI interrupts are also disabled.
@@ -1580,17 +1611,8 @@ static void en_dis_able_nic_intrs(struct
writeq(temp64, &bar0->general_int_mask);
/*
* All MAC block error interrupts are disabled for now
- * except the link status change interrupt.
* TODO
*/
- val64 = MAC_INT_STATUS_RMAC_INT;
- temp64 = readq(&bar0->mac_int_mask);
- temp64 &= ~((u64) val64);
- writeq(temp64, &bar0->mac_int_mask);
-
- val64 = readq(&bar0->mac_rmac_err_mask);
- val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
- writeq(val64, &bar0->mac_rmac_err_mask);
} else if (flag == DISABLE_INTRS) {
/*
* Disable MAC Intrs in the general intr mask register
@@ -1879,8 +1901,10 @@ static int start_nic(struct s2io_nic *ni
}
/* Enable select interrupts */
- interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
- RX_MAC_INTR | MC_INTR;
+ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | MC_INTR;
+ interruptible |= TX_PIC_INTR | RX_PIC_INTR;
+ interruptible |= TX_MAC_INTR | RX_MAC_INTR;
+
en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
/*
@@ -2004,8 +2028,9 @@ static void stop_nic(struct s2io_nic *ni
config = &nic->config;
/* Disable all interrupts */
- interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
- RX_MAC_INTR | MC_INTR;
+ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | MC_INTR;
+ interruptible |= TX_PIC_INTR | RX_PIC_INTR;
+ interruptible |= TX_MAC_INTR | RX_MAC_INTR;
en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
/* Disable PRCs */
@@ -2618,10 +2643,12 @@ static void alarm_intr_handler(struct s2
register u64 val64 = 0, err_reg = 0;
/* Handling link status change error Intr */
- err_reg = readq(&bar0->mac_rmac_err_reg);
- writeq(err_reg, &bar0->mac_rmac_err_reg);
- if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
- schedule_work(&nic->set_link_task);
+ if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
+ err_reg = readq(&bar0->mac_rmac_err_reg);
+ writeq(err_reg, &bar0->mac_rmac_err_reg);
+ if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
+ schedule_work(&nic->set_link_task);
+ }
}
/* Handling Ecc errors */
@@ -2947,7 +2974,7 @@ int s2io_open(struct net_device *dev)
* Nic is initialized
*/
netif_carrier_off(dev);
- sp->last_link_state = 0; /* Unkown link state */
+ sp->last_link_state = LINK_DOWN;
/* Initialize H/W and enable interrupts */
if (s2io_card_up(sp)) {
@@ -3159,6 +3186,53 @@ s2io_alarm_handle(unsigned long data)
mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
}
+static void s2io_txpic_intr_handle(nic_t *sp)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64;
+
+ val64 = readq(&bar0->pic_int_status);
+ if (val64 & PIC_INT_GPIO) {
+ val64 = readq(&bar0->gpio_int_reg);
+ if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
+ (val64 & GPIO_INT_REG_LINK_UP)) {
+ val64 |= GPIO_INT_REG_LINK_DOWN;
+ val64 |= GPIO_INT_REG_LINK_UP;
+ writeq(val64, &bar0->gpio_int_reg);
+ goto masking;
+ }
+
+ if (((sp->last_link_state == LINK_UP) &&
+ (val64 & GPIO_INT_REG_LINK_DOWN)) ||
+ ((sp->last_link_state == LINK_DOWN) &&
+ (val64 & GPIO_INT_REG_LINK_UP))) {
+ val64 = readq(&bar0->gpio_int_mask);
+ val64 |= GPIO_INT_MASK_LINK_DOWN;
+ val64 |= GPIO_INT_MASK_LINK_UP;
+ writeq(val64, &bar0->gpio_int_mask);
+ s2io_set_link((unsigned long)sp);
+ }
+masking:
+ if (sp->last_link_state == LINK_UP) {
+ /*enable down interrupt */
+ val64 = readq(&bar0->gpio_int_mask);
+ /* unmasks link down intr */
+ val64 &= ~GPIO_INT_MASK_LINK_DOWN;
+ /* masks link up intr */
+ val64 |= GPIO_INT_MASK_LINK_UP;
+ writeq(val64, &bar0->gpio_int_mask);
+ } else {
+ /*enable UP Interrupt */
+ val64 = readq(&bar0->gpio_int_mask);
+ /* unmasks link up interrupt */
+ val64 &= ~GPIO_INT_MASK_LINK_UP;
+ /* masks link down interrupt */
+ val64 |= GPIO_INT_MASK_LINK_DOWN;
+ writeq(val64, &bar0->gpio_int_mask);
+ }
+ }
+}
+
/**
* s2io_isr - ISR handler of the device .
* @irq: the irq of the device.
@@ -3241,6 +3315,8 @@ static irqreturn_t s2io_isr(int irq, voi
tx_intr_handler(&mac_control->fifos[i]);
}
+ if (reason & GEN_INTR_TXPIC)
+ s2io_txpic_intr_handle(sp);
/*
* If the Rx buffer count is below the panic threshold then
* reallocate the buffers from the interrupt handler itself,
@@ -4644,11 +4720,13 @@ static void s2io_set_link(unsigned long
}
subid = nic->pdev->subsystem_device;
- /*
- * Allow a small delay for the NICs self initiated
- * cleanup to complete.
- */
- msleep(100);
+ if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
+ /*
+ * Allow a small delay for the NICs self initiated
+ * cleanup to complete.
+ */
+ msleep(100);
+ }
val64 = readq(&bar0->adapter_status);
if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
@@ -4666,13 +4744,16 @@ static void s2io_set_link(unsigned long
val64 |= ADAPTER_LED_ON;
writeq(val64, &bar0->adapter_control);
}
- val64 = readq(&bar0->adapter_status);
- if (!LINK_IS_UP(val64)) {
- DBG_PRINT(ERR_DBG, "%s:", dev->name);
- DBG_PRINT(ERR_DBG, " Link down");
- DBG_PRINT(ERR_DBG, "after ");
- DBG_PRINT(ERR_DBG, "enabling ");
- DBG_PRINT(ERR_DBG, "device \n");
+ if (s2io_link_fault_indication(nic) ==
+ MAC_RMAC_ERR_TIMER) {
+ val64 = readq(&bar0->adapter_status);
+ if (!LINK_IS_UP(val64)) {
+ DBG_PRINT(ERR_DBG, "%s:", dev->name);
+ DBG_PRINT(ERR_DBG, " Link down");
+ DBG_PRINT(ERR_DBG, "after ");
+ DBG_PRINT(ERR_DBG, "enabling ");
+ DBG_PRINT(ERR_DBG, "device \n");
+ }
}
if (nic->device_enabled_once == FALSE) {
nic->device_enabled_once = TRUE;
^ permalink raw reply
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