* Re: e1000: Question about polling
From: Jarek Poplawski @ 2008-02-20 7:50 UTC (permalink / raw)
To: Badalian Vyacheslav; +Cc: netdev
In-Reply-To: <47B94D5C.2070509@bigtelecom.ru>
On 18-02-2008 10:18, Badalian Vyacheslav wrote:
> Hello all.
Hi,
> Interesting think:
>
> Have PC that do NAT. Bandwidth about 600 mbs.
>
> Have 4 CPU (2xCoRe 2 DUO "HT OFF" 3.2 HZ).
>
> irqbalance in kernel is off.
>
> nat2 ~ # cat /proc/irq/217/smp_affinity
> 00000001
> nat2 ~ # cat /proc/irq/218/smp_affinity
> 00000003
>
> Load SI on CPU0 and CPU1 is about 90%
>
> Good... try do
> echo ffffffff > /proc/irq/217/smp_affinity
> echo ffffffff > /proc/irq/218/smp_affinity
>
> Get 100% SI at CPU0
>
> Question Why?
I think you should show here /proc/interrupts in all these cases.
>
> I listen that if use IRQ from 1 netdevice to 1 CPU i can get 30%
> perfomance... but i have 4 CPU... i must get more perfomance if i cat
> "ffffffff" to smp_affinity.
>
> picture looks liks this:
> 0-3 CPU get over 50% SI.... bandwith up.... 55% SI... bandwith up...
> 100% SI on CPU0....
>
> I remember patch to fix problem like it... patched function
> e1000_clean... kernel on pc have this patch (2.6.24-rc7-git2)... e1000
> driver work much better (i up to 1.5-2x bandwidth before i get 100% SI),
> but i think that it not get 100% that it can =)
If some patch works for you, and you can show here its advantages,
you should probably add here some link and request for merging.
BTW, I wonder if you tried to check if changing CONFIG_HZ makes any
difference here?
Regards,
Jarek P.
^ permalink raw reply
* Re: tbench regression in 2.6.25-rc1
From: David Miller @ 2008-02-20 8:14 UTC (permalink / raw)
To: dada1; +Cc: yanmin_zhang, Valdis.Kletnieks, herbert, linux-kernel, netdev
In-Reply-To: <47BBD8E9.2090700@cosmosbay.com>
From: Eric Dumazet <dada1@cosmosbay.com>
Date: Wed, 20 Feb 2008 08:38:17 +0100
> Thanks very much Yanmin, I think we can apply your patch as is, if no
> regression was found for 32bits.
Great. Can I get a resubmission of the patch with a cleaned up
changelog entry that describes in the regression along with the
changelog bits I saw in the most recent version of the patch?
An explicit "Acked-by:" from Eric would be nice too :-)
Thanks!
^ permalink raw reply
* RE: e1000: Question about polling
From: Brandeburg, Jesse @ 2008-02-20 8:15 UTC (permalink / raw)
To: Badalian Vyacheslav, netdev
In-Reply-To: <47B94D5C.2070509@bigtelecom.ru>
Badalian Vyacheslav wrote:
> Hello all.
>
> Interesting think:
>
> Have PC that do NAT. Bandwidth about 600 mbs.
>
> Have 4 CPU (2xCoRe 2 DUO "HT OFF" 3.2 HZ).
>
> irqbalance in kernel is off.
>
> nat2 ~ # cat /proc/irq/217/smp_affinity
> 00000001
this binds all 217 irq interrupts to cpu 0
> nat2 ~ # cat /proc/irq/218/smp_affinity
> 00000003
do you mean to be balancing interrupts between core 1 and 2 here?
1 = cpu 0
2 = cpu 1
4 = cpu 2
8 = cpu 3
so 1+2 = 3 for irq 218, ie balancing between the two.
sometimes the cpus will have a paired cache, depending on your bios it
will be organized like cpu 0/2 = shared cache, and cput 1/3 = shared
cache.
you can find this out by looking at physical ID and CORE ID in
/proc/cpuinfo
> Load SI on CPU0 and CPU1 is about 90%
>
> Good... try do
> echo ffffffff > /proc/irq/217/smp_affinity
> echo ffffffff > /proc/irq/218/smp_affinity
>
> Get 100% SI at CPU0
>
> Question Why?
because as each adapter generating interrupts gets rotated through cpu0,
it gets "stuck" on cpu0 because the napi scheduling can only run one at
a time, and so each is always waiting in line behind the other to run
its napi poll, always fills its quota (work_done is always != 0) and
keeps interrupts disabled "forever"
> I listen that if use IRQ from 1 netdevice to 1 CPU i can get 30%
> perfomance... but i have 4 CPU... i must get more perfomance if i cat
> "ffffffff" to smp_affinity.
only if your performance is not cache limited but cpu horsepower
limited. you're sacrificing cache coherency for cpu power, but if that
works for you then great.
> picture looks liks this:
> 0-3 CPU get over 50% SI.... bandwith up.... 55% SI... bandwith up...
> 100% SI on CPU0....
>
> I remember patch to fix problem like it... patched function
> e1000_clean... kernel on pc have this patch (2.6.24-rc7-git2)...
> e1000 driver work much better (i up to 1.5-2x bandwidth before i get
> 100% SI), but i think that it not get 100% that it can =)
the patch helps a little because it decreases the amount of time the
driver spends in napi mode, basically shortening the exit condition
(which reenables interrupts, and therefore balancing) to work_done <
budget, not work_done == 0.
> Thanks for answers and sorry for my English
you basically can't get much more than one cpu can do for each nic. its
possible to get a little more, but my guess is you won't get much. The
best thing you can do is make sure as much traffic as possible stays in
the same cache, on two different cores.
you can try turning off NAPI mode either in the .config, or build the
sourceforge driver with CFLAGS_EXTRA=-DE1000_NO_NAPI, which seems
counterintuitive, but with the non-napi e1000 pushing packets to the
backlog queue on each cpu, you may actually get better performance due
to the balancing.
some day soon (maybe) we'll have some coherent way to have one tx and rx
interrupt per core, and enough queues for each port to be able to handle
1 queue per core.
good luck,
Jesse
^ permalink raw reply
* Re: [net-2.6][DRIVER][VETH] fix dev refcount race
From: David Miller @ 2008-02-20 8:22 UTC (permalink / raw)
To: dlezcano; +Cc: xemul, netdev
In-Reply-To: <47BB0138.1000104@fr.ibm.com>
From: Daniel Lezcano <dlezcano@fr.ibm.com>
Date: Tue, 19 Feb 2008 17:18:00 +0100
> veth: fix dev refcount race
>
> When deleting the veth driver, veth_close calls netif_carrier_off
> for the two extremities of the network device. netif_carrier_off on
> the peer device will fire an event and hold a reference on the peer
> device. Just after, the peer is unregistered taking the rtnl_lock while
> the linkwatch_event is scheduled. If __linkwatch_run_queue does not
> occurs before the unregistering, unregister_netdevice will wait for
> the dev refcount to reach zero holding the rtnl_lock and linkwatch_event
> will wait for the rtnl_lock and hold the dev refcount.
>
> Signed-off-by: Daniel Lezcano <dlezcano@fr.ibm.com>
Thank you for fixing this bug, patch applied.
^ permalink raw reply
* Re: [Lksctp-developers] [PATCH][SCTP]: Pick up an orphaned sctp_sockets_allocated counter.
From: David Miller @ 2008-02-20 8:23 UTC (permalink / raw)
To: vladislav.yasevich; +Cc: xemul, netdev, lksctp-developers
In-Reply-To: <47BB0740.2070104@hp.com>
From: Vlad Yasevich <vladislav.yasevich@hp.com>
Date: Tue, 19 Feb 2008 11:43:44 -0500
> Pavel Emelyanov wrote:
> > This counter is currently write-only.
> >
> > Drawing an analogy with the similar tcp counter, I think
> > that this one should be pointed by the sockets_allocated
> > members of sctp_prot and sctpv6_prot.
> >
> > Or should it be instead removed at all?
> >
> > Signed-off-by: Pavel Emelyanov <xemul@openvz.org>
>
> Ack. Looks like it got missed. It should be added.
Applied, thanks everyone.
^ permalink raw reply
* Re: [PATCH] [NETNS]: Namespace leak in pneigh_lookup.
From: David Miller @ 2008-02-20 8:26 UTC (permalink / raw)
To: den; +Cc: netdev, containers, devel, dlezcano
In-Reply-To: <1203426758-27813-1-git-send-email-den@openvz.org>
From: "Denis V. Lunev" <den@openvz.org>
Date: Tue, 19 Feb 2008 16:12:38 +0300
> release_net is missed on the error path in pneigh_lookup.
>
> Signed-off-by: Denis V. Lunev <den@openvz.org>
Applied, thanks a lot.
^ permalink raw reply
* Re: [PATCH] [NETLABEL] Minor cleanup: remove unused method definition
From: David Miller @ 2008-02-20 8:27 UTC (permalink / raw)
To: paul.moore; +Cc: ramirose, netdev, casey
In-Reply-To: <200802191108.27168.paul.moore@hp.com>
From: Paul Moore <paul.moore@hp.com>
Date: Tue, 19 Feb 2008 11:08:27 -0500
> On Tuesday 19 February 2008 9:25:31 am Rami Rosen wrote:
> > Hi,
> >
> > This patch removes definition of netlbl_cfg_cipsov4_del() method in
> > netlabel/netlabel_kapi.c and in include/net/netlabel.h as it is not
> > used.
> >
> >
> > Regards,
> > Rami Rosen
> >
> >
> > Signed-off-by: Rami Rosen <ramirose@gmail.com>
>
> This was added for use by Smack (and any other LSMs which want to
> configure NetLabel directly) and since this is an area that is
> undergoing a lot of churn at this point I'd prefer if this function was
> left in place for the time being.
>
> At a later date if this function is still unused, I'll gladly ack it's
> removal or do so myself.
Ok, let's leave it in for now.
^ permalink raw reply
* Re: [2.6.25 patch] fix broken error handling in ieee80211_sta_process_addba_request()
From: Tomas Winkler @ 2008-02-20 8:38 UTC (permalink / raw)
To: Jarek Poplawski
Cc: Adrian Bunk, Ron Rindjunsky, John W. Linville, David S. Miller,
netdev, linux-kernel
In-Reply-To: <20080220064613.GA3885@ff.dom.local>
On Feb 20, 2008 8:46 AM, Jarek Poplawski <jarkao2@gmail.com> wrote:
> On 19-02-2008 23:58, Adrian Bunk wrote:
> ...
> > --- a/net/mac80211/ieee80211_sta.c
> > +++ b/net/mac80211/ieee80211_sta.c
> > @@ -1116,9 +1116,10 @@ static void ieee80211_sta_process_addba_request(struct net_device *dev,
> ...
> > + printk(KERN_ERR "can not allocate reordering buffer "
>
> + printk(KERN_ERR "cannot allocate reordering buffer "
>
> Probably this can be fixed during the commit.
>
> Jarek P
.
ACK: both patches.
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: tbench regression in 2.6.25-rc1
From: Zhang, Yanmin @ 2008-02-20 8:41 UTC (permalink / raw)
To: David Miller; +Cc: dada1, Valdis.Kletnieks, herbert, linux-kernel, netdev
In-Reply-To: <20080220.001450.132579707.davem@davemloft.net>
Comparing with kernel 2.6.24, tbench result has regression with
2.6.25-rc1.
1) On 2 quad-core processor stoakley: 4%.
2) On 4 quad-core processor tigerton: more than 30%.
bisect located below patch.
b4ce92775c2e7ff9cf79cca4e0a19c8c5fd6287b is first bad commit
commit b4ce92775c2e7ff9cf79cca4e0a19c8c5fd6287b
Author: Herbert Xu <herbert@gondor.apana.org.au>
Date: Tue Nov 13 21:33:32 2007 -0800
[IPV6]: Move nfheader_len into rt6_info
The dst member nfheader_len is only used by IPv6. It's also currently
creating a rather ugly alignment hole in struct dst. Therefore this patch
moves it from there into struct rt6_info.
Above patch changes the cache line alignment, especially member __refcnt. I did a
testing by adding 2 unsigned long pading before lastuse, so the 3 members,
lastuse/__refcnt/__use, are moved to next cache line. The performance is recovered.
I created a patch to rearrange the members in struct dst_entry.
With Eric and Valdis Kletnieks's suggestion, I made finer arrangement.
1) Move tclassid under ops in case CONFIG_NET_CLS_ROUTE=y. So sizeof(dst_entry)=200
no matter if CONFIG_NET_CLS_ROUTE=y/n. I tested many patches on my 16-core tigerton by
moving tclassid to different place. It looks like tclassid could also have impact on
performance.
If moving tclassid before metrics, or just don't move tclassid, the performance isn't
good. So I move it behind metrics.
2) Add comments before __refcnt.
On 16-core tigerton:
If CONFIG_NET_CLS_ROUTE=y, the result with below patch is about 18% better than
the one without the patch;
If CONFIG_NET_CLS_ROUTE=n, the result with below patch is about 30% better than
the one without the patch.
With 32bit 2.6.25-rc1 on 8-core stoakley, the new patch doesn't introduce regression.
Thank Eric, Valdis, and David!
Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com>
Acked-by: Eric Dumazet <dada1@cosmosbay.com>
---
--- linux-2.6.25-rc1/include/net/dst.h 2008-02-21 14:33:43.000000000 +0800
+++ linux-2.6.25-rc1_work/include/net/dst.h 2008-02-22 12:52:19.000000000 +0800
@@ -52,15 +52,10 @@ struct dst_entry
unsigned short header_len; /* more space at head required */
unsigned short trailer_len; /* space to reserve at tail */
- u32 metrics[RTAX_MAX];
- struct dst_entry *path;
-
- unsigned long rate_last; /* rate limiting for ICMP */
unsigned int rate_tokens;
+ unsigned long rate_last; /* rate limiting for ICMP */
-#ifdef CONFIG_NET_CLS_ROUTE
- __u32 tclassid;
-#endif
+ struct dst_entry *path;
struct neighbour *neighbour;
struct hh_cache *hh;
@@ -70,10 +65,20 @@ struct dst_entry
int (*output)(struct sk_buff*);
struct dst_ops *ops;
-
- unsigned long lastuse;
+
+ u32 metrics[RTAX_MAX];
+
+#ifdef CONFIG_NET_CLS_ROUTE
+ __u32 tclassid;
+#endif
+
+ /*
+ * __refcnt wants to be on a different cache line from
+ * input/output/ops or performance tanks badly
+ */
atomic_t __refcnt; /* client references */
int __use;
+ unsigned long lastuse;
union {
struct dst_entry *next;
struct rtable *rt_next;
^ permalink raw reply
* Re: e1000: Question about polling
From: Badalian Vyacheslav @ 2008-02-20 9:15 UTC (permalink / raw)
To: Brandeburg, Jesse; +Cc: netdev
In-Reply-To: <36D9DB17C6DE9E40B059440DB8D95F520474680C@orsmsx418.amr.corp.intel.com>
Very big thanks for this answer. You ask for all my questions and for
all future questions too. Thanks Again!
> Badalian Vyacheslav wrote:
>
>> Hello all.
>>
>> Interesting think:
>>
>> Have PC that do NAT. Bandwidth about 600 mbs.
>>
>> Have 4 CPU (2xCoRe 2 DUO "HT OFF" 3.2 HZ).
>>
>> irqbalance in kernel is off.
>>
>> nat2 ~ # cat /proc/irq/217/smp_affinity
>> 00000001
>>
> this binds all 217 irq interrupts to cpu 0
>
>
>> nat2 ~ # cat /proc/irq/218/smp_affinity
>> 00000003
>>
>
> do you mean to be balancing interrupts between core 1 and 2 here?
> 1 = cpu 0
> 2 = cpu 1
> 4 = cpu 2
> 8 = cpu 3
>
> so 1+2 = 3 for irq 218, ie balancing between the two.
>
> sometimes the cpus will have a paired cache, depending on your bios it
> will be organized like cpu 0/2 = shared cache, and cput 1/3 = shared
> cache.
> you can find this out by looking at physical ID and CORE ID in
> /proc/cpuinfo
>
>
>> Load SI on CPU0 and CPU1 is about 90%
>>
>> Good... try do
>> echo ffffffff > /proc/irq/217/smp_affinity
>> echo ffffffff > /proc/irq/218/smp_affinity
>>
>> Get 100% SI at CPU0
>>
>> Question Why?
>>
>
> because as each adapter generating interrupts gets rotated through cpu0,
> it gets "stuck" on cpu0 because the napi scheduling can only run one at
> a time, and so each is always waiting in line behind the other to run
> its napi poll, always fills its quota (work_done is always != 0) and
> keeps interrupts disabled "forever"
>
>
>> I listen that if use IRQ from 1 netdevice to 1 CPU i can get 30%
>> perfomance... but i have 4 CPU... i must get more perfomance if i cat
>> "ffffffff" to smp_affinity.
>>
>
> only if your performance is not cache limited but cpu horsepower
> limited. you're sacrificing cache coherency for cpu power, but if that
> works for you then great.
>
>
>> picture looks liks this:
>> 0-3 CPU get over 50% SI.... bandwith up.... 55% SI... bandwith up...
>> 100% SI on CPU0....
>>
>> I remember patch to fix problem like it... patched function
>> e1000_clean... kernel on pc have this patch (2.6.24-rc7-git2)...
>> e1000 driver work much better (i up to 1.5-2x bandwidth before i get
>> 100% SI), but i think that it not get 100% that it can =)
>>
>
> the patch helps a little because it decreases the amount of time the
> driver spends in napi mode, basically shortening the exit condition
> (which reenables interrupts, and therefore balancing) to work_done <
> budget, not work_done == 0.
>
>
>> Thanks for answers and sorry for my English
>>
>
> you basically can't get much more than one cpu can do for each nic. its
> possible to get a little more, but my guess is you won't get much. The
> best thing you can do is make sure as much traffic as possible stays in
> the same cache, on two different cores.
>
> you can try turning off NAPI mode either in the .config, or build the
> sourceforge driver with CFLAGS_EXTRA=-DE1000_NO_NAPI, which seems
> counterintuitive, but with the non-napi e1000 pushing packets to the
> backlog queue on each cpu, you may actually get better performance due
> to the balancing.
>
> some day soon (maybe) we'll have some coherent way to have one tx and rx
> interrupt per core, and enough queues for each port to be able to handle
> 1 queue per core.
>
> good luck,
> Jesse
>
>
^ permalink raw reply
* Re: e1000: Question about polling
From: Badalian Vyacheslav @ 2008-02-20 9:25 UTC (permalink / raw)
To: Jarek Poplawski; +Cc: netdev
In-Reply-To: <20080220075054.GB3885@ff.dom.local>
Sorry for little information and mistakes in letter. Jesse Brandeburg
ask for all my questions. In future i will try to be more accurate then
write letters and post more info.
Please not think that it disrespect for you. Its simple language barrier =(
> On 18-02-2008 10:18, Badalian Vyacheslav wrote:
>
>> Hello all.
>>
>
> Hi,
>
>
>> Interesting think:
>>
>> Have PC that do NAT. Bandwidth about 600 mbs.
>>
>> Have 4 CPU (2xCoRe 2 DUO "HT OFF" 3.2 HZ).
>>
>> irqbalance in kernel is off.
>>
>> nat2 ~ # cat /proc/irq/217/smp_affinity
>> 00000001
>> nat2 ~ # cat /proc/irq/218/smp_affinity
>> 00000003
>>
>> Load SI on CPU0 and CPU1 is about 90%
>>
>> Good... try do
>> echo ffffffff > /proc/irq/217/smp_affinity
>> echo ffffffff > /proc/irq/218/smp_affinity
>>
>> Get 100% SI at CPU0
>>
>> Question Why?
>>
>
> I think you should show here /proc/interrupts in all these cases.
>
>
>> I listen that if use IRQ from 1 netdevice to 1 CPU i can get 30%
>> perfomance... but i have 4 CPU... i must get more perfomance if i cat
>> "ffffffff" to smp_affinity.
>>
>> picture looks liks this:
>> 0-3 CPU get over 50% SI.... bandwith up.... 55% SI... bandwith up...
>> 100% SI on CPU0....
>>
>> I remember patch to fix problem like it... patched function
>> e1000_clean... kernel on pc have this patch (2.6.24-rc7-git2)... e1000
>> driver work much better (i up to 1.5-2x bandwidth before i get 100% SI),
>> but i think that it not get 100% that it can =)
>>
>
> If some patch works for you, and you can show here its advantages,
> you should probably add here some link and request for merging.
>
> BTW, I wonder if you tried to check if changing CONFIG_HZ makes any
> difference here?
>
> Regards,
> Jarek P.
>
>
^ permalink raw reply
* Re: e1000: Question about polling
From: Jarek Poplawski @ 2008-02-20 9:47 UTC (permalink / raw)
To: Badalian Vyacheslav; +Cc: netdev
In-Reply-To: <47BBF20C.1050706@bigtelecom.ru>
On Wed, Feb 20, 2008 at 12:25:32PM +0300, Badalian Vyacheslav wrote:
...
> Please not think that it disrespect for you. Its simple language barrier =(
OK! Don't disrespect for me - I'll try fix my English next time!)
Jarek P.
^ permalink raw reply
* [PATCH 00/04] smc91x: request bus width using platform data
From: Magnus Damm @ 2008-02-20 9:57 UTC (permalink / raw)
To: netdev; +Cc: Magnus Damm, lethal, nico, akpm
These patches make it possible to request bus width in the platform data.
Instead of keep on updating smc91x.h with board specific configuration,
use platform data to pass along bus width and irq flags to the driver.
This change is designed to be backwards-compatible, so all boards configured
in the header file should just work as usual.
[PATCH 01/04] smc91x: pass along private data
[PATCH 02/04] smc91x: introduce platform data flags
[PATCH 03/04] smc91x: make superh use default config
[PATCH 04/04] smc91x: add insw/outsw to default config
Tested with and without platform data on a SuperH sh7722 MigoR board.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
drivers/net/smc91x.c | 340 +++++++++++++++++++++++++-----------------------
drivers/net/smc91x.h | 336 ++++++++++++++++++++++-------------------------
include/linux/smc91x.h | 13 +
3 files changed, 353 insertions(+), 336 deletions(-)
^ permalink raw reply
* [PATCH 01/04] smc91x: pass along private data
From: Magnus Damm @ 2008-02-20 9:57 UTC (permalink / raw)
To: netdev; +Cc: Magnus Damm, lethal, nico, akpm
In-Reply-To: <20080220095740.22645.36783.sendpatchset@clockwork.opensource.se>
Pass a private data pointer to macros and functions. This makes it easy
to later on make run time decisions. This patch does not change any logic.
These changes should be optimized away during compilation.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
drivers/net/smc91x.c | 309 +++++++++++++++++++++++++-------------------------
drivers/net/smc91x.h | 254 ++++++++++++++++++++---------------------
2 files changed, 284 insertions(+), 279 deletions(-)
--- 0001/drivers/net/smc91x.c
+++ work/drivers/net/smc91x.c 2008-02-20 16:52:48.000000000 +0900
@@ -220,23 +220,23 @@ static void PRINT_PKT(u_char *buf, int l
/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(x) do { \
+#define SMC_ENABLE_INT(priv, x) do { \
unsigned char mask; \
- spin_lock_irq(&lp->lock); \
- mask = SMC_GET_INT_MASK(); \
+ spin_lock_irq(&priv->lock); \
+ mask = SMC_GET_INT_MASK(priv); \
mask |= (x); \
- SMC_SET_INT_MASK(mask); \
- spin_unlock_irq(&lp->lock); \
+ SMC_SET_INT_MASK(priv, mask); \
+ spin_unlock_irq(&priv->lock); \
} while (0)
/* this disables an interrupt from the interrupt mask register */
-#define SMC_DISABLE_INT(x) do { \
+#define SMC_DISABLE_INT(priv, x) do { \
unsigned char mask; \
- spin_lock_irq(&lp->lock); \
- mask = SMC_GET_INT_MASK(); \
+ spin_lock_irq(&priv->lock); \
+ mask = SMC_GET_INT_MASK(priv); \
mask &= ~(x); \
- SMC_SET_INT_MASK(mask); \
- spin_unlock_irq(&lp->lock); \
+ SMC_SET_INT_MASK(priv, mask); \
+ spin_unlock_irq(&priv->lock); \
} while (0)
/*
@@ -244,10 +244,10 @@ static void PRINT_PKT(u_char *buf, int l
* if at all, but let's avoid deadlocking the system if the hardware
* decides to go south.
*/
-#define SMC_WAIT_MMU_BUSY() do { \
- if (unlikely(SMC_GET_MMU_CMD() & MC_BUSY)) { \
+#define SMC_WAIT_MMU_BUSY(priv) do { \
+ if (unlikely(SMC_GET_MMU_CMD(priv) & MC_BUSY)) { \
unsigned long timeout = jiffies + 2; \
- while (SMC_GET_MMU_CMD() & MC_BUSY) { \
+ while (SMC_GET_MMU_CMD(priv) & MC_BUSY) { \
if (time_after(jiffies, timeout)) { \
printk("%s: timeout %s line %d\n", \
dev->name, __FILE__, __LINE__); \
@@ -273,8 +273,8 @@ static void smc_reset(struct net_device
/* Disable all interrupts, block TX tasklet */
spin_lock_irq(&lp->lock);
- SMC_SELECT_BANK(2);
- SMC_SET_INT_MASK(0);
+ SMC_SELECT_BANK(lp, 2);
+ SMC_SET_INT_MASK(lp, 0);
pending_skb = lp->pending_tx_skb;
lp->pending_tx_skb = NULL;
spin_unlock_irq(&lp->lock);
@@ -290,15 +290,15 @@ static void smc_reset(struct net_device
* This resets the registers mostly to defaults, but doesn't
* affect EEPROM. That seems unnecessary
*/
- SMC_SELECT_BANK(0);
- SMC_SET_RCR(RCR_SOFTRST);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_RCR(lp, RCR_SOFTRST);
/*
* Setup the Configuration Register
* This is necessary because the CONFIG_REG is not affected
* by a soft reset
*/
- SMC_SELECT_BANK(1);
+ SMC_SELECT_BANK(lp, 1);
cfg = CONFIG_DEFAULT;
@@ -316,7 +316,7 @@ static void smc_reset(struct net_device
*/
cfg |= CONFIG_EPH_POWER_EN;
- SMC_SET_CONFIG(cfg);
+ SMC_SET_CONFIG(lp, cfg);
/* this should pause enough for the chip to be happy */
/*
@@ -329,12 +329,12 @@ static void smc_reset(struct net_device
udelay(1);
/* Disable transmit and receive functionality */
- SMC_SELECT_BANK(0);
- SMC_SET_RCR(RCR_CLEAR);
- SMC_SET_TCR(TCR_CLEAR);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_RCR(lp, RCR_CLEAR);
+ SMC_SET_TCR(lp, TCR_CLEAR);
- SMC_SELECT_BANK(1);
- ctl = SMC_GET_CTL() | CTL_LE_ENABLE;
+ SMC_SELECT_BANK(lp, 1);
+ ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
/*
* Set the control register to automatically release successfully
@@ -345,12 +345,12 @@ static void smc_reset(struct net_device
ctl |= CTL_AUTO_RELEASE;
else
ctl &= ~CTL_AUTO_RELEASE;
- SMC_SET_CTL(ctl);
+ SMC_SET_CTL(lp, ctl);
/* Reset the MMU */
- SMC_SELECT_BANK(2);
- SMC_SET_MMU_CMD(MC_RESET);
- SMC_WAIT_MMU_BUSY();
+ SMC_SELECT_BANK(lp, 2);
+ SMC_SET_MMU_CMD(lp, MC_RESET);
+ SMC_WAIT_MMU_BUSY(lp);
}
/*
@@ -365,19 +365,19 @@ static void smc_enable(struct net_device
DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
/* see the header file for options in TCR/RCR DEFAULT */
- SMC_SELECT_BANK(0);
- SMC_SET_TCR(lp->tcr_cur_mode);
- SMC_SET_RCR(lp->rcr_cur_mode);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_TCR(lp, lp->tcr_cur_mode);
+ SMC_SET_RCR(lp, lp->rcr_cur_mode);
- SMC_SELECT_BANK(1);
- SMC_SET_MAC_ADDR(dev->dev_addr);
+ SMC_SELECT_BANK(lp, 1);
+ SMC_SET_MAC_ADDR(lp, dev->dev_addr);
/* now, enable interrupts */
mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
if (lp->version >= (CHIP_91100 << 4))
mask |= IM_MDINT;
- SMC_SELECT_BANK(2);
- SMC_SET_INT_MASK(mask);
+ SMC_SELECT_BANK(lp, 2);
+ SMC_SET_INT_MASK(lp, mask);
/*
* From this point the register bank must _NOT_ be switched away
@@ -400,8 +400,8 @@ static void smc_shutdown(struct net_devi
/* no more interrupts for me */
spin_lock_irq(&lp->lock);
- SMC_SELECT_BANK(2);
- SMC_SET_INT_MASK(0);
+ SMC_SELECT_BANK(lp, 2);
+ SMC_SET_INT_MASK(lp, 0);
pending_skb = lp->pending_tx_skb;
lp->pending_tx_skb = NULL;
spin_unlock_irq(&lp->lock);
@@ -409,14 +409,14 @@ static void smc_shutdown(struct net_devi
dev_kfree_skb(pending_skb);
/* and tell the card to stay away from that nasty outside world */
- SMC_SELECT_BANK(0);
- SMC_SET_RCR(RCR_CLEAR);
- SMC_SET_TCR(TCR_CLEAR);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_RCR(lp, RCR_CLEAR);
+ SMC_SET_TCR(lp, TCR_CLEAR);
#ifdef POWER_DOWN
/* finally, shut the chip down */
- SMC_SELECT_BANK(1);
- SMC_SET_CONFIG(SMC_GET_CONFIG() & ~CONFIG_EPH_POWER_EN);
+ SMC_SELECT_BANK(lp, 1);
+ SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
#endif
}
@@ -431,17 +431,17 @@ static inline void smc_rcv(struct net_d
DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
- packet_number = SMC_GET_RXFIFO();
+ packet_number = SMC_GET_RXFIFO(lp);
if (unlikely(packet_number & RXFIFO_REMPTY)) {
PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
return;
}
/* read from start of packet */
- SMC_SET_PTR(PTR_READ | PTR_RCV | PTR_AUTOINC);
+ SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
/* First two words are status and packet length */
- SMC_GET_PKT_HDR(status, packet_len);
+ SMC_GET_PKT_HDR(lp, status, packet_len);
packet_len &= 0x07ff; /* mask off top bits */
DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
dev->name, packet_number, status,
@@ -460,8 +460,8 @@ static inline void smc_rcv(struct net_d
dev->name, packet_len, status);
status |= RS_TOOSHORT;
}
- SMC_WAIT_MMU_BUSY();
- SMC_SET_MMU_CMD(MC_RELEASE);
+ SMC_WAIT_MMU_BUSY(lp);
+ SMC_SET_MMU_CMD(lp, MC_RELEASE);
dev->stats.rx_errors++;
if (status & RS_ALGNERR)
dev->stats.rx_frame_errors++;
@@ -490,8 +490,8 @@ static inline void smc_rcv(struct net_d
if (unlikely(skb == NULL)) {
printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
dev->name);
- SMC_WAIT_MMU_BUSY();
- SMC_SET_MMU_CMD(MC_RELEASE);
+ SMC_WAIT_MMU_BUSY(lp);
+ SMC_SET_MMU_CMD(lp, MC_RELEASE);
dev->stats.rx_dropped++;
return;
}
@@ -510,10 +510,10 @@ static inline void smc_rcv(struct net_d
*/
data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
data = skb_put(skb, data_len);
- SMC_PULL_DATA(data, packet_len - 4);
+ SMC_PULL_DATA(lp, data, packet_len - 4);
- SMC_WAIT_MMU_BUSY();
- SMC_SET_MMU_CMD(MC_RELEASE);
+ SMC_WAIT_MMU_BUSY(lp);
+ SMC_SET_MMU_CMD(lp, MC_RELEASE);
PRINT_PKT(data, packet_len - 4);
@@ -591,7 +591,7 @@ static void smc_hardware_send_pkt(unsign
}
lp->pending_tx_skb = NULL;
- packet_no = SMC_GET_AR();
+ packet_no = SMC_GET_AR(lp);
if (unlikely(packet_no & AR_FAILED)) {
printk("%s: Memory allocation failed.\n", dev->name);
dev->stats.tx_errors++;
@@ -601,8 +601,8 @@ static void smc_hardware_send_pkt(unsign
}
/* point to the beginning of the packet */
- SMC_SET_PN(packet_no);
- SMC_SET_PTR(PTR_AUTOINC);
+ SMC_SET_PN(lp, packet_no);
+ SMC_SET_PTR(lp, PTR_AUTOINC);
buf = skb->data;
len = skb->len;
@@ -614,13 +614,13 @@ static void smc_hardware_send_pkt(unsign
* Send the packet length (+6 for status words, length, and ctl.
* The card will pad to 64 bytes with zeroes if packet is too small.
*/
- SMC_PUT_PKT_HDR(0, len + 6);
+ SMC_PUT_PKT_HDR(lp, 0, len + 6);
/* send the actual data */
- SMC_PUSH_DATA(buf, len & ~1);
+ SMC_PUSH_DATA(lp, buf, len & ~1);
/* Send final ctl word with the last byte if there is one */
- SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG);
+ SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
/*
* If THROTTLE_TX_PKTS is set, we stop the queue here. This will
@@ -634,14 +634,14 @@ static void smc_hardware_send_pkt(unsign
netif_stop_queue(dev);
/* queue the packet for TX */
- SMC_SET_MMU_CMD(MC_ENQUEUE);
+ SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
smc_special_unlock(&lp->lock);
dev->trans_start = jiffies;
dev->stats.tx_packets++;
dev->stats.tx_bytes += len;
- SMC_ENABLE_INT(IM_TX_INT | IM_TX_EMPTY_INT);
+ SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
done: if (!THROTTLE_TX_PKTS)
netif_wake_queue(dev);
@@ -688,7 +688,7 @@ static int smc_hard_start_xmit(struct sk
smc_special_lock(&lp->lock);
/* now, try to allocate the memory */
- SMC_SET_MMU_CMD(MC_ALLOC | numPages);
+ SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
/*
* Poll the chip for a short amount of time in case the
@@ -696,9 +696,9 @@ static int smc_hard_start_xmit(struct sk
*/
poll_count = MEMORY_WAIT_TIME;
do {
- status = SMC_GET_INT();
+ status = SMC_GET_INT(lp);
if (status & IM_ALLOC_INT) {
- SMC_ACK_INT(IM_ALLOC_INT);
+ SMC_ACK_INT(lp, IM_ALLOC_INT);
break;
}
} while (--poll_count);
@@ -710,7 +710,7 @@ static int smc_hard_start_xmit(struct sk
/* oh well, wait until the chip finds memory later */
netif_stop_queue(dev);
DBG(2, "%s: TX memory allocation deferred.\n", dev->name);
- SMC_ENABLE_INT(IM_ALLOC_INT);
+ SMC_ENABLE_INT(lp, IM_ALLOC_INT);
} else {
/*
* Allocation succeeded: push packet to the chip's own memory
@@ -736,19 +736,19 @@ static void smc_tx(struct net_device *de
DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
/* If the TX FIFO is empty then nothing to do */
- packet_no = SMC_GET_TXFIFO();
+ packet_no = SMC_GET_TXFIFO(lp);
if (unlikely(packet_no & TXFIFO_TEMPTY)) {
PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
return;
}
/* select packet to read from */
- saved_packet = SMC_GET_PN();
- SMC_SET_PN(packet_no);
+ saved_packet = SMC_GET_PN(lp);
+ SMC_SET_PN(lp, packet_no);
/* read the first word (status word) from this packet */
- SMC_SET_PTR(PTR_AUTOINC | PTR_READ);
- SMC_GET_PKT_HDR(tx_status, pkt_len);
+ SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
+ SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
dev->name, tx_status, packet_no);
@@ -771,17 +771,17 @@ static void smc_tx(struct net_device *de
}
/* kill the packet */
- SMC_WAIT_MMU_BUSY();
- SMC_SET_MMU_CMD(MC_FREEPKT);
+ SMC_WAIT_MMU_BUSY(lp);
+ SMC_SET_MMU_CMD(lp, MC_FREEPKT);
/* Don't restore Packet Number Reg until busy bit is cleared */
- SMC_WAIT_MMU_BUSY();
- SMC_SET_PN(saved_packet);
+ SMC_WAIT_MMU_BUSY(lp);
+ SMC_SET_PN(lp, saved_packet);
/* re-enable transmit */
- SMC_SELECT_BANK(0);
- SMC_SET_TCR(lp->tcr_cur_mode);
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_TCR(lp, lp->tcr_cur_mode);
+ SMC_SELECT_BANK(lp, 2);
}
@@ -793,7 +793,7 @@ static void smc_mii_out(struct net_devic
void __iomem *ioaddr = lp->base;
unsigned int mii_reg, mask;
- mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO);
+ mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
mii_reg |= MII_MDOE;
for (mask = 1 << (bits - 1); mask; mask >>= 1) {
@@ -802,9 +802,9 @@ static void smc_mii_out(struct net_devic
else
mii_reg &= ~MII_MDO;
- SMC_SET_MII(mii_reg);
+ SMC_SET_MII(lp, mii_reg);
udelay(MII_DELAY);
- SMC_SET_MII(mii_reg | MII_MCLK);
+ SMC_SET_MII(lp, mii_reg | MII_MCLK);
udelay(MII_DELAY);
}
}
@@ -815,16 +815,16 @@ static unsigned int smc_mii_in(struct ne
void __iomem *ioaddr = lp->base;
unsigned int mii_reg, mask, val;
- mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO);
- SMC_SET_MII(mii_reg);
+ mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
+ SMC_SET_MII(lp, mii_reg);
for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
- if (SMC_GET_MII() & MII_MDI)
+ if (SMC_GET_MII(lp) & MII_MDI)
val |= mask;
- SMC_SET_MII(mii_reg);
+ SMC_SET_MII(lp, mii_reg);
udelay(MII_DELAY);
- SMC_SET_MII(mii_reg | MII_MCLK);
+ SMC_SET_MII(lp, mii_reg | MII_MCLK);
udelay(MII_DELAY);
}
@@ -840,7 +840,7 @@ static int smc_phy_read(struct net_devic
void __iomem *ioaddr = lp->base;
unsigned int phydata;
- SMC_SELECT_BANK(3);
+ SMC_SELECT_BANK(lp, 3);
/* Idle - 32 ones */
smc_mii_out(dev, 0xffffffff, 32);
@@ -852,12 +852,12 @@ static int smc_phy_read(struct net_devic
phydata = smc_mii_in(dev, 18);
/* Return to idle state */
- SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO));
+ SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
__FUNCTION__, phyaddr, phyreg, phydata);
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 2);
return phydata;
}
@@ -870,7 +870,7 @@ static void smc_phy_write(struct net_dev
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
- SMC_SELECT_BANK(3);
+ SMC_SELECT_BANK(lp, 3);
/* Idle - 32 ones */
smc_mii_out(dev, 0xffffffff, 32);
@@ -879,12 +879,12 @@ static void smc_phy_write(struct net_dev
smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
/* Return to idle state */
- SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO));
+ SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
__FUNCTION__, phyaddr, phyreg, phydata);
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 2);
}
/*
@@ -957,9 +957,9 @@ static int smc_phy_fixed(struct net_devi
smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
/* Re-Configure the Receive/Phy Control register */
- SMC_SELECT_BANK(0);
- SMC_SET_RPC(lp->rpc_cur_mode);
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_RPC(lp, lp->rpc_cur_mode);
+ SMC_SELECT_BANK(lp, 2);
return 1;
}
@@ -1050,8 +1050,8 @@ static void smc_phy_check_media(struct n
lp->tcr_cur_mode &= ~TCR_SWFDUP;
}
- SMC_SELECT_BANK(0);
- SMC_SET_TCR(lp->tcr_cur_mode);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_TCR(lp, lp->tcr_cur_mode);
}
}
@@ -1100,8 +1100,8 @@ static void smc_phy_configure(struct wor
PHY_INT_SPDDET | PHY_INT_DPLXDET);
/* Configure the Receive/Phy Control register */
- SMC_SELECT_BANK(0);
- SMC_SET_RPC(lp->rpc_cur_mode);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_RPC(lp, lp->rpc_cur_mode);
/* If the user requested no auto neg, then go set his request */
if (lp->mii.force_media) {
@@ -1158,7 +1158,7 @@ static void smc_phy_configure(struct wor
smc_phy_check_media(dev, 1);
smc_phy_configure_exit:
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 2);
spin_unlock_irq(&lp->lock);
lp->work_pending = 0;
}
@@ -1200,9 +1200,9 @@ static void smc_10bt_check_media(struct
old_carrier = netif_carrier_ok(dev) ? 1 : 0;
- SMC_SELECT_BANK(0);
- new_carrier = (SMC_GET_EPH_STATUS() & ES_LINK_OK) ? 1 : 0;
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 0);
+ new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
+ SMC_SELECT_BANK(lp, 2);
if (init || (old_carrier != new_carrier)) {
if (!new_carrier) {
@@ -1224,11 +1224,11 @@ static void smc_eph_interrupt(struct net
smc_10bt_check_media(dev, 0);
- SMC_SELECT_BANK(1);
- ctl = SMC_GET_CTL();
- SMC_SET_CTL(ctl & ~CTL_LE_ENABLE);
- SMC_SET_CTL(ctl);
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 1);
+ ctl = SMC_GET_CTL(lp);
+ SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
+ SMC_SET_CTL(lp, ctl);
+ SMC_SELECT_BANK(lp, 2);
}
/*
@@ -1252,22 +1252,22 @@ static irqreturn_t smc_interrupt(int irq
* ISR. */
SMC_INTERRUPT_PREAMBLE;
- saved_pointer = SMC_GET_PTR();
- mask = SMC_GET_INT_MASK();
- SMC_SET_INT_MASK(0);
+ saved_pointer = SMC_GET_PTR(lp);
+ mask = SMC_GET_INT_MASK(lp);
+ SMC_SET_INT_MASK(lp, 0);
/* set a timeout value, so I don't stay here forever */
timeout = MAX_IRQ_LOOPS;
do {
- status = SMC_GET_INT();
+ status = SMC_GET_INT(lp);
DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
dev->name, status, mask,
- ({ int meminfo; SMC_SELECT_BANK(0);
- meminfo = SMC_GET_MIR();
- SMC_SELECT_BANK(2); meminfo; }),
- SMC_GET_FIFO());
+ ({ int meminfo; SMC_SELECT_BANK(lp, 0);
+ meminfo = SMC_GET_MIR(lp);
+ SMC_SELECT_BANK(lp, 2); meminfo; }),
+ SMC_GET_FIFO(lp));
status &= mask;
if (!status)
@@ -1277,7 +1277,7 @@ static irqreturn_t smc_interrupt(int irq
/* do this before RX as it will free memory quickly */
DBG(3, "%s: TX int\n", dev->name);
smc_tx(dev);
- SMC_ACK_INT(IM_TX_INT);
+ SMC_ACK_INT(lp, IM_TX_INT);
if (THROTTLE_TX_PKTS)
netif_wake_queue(dev);
} else if (status & IM_RCV_INT) {
@@ -1292,9 +1292,9 @@ static irqreturn_t smc_interrupt(int irq
mask &= ~IM_TX_EMPTY_INT;
/* update stats */
- SMC_SELECT_BANK(0);
- card_stats = SMC_GET_COUNTER();
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 0);
+ card_stats = SMC_GET_COUNTER(lp);
+ SMC_SELECT_BANK(lp, 2);
/* single collisions */
dev->stats.collisions += card_stats & 0xF;
@@ -1304,26 +1304,26 @@ static irqreturn_t smc_interrupt(int irq
dev->stats.collisions += card_stats & 0xF;
} else if (status & IM_RX_OVRN_INT) {
DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
- ({ int eph_st; SMC_SELECT_BANK(0);
- eph_st = SMC_GET_EPH_STATUS();
- SMC_SELECT_BANK(2); eph_st; }) );
- SMC_ACK_INT(IM_RX_OVRN_INT);
+ ({ int eph_st; SMC_SELECT_BANK(lp, 0);
+ eph_st = SMC_GET_EPH_STATUS(lp);
+ SMC_SELECT_BANK(lp, 2); eph_st; }));
+ SMC_ACK_INT(lp, IM_RX_OVRN_INT);
dev->stats.rx_errors++;
dev->stats.rx_fifo_errors++;
} else if (status & IM_EPH_INT) {
smc_eph_interrupt(dev);
} else if (status & IM_MDINT) {
- SMC_ACK_INT(IM_MDINT);
+ SMC_ACK_INT(lp, IM_MDINT);
smc_phy_interrupt(dev);
} else if (status & IM_ERCV_INT) {
- SMC_ACK_INT(IM_ERCV_INT);
+ SMC_ACK_INT(lp, IM_ERCV_INT);
PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name);
}
} while (--timeout);
/* restore register states */
- SMC_SET_PTR(saved_pointer);
- SMC_SET_INT_MASK(mask);
+ SMC_SET_PTR(lp, saved_pointer);
+ SMC_SET_INT_MASK(lp, mask);
spin_unlock(&lp->lock);
if (timeout == MAX_IRQ_LOOPS)
@@ -1366,13 +1366,13 @@ static void smc_timeout(struct net_devic
DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
spin_lock_irq(&lp->lock);
- status = SMC_GET_INT();
- mask = SMC_GET_INT_MASK();
- fifo = SMC_GET_FIFO();
- SMC_SELECT_BANK(0);
- eph_st = SMC_GET_EPH_STATUS();
- meminfo = SMC_GET_MIR();
- SMC_SELECT_BANK(2);
+ status = SMC_GET_INT(lp);
+ mask = SMC_GET_INT_MASK(lp);
+ fifo = SMC_GET_FIFO(lp);
+ SMC_SELECT_BANK(lp, 0);
+ eph_st = SMC_GET_EPH_STATUS(lp);
+ meminfo = SMC_GET_MIR(lp);
+ SMC_SELECT_BANK(lp, 2);
spin_unlock_irq(&lp->lock);
PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
"MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
@@ -1492,13 +1492,13 @@ static void smc_set_multicast_list(struc
}
spin_lock_irq(&lp->lock);
- SMC_SELECT_BANK(0);
- SMC_SET_RCR(lp->rcr_cur_mode);
+ SMC_SELECT_BANK(lp, 0);
+ SMC_SET_RCR(lp, lp->rcr_cur_mode);
if (update_multicast) {
- SMC_SELECT_BANK(3);
- SMC_SET_MCAST(multicast_table);
+ SMC_SELECT_BANK(lp, 3);
+ SMC_SET_MCAST(lp, multicast_table);
}
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(lp, 2);
spin_unlock_irq(&lp->lock);
}
@@ -1702,8 +1702,9 @@ static const struct ethtool_ops smc_etht
* I just deleted auto_irq.c, since it was never built...
* --jgarzik
*/
-static int __init smc_findirq(void __iomem *ioaddr)
+static int __init smc_findirq(struct smc_local *lp)
{
+ void __iomem *ioaddr = lp->base;
int timeout = 20;
unsigned long cookie;
@@ -1717,14 +1718,14 @@ static int __init smc_findirq(void __iom
* when done.
*/
/* enable ALLOCation interrupts ONLY */
- SMC_SELECT_BANK(2);
- SMC_SET_INT_MASK(IM_ALLOC_INT);
+ SMC_SELECT_BANK(lp, 2);
+ SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
/*
* Allocate 512 bytes of memory. Note that the chip was just
* reset so all the memory is available
*/
- SMC_SET_MMU_CMD(MC_ALLOC | 1);
+ SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
/*
* Wait until positive that the interrupt has been generated
@@ -1732,7 +1733,7 @@ static int __init smc_findirq(void __iom
do {
int int_status;
udelay(10);
- int_status = SMC_GET_INT();
+ int_status = SMC_GET_INT(lp);
if (int_status & IM_ALLOC_INT)
break; /* got the interrupt */
} while (--timeout);
@@ -1745,7 +1746,7 @@ static int __init smc_findirq(void __iom
*/
/* and disable all interrupts again */
- SMC_SET_INT_MASK(0);
+ SMC_SET_INT_MASK(lp, 0);
/* and return what I found */
return probe_irq_off(cookie);
@@ -1788,7 +1789,7 @@ static int __init smc_probe(struct net_d
DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
/* First, see if the high byte is 0x33 */
- val = SMC_CURRENT_BANK();
+ val = SMC_CURRENT_BANK(lp);
DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
if ((val & 0xFF00) != 0x3300) {
if ((val & 0xFF) == 0x33) {
@@ -1804,8 +1805,8 @@ static int __init smc_probe(struct net_d
* The above MIGHT indicate a device, but I need to write to
* further test this.
*/
- SMC_SELECT_BANK(0);
- val = SMC_CURRENT_BANK();
+ SMC_SELECT_BANK(lp, 0);
+ val = SMC_CURRENT_BANK(lp);
if ((val & 0xFF00) != 0x3300) {
retval = -ENODEV;
goto err_out;
@@ -1817,8 +1818,8 @@ static int __init smc_probe(struct net_d
* register to bank 1, so I can access the base address
* register
*/
- SMC_SELECT_BANK(1);
- val = SMC_GET_BASE();
+ SMC_SELECT_BANK(lp, 1);
+ val = SMC_GET_BASE(lp);
val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
printk("%s: IOADDR %p doesn't match configuration (%x).\n",
@@ -1830,8 +1831,8 @@ static int __init smc_probe(struct net_d
* recognize. These might need to be added to later,
* as future revisions could be added.
*/
- SMC_SELECT_BANK(3);
- revision_register = SMC_GET_REV();
+ SMC_SELECT_BANK(lp, 3);
+ revision_register = SMC_GET_REV(lp);
DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
version_string = chip_ids[ (revision_register >> 4) & 0xF];
if (!version_string || (revision_register & 0xff00) != 0x3300) {
@@ -1855,8 +1856,8 @@ static int __init smc_probe(struct net_d
spin_lock_init(&lp->lock);
/* Get the MAC address */
- SMC_SELECT_BANK(1);
- SMC_GET_MAC_ADDR(dev->dev_addr);
+ SMC_SELECT_BANK(lp, 1);
+ SMC_GET_MAC_ADDR(lp, dev->dev_addr);
/* now, reset the chip, and put it into a known state */
smc_reset(dev);
@@ -1881,7 +1882,7 @@ static int __init smc_probe(struct net_d
trials = 3;
while (trials--) {
- dev->irq = smc_findirq(ioaddr);
+ dev->irq = smc_findirq(lp);
if (dev->irq)
break;
/* kick the card and try again */
--- 0001/drivers/net/smc91x.h
+++ work/drivers/net/smc91x.h 2008-02-20 17:03:45.000000000 +0900
@@ -720,7 +720,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Transmit Control Register
/* BANK 0 */
-#define TCR_REG SMC_REG(0x0000, 0)
+#define TCR_REG(priv) SMC_REG(priv, 0x0000, 0)
#define TCR_ENABLE 0x0001 // When 1 we can transmit
#define TCR_LOOP 0x0002 // Controls output pin LBK
#define TCR_FORCOL 0x0004 // When 1 will force a collision
@@ -739,7 +739,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
// EPH Status Register
/* BANK 0 */
-#define EPH_STATUS_REG SMC_REG(0x0002, 0)
+#define EPH_STATUS_REG(priv) SMC_REG(priv, 0x0002, 0)
#define ES_TX_SUC 0x0001 // Last TX was successful
#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
@@ -758,7 +758,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Receive Control Register
/* BANK 0 */
-#define RCR_REG SMC_REG(0x0004, 0)
+#define RCR_REG(priv) SMC_REG(priv, 0x0004, 0)
#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
#define RCR_PRMS 0x0002 // Enable promiscuous mode
#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
@@ -775,17 +775,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Counter Register
/* BANK 0 */
-#define COUNTER_REG SMC_REG(0x0006, 0)
+#define COUNTER_REG(priv) SMC_REG(priv, 0x0006, 0)
// Memory Information Register
/* BANK 0 */
-#define MIR_REG SMC_REG(0x0008, 0)
+#define MIR_REG(priv) SMC_REG(priv, 0x0008, 0)
// Receive/Phy Control Register
/* BANK 0 */
-#define RPC_REG SMC_REG(0x000A, 0)
+#define RPC_REG(priv) SMC_REG(priv, 0x000A, 0)
#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
@@ -819,7 +819,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Configuration Reg
/* BANK 1 */
-#define CONFIG_REG SMC_REG(0x0000, 1)
+#define CONFIG_REG(priv) SMC_REG(priv, 0x0000, 1)
#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
@@ -831,24 +831,24 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Base Address Register
/* BANK 1 */
-#define BASE_REG SMC_REG(0x0002, 1)
+#define BASE_REG(priv) SMC_REG(priv, 0x0002, 1)
// Individual Address Registers
/* BANK 1 */
-#define ADDR0_REG SMC_REG(0x0004, 1)
-#define ADDR1_REG SMC_REG(0x0006, 1)
-#define ADDR2_REG SMC_REG(0x0008, 1)
+#define ADDR0_REG(priv) SMC_REG(priv, 0x0004, 1)
+#define ADDR1_REG(priv) SMC_REG(priv, 0x0006, 1)
+#define ADDR2_REG(priv) SMC_REG(priv, 0x0008, 1)
// General Purpose Register
/* BANK 1 */
-#define GP_REG SMC_REG(0x000A, 1)
+#define GP_REG(priv) SMC_REG(priv, 0x000A, 1)
// Control Register
/* BANK 1 */
-#define CTL_REG SMC_REG(0x000C, 1)
+#define CTL_REG(priv) SMC_REG(priv, 0x000C, 1)
#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
@@ -861,7 +861,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
// MMU Command Register
/* BANK 2 */
-#define MMU_CMD_REG SMC_REG(0x0000, 2)
+#define MMU_CMD_REG(priv) SMC_REG(priv, 0x0000, 2)
#define MC_BUSY 1 // When 1 the last release has not completed
#define MC_NOP (0<<5) // No Op
#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
@@ -875,30 +875,30 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Packet Number Register
/* BANK 2 */
-#define PN_REG SMC_REG(0x0002, 2)
+#define PN_REG(priv) SMC_REG(priv, 0x0002, 2)
// Allocation Result Register
/* BANK 2 */
-#define AR_REG SMC_REG(0x0003, 2)
+#define AR_REG(priv) SMC_REG(priv, 0x0003, 2)
#define AR_FAILED 0x80 // Alocation Failed
// TX FIFO Ports Register
/* BANK 2 */
-#define TXFIFO_REG SMC_REG(0x0004, 2)
+#define TXFIFO_REG(priv) SMC_REG(priv, 0x0004, 2)
#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
// RX FIFO Ports Register
/* BANK 2 */
-#define RXFIFO_REG SMC_REG(0x0005, 2)
+#define RXFIFO_REG(priv) SMC_REG(priv, 0x0005, 2)
#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
-#define FIFO_REG SMC_REG(0x0004, 2)
+#define FIFO_REG(priv) SMC_REG(priv, 0x0004, 2)
// Pointer Register
/* BANK 2 */
-#define PTR_REG SMC_REG(0x0006, 2)
+#define PTR_REG(priv) SMC_REG(priv, 0x0006, 2)
#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
#define PTR_READ 0x2000 // When 1 the operation is a read
@@ -906,17 +906,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Data Register
/* BANK 2 */
-#define DATA_REG SMC_REG(0x0008, 2)
+#define DATA_REG(priv) SMC_REG(priv, 0x0008, 2)
// Interrupt Status/Acknowledge Register
/* BANK 2 */
-#define INT_REG SMC_REG(0x000C, 2)
+#define INT_REG(priv) SMC_REG(priv, 0x000C, 2)
// Interrupt Mask Register
/* BANK 2 */
-#define IM_REG SMC_REG(0x000D, 2)
+#define IM_REG(priv) SMC_REG(priv, 0x000D, 2)
#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
#define IM_ERCV_INT 0x40 // Early Receive Interrupt
#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
@@ -929,15 +929,15 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Multicast Table Registers
/* BANK 3 */
-#define MCAST_REG1 SMC_REG(0x0000, 3)
-#define MCAST_REG2 SMC_REG(0x0002, 3)
-#define MCAST_REG3 SMC_REG(0x0004, 3)
-#define MCAST_REG4 SMC_REG(0x0006, 3)
+#define MCAST_REG1(priv) SMC_REG(priv, 0x0000, 3)
+#define MCAST_REG2(priv) SMC_REG(priv, 0x0002, 3)
+#define MCAST_REG3(priv) SMC_REG(priv, 0x0004, 3)
+#define MCAST_REG4(priv) SMC_REG(priv, 0x0006, 3)
// Management Interface Register (MII)
/* BANK 3 */
-#define MII_REG SMC_REG(0x0008, 3)
+#define MII_REG(priv) SMC_REG(priv, 0x0008, 3)
#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
#define MII_MDOE 0x0008 // MII Output Enable
#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
@@ -948,20 +948,20 @@ smc_pxa_dma_irq(int dma, void *dummy)
// Revision Register
/* BANK 3 */
/* ( hi: chip id low: rev # ) */
-#define REV_REG SMC_REG(0x000A, 3)
+#define REV_REG(priv) SMC_REG(priv, 0x000A, 3)
// Early RCV Register
/* BANK 3 */
/* this is NOT on SMC9192 */
-#define ERCV_REG SMC_REG(0x000C, 3)
+#define ERCV_REG(priv) SMC_REG(priv, 0x000C, 3)
#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
// External Register
/* BANK 7 */
-#define EXT_REG SMC_REG(0x0000, 7)
+#define EXT_REG(priv) SMC_REG(priv, 0x0000, 7)
#define CHIP_9192 3
@@ -1085,9 +1085,9 @@ static const char * chip_ids[ 16 ] = {
*/
#if SMC_DEBUG > 0
-#define SMC_REG(reg, bank) \
+#define SMC_REG(priv, reg, bank) \
({ \
- int __b = SMC_CURRENT_BANK(); \
+ int __b = SMC_CURRENT_BANK(priv); \
if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
printk( "%s: bank reg screwed (0x%04x)\n", \
CARDNAME, __b ); \
@@ -1096,7 +1096,7 @@ static const char * chip_ids[ 16 ] = {
reg<<SMC_IO_SHIFT; \
})
#else
-#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
+#define SMC_REG(priv, reg, bank) (reg<<SMC_IO_SHIFT)
#endif
/*
@@ -1110,65 +1110,65 @@ static const char * chip_ids[ 16 ] = {
*/
#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
-#define SMC_GET_PN() \
- ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
- : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
+#define SMC_GET_PN(priv) \
+ (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG(priv))) \
+ : (SMC_inw(ioaddr, PN_REG(priv)) & 0xFF))
-#define SMC_SET_PN(x) \
+#define SMC_SET_PN(priv, x) \
do { \
if (SMC_MUST_ALIGN_WRITE) \
- SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
+ SMC_outl((x)<<16, ioaddr, SMC_REG(priv, 0, 2)); \
else if (SMC_CAN_USE_8BIT) \
- SMC_outb(x, ioaddr, PN_REG); \
+ SMC_outb(x, ioaddr, PN_REG(priv)); \
else \
- SMC_outw(x, ioaddr, PN_REG); \
+ SMC_outw(x, ioaddr, PN_REG(priv)); \
} while (0)
-#define SMC_GET_AR() \
- ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
- : (SMC_inw(ioaddr, PN_REG) >> 8) )
+#define SMC_GET_AR(priv) \
+ (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG(priv))) \
+ : (SMC_inw(ioaddr, PN_REG(priv)) >> 8))
-#define SMC_GET_TXFIFO() \
- ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
- : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
+#define SMC_GET_TXFIFO(priv) \
+ (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG(priv))) \
+ : (SMC_inw(ioaddr, TXFIFO_REG(priv)) & 0xFF))
-#define SMC_GET_RXFIFO() \
- ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
- : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
+#define SMC_GET_RXFIFO(priv) \
+ (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG(priv))) \
+ : (SMC_inw(ioaddr, TXFIFO_REG(priv)) >> 8))
-#define SMC_GET_INT() \
- ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
- : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
+#define SMC_GET_INT(priv) \
+ (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG(priv))) \
+ : (SMC_inw(ioaddr, INT_REG(priv)) & 0xFF))
-#define SMC_ACK_INT(x) \
+#define SMC_ACK_INT(priv, x) \
do { \
if (SMC_CAN_USE_8BIT) \
- SMC_outb(x, ioaddr, INT_REG); \
+ SMC_outb(x, ioaddr, INT_REG(priv)); \
else { \
unsigned long __flags; \
int __mask; \
local_irq_save(__flags); \
- __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
- SMC_outw( __mask | (x), ioaddr, INT_REG ); \
+ __mask = SMC_inw(ioaddr, INT_REG(priv)) & ~0xff; \
+ SMC_outw(__mask | (x), ioaddr, INT_REG(priv)); \
local_irq_restore(__flags); \
} \
} while (0)
-#define SMC_GET_INT_MASK() \
- ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
- : (SMC_inw( ioaddr, INT_REG ) >> 8) )
+#define SMC_GET_INT_MASK(priv) \
+ (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG(priv))) \
+ : (SMC_inw(ioaddr, INT_REG(priv)) >> 8))
-#define SMC_SET_INT_MASK(x) \
+#define SMC_SET_INT_MASK(priv, x) \
do { \
if (SMC_CAN_USE_8BIT) \
- SMC_outb(x, ioaddr, IM_REG); \
+ SMC_outb(x, ioaddr, IM_REG(priv)); \
else \
- SMC_outw((x) << 8, ioaddr, INT_REG); \
+ SMC_outw((x) << 8, ioaddr, INT_REG(priv)); \
} while (0)
-#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
+#define SMC_CURRENT_BANK(priv) SMC_inw(ioaddr, BANK_SELECT)
-#define SMC_SELECT_BANK(x) \
+#define SMC_SELECT_BANK(priv, x) \
do { \
if (SMC_MUST_ALIGN_WRITE) \
SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
@@ -1176,118 +1176,119 @@ static const char * chip_ids[ 16 ] = {
SMC_outw(x, ioaddr, BANK_SELECT); \
} while (0)
-#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
+#define SMC_GET_BASE(priv) SMC_inw(ioaddr, BASE_REG(priv))
-#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
+#define SMC_SET_BASE(priv, x) SMC_outw(x, ioaddr, BASE_REG(priv))
-#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
+#define SMC_GET_CONFIG(priv) SMC_inw(ioaddr, CONFIG_REG(priv))
-#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
+#define SMC_SET_CONFIG(priv, x) SMC_outw(x, ioaddr, CONFIG_REG(priv))
-#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
+#define SMC_GET_COUNTER(priv) SMC_inw(ioaddr, COUNTER_REG(priv))
-#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
+#define SMC_GET_CTL(priv) SMC_inw(ioaddr, CTL_REG(priv))
-#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
+#define SMC_SET_CTL(priv, x) SMC_outw(x, ioaddr, CTL_REG(priv))
-#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
+#define SMC_GET_MII(priv) SMC_inw(ioaddr, MII_REG(priv))
-#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
+#define SMC_SET_MII(priv, x) SMC_outw(x, ioaddr, MII_REG(priv))
-#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
+#define SMC_GET_MIR(priv) SMC_inw(ioaddr, MIR_REG(priv))
-#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
+#define SMC_SET_MIR(priv, x) SMC_outw(x, ioaddr, MIR_REG(priv))
-#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
+#define SMC_GET_MMU_CMD(priv) SMC_inw(ioaddr, MMU_CMD_REG(priv))
-#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
+#define SMC_SET_MMU_CMD(priv, x) SMC_outw(x, ioaddr, MMU_CMD_REG(priv))
-#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
+#define SMC_GET_FIFO(priv) SMC_inw(ioaddr, FIFO_REG(priv))
-#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
+#define SMC_GET_PTR(priv) SMC_inw(ioaddr, PTR_REG(priv))
-#define SMC_SET_PTR(x) \
+#define SMC_SET_PTR(priv, x) \
do { \
if (SMC_MUST_ALIGN_WRITE) \
- SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
+ SMC_outl((x)<<16, ioaddr, SMC_REG(priv, 4, 2)); \
else \
- SMC_outw(x, ioaddr, PTR_REG); \
+ SMC_outw(x, ioaddr, PTR_REG(priv)); \
} while (0)
-#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
+#define SMC_GET_EPH_STATUS(priv) SMC_inw(ioaddr, EPH_STATUS_REG(priv))
-#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
+#define SMC_GET_RCR(priv) SMC_inw(ioaddr, RCR_REG(priv))
-#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
+#define SMC_SET_RCR(priv, x) SMC_outw(x, ioaddr, RCR_REG(priv))
-#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
+#define SMC_GET_REV(priv) SMC_inw(ioaddr, REV_REG(priv))
-#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
+#define SMC_GET_RPC(priv) SMC_inw(ioaddr, RPC_REG(priv))
-#define SMC_SET_RPC(x) \
+#define SMC_SET_RPC(priv, x) \
do { \
if (SMC_MUST_ALIGN_WRITE) \
- SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
+ SMC_outl((x)<<16, ioaddr, SMC_REG(priv, 8, 0)); \
else \
- SMC_outw(x, ioaddr, RPC_REG); \
+ SMC_outw(x, ioaddr, RPC_REG(priv)); \
} while (0)
-#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
+#define SMC_GET_TCR(priv) SMC_inw(ioaddr, TCR_REG(priv))
-#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
+#define SMC_SET_TCR(priv, x) SMC_outw(x, ioaddr, TCR_REG(priv))
#ifndef SMC_GET_MAC_ADDR
-#define SMC_GET_MAC_ADDR(addr) \
+#define SMC_GET_MAC_ADDR(priv, addr) \
do { \
unsigned int __v; \
- __v = SMC_inw( ioaddr, ADDR0_REG ); \
+ __v = SMC_inw(ioaddr, ADDR0_REG(priv)); \
addr[0] = __v; addr[1] = __v >> 8; \
- __v = SMC_inw( ioaddr, ADDR1_REG ); \
+ __v = SMC_inw(ioaddr, ADDR1_REG(priv)); \
addr[2] = __v; addr[3] = __v >> 8; \
- __v = SMC_inw( ioaddr, ADDR2_REG ); \
+ __v = SMC_inw(ioaddr, ADDR2_REG(priv)); \
addr[4] = __v; addr[5] = __v >> 8; \
} while (0)
#endif
-#define SMC_SET_MAC_ADDR(addr) \
+#define SMC_SET_MAC_ADDR(priv, addr) \
do { \
- SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
- SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
- SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
+ SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(priv)); \
+ SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(priv)); \
+ SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(priv)); \
} while (0)
-#define SMC_SET_MCAST(x) \
+#define SMC_SET_MCAST(priv, x) \
do { \
const unsigned char *mt = (x); \
- SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
- SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
- SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
- SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
+ SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(priv)); \
+ SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(priv)); \
+ SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(priv)); \
+ SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(priv)); \
} while (0)
-#define SMC_PUT_PKT_HDR(status, length) \
+#define SMC_PUT_PKT_HDR(priv, status, length) \
do { \
if (SMC_CAN_USE_32BIT) \
- SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
+ SMC_outl((status) | (length)<<16, ioaddr, \
+ DATA_REG(priv)); \
else { \
- SMC_outw(status, ioaddr, DATA_REG); \
- SMC_outw(length, ioaddr, DATA_REG); \
+ SMC_outw(status, ioaddr, DATA_REG(priv)); \
+ SMC_outw(length, ioaddr, DATA_REG(priv)); \
} \
} while (0)
-#define SMC_GET_PKT_HDR(status, length) \
+#define SMC_GET_PKT_HDR(priv, status, length) \
do { \
if (SMC_CAN_USE_32BIT) { \
- unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
+ unsigned int __val = SMC_inl(ioaddr, DATA_REG(priv)); \
(status) = __val & 0xffff; \
(length) = __val >> 16; \
} else { \
- (status) = SMC_inw(ioaddr, DATA_REG); \
- (length) = SMC_inw(ioaddr, DATA_REG); \
+ (status) = SMC_inw(ioaddr, DATA_REG(priv)); \
+ (length) = SMC_inw(ioaddr, DATA_REG(priv)); \
} \
} while (0)
-#define SMC_PUSH_DATA(p, l) \
+#define SMC_PUSH_DATA(priv, p, l) \
do { \
if (SMC_CAN_USE_32BIT) { \
void *__ptr = (p); \
@@ -1295,23 +1296,25 @@ static const char * chip_ids[ 16 ] = {
void __iomem *__ioaddr = ioaddr; \
if (__len >= 2 && (unsigned long)__ptr & 2) { \
__len -= 2; \
- SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
+ SMC_outw(*(u16 *)__ptr, ioaddr, \
+ DATA_REG(priv)); \
__ptr += 2; \
} \
if (SMC_CAN_USE_DATACS && lp->datacs) \
__ioaddr = lp->datacs; \
- SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
+ SMC_outsl(__ioaddr, DATA_REG(priv), __ptr, __len>>2); \
if (__len & 2) { \
__ptr += (__len & ~3); \
- SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
+ SMC_outw(*((u16 *)__ptr), ioaddr, \
+ DATA_REG(priv)); \
} \
} else if (SMC_CAN_USE_16BIT) \
- SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
+ SMC_outsw(ioaddr, DATA_REG(priv), p, (l) >> 1); \
else if (SMC_CAN_USE_8BIT) \
- SMC_outsb(ioaddr, DATA_REG, p, l); \
+ SMC_outsb(ioaddr, DATA_REG(priv), p, l); \
} while (0)
-#define SMC_PULL_DATA(p, l) \
+#define SMC_PULL_DATA(priv, p, l) \
do { \
if (SMC_CAN_USE_32BIT) { \
void *__ptr = (p); \
@@ -1333,16 +1336,17 @@ static const char * chip_ids[ 16 ] = {
*/ \
__ptr -= 2; \
__len += 2; \
- SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
+ SMC_SET_PTR(priv, \
+ 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
} \
if (SMC_CAN_USE_DATACS && lp->datacs) \
__ioaddr = lp->datacs; \
__len += 2; \
- SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
+ SMC_insl(__ioaddr, DATA_REG(priv), __ptr, __len>>2); \
} else if (SMC_CAN_USE_16BIT) \
- SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
+ SMC_insw(ioaddr, DATA_REG(priv), p, (l) >> 1); \
else if (SMC_CAN_USE_8BIT) \
- SMC_insb(ioaddr, DATA_REG, p, l); \
+ SMC_insb(ioaddr, DATA_REG(priv), p, l); \
} while (0)
#endif /* _SMC91X_H_ */
^ permalink raw reply
* [PATCH 02/04] smc91x: introduce platform data flags
From: Magnus Damm @ 2008-02-20 9:58 UTC (permalink / raw)
To: netdev; +Cc: Magnus Damm, lethal, nico, akpm
In-Reply-To: <20080220095740.22645.36783.sendpatchset@clockwork.opensource.se>
This patch introduces struct smc91x_platdata and modifies the driver so
bus width is checked during run time using SMC_nBIT() instead of
SMC_CAN_USE_nBIT.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
drivers/net/smc91x.c | 31 ++++++++++++++++++++++++-----
drivers/net/smc91x.h | 50 ++++++++++++++++++++++++++----------------------
include/linux/smc91x.h | 13 ++++++++++++
3 files changed, 67 insertions(+), 27 deletions(-)
--- 0017/drivers/net/smc91x.c
+++ work/drivers/net/smc91x.c 2008-02-20 17:04:41.000000000 +0900
@@ -1997,6 +1997,8 @@ err_out:
static int smc_enable_device(struct platform_device *pdev)
{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct smc_local *lp = netdev_priv(ndev);
unsigned long flags;
unsigned char ecor, ecsr;
void __iomem *addr;
@@ -2039,7 +2041,7 @@ static int smc_enable_device(struct plat
* Set the appropriate byte/word mode.
*/
ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
- if (!SMC_CAN_USE_16BIT)
+ if (!SMC_16BIT(lp))
ecsr |= ECSR_IOIS8;
writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
local_irq_restore(flags);
@@ -2124,10 +2126,11 @@ static void smc_release_datacs(struct pl
*/
static int smc_drv_probe(struct platform_device *pdev)
{
+ struct smc91x_platdata *pd = pdev->dev.platform_data;
+ struct smc_local *lp;
struct net_device *ndev;
struct resource *res, *ires;
unsigned int __iomem *addr;
- unsigned long irq_flags = SMC_IRQ_FLAGS;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
@@ -2152,6 +2155,24 @@ static int smc_drv_probe(struct platform
}
SET_NETDEV_DEV(ndev, &pdev->dev);
+ /* get configuration from platform data, only allow use of
+ * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
+ */
+
+ lp = netdev_priv(ndev);
+ if (pd)
+ memcpy(&lp->cfg, pd, sizeof(lp->cfg));
+ else {
+ lp->cfg.flags = SMC91X_USE_8BIT;
+ lp->cfg.flags |= SMC91X_USE_16BIT;
+ lp->cfg.flags |= SMC91X_USE_32BIT;
+ lp->cfg.irq_flags = SMC_IRQ_FLAGS;
+ }
+
+ lp->cfg.flags &= ~(SMC_CAN_USE_8BIT ? 0 : SMC91X_USE_8BIT);
+ lp->cfg.flags &= ~(SMC_CAN_USE_16BIT ? 0 : SMC91X_USE_16BIT);
+ lp->cfg.flags &= ~(SMC_CAN_USE_32BIT ? 0 : SMC91X_USE_32BIT);
+
ndev->dma = (unsigned char)-1;
ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -2162,7 +2183,7 @@ static int smc_drv_probe(struct platform
ndev->irq = ires->start;
if (SMC_IRQ_FLAGS == -1)
- irq_flags = ires->flags & IRQF_TRIGGER_MASK;
+ lp->cfg.irq_flags = ires->flags & IRQF_TRIGGER_MASK;
ret = smc_request_attrib(pdev);
if (ret)
@@ -2170,6 +2191,7 @@ static int smc_drv_probe(struct platform
#if defined(CONFIG_SA1100_ASSABET)
NCR_0 |= NCR_ENET_OSC_EN;
#endif
+ platform_set_drvdata(pdev, ndev);
ret = smc_enable_device(pdev);
if (ret)
goto out_release_attrib;
@@ -2188,8 +2210,7 @@ static int smc_drv_probe(struct platform
}
#endif
- platform_set_drvdata(pdev, ndev);
- ret = smc_probe(ndev, addr, irq_flags);
+ ret = smc_probe(ndev, addr, lp->cfg.irq_flags);
if (ret != 0)
goto out_iounmap;
--- 0017/drivers/net/smc91x.h
+++ work/drivers/net/smc91x.h 2008-02-20 17:08:35.000000000 +0900
@@ -34,6 +34,7 @@
#ifndef _SMC91X_H_
#define _SMC91X_H_
+#include <linux/smc91x.h>
/*
* Define your architecture specific bus configuration parameters here.
@@ -526,8 +527,13 @@ struct smc_local {
#endif
void __iomem *base;
void __iomem *datacs;
+
+ struct smc91x_platdata cfg;
};
+#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
+#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
+#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
#ifdef SMC_USE_PXA_DMA
/*
@@ -1108,41 +1114,41 @@ static const char * chip_ids[ 16 ] = {
*
* Enforce it on any 32-bit capable setup for now.
*/
-#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
+#define SMC_MUST_ALIGN_WRITE(priv) SMC_32BIT(priv)
#define SMC_GET_PN(priv) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG(priv))) \
+ (SMC_8BIT(priv) ? (SMC_inb(ioaddr, PN_REG(priv))) \
: (SMC_inw(ioaddr, PN_REG(priv)) & 0xFF))
#define SMC_SET_PN(priv, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(priv)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(priv, 0, 2)); \
- else if (SMC_CAN_USE_8BIT) \
+ else if (SMC_8BIT(priv)) \
SMC_outb(x, ioaddr, PN_REG(priv)); \
else \
SMC_outw(x, ioaddr, PN_REG(priv)); \
} while (0)
#define SMC_GET_AR(priv) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG(priv))) \
+ (SMC_8BIT(priv) ? (SMC_inb(ioaddr, AR_REG(priv))) \
: (SMC_inw(ioaddr, PN_REG(priv)) >> 8))
#define SMC_GET_TXFIFO(priv) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG(priv))) \
+ (SMC_8BIT(priv) ? (SMC_inb(ioaddr, TXFIFO_REG(priv))) \
: (SMC_inw(ioaddr, TXFIFO_REG(priv)) & 0xFF))
#define SMC_GET_RXFIFO(priv) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG(priv))) \
+ (SMC_8BIT(priv) ? (SMC_inb(ioaddr, RXFIFO_REG(priv))) \
: (SMC_inw(ioaddr, TXFIFO_REG(priv)) >> 8))
#define SMC_GET_INT(priv) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG(priv))) \
+ (SMC_8BIT(priv) ? (SMC_inb(ioaddr, INT_REG(priv))) \
: (SMC_inw(ioaddr, INT_REG(priv)) & 0xFF))
#define SMC_ACK_INT(priv, x) \
do { \
- if (SMC_CAN_USE_8BIT) \
+ if (SMC_8BIT(priv)) \
SMC_outb(x, ioaddr, INT_REG(priv)); \
else { \
unsigned long __flags; \
@@ -1155,12 +1161,12 @@ static const char * chip_ids[ 16 ] = {
} while (0)
#define SMC_GET_INT_MASK(priv) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG(priv))) \
+ (SMC_8BIT(priv) ? (SMC_inb(ioaddr, IM_REG(priv))) \
: (SMC_inw(ioaddr, INT_REG(priv)) >> 8))
#define SMC_SET_INT_MASK(priv, x) \
do { \
- if (SMC_CAN_USE_8BIT) \
+ if (SMC_8BIT(priv)) \
SMC_outb(x, ioaddr, IM_REG(priv)); \
else \
SMC_outw((x) << 8, ioaddr, INT_REG(priv)); \
@@ -1170,7 +1176,7 @@ static const char * chip_ids[ 16 ] = {
#define SMC_SELECT_BANK(priv, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(priv)) \
SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
else \
SMC_outw(x, ioaddr, BANK_SELECT); \
@@ -1208,7 +1214,7 @@ static const char * chip_ids[ 16 ] = {
#define SMC_SET_PTR(priv, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(priv)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(priv, 4, 2)); \
else \
SMC_outw(x, ioaddr, PTR_REG(priv)); \
@@ -1226,7 +1232,7 @@ static const char * chip_ids[ 16 ] = {
#define SMC_SET_RPC(priv, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(priv)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(priv, 8, 0)); \
else \
SMC_outw(x, ioaddr, RPC_REG(priv)); \
@@ -1267,7 +1273,7 @@ static const char * chip_ids[ 16 ] = {
#define SMC_PUT_PKT_HDR(priv, status, length) \
do { \
- if (SMC_CAN_USE_32BIT) \
+ if (SMC_32BIT(priv)) \
SMC_outl((status) | (length)<<16, ioaddr, \
DATA_REG(priv)); \
else { \
@@ -1278,7 +1284,7 @@ static const char * chip_ids[ 16 ] = {
#define SMC_GET_PKT_HDR(priv, status, length) \
do { \
- if (SMC_CAN_USE_32BIT) { \
+ if (SMC_32BIT(priv)) { \
unsigned int __val = SMC_inl(ioaddr, DATA_REG(priv)); \
(status) = __val & 0xffff; \
(length) = __val >> 16; \
@@ -1290,7 +1296,7 @@ static const char * chip_ids[ 16 ] = {
#define SMC_PUSH_DATA(priv, p, l) \
do { \
- if (SMC_CAN_USE_32BIT) { \
+ if (SMC_32BIT(priv)) { \
void *__ptr = (p); \
int __len = (l); \
void __iomem *__ioaddr = ioaddr; \
@@ -1308,15 +1314,15 @@ static const char * chip_ids[ 16 ] = {
SMC_outw(*((u16 *)__ptr), ioaddr, \
DATA_REG(priv)); \
} \
- } else if (SMC_CAN_USE_16BIT) \
+ } else if (SMC_16BIT(priv)) \
SMC_outsw(ioaddr, DATA_REG(priv), p, (l) >> 1); \
- else if (SMC_CAN_USE_8BIT) \
+ else if (SMC_8BIT(priv)) \
SMC_outsb(ioaddr, DATA_REG(priv), p, l); \
} while (0)
#define SMC_PULL_DATA(priv, p, l) \
do { \
- if (SMC_CAN_USE_32BIT) { \
+ if (SMC_32BIT(priv)) { \
void *__ptr = (p); \
int __len = (l); \
void __iomem *__ioaddr = ioaddr; \
@@ -1343,9 +1349,9 @@ static const char * chip_ids[ 16 ] = {
__ioaddr = lp->datacs; \
__len += 2; \
SMC_insl(__ioaddr, DATA_REG(priv), __ptr, __len>>2); \
- } else if (SMC_CAN_USE_16BIT) \
+ } else if (SMC_16BIT(priv)) \
SMC_insw(ioaddr, DATA_REG(priv), p, (l) >> 1); \
- else if (SMC_CAN_USE_8BIT) \
+ else if (SMC_8BIT(priv)) \
SMC_insb(ioaddr, DATA_REG(priv), p, l); \
} while (0)
--- /dev/null
+++ work/include/linux/smc91x.h 2008-02-20 17:04:41.000000000 +0900
@@ -0,0 +1,13 @@
+#ifndef __SMC91X_H__
+#define __SMC91X_H__
+
+#define SMC91X_USE_8BIT (1 << 0)
+#define SMC91X_USE_16BIT (1 << 1)
+#define SMC91X_USE_32BIT (1 << 2)
+
+struct smc91x_platdata {
+ unsigned long flags;
+ unsigned long irq_flags; /* IRQF_... */
+};
+
+#endif /* __SMC91X_H__ */
^ permalink raw reply
* [PATCH 03/04] smc91x: make superh use default config
From: Magnus Damm @ 2008-02-20 9:58 UTC (permalink / raw)
To: netdev; +Cc: Magnus Damm, lethal, nico, akpm
In-Reply-To: <20080220095740.22645.36783.sendpatchset@clockwork.opensource.se>
Removes superh board specific configuration from the header file. These boards
will instead be configured using platform data.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
drivers/net/smc91x.h | 30 ------------------------------
1 file changed, 30 deletions(-)
--- 0018/drivers/net/smc91x.h
+++ work/drivers/net/smc91x.h 2008-02-20 17:09:28.000000000 +0900
@@ -292,36 +292,6 @@ SMC_outw(u16 val, void __iomem *ioaddr,
#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
-#elif defined(CONFIG_SUPERH)
-
-#ifdef CONFIG_SOLUTION_ENGINE
-#define SMC_IRQ_FLAGS (0)
-#define SMC_CAN_USE_8BIT 0
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-#define SMC_IO_SHIFT 0
-#define SMC_NOWAIT 1
-
-#define SMC_inw(a, r) inw((a) + (r))
-#define SMC_outw(v, a, r) outw(v, (a) + (r))
-#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
-
-#else /* BOARDS */
-
-#define SMC_CAN_USE_8BIT 1
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-
-#define SMC_inb(a, r) inb((a) + (r))
-#define SMC_inw(a, r) inw((a) + (r))
-#define SMC_outb(v, a, r) outb(v, (a) + (r))
-#define SMC_outw(v, a, r) outw(v, (a) + (r))
-#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
-
-#endif /* BOARDS */
-
#elif defined(CONFIG_M32R)
#define SMC_CAN_USE_8BIT 0
^ permalink raw reply
* [PATCH 04/04] smc91x: add insw/outsw to default config
From: Magnus Damm @ 2008-02-20 9:58 UTC (permalink / raw)
To: netdev; +Cc: Magnus Damm, lethal, nico, akpm
In-Reply-To: <20080220095740.22645.36783.sendpatchset@clockwork.opensource.se>
This patch makes sure SMC_insw()/SMC_outsw() are defined for the
default configuration. Without this change BUG()s will be triggered
when using 16-bit only platform data and the default configuration.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
drivers/net/smc91x.h | 2 ++
1 file changed, 2 insertions(+)
--- 0019/drivers/net/smc91x.h
+++ work/drivers/net/smc91x.h 2008-02-20 17:11:19.000000000 +0900
@@ -446,6 +446,8 @@ static inline void LPD7_SMC_outsw (unsig
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_outl(v, a, r) writel(v, (a) + (r))
+#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
+#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
^ permalink raw reply
* Re: [NETFILTER]: Introduce nf_inet_address
From: Jan Engelhardt @ 2008-02-20 10:24 UTC (permalink / raw)
To: Patrick McHardy; +Cc: David Woodhouse, netdev, David S. Miller, varekova
In-Reply-To: <47BAEB6C.1030609@trash.net>
On Feb 19 2008 15:45, Patrick McHardy wrote:
>>
>> It's in busybox 1.9.1. Just including <netinet/in.h> seems to be
>> sufficient to make it happy again. I wonder if netfilter.h should
>> include that for itself?
>
> That would break iptables compilation, which already includes
> linux/in.h in some files. I guess the best fix for now is to
> include netinet/in.h in busybox and long-term clean this up
> properly.
>
If <linux/netfilter.h> includes <linux/in.h>, userspace compilation
fails (clashing defs, etc.); if <linux/netfilter.h> includes
<netinet/in.h>, kernel compilation fails (file not found).
What comes to mind is the ugly hack we had for a few days:
#ifdef __KERNEL__
# include <linux/in.h>
#else
# include <netinet/in.h>
#endif
and I think we should not impose any inclusion rules on userspace
this way.
Right now, it is solved this way:
kernel .c files explicitly include <linux/in.h> when loading
<linux/netfilter.h>,
userspace .c files explicitly includ <netinet/in.h> when loading
<linux/netfilter.h>. And that seems to work out.
^ permalink raw reply
* Re: e1000: Question about polling
From: Badalian Vyacheslav @ 2008-02-20 11:54 UTC (permalink / raw)
To: Jarek Poplawski; +Cc: netdev
In-Reply-To: <20080220094756.GC3885@ff.dom.local>
Khrm.... i try to say that i have language barrier and some time may
wrong compose clauses. Example below =)
"I'll try fix my English next time!"
Vyacheslav
> On Wed, Feb 20, 2008 at 12:25:32PM +0300, Badalian Vyacheslav wrote:
> ...
>
>> Please not think that it disrespect for you. Its simple language barrier =(
>>
>
> OK! Don't disrespect for me - I'll try fix my English next time!)
>
> Jarek P.
>
>
^ permalink raw reply
* Re: e1000: Question about polling
From: Jarek Poplawski @ 2008-02-20 12:25 UTC (permalink / raw)
To: Badalian Vyacheslav; +Cc: netdev, jesse.brandeburg
In-Reply-To: <47BC14F3.9000305@bigtelecom.ru>
On Wed, Feb 20, 2008 at 02:54:27PM +0300, Badalian Vyacheslav wrote:
> Khrm.... i try to say that i have language barrier and some time may
> wrong compose clauses. Example below =)
No, only a bit joking...
> "I'll try fix my English next time!"
Don't worry Vyacheslav: I think your message was understandable enough
if you got good answer from Jesse. (And I've learned something BTW too;
Thanks Jesse!) And after all it's not a language group: we care here
for serious problems!
Jarek P.
^ permalink raw reply
* Re: [VLAN] vlan_skb_recv
From: Patrick McHardy @ 2008-02-20 12:27 UTC (permalink / raw)
To: Ben Greear; +Cc: Linux 802.1Q VLAN, Stephen Anderson, Linux Netdev List
In-Reply-To: <47B31B96.7010801@candelatech.com>
Ben Greear wrote:
> Stephen Anderson wrote:
>> Hello,
>>
>> To help increase throughput and bypass the backlog queue, I changed the
>> netif_rx() to netif_receive_skb() in vlan_skb_recv(). What's the
>> argument for using netif_rx() other than legacy maintenance? At this
>> point, interrupt context should not be an issue. Layer 2 performance
>> has been a big focus in my area of development.
I guess the only point is to reduce stack usage. Its probably not
a problem with only VLAN, but it might be with further tunnels,
IPsec, ...
>> I'm sure you have seen many attempts to implement a single VLAN aware
>> IVL FDB in the past and I was wondering which attempt do you feel was
>> the best? Have you ever considered integrating your VLAN support
>> natively into the bridging code base or know of any attempts to do just
>> that?
Without having thought about this much, it seems to me that
it needs to be integrated in the bridge fdb to work properly.
^ permalink raw reply
* pci_device_id cleanups
From: Jonas Bonn @ 2008-02-20 12:53 UTC (permalink / raw)
To: linux-kernel, netdev; +Cc: greg
The PCI_DEVICE_TABLE patch I sent earlier doesn't necessarily make much sense by itself... here is a set of patches that apply this macro, in turn moving a lot of this data into __devinitconst which is discardable in certain situations. Hopefully the benefit of this approach is a bit clearer now.
drivers/net/3c59x.c | 2 +-
drivers/net/amd8111e.c | 2 +-
drivers/net/arcnet/com20020-pci.c | 2 +-
drivers/net/defxx.c | 2 +-
drivers/net/hamachi.c | 2 +-
drivers/net/niu.c | 2 +-
drivers/net/pasemi_mac.c | 2 +-
drivers/net/sk98lin/skge.c | 2 +-
drivers/net/skfp/skfddi.c | 2 +-
drivers/net/starfire.c | 2 +-
drivers/net/sunhme.c | 2 +-
drivers/net/tlan.c | 2 +-
drivers/net/wan/dscc4.c | 2 +-
drivers/net/wan/lmc/lmc_main.c | 2 +-
include/linux/pci.h | 9 +++++++++
15 files changed, 23 insertions(+), 14 deletions(-)
^ permalink raw reply
* [PATCH] Add PCI_DEVICE_TABLE macro
From: Jonas Bonn @ 2008-02-20 12:53 UTC (permalink / raw)
To: linux-kernel, netdev; +Cc: greg, Jonas Bonn
In-Reply-To: <1203512031-14318-1-git-send-email-jonas@southpole.se>
The definitions of struct pci_device_id arrays should generally follow
the same pattern across the entire kernel. This macro defines this
array as const and puts it into the __devinitconst section.
Signed-off-by: Jonas Bonn <jonas@southpole.se>
---
include/linux/pci.h | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 87195b6..c7a91b1 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -389,6 +389,15 @@ struct pci_driver {
#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
/**
+ * PCI_DEVICE_TABLE - macro used to describe a pci device table
+ * @_table: device table name
+ *
+ * This macro is used to create a struct pci_device_id array (a device table)
+ * in a generic manner.
+ */
+#define PCI_DEVICE_TABLE(_table) const struct pci_device_id _table[] __devinitconst
+
+/**
* PCI_DEVICE - macro used to describe a specific pci device
* @vend: the 16 bit PCI Vendor ID
* @dev: the 16 bit PCI Device ID
--
1.5.3.8
^ permalink raw reply related
* [PATCH] [net] use PCI_DEVICE_TABLE: makes struct pci_device_id array const and adds section attribute __devinitconst
From: Jonas Bonn @ 2008-02-20 12:53 UTC (permalink / raw)
To: linux-kernel, netdev; +Cc: greg, Jonas Bonn
In-Reply-To: <1203512031-14318-3-git-send-email-jonas@southpole.se>
Signed-off-by: Jonas Bonn <jonas@southpole.se>
---
drivers/net/amd8111e.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c
index 85f7276..a4ad2fb 100644
--- a/drivers/net/amd8111e.c
+++ b/drivers/net/amd8111e.c
@@ -113,7 +113,7 @@ MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0
module_param_array(dynamic_ipg, bool, NULL, 0);
MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
-static struct pci_device_id amd8111e_pci_tbl[] = {
+static PCI_DEVICE_TABLE(amd8111e_pci_tbl) = {
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
--
1.5.3.8
^ permalink raw reply related
* [PATCH] [net] use PCI_DEVICE_TABLE: makes struct pci_device_id array const and adds section attribute __devinitconst
From: Jonas Bonn @ 2008-02-20 12:53 UTC (permalink / raw)
To: linux-kernel, netdev; +Cc: greg, Jonas Bonn
In-Reply-To: <1203512031-14318-2-git-send-email-jonas@southpole.se>
Signed-off-by: Jonas Bonn <jonas@southpole.se>
---
drivers/net/hamachi.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/hamachi.c b/drivers/net/hamachi.c
index b53f6b6..d8056e9 100644
--- a/drivers/net/hamachi.c
+++ b/drivers/net/hamachi.c
@@ -1987,7 +1987,7 @@ static void __devexit hamachi_remove_one (struct pci_dev *pdev)
}
}
-static struct pci_device_id hamachi_pci_tbl[] = {
+static PCI_DEVICE_TABLE(hamachi_pci_tbl) = {
{ 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, },
{ 0, }
};
--
1.5.3.8
^ permalink raw reply related
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